DESIGN OF A MINI-UART USING VHDL - JIT - Journals

Journal of Industrial Technology 11 (2), 2002, 67-76

DESIGN OF A MINI-UART USING VHDL

Liakot Ali1, Roslina Sidek1, Ishak Aris1, Mohd. Alauddin Mohd. Ali2 and Bambang Sunaryo Suparjo

1Department of Electrical and Electronic Engineering Universiti Putra Malaysia, 43400 Serdang, Selangor, Malaysia

2Department of Electrical, Electronic and Systems Engineering Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia

([email protected])

RINGKASAN: Kertas kerja ini membincangkan perkara berkenaan dengan rekabentuk universal assinkronus penerima dan pemancar (UART) kecil dengan

menggunakan bahasa diskripsi perkakasan litar bersepadu yang sangat pantas (VHDL). Rekabentuk ini dikompilasi dan disimulasi dengan menggunakan perisian Altera MAXPLUS-1/ EDA dan dilaksanakan dengan menggunakan teknologi Altera FPGA. Keputusan daripada verifikasi perkakasan menggunakan osiloskop juga disertakan. Keputusan simulasi yang diperolehi dari modul pemancar dan penerima UART menunjukkan ianya berfungsi dengan baik di dalam perhubungan data

bersiri. Paras logik isyarat di dalam keputusan verifikasi perkakasan mengesahkan keputusan simulasi dan memastikan ketepatan rekabentuk. Berdasarkan kepada ciri modulariti dan saiz kompak bagi UART yang dicadangkan, ianya adalah sesuai untuk aplikasi sistem di dalam cip (SOC).

ABSTRACT: This paper presents the design of a mini-universal asynchronous receiver and transmitter (UART) using very high-speed integrated circuit (IC) hardware

description language (VHDL). The design is compiled and simulated under Altera MAXPLUS-11 EDA (Electronic design automation) Software environment and is implemented using Altera FPGA (Field programmable gate array) technology.

Hardware verification results using oscilloscope are also presented. Simulation results of the transmitter and receiver modules of the UART show that it is functioning properly in serial data communication. Logic levels of the signals in the hardware verification results verify the simulation results and ensure the accuracy of the design. Due to modularity feature and compact size of the proposed UART, it is ideal for system-on-a-chip (SOC) application.

KEYWORDS: UART, VHDL, FPGA, SOC

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Liakot Ali, Roslina Sidek, Ishak Aris, Mohd. Alauddin Mohd. Ali and Bambang Sunaryo Suparjo

INTRODUCTION

UART is a key component for serial data communication. It is named asynchronous because

in the UART protocol, the transmitter and the receiver do not share a clock signal. That is,

a clock signal does not emanate from one UART transmitter to the other UART receiver.

Since no common clock is shared, a known data transfer rate (baud rate) must be agreed

upon prior to data transmission. That is, the receiving UART needs to know the transmitting

UART's baud rate (and conversely the transmitter needs to know the receiver's baud rate,

if any) . In almost all cases the receiving and transmitting baud rates are the same. The

transmitter shifts out the data starting with the LSB first. UART converts serial data to parallel

and vice versa. A CPU communicates with a UART via its parallel interface; a modem or

other peripheral devices communicates with a UART via its serial interface.

UARTs such as NS16450A and NS16550A of National Semiconductor Company (NSC) ,

SC26C198 and SC28L92 from Philips Company are available in the market (Anom., 2002).

They are used as discrete component in designing electronic system. Design of UART chip

has been discussed in some literature where it has been used as a platform to carry out

experiments to solve different research problems (Yunshan and Marshall, 2001; O'Neill

et. al. 2001; Yeandel et. al., 1997). Yeandel et. al. (1997) described on-line testability issue

while O'Neill et. al. (2001) highlighted issues related to high speed serial communication

and Yunshan and Marshall (2001) implemented IFIS (If it Fails It Stops) testability methodology

using UART chip; The design of the UART chip presented in this paper claims uniqueness

for its modularity feature and use of the VHDL code. VHDL is now an industry standard IC

design tool that shortens the design cycle of a chip by efficiently describing its behaviour

(Bhasker, 1992, Perry and Douglas, 1994). It is technology independent. If a particular IC

fabrication process becomes outdated, it is possible to synthesise a new level of design by

only changing the synthesising technology file but using the same VHDL code.

BASIC UART OPERATION

Main components of a UART are a transmitter module, a receiver module, a baud-rate

generator and a control circuit. Figure 1 shows the block diagram of a mini-UART chip.

While no data is being transmitted , a logic 1 must be placed in the XMIT line. A data

packet is composed of 1 start bit , which is always a logic 0, followed by a programmable

number of data bits (typically between 6 to 8) , an optional parity bit, and a programmable

number of stop bits (typically 1 but it may be 1.5 or 2) . The stop bit must always be

logic 1. Figure 2 shows a basic UART data packet.

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Data signals - .

Input control signals

elk

Control Logic

Baud-rate generator

Xmitter

Receiver

Design of a Mini-UART Using VHDL

Baud_clk

Xmit_signal (serial-out bit)

Recv_signal (serial-in bit)

Figure 1. Block diagram of a basic UART

start bit (logicO)

data b~e (16N8 bits) 0)

pari~ bit stop bit ( optional) (logic 1)

~§~I DO I 01 I 021 001 D4 I 05 I D6 I D7 I PB ffi~~ time

Figure 2. Basic data format for a UART protocol

In data transmission through UART, once the baud rate has been established (prior to initial communication), both the transmitter and the receiver's internal clock is set to the same frequency (though not the same phase). The receiver "synchronises" its internal clock to that of the transmitter's at the beginning of every data packet received. This allows the receiver to sample the data bit at the bit-cell center.

A key concept in UART design is that UART's internal clock runs at a much faster rate than the baud rate. For example, the popular 16450 UART controller runs its internal clock at 16 times the baud rate. This allows the UART receiver to sample the incoming data with granularity of 1/16 the baud-rate period. The greater the granularity, the receiver has greater immunity with the baud rate error. The receiver detects the start bit by detecting the transition from logic 1 to logic O (note that while the data line is idle, the logic level is high). Once the start-bit is detected, the next data bit's "centre" can be assured to be 24 ticks minus 2 (worse case synchroniser uncertainty) (NSC, 1995). From then on, every next data bit centre is 16 clock ticks later. Figure 3 illustrates this point.

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T = 1/Baud Rate . Bit-cell period Tua = T/16

T .__......

UART receiver samples the incoming data using x16 Baud Rate Clock

j :i:sn 00 I D1 I 021 001 D4 I D5 I D6 I D7 I PB t ~~··.

t detect start bit by sensing transition from logic 1 to logic O

sample incoming data at the bit-cell centre

Figure 3. Data sampling by a UART

I sample stop bit

PROPOSED ARCHITECTURE OF THE UART WITH SIMULATION

Figure 4 shows the design flow diagram of the UART. VHDL under MAXPLUS-11 EDA

(electronic design automation) software has been used for the design and simulation of the

UART (Altera, 1998; Mano, 2002; Nelson et. al. 1995; Wakerly, 2000) . Block by block design

technique has been used in the proposed design. Every micro-functional block is designed

and simulated in this approach and once its functionality is verified then another block is

designed using the same approach. Finally, all the blocks are integrated and the whole

system is verifed again .

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I Design using I ,---------,------_: VHDL . _....-----------,-----,

I

No

No

t Transmitter .

Block-byBlock Design

Transmitter Testing

Hardware Verification

'

t Receiver

Block-byBlock Design

Testingwith ~ PLD . -~

Yes

Verified

~--- Complete

Figure 4. Design flow diagram of the UART

No

No

Main modules of UART are a transmitter and a receiver module. Figure 5 shows the block diagram of the transmitter module.

smltter Tran Control Register

tbre I tre - Transmitter u t mr Controller start-ntbrl trc

Transmitter Transmitter Buffer - __.. -Transmitter

tbr Register Register Parity

Multiplexer Generator

stop-

Figure 5. Block diagram of the transmitter module of the UART

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Figure 6 shows the simulation result of the transmitter module. It shows that the data bits

sent in parallel have been changed into a serial data stream. The figure is divided into two

parts, A and B. In part A, the timing diagram shows that when the master reset signal

(m_reset) is in logic low and when the ntbrl signal transits from logic high to logic low, the

outbit signal from the transmitter register output starts to transmit. It can be seen that the

transmission starts with a start bit (logic low), followed by eight data bits, a parity bit (logic

low if odd parity and logic high if even parity) and two stop bits (logic high) . When there

is no transmission, the outbit line remains high indicating idle state. It also shows that when

a second ntbrl signal is given within the 16 clock pulses, the tbre signal (transmitter buffer

register empty) goes low indicating that the transmitter buffer register is not empty.

Ref j a.ans j li8 Time: ....,! 9=.9=6u=s ___ ~j Interval: ~I 9=.9~6u~s ___ _ '-='=----~ a.ans

Name: Value:

B- txclk a _.. ntbrl

.- m_reset

ilD'"" in7 a

m,- in6 a

m,- in5 a DP- in4 a n- in3 a a,- in2

a- in1 a

IP- ina a

...- Ire

-iliili7 tbre

..a, outbit a

Figure 6. Simulation result of the transmitter

Part A shows that serial bit stream for transmission is '011100110011'. The first bit (0)

indicates start bit, which is logic low. The next eight bits (11100110) are data bits. Logic level

of these data bits is similar to that of the parallel data bits (from inO to in?). The 101h bit (0)

is parity bit. Logic level of this bit is low because there is odd number of '1 's in the data

bits. The eleventh (1) and twelfth (1) bits are stop bits, which are logic high. Part B shows

the same operation occurred and the data converted into the serial stream is '010111101111 '.

Here the logic level of start bit and stop bits are the same as that in part A but the parity

bit is logic high because the number of 1 's in the data bits is even. It can be concluded that

the transmitter module is capable of converting 8 bit parallel data to 8 bit serial data and

adding necessary control bits in the accurate format for secure transmission.

72


Figures 7 and 8 show the hardware verification results of the transmitter module displayed

using an oscilloscope.

Figure 7. Serial output for input data bits 'O 1O10111' from oscilloscope

Figure 8. Serial output for input data bits '01100010' from oscilloscope

73


Figures l and 8 show that the serial output data bits are similar to that of the parallel input data bits and control bits (start bit, parity bit and stop bits) are in the accurate format. It verifies

that the design of the transmitter module implemented in the hardware is functioning properly. ,,

Figure 9 shows the receiver module of the UART. The operation of the receiver module is

the opposite of the transmitter module. It receives data in serial and converts it into parallel output. The serial data is received at the receiver register input (rri). Then the data passes

through the receiver shift register, receiver register and to the receiver buffer register to become the output in parallel form. The parity checker checks the parity bit generated from

the transmission and a parity error is said to occur if the parity error flag is high. Similarly the stop checker checks the two stop bits and a framing error is said to occur if the frame

error flag is high.

Control Register--~

dr oe

Receiver

Receiver Controller -------------+-~ rri

mr ndrr rrc

rbr •::-----Receiver Receiver

Buffer +-- Register Register

pe---------~ Parity

Checker

Receiver Shift

Register

Stop le --------------- 1 Checker

Figure 9. Block diagram of the receiver module of the UART

The operation of the receiver begins with the detection from logic high to logic low of the

start bit that will initiate the counter to start counting. The counter counts from Oto 15. When the counter reaches its eleventh count, it starts the sampling of data from the receiver shift register. The counter continues to count up to 15 and stop counting. The contents of the

receiver shift register are cleared by the clear signal before another start bit is detected to

begin another new operation.

Figure 10 shows the simulation result of the receiver module. m_reset indicates master reset

input signal. When this signal is low, the receiver will perform its normal operation. PE and

FE are output signals for indicating parity error and framing error respectively. CTRL_OUT

and DR are also output signals. When logic level of CTRL_OUT is high, serial data received by the receiver module appears in the output. Logic level high at the DR output indicates that a data word has been transferred to the receiver buffer register.

74

Design of a Mini-UART Using VHDL,

Start bit

Ref lo.ons

Name: Value:

iii'- RRC 0

ir rri 1

r m_reset 0

e PE 0

• out? 0

e out6 0

"ll} out5 0

-e out4 0

.- out3 0

o out2 0

e out1 0 @ outO 0 ~ FE 0 -d DR 0

• CTRL~OUT 0

A B

Figure 10. Simulation result of the Receiver Module of the UART

It is seen in part A that there is a start bit signal at the rri input followed by the data bits '10010111'. Once the data word is received, CTRL_OUT signal goes high and the received data appears at the parallel output line (outO to out?) which has been shown in part B. The binary data at the output is '10010111' which is similar to that of the one shown in part A. It can be concluded from the timing diagram as shown in Figure 10 that the receiver is functioning properly.

CONCLUSION

Design of a mini-UART chip using VHDL is presented in this paper. The VHDL code is reusable to keep pace with a new technology of IC fabrication and easy to modify for future enhancements. All the functional blocks of the transmitter and the receiver module of the chip have been simulated and verified by MAXPLUS-11 software. Simulation results of the transmitter and receiver modules of the UART show that it can accurately transmit and receive data in a serial data communication. The transmitter and the receiver modules are independent and due to this modularity feature, it is ideal for SOC application. The design has been implemented using ALTERA FPGA technology. The signals measured in the

75

·'

Liako(Al(flo§lina Sidek, Ishak Aris, Mohd. Alauddin Mohd. Ali and Bambang Sunaryo Suparjo

FPGA hardware verify the simulation result and strongly indicate the proper functionality

of the design . .

REFERENCES

Altera (1998) . Data Book, Altera Corporation, San Jose, USA.

Anom. (2002), http://www.semiconductors.philips.com/news/publications/contenVfile_ 4 64.html.

Bhasker, J. (1992). VHDL primer, McGraw-Hill, London, UK.

a< Mano, M. M. (2002). Digital design, Prentice-Hall International Inc., New Jersey, USA.

Nelson, V. P., Nagle, H. T. and Irwin, J. D. (1995). Digital logic circuit analysis, Prentice-Hall

International Inc., New Jersey, USA.

NSC (National Semiconductor) (1995). PC165500, Universal Asynchro,nous Receiver/

Transmitter with FIFOs,) : Datasheets. ,,,.·/ •j

O'Neill, B.C., Clark, S. and Wong, K.L. (2001 ). Serial communication circuit with optimized skew characteristics. IEEE Comm. Lett. 5(6), pp 260-262.

Perry and Douglas, L. (1994) . VHDL: programming by examples. McGraw-Hill, London, UK.

Wakerly, J. F. (2000). Digital design, Prentice-Hall International Inc., New Jersey, USA.

Yeandel, J., Thulborn, D. and Jones, S. (1997). An on-line testable UART implemented using IFIS, Proceedings of 15'h IEEE VLSI Test Symp. pp 344-349.

Yunshan, Z. and Marshall, T. (2001 ). Design verification using formal techniques, IEEE

Proceedings of 4rh International Conference on ASIC. pp 21-28.

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