Design and implementation of flexible and stretchable systems

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Design and implementation of flexible and stretchable systems

Mario Gonzalez a,⇑, Bart Vandevelde a, Wim Christiaens b, Yung-Yu Hsu a, François Iker a,Frederick Bossuyt a, Jan Vanfleteren a,b, Olaf van der Sluis c, P.H.M. Timmermans c

a IMEC, Kapeldreef 75, 3001, Belgiumb ELIS Department, Ghent University, Belgiumc Philips Applied Technologies, The Netherlands

a r t i c l e i n f o

Article history:Received 30 September 2010Received in revised form 19 February 2011Accepted 6 March 2011Available online 23 March 2011

a b s t r a c t

This paper presents a summary of the modeling and technology developments for flexible and stretchableelectronics. These technologies can achieve mechanically bendable and stretchable subsystems by incor-porating the electronic circuit into a matrix made of a soft polymer. The base substrate used for the fab-rication of flexible circuits is a uniform polyimide layer, while silicones or polyurethanes materials arepreferred for the stretchable circuits. The method developed for chip embedding and interconnectionsis named Ultra Thin Chip Package (UTCP). Extensions of this technology can be achieved by stackingand embedding thin dies in polyimide, providing large benefits in electrical performance and still allow-ing some mechanical flexibility. These flexible circuits can be converted into stretchable circuits byreplacing the polyimide by a soft and elastic silicone material.

The integration of ultra thin dies at package level, with thickness in the range of 10–30 lm, into flexibleand/or stretchable materials are demonstrated. Furthermore, the design and reliability test of stretchablemetal interconnections at board level are analyzed by both experiments and finite element modeling. Wehave shown through finite element modeling and experimental validation that an appropriate thermo-mechanical design is necessary to achieve mechanically reliable circuits and thermally optimizedpackages.

� 2011 Elsevier Ltd. All rights reserved.

1. Flexible electronics

Flexible substrates are often an interesting alternative forreplacing the rigid printed circuit boards (PBC) because of theirlight weight and flexibility. In many cases, flexible substrates havea higher mechanical reliability than the counterpart rigid boardsdue to their inherent ability to deform which can reduce the in-plane stresses generated during the different thermal processingsteps. In order to achieve this flexibility, thinned dies in the orderof 10–30 lm are embedded in the inner layers of the flexibleboards.

One of the most common integration approaches consist in con-necting, with flip chip technology, the dies to the circuit printedwires. However, some known issues from this approach are theimpossibility of testing the dies before embedding, the high preci-sion requirements for the placement of the bare die and the needfor very fine pitch flexible printed circuit compatible with thepad pitch of the embedded chip. Another approach is to place thedie in an interposer that allows, among other advantages, the pos-sibility to test the chip before embedding and provides a fan out,

eliminating in this way the need of high density PCB’s and the highprecision placement [1]. This novel packaging concept, named Ul-tra Thin Chip Package (UTCP), is based on the concept of embed-ding ultra thin chips, with thicknesses below 30 lm, in betweentwo layers of polyimide, resulting in a chip package with a totalthickness of only 50–60 lm. This package can be assembled onPCB or flex, or can be embedded in a stack of PCB layers. Detailsof the process flow are described in [2,3].

An example of the UTCP package and the metallization is shownin Fig. 1. The metallization includes a small fan out of the 64 diecontacts to a 9 � 9 mm2 package with a pitch of 500 lm. The largerfan out include contacts of 650 � 1300 lm2 forming a package of30 � 30 mm2. The outermost contacts can be used, for instance,to connect the integrated microcontroller for programming andtesting. The inner contacts are used for embedding the UTCP pack-age in multilayer flex boards. In this image, an SMD resistor and aLED are mounted on top of the package for visually demonstratingthe functionality after processing. The integration of this packagein a wireless ECG system has been demonstrated in [4–6].

1.1. Thin chip stacks in flexible packages

Extreme miniaturization can be achieved by embedding ultrathin dies in a dielectric material and afterwards integrate the

0026-2714/$ - see front matter � 2011 Elsevier Ltd. All rights reserved.doi:10.1016/j.microrel.2011.03.012

⇑ Corresponding author. Address: IMEC, Kapeldreef 75, 3001, Leuven, Belgium.Tel.: +32 16 28 86 02.

E-mail address: [email protected] (M. Gonzalez).

Microelectronics Reliability 51 (2011) 1069–1076

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different packages using 3D interconnections. Besides the advan-tage of saving space, die stacking may also result in an enhancedelectrical performance, as a result of the shorter interconnectionsbetween circuits.

Stacking thin dies using UTCP technology provides large bene-fits in electrical performance, density, weight and even allowssome mechanical flexibility which is a unique property for astacked die solution. However, the thermal resistance and the ther-mally induced mechanical stresses during processing need to betaken into consideration for this packaging concept and thereforerequire an optimization of the design based on Finite ElementModeling (FEM) simulations.

1.1.1. Thermal analysisIn the thermal simulation study, the objective is to get a first or-

der of magnitude of the thermal resistance of the stacked package.

The thermal resistance is expressed as �C/W and is a measure forits performance to remove heat from the die to the environment.The considered stacked package, based on IMEC’s UTCP technology,consists of two dies in between a thin film laminated structure. In afirst instance, only the thermal resistance of the package itself isconsidered. The solder ball pads are assumed to be at the referencetemperature (which is set to 0 �C). The heat exchange through nat-ural convection over the surface is neglected as the outside flexmaterial is a poor conductor and the total area is also small.

A 3D Finite Element Model (Fig. 2) has been built including twosilicon dies with 20 lm thickness. The copper tracks towards thesecond level bond pads were modeled in detail because the coppermetallization is the main path for heat transfer through the package.The thermal conductivity of copper is about three orders of magni-tude higher than the dielectric and adhesive materials (kCu = 380 W/m K; kadhesive = 1.1 W/m K; kdielectric = 0.29 W/m K). The silicon isalso a very good conductor, but as the dies are thinned down to20 lm, the spreading performance of the die itself is lower thanthe one of a regular full thickness die. This is in particular importantfor local hot spots on the die, which are not considered in this study.

Fig. 3 depicts the temperature distribution when 0.1 W are dis-sipated in each die (total power = 0.2 W). The highest temperaturedrop is found over the tiny copper tracks from the die to the vias. Asecond simulation for the same structure with a double thicknessof the copper metallization (2 lm instead of 1 lm) shows thatthe temperature gradient over the structure is almost half of thefirst structure with 1 lm copper tracks. Further improvement ofthe design can be done by applying lots of dummy copper planesas local heat spreaders. However, this is only needed for relativehigh power applications (when P > 0.1 W).

1.1.2. Thermo-mechanical analysisIn the thermo-mechanical simulation work, the focus is on

calculating the stresses and the thermal induced warpage after

Fig. 1. UTCP package of MSP430F149 microcontroller.

Fig. 2. Finite Element Model of a stack of two UTCP packages. (a) Full 3D model; (b) silicon die and copper interconnections.

1070 M. Gonzalez et al. / Microelectronics Reliability 51 (2011) 1069–1076


processing. Because the polymer materials are cured at tempera-tures around 250 �C, relative high stresses are induced in the thindies. Moreover, as the total thickness of a UTCP is small, the stiff-ness of the overall structure is insufficient to overcome the strongwarpage after cooling, giving rise to integration problems duringthe subsequent processing steps. Even if the package is attachedto a temporary carrier; a strong warpage can cause self-detach-ment from the carrier. An example of the calculated warpage ofthe UTCP after processing, once released from the carrier, is shownin Fig. 4.

2. Stretchable electronic

The basic principle of stretchable electronics is to interconnectrigid or flexible interposers, containing the electronic components,by means of elastic electrical conductors. In order to protect thecircuit from environmental factors and to provide a mechanicalstability, the interposers and the interconnections are embeddedinto an elastic polymer.

Even though stretchable electronic technology is not as matureas the flexible circuit technology, many different concepts havebeen proposed in recent years, covering a wide range of applica-tions with dimensions of only few hundreds of microns [7,8], to

some tens of centimeters [9,10]. Each technology presents someadvantages and disadvantages among each other, and the choiceof the technology depends largely on its final application.

One concept consists in depositing a thin metal film in apre-stretched substrate. It is reported that once the substrate isreleased, the metal will deform out-of-plane forming a controlledbuckled structure [11]. Even though this unique design offers acontrollable stretchability without losing electrical performance,it is limited to relatively small circuits and deformation of only afew percent.

A similar process technology involving the deposition of a thinmetal on a silicone material has been investigated in [12,13]. It hasbeen proven that while stretching a 100 nm gold film placed on topof an elastic substrate, multiple microcracks are formed in themetal during the stretching allowing deformations up to 50%.Drawbacks of this technique are the electrical restrictions ofextremely thin metal films, the need for high cost equipment andthe processing of nonstandard assembly technology on thosesubstrates. Furthermore, the number of microcracks increase asthe substrate is deformed and therefore, a change in the resistanceof the line is observed during the deformation. Some applicationsof this technology include electronic circuits used for skin electron-ics [14] and microelectrode arrays used for monitoring the neuronactivity in the brain [15]. The choice in IMEC technology is based

Fig. 3. Temperature distribution in �C over the stacked die package (0.1 W dissipation per die). As boundary condition, a fixed temperature of 0 �C is applied to the solder pads(=bottom of the via through the stack).

Fig. 4. Calculated warpage of one UTCP after processing.

M. Gonzalez et al. / Microelectronics Reliability 51 (2011) 1069–1076 1071


on the realization of high electrical performance metallicinterconnections patterned as a planar 2D spring and embeddedin silicone elastomers. An example of such design is depicted inFig. 5.

Depending on the desired metal track dimensions, it is possibleto use either a Mold Interconnect Device (MID) technology [16,17],or use a standard thin film technology at wafer level [18]. In thefirst case, the metal meanders are formed either by using electro-plating, photolithography and wet etching or laser patterning[19]. In all these cases, standard rigid packages are connected withthe elastic electrical interconnections using either conductiveadhesives or conventional lead free SnAgCu alloys. Finally, the cir-cuits are embedded in an elastic material such as poly(dimethylsiloxane) (PDMS) or polyurethane (PU). More than 100% deforma-tion has been achieved with this technology and reliability of sev-eral thousand of cycles has been achieved [20,21]. High densityinterconnections are also being investigated combining technolo-gies such as die thinning and stretchable circuit technology. Thistechnology named Ultra Thin Chip Flexible (UTCF) consists inembedding thin dies and metal interconnects in a polymer at waferlevel, and then release them from the wafer [18].

2.1. Wafer level stretchable circuits

High density stretchable interposers have been developed inIMEC. This technology consists in embedding a thin silicon die(below 20 lm) and the metal interconnections in a stretchablepolymer. All operations, except dies transfer, are done in awafer-level packaging process manner, allowing fast processingof a large number of dies, minimizing costs and time. Thanks toits ease of application, the metallization can be designed with com-plex geometries allowing some degree of stretchability.

Fig. 6 depicts an example of a thin embedded die and the metalinterconnections before and after releasing from the wafer. Asstretchable substrate, a photo sensitive spin on silicone, WL5150,has been used because of its high elasticity and low induced stres-ses from the relatively low Young’s modulus (<160 MPa) and largeelongation to break (�37%). The temperature stability of the mate-rial up to 300 �C allows for further assembly while remaining un-der CMOS compatible process temperature (<400 �C).

To allow stretchability of the package, metal interconnectionshave to be stretchable as well. We therefore use a specific designof metal lines with a kind of sinusoidal shape allowing to stretchthem such as a 2D spring. In this design, pitch on the die is100 lm (80 lm pads) are fanned-out to a 400 lm pitch (300 lmpads). This ‘‘large’’ pitch is compatible with stretchable board

technologies. The dimensions on this design are typical for stan-dard targeted applications.

In this activity, extensive FEM simulations are carried out in or-der to maximize stretchability of the overall embedded subsystemin general and of the metal interconnect in particular. As the re-quired stretchability of these interposers will not exceed 10%, ahorseshoe design is not necessary.

Fig. 7 illustrate a comparison of the permanent deformation ofthe copper between straight lines and the meandered lines. Dueto the symmetry, only half of the structure has to be modeled, witha symmetry plane applied in the left side of the model. In the rightside, a uniform displacement is applied, giving a total deformationin the package of 5%. As the rigid silicon chip does not elongate, theeffective stretch in the copper meanders is 8.7%. As it can be seen inFig. 7, the meandered lines are more reliable than straight lines be-cause of the lower plastic strain. Even though there is a reductionin the plastic strain of the meander line compared to the straightlines, the plastic strain is concentrated in specific zones of thecurve, therefore further optimization of the transition zone from ri-gid (silicon die) to stretchable (copper meanders) need to be inves-tigated. Further improvements have been observed by reducing thecopper track width.

In order to keep a low electrical resistance and increase, at thesame time, the stretchability of the meanders, multiple coppermeanders, parallel to each other are designed as shown in Figs. 8and 9.

In the case of multiple metal conductors forming a single line,electrical bridges are placed between the tracks in the regionswhere the lowest deformation is observed (Fig. 8). These bridgeshelp to keep the continuity of the lines after failing in a specific re-gion. In other words, if a metal track fails, only one section of theline is lost (between two bridges) in electrical connection insteadof the failure of the whole track. This redundancy helps to increasethe reliability of the system.

2.2. Board level stretchable circuits

Metal conductors are by nature only elastic for a few percentbefore break, therefore the design of the metal meanders is adominant factor to give stretchability to a non-stretchable mate-rial. FEM has been widely used to characterize the shape of theconductors in order to allow high deformations without perma-nent damage. Based on these results, a horseshoe metal trackFig. 5. Stretchable copper interconnection.

Fig. 6. Thin dies embedded into dielectric and interconnected with metals beforerelease (on wafer).



shape is proposed. In this design, the stresses are distributed in awider region instead of concentrated in the apex of the curve.

The damage in the metal is significantly reduced by applyingnarrow metallization schemes and low elastic modulus of thesubstrate [16,21]. Fig. 9 shows an example of a horseshoe design.The metal used for the interconnections is copper, with a Young’smodulus of 117 GPa. The substrate is a silicone, modeled as aNeo–Hokean material with C10 = 0.157 MPa. After deforming thesystem 30%, the maximum plastic strain in the copper is only4.83%.

The deformation of the interconnection lines can be differentwhen several meanders are close to each other, or depending onthe position of the lines. An example of this phenomenon is shownin Fig. 10. A total nominal deformation of 25% is applied in a uniax-ial manner. In the entire test sample we can observe three regions ofinterest: the clamping zone, where no in-plane deformation is ap-plied; a transition zone, following the rigid clamp, where a complexdeformation is presented, and a stable and homogeneous regionwhere all the meanders deform in the same mode.

From the reliability point of view, the transition zone is the crit-ical region; because of the different deformation modes are ob-served and the maximum elongation of the meanders isobserved. As no contraction is allowed in the ‘‘Y’’ direction, thesubstrate and copper meanders in this region are deformed as aplanar extension test and shows slightly higher damage whencompared to the uniaxial tensile test. Moreover, the outermostmeanders are bended and stretched at the same time, while thecenter meanders are only stretched. This means that the totaldeformation of the outermost copper meanders is higher (lowerreliability) than the deformation of the central meanders. This ef-fect is illustrated in Fig. 11.

In some applications, where high density interconnections andlow stretchability are required, the horseshoe design is not longera suitable design. Due to the shape of the horseshoe, it is not pos-sible to ‘‘stack’’ parallel lines; therefore the minimum pitch is gov-erned by the amplitude of the meander. For those applications apattern with a zigzag structure is designed as shown in Fig. 12. Thisdesign, as the horseshoe, presents the characteristic that its electri-cal resistance is independent on the elongation before metal rup-ture. Stretchability beyond 40% has been demonstrated with thisdesign [22].

Fig. 7. FEM of thin dies and metal interconnections embedded in a silicone encapsulant. Left image: straight interconnections. Right image: double meander intercon-nections.

Fig. 8. Stretchable metal interconnections including electrical bridges betweenmeanders.



2.3. Reliability and failure analysis

As it was discussed in Sections 2.1 and 2.2, the reliability of thestretchable interconnections depends not only on the constitutivebehavior of the substrate and the metal interconnections but alsoon the mechanical design and the applied deformation. FEM simu-lations results presented here were done for a specific design anddeformation and presented as the maximum plastic strain in thecopper. During fatigue cycles, much smaller but periodic, elonga-tions are applied to the circuits producing a fatigue failure of themetals. In order to model the fatigue test and estimate the fatiguelifetime, the stretchable circuit was subjected to cyclic deforma-tions at a specific percentage and a FEM model was used tocalculate the accumulated plastic strain per cycle for the sameelongation. These kinds of tests were repeated for seven differentelongations going from 2.6% to 22%. In this way, we ‘‘translate’’the applied strain into a damage criterion (plastic strain). If anew design is created or the thickness of the substrate is modified,we can use the FEM to calculate the plastic strain and thereforeestimate the fatigue lifetime. The result of this ‘‘translation’’ isdepicted graphically in Fig. 13. In this plot, the accumulated plastic

strain per cycle is the value calculated by FEM, whereas the life-time is obtained experimentally. An equation based on theCoffin–Manson law is used to fit the data points into a correlationcurve.

In order to observe the failure mechanism, a home built stagewas mounted directly in the SEM in order to monitor in situ thedeformation mechanism of the horseshoes shaped metal tracks.The samples were specially designed, with the copper exposed inthe surface of the silicone. In this way, it was possible to take highresolution images of the elastic interconnections at differentphases of the deformation. Fig. 14 shows a horseshoe meander de-formed 100%. Several observations are done from these images.Firstly, although the copper metal is deposited in-plane, duringthe deformation, a combined ‘‘opening’’ of the horseshoe andtwisting of the metal is observed giving rise to an out-of-planedeformation of the meander. This mechanism is beneficial for thereliability because it implies a lower induced plastic strain. Sec-ondly, before the final break of the copper track, an interfacialdelamination is observed. More detailed explanation of this mech-anism are presented experimentally by Hsu in [22] and numeri-cally by van der Sluis in [23].

Fig. 9. Equivalent plastic strain in the horseshoe design after deformation of 30%. Dashed line shows the original dimensions of the substrate. Substrate has been modeledas hyperelastic material represented with a Neo–Hooke model with C10 = 0.157 MPa.

Fig. 10. Deformation of multi-line circuit.



In order to understand the mechanisms leading to a delamina-tion of the copper meanders from the silicone substrate, the inter-face properties were characterized by a series of peel-tests done ina uniform copper layer deposited on top of a silicone substrate.These samples followed the same process flow as the one used tofabricate the stretchable circuits. In these tests, the necessary forceto peel-off the thin film from the substrate is monitored as afunction of the clamp displacement and the adhesion energy iscalculated from these experiments. The obtained interface param-eters were used in a FEM in a form of interfacial cohesive elementslocated in the interface between the copper and the silicone. Amodel simulating the deformation of a representative horseshoesection was done. An example of this model is shown in Fig. 15.The original location of the copper film is indicated as the curvedthin lines on the substrate. A very good agreement between thein situ experiment and the delamination model is observed. A

Fig. 11. Equivalent plastic strain in the copper meander within the transition zone (values in %). Red curves indicate the displacement direction. (For interpretation of thereferences to color in this figure legend, the reader is referred to the web version of this article.)

Fig. 12. Schematic of the pitch comparison between zigzag and horseshoeinterconnections.

Fig. 13. Fatigue lifetime of copper line versus simulated plastic strain. Coppermodeled as a perfect plastic material.

Fig. 14. SEM image of a horseshoe patterned interconnect stretched 100%.



detailed explanation of the peel test experiments and the FEM waspresented by van der Sluis in [23].

3. Conclusions

It is believed that in the future many electronic assemblies onrigid substrates will be replaced by mechanically flexible or evenstretchable alternatives. The success of flexible and stretchableelectronics is based in the broad number of applications wherethe weight, size, cost and shape among others are an asset. This pa-per summarizes the ongoing activities for the integration of IC at awafer level and board level for flexible, stretchable and potentiallysmaller devices.

Acknowledgments

The presented work was performed in the frame of the ProjectsTIPS and STELLA, which are financially supported by the EuropeanCommission FP7 and FP6 programs respectively.

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Fig. 15. FEM of a 67% stretched horseshoe pattern interconnect, showing theoriginal and final position of the copper meander.


Design and implementation of flexible and stretchable systems

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