CHAPTER 34
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Transcript of CHAPTER 34
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-1
CHAPTER 34
Fabrication of Microelectronic Devices*
*By Kent M. Kalpakjian
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-2
Printed Circuit Boards
Figure 34.1 A collection ofprinted circuit boards. Source:Phoenix Technologies, Inc.
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-3
FabricationSequence of
and IntegratedCircuit
Figure 34.2General fabricationsequence forintegrated circuits.
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-4
MOS Transistor Cross-Sections
Figure 34.3 Cross-sectional views of thefabrication of a MOStransistor. Source: R. C.Jaeger.
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-5
Chemical Vapor Deposition
Figure 34.4 Schematic diagrams of (a) continuous, atmospheric-pressure CVD reactor and (b) low-pressureCVD. Source: S. M. Sze.
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-6
Silicon Dioxide Growth
Figure 34.5 Growth ofsilicon dioxide, showingconsumption of silicon.Source: S. M. Sze.
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-7
Pattern Transfer by Lithography
Figure 34.6 Pattern transfer by lithography. Note that the mask in step three can be a positive or negative imageof the pattern. Source: After W. C. Till and J. T. Luxon.
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-8
Etching and Ion Implantation
Figure 34.7 Etching profiles resulting from (a) isotropic wet etching and (b) anisotropic dryetching. Source: R. C. Jaeger.
Figure 34.8 Apparatus for ionimplantation
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-9
pn Junction Diode
Figure 34.9 (continued)
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-10
pn Junction Diode (cont.)
Figure 34.9
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-11
Two-Level Metal Interconnect
Figure 34.10 (a) Scanning electron microscopephotograph of a two-level metal interconnect. Notethe varying surface topography. Source: NationalSemiconductor Corporation. (b) Schematic drawingof a two-level metal interconnect structure. Source: R.C. Jaeger.
(a) (b)
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-12
Bonding and Packaging
(a) (b) (c)
Figure 34.11 (a) SEM photograph of wire bonds connecting package leads (left-hand side) to die bondingpads. (b) and (c) Detailed views of (a). Source: Courtesy of Micron Technology, Inc.
Kalpakjian • SchmidManufacturing Engineering and Technology © 2001 Prentice-Hall Page 34-13
Integrated Circuit Packages
Figure 34.12 Schematic illustrations of different IC packages: (a) dual-in-line (DIP), and (b) ceramic flat pack,and (c) common surface mount configuration. Sources: R. C. Jaeger and A. B. Glaser; G. E. Subak-Sharpe.