Automated synthesis for testability

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 36, NO. 2, MAY 1989 263

Automated Synthesis for Testability

A bstract-This paper presents an integrated, compiler-driven approach to digital chip design that automates mask layout and test pattern generation for 100-percent stuck-at fault coverage. This approach is well suited for designs where it is most important to minimize the design cycle time rather than the silicon area.

We show by that compiling from a unified design specification followed by logic synthesis, we can significantly reduce the problem of automatic test pattern generation. This paper bridges a language-based design capture and logic synthesis with hierarchical test pattern generation and redundancy removal techniques. A section on benchmark results highlights the close coupling of a language-based design specification, logic synthesis, and testability.

I . INTRODUCTION ESIGN FOR testability techniques offer guidelines to D reduce the cost of testing and test pattern generation [l].

However, in a typical design environment, such as schematic capture, the many degrees of freedom to interconnect logic can easily produce a design for which test patterns cannot be generated with reasonable cost. In the worst case, fault coverage may be low and the design may contain redundant logic, making test generation impossible for such faults. Modifying manually generated logic designs or customized layouts to improve testability is often considered unproductive since such problems are typically detected after a relatively long design cycle.

This paper presents an integrated, compiler-driven approach to digital design that automates mask layout and test generation for 100 percent stuck-at fault coverage. We achieve these objectives by partitioning the design process into four major steps:

1) unified structural/functional design specification, followed by hierarchical compilation into standard cells and modules of Boolean equations;

2) synthesis of Boolean equations into modules of standard cells;

3) netlist audit for conformance to scan-based design rules, followed by automatic test pattern generation;

4) standard cell placement, routing, and chip layout.

Manuscript received November 16, 1988; revised December 19, 1988. This work was supported by the Microelectronics Center of North Carolina. Grants from RTI and BNR have supported some of the work on testability.

F. Brglez is with BNR, Research Triangle Park, NC 27709, and with the Microelectronics Center of North Carolina, Research Triangle Park, NC 27709.

D. Bryan and R. Lisanke are with the Microelectronics Center of North Carolina, Research Triangle Park, NC 27709.

J. Calhoun is with the Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27650.

G. Kedem is with the Computer Science Department, Duke University, Durham, NC 27706.

IEEE Log Number 8926815.

--

I / I

IC Layout Generation Sys!em

._____....._______.......

Silicon Foundly

Chip

I

IC Tester System

Fig. 1. Automating for testability within the OASIS concept.

We show that routine application of steps 1 and 2 significantly reduces the problem of test pattern generation in step 3. The links between steps 1-4 are illustrated in Fig. 1 and form the basis of the Open Architecture Silicon Implementa- tion System (OASIS), which is being developed at the Microelectronics Center of North Carolina (MCNC) in cooperation with participating institutions and industrial affiliates 121. The notion of “open architecture” implies system compatibility with software available in the public domain. Currently, the OASIS concept as shown in Fig. 1 relies on ESPRESSO from UC-Berkeley [3] for minimization of two- level Boolean equations, on the fast fault simulator from the Technical University of Munich [4] for part of the test pattern generation process, and on the RNL simulator [5] from the University of Washington during the multilevel multimode system simulation and verification. OASIS has evolved from an earlier standard-cell-based silicon compiler prototype 161 and the work detailed in [7]-[12]. Several chips have been designed, manufactured, and tested successfully with the current generation of OASIS.

This paper is divided into four major parts: an introduction to the unified structural/functional design specification, a logic synthesis system overview, the modular components of the testability system, and a section on benchmark results. The benchmarks have been chosen to highlight the close coupling of a language-based design specification, logic synthesis, and

0278-0046/89/0500-0263$01 .00 0 1989 IEEE

264 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 36, NO. 2, MAY 1989

testability. These topics are on the current research agenda of several teams [ 131-[ 161.

11. A STRUCTURAL/FUNCTIONAL DESIGN SPECIFICATION

This section introduces the programming language LOGIC- I11 as a means of complete design specification. Following an overview of LOGIC-I11 syntax, we illustrate the hierarchy of LOGIC-111 and its impact on testability specifications. A. Overview of LOGIC-III

LOGIC-I11 is a Pascal-like language that allows the designer to completely specify a large digital system. The language combines functional descriptions of finite state machines and decoding logic with hierarchical structural descriptions of computational circuits. We argue that the expressive power of a programming language is effective in describing large digital systems. The description is concise and clear; it is easy to understand and to modify. An algebraic programming language such as Pascal is especially suitable for describing the actions of a finite state machine. Moreover, the process of translating functional descriptions of state machines to efficient circuits is well understood. However, functional description alone is not enough. Functional units such as multipliers could be mapped into many different hardware realizations, spanning a wide spectrum of trade-offs between size, speed, and power. Some circuits cannot be described as Boolean functions (since their truth tables will explode) and the only practical way to express them is in terms of their structure. By combining functional and structural descriptions into a single programming language, we are now able to proceed in a consistent and effective manner with compilation all the way to the mask level.

The language supports two module types: a finite state machine module (FSM-module), to describe a single FSM or decoding logic, and a NET-module, to describe the structure of a circuit as an interconnection of FSM-modules and NET- modules. The language retains the expressive power of Pascal so that arbitrary connections can also be programmed.

Each FSM-module describes a single state machine and is essentially a LOGIC-II program [6, 71. The module has a list of formal parameters that are: INPUT, CLOCKED-INPUT, OUTPUT, CLOCKED-OUTPUT, STATE, INTEGER, or BOOLEAN. There is a declaration section defining the local variables and symbolic states. The main body of the module is a list of instructions describing the state machine. IF-THEN- ELSE and CASE statements are used for describing logical implications, and vector assignments are used for coding sets of Boolean variables as integers. Also, loops and conditionals are used to direct the flow of execution.

For example:

FSM-module controller( Cars, LongTimeout, ShortTimeout : INPUT ; StartTimer : CLOCKED-OUTPUT ; HYLight, FarmLight: array [0 .. 11 of

CLOCKED-OUTPUT) ;

green, yellow ,red: INTEGER; HYyellow, HYgreen,Farmyellow,Farmgreen : STATE;

var

begin (* Define the color encoding *)

green := 0; yellow := 2; red := 1;

case (* The main FSM Definition *) HYgreen : (* Highway light is green *)

begin FarmLight := red; HYLight : = green ; if (Cars and LongTimeout) then

begin HYyellow : = 1 ; StartTimer : = 1; end

HYgreen : = 1 ; else

end; (* end of states = HYgreen case *)

HYyellow : (* Highway light is yellow *) begin

end; (* end of states = Farmgreen *)

end; (* end of case *) end. (* end of FSM definition *)

The above example shows an FSM-module that describes the highway controller in [17]. Note that we use symbolic states and one-hot coding to describe the transitions. Alterna- tively, we could have explicitly assigned the state coding. Each FSM-module is compiled either into a netlist of standard cells [7]-[8] or a PLA-based FSM [18]. In principle, two NET-modules are generated for each FSM-module: the first module connects D-type scannable flip-flops that map directly from the symbolic states, the second module connects a set of standard combinational cells generated by the logic synthesis process described in a separate section.

Each NET-module has a list of formal parameters: INYU 1,

OUTPUT, BIDIRECTIONAL, INTEGER, or BOOLEAN, followed by a declaration section describing the nodes and local variables. The body of the module consists of statements that connect other modules, FSM-modules, NET-modules, or even primitive modules such as transistors or capacitors. Statements such as IF-THEN-ELSE, FOR, WHILE, and UNTIL direct the flow of execution or they control the way connections are made. In addition, INTEGER and BOOLEAN variables serve for computation or are passed as parameters to other modules.

The addition of programming language constructs to the netlist descriptions makes is possible to define parameterized macros, write algorithms to choose different hardware structures for different sets of parameters, and define the hardware at different levels of detail.

BRGLEZ et al.: AUTOMATED SYNTHESIS FOR TESTABILITY 265

For example:

NET-module adder(Cin:INPUT; A,B:array[O. .N - 11 of INPUT; Ovflw : OUTPUT; Sum: ARRAY[O. .N - 11 of OUTPUT; N: INTEGER;); VAR

j : INTEGER; TempN: ARRAY[O. .N - 11 OF NODE: BEGIN

IF N > = 12 THEN CLA-adder(Cin, A, B,

ELSE BEGIN Ovflw ,Sum,N)

Full-Adder(Cin,A[O] ,B[O] ,Sum[O] ,

For j := 1 T O N - 1 DO TempWI) ;

Full-Adder(TempNlj1, Alj], Blj], Sumti], TempNlj + 11) ;

connect(TempN[N] , Ovflw) ; END (* else *)

END (* module *)

The above example shows a selection of two distinct adder implementations: a ripple adder of up to 12 bits, or a carry look-ahead adder when a larger module is required. The choices are dictated by performance and area considerations. The 1-bit Full-Adder macro above would be modeled at the transistor level, the standard-cell level as well as the functional level.

The user controls level to which the compiler expands each macro. As shown in Fig. 1 the choice depends on the target application. The simulator would typically expect a variety of representations starting at the the switch-level. On the other hand, the layout system would typically expect the modules at the standard-cell level, and the nominal test generation system expects them at the gate level. Additional details of exploiting higher levels of hierarchy for test pattern generation are outlined in a separate section.

B. LOGIC-111 Hierarchy and Implications for Testability

We now present three design examples to illustrate the use of LOGIC-111 to generate hierarchical scan-based circuits. Each example introduces a circuit with different testability problems and shows how LOGIC-111, in conjunction with test generation techniques, produces 100 percent testable logic.

I) Scan-Testable CIRCUIT and NETMODULE Hier- archy. In this example we extend the traffic controller example [ 171 to illustrate the basic hierarchy and capabilities of LOGIC-111. The top level of LOGIC-I11 hierarchy is “CIRCUIT,” as shown below and illustrated in Fig. 2.

CIRCUIT highway;

VAR reset : RESET; Phil, Phi2 , Phi-test : CLOCK; Cars : INPUT; Long, Short, StartTimer : NODE; HL, FL : array [0..1] of NODE; H-lights, F-lights: array [0..2] of OUTPUT;

NET-UOWLE Dnodrr

(HL. FL anay[O I] ol INPUT,

H-lghts anayI0 21 of OUTPUT,

FSU-UOWLE Conmlbr

(Cars, Long, Short INPUT,

HL. FL arraylo 11 of OUTPUT,

Staft-limer CLOCKED-OUTPUT.).

reset Phl Pht2 Phi-lest scan uo (aner roubq)

Fig. 2. Scan-testable CIRCUIT or NET-MODULE hierarchy in LOGIC- III .

BEGIN

Timer (StartTimer, Short, Long) ; Controller (Cars, Long, Short, StartTimer, HL, FL): Decoder (HL, FL, H-lights, F-lights);

END.

At the level illustrated in Fig. 2, we see the interconnection of FSM-modules and NET-modules. Expanding any NET- module could produce a similar arrangement in principle. Except for signals of type “NODE,” all other signal types at the CIRCUIT level are pin signals, some of which are global, such as RESET and CLOCK. LOGIC-I11 automatically connects RESET and CLOCK signals to all D-type flip-flops. All flip-flops are implicitly connected into the scan chain in natural order until the circuit has been routed for layout; in this case specific scan-in and scan-out pins are identified.

Despite the apparent automation for scan-based testability, design rule violations can still occur. For example, an asynchronous loop between two FSM-modules will be flagged by the audit software if the user neglects to declare signal “Start Timer” as a clocked output. On the other hand, the benefit of the design automation is the nearly instantaneous feedback, the facility to make a design correction at a high level, and the ability to perform a simple recompile of the design.

2) N-Bit Array Multiplier, Modijied for 100 Percent Testability. We will use the array multiplier, shown for N = 4 in Fig. 3, to highlight several opportunities to improve the design. First, we take advantage of the regular structure of the design to write a LOGIC-I11 program that interconnects the basic building blocks consisting of AND gates, half-adders (HA), and full adders (FA). Next, we can describe the adder modules as FSM-modules and have logic synthesis produce, hierarchically, the first complete netlist of the multiplier. Lastly, we can generate test patterns and establish testability. In this case, we find that a particular full adder, in a position ( i = 2, j = N - 2), has a consistent redundancy that we choose to remove in accordance with the procedure described in a later section of this paper. We replace this full adder with a module that has redundancies removed, then modify the LOGIC-I11 program with only a few additional lines to take the


FA ... full-adder P7 Pg PS p4

Note: The shaded FA has been modified for 100%. testability Fig. 3. An example of an N-bit array multiplier, modified for 1 0 0 percent

testability.

exceptions into account when compiling into the netlist. The partial LOGIC-I11 code for the array multiplier is shown below:

CIRCUIT multl6-r; VAR A, B : array[0..15] of INPUT;

P : array[0..31] of OUTPUT; And-array : array[O.. 151 of NODE; N : INTEGER;

N := 16; AndNodes (N, A, B, And-array); Product(N, And-array, P);

BEGIN

END.

NET-MODULE Product (N : integer; And-array : array [O. .N - 1,

0. .N - 11 of INPUT; P : array [O. .N*2 - 11 of OUTPUT;); *

* BEGIN for i : = 0 to N do

begin * *

if ( i = 2) then (* CONNECT A MODIFIED FULL-ADDER MODULE

FA-MOD TO MAINTAIN 100 % TESTABILITY *) begin

for j := 0 to N - 3 do begin

FA(And-array[i,Jl,C[i - lJ] ,

256 \ sel-a

1

2

3

* *

I I

Fig. 4. Boolean specifications for all primitive modules in a MAX circuit.

end; j := N -2; FA-MOD(And-array[i,j],

connect(S[i,N - 11 ,And-array[i, C[i - l,jl,S[i - 1 j + 11, S[i,j],C[i,j]);

N- 11); end

else if(i < = N - 1) then

* * 3) 256-Input MAX-Unit. As shown in Fig. 4, only three

basic logic-level modules are used to make up a complex MAX-unit in a VLSI chip containing a fuzzy logic inference engine [19]: an OR gate, a 2-1 multiplexer, and a select unit. These three units combine into an 8-input 4-output bit comparator, several of which are connected into a tree. It is relatively straightforward to generate a complete specification in LOGIC-LII that compiles into a netlist. The major point of this example is to depict an intermediate form of module specifications that were also generated by compiling LOGIC- LII: the minimized on-set and off-set. It is this representation that is employed in hierarchical test pattern generation in Section IV. Since this circuit has 256 inputs and only four outputs, it cannot be fully tested with random patterns. Only deterministic test pattern generation establishes 100 percent testability, and the advantages of hierarchical test pattern generation will be clearly demonstrated in the benchmark section.

HI. AUTOMATIC SYNTHESIS OF TESTABLE LOGIC

Automatic logic synthesis transforms logic equations into a multilevel network of realizable logic gates. Synthesis also attempts to meet design constraints and make optimal use of a technology (e.g., CMOS standard-cell library).

Fig. 5 illustrates several of the procedures used in automatic logic synthesis. First, minimization algorithms eliminate

S[i - 1 j + l],S[i,j],C[i,j]); redundancy in the equations and reduce the number of product


Boolean Equations U - Decomposition

Boolean Equations

!I+

Fig. 5 . Automatic logic synthesis.

terms and literals [3], [20]. Decomposition and factoring yield an equivalent multilevel representation which, for most logic, will consume less area and operate faster than a two-level implementation [8], [21]-[24]. Finally, the technology mapping step optimally transforms multilevel equations into a netlist of available library cells, subject to design constraints [6], [8], [lo], [25], [26]. The following sections provide more detail on each of these logic synthesis procedures.

A . Logic Minimization Two-level logic minimization addresses the problem of

eliminating redundant terms and unnecessary literals of the terms to produce an equivalent logic representation (truth table) with a lower implementation cost and other desirable features. Minimization of two-level logic has recently become highly developed, to the point where good heuristics now exist. The program ESPRESSO [3] employs many of the latest heuristics.

A minimal logic representation is both prime and irredundant. A sum-of-products logic representation is irredundant if and only if no term can be deleted without changing the Boolean function. Conversely, redundant terms may be removed without changing the logic function. A product term of a sum-of-product representation is prime if and only if all literals of the term are necessary. Any nonprime terms can be expanded by removing one or more literals without affecting the logic function.

B. Decomposition and Factoring Decomposition transforms two-level equations into a multi-

level, factored form [2 11, [27]. Decomposition objectives include finding repeated subexpressions and, more generally, decreasing the total number of literals which is related to the final hardware implementation cost. Logic gates of a cell library generally have some fan-in restrictions which decomposition, in part, helps meet. Generally, decomposition increases the number of levels of logic while decreasing the average fan-in per gate.

One measure of the quality of a logic description is the total number of literals in a description. This corresponds to the total number of gate inputs in the description. Other measures

a b

d f l = ac +ade + bc + bde

f2 = afg + bfg + efg e f 9

f l = (a + b)(c + de)

f2 = ((a+b) + e) f g

a b

C

d e

f 9

11

12

Fig. 6. Decomposition example

f l = a c + a d e + b c + b d e

f2 = afg + bfg + efg I L k z l Generate Candidate

3. ( c + d e ) = c + s = r I 4. ( a + b + e ) = q + e = t

1 Substitute I 11 =qr 12 z fgt

q = (a + b) s (de) r = (c + de) t = (a + b +e)

awing v I Yes

U) technology mapping

Fig. 7. Generic decomposition procedure.

are average fan-in per gate, and equivalently, total number of gates.

Fig. 6 shows how decomposition and factoring improve the quality of a logic implementation. The two-level logic implementation has 26 gate inputs and nine gates. The multilevel logic decreases these costs to 13 gate inputs and six gates. Here, the input equations have been algebraically factored and parenthesized, and new intermediate variables q, r, s, and t have been created.

Fig. 7 illustrates, in general, how to transform two-level to multilevel logic. The first step in the decomposition procedure


14 Transistor Pairs 7 Transistor Pairs

Fig. 8. Technology mapping example.

I Mulllpla Trial Lil I - -c

Gate Slzlng and Butter lnsertlon

Fig. 9. Technology mapping system.

is generation of candidate subexpressions to be used as possible substitutions. Next, the selection step chooses the best subexpressions from among those generated. Finally, the substitution step creates new intermediate variables for the selected subexpressions and uses these variables instead of the complete subexpression wherever possible in the logic equations. The term factoring means creating new intermediates in a single-output function or within a single output of a multi- output function.

Our program DECAF is an implementation of decomposition that produces multilevel logic suitable for technology mapping, the next phase in logic synthesis.

C. Technology Mapping Procedure Technology mapping transforms multilevel logic equations

into a netlist of realizable logic cells, with the objective of minimizing area, propagation delay, power consumption, etc. Fig. 8 shows both a trivial realization of a set of multilevel equations and an area-optimized technology mapping, which reduces the required transistor count from 14 to 7.

The technology mapping procedure McMAP employs several steps to transform factored equations into gates, as illustrated by Fig. 9. First, large AND’S and OR’S are partitioned into trees (tree operation), reducing gate fan-in and creating initial feasible circuit configurations for subsequent technology mapping operations. Next, simple gates are merged into

circuit area and performance (merge operation). The merge operation performs the inverse of the tree operation; together, the two operations constitute a global transformation from one circuit topology to another. After performing the tree and merge operations, McMAP converts each gate to negative logic and determines the phase (eg. NAND/AOI or NOR/OAI) that will minimize the total number of inverters (gate-phase

larger AND, OR, AND-OR, and OR-AND StrUCtUreS tQ improve

operation). A gate-sizing and buffer-insertion procedure selects gates with high drive capability and buffers high fan-out lines whenever it improves a circuit’s timing performance.

Two versions of each technology mapping operation exist: an area-optimizing version and a timing-optimizing version. The timing-optimizing version makes use of static timing analysis to minimize the critical path delay by making transformations that reduce this delay and by rejecting transformations that increase it. The area-optimizing version makes all area-improving transformations regardless of the impact on timing.

IV. AUTOMATIC TEST PATTERN GENERATION Large-scale test pattern generation, even for single stuck-at

faults, presents a formidable problem. For some designs, especially unstructured and sequential, no practical amount of CPU resource can generate test patterns with adequate fault coverage. The synthesis procedures presented earlier in this paper produce designs that can be structured into a scan mode for purposes of test generation and testing. We show in the remainder of this paper that, for such designs, test patterns with fault coverage of 100 percent can be achieved with reasonable CPU resources. In this section we present an overview of the scan-based testability system as an integral part of OASIS, highlighting the areas of hierarchical deterministic test pattern generation and redundancy identification and removal.

A . Background Computer manufacturers have been developing and using

comprehensive scan-based automatic test pattern generation systems for more than a decade. The best known examples are NEC’s Scan-Path design system [28] and IBM’s Level- Sensitive Scan Design (LSSD) system [29]. While these systems continue to evolve, similar systems are being introduced by others [30]-[33]. Major differences between the systems arise from distinctive clocking methodologies and choices of scannable flip-flops. These choices lead to a variety of “front-end” audit programs that must be supported in order to verify compliance with specific design rules. The final output of every audit program is an acyclic graph of logic gates and modules; it is this graph that forms the basis for all subsequent automated testability and test pattern generation procedures.

The research to minimize the overhead of scannable designs and to develop effective design audits has not been as broad- based as the combined research to discover new testability analysis, fault simulation, and test pattern generation algorithms for combinational logic. In this decade, automatic test pattern generation for large-scale scan-based designs has been advanced by several new and rapidly evolving systems and algorithms [34]-[37]. Most notably, the role of testability analysis and fault simulation has been revisited and enhanced [38]-[43], and novel approaches to automatic test pattern generation have been benchmarked successfully [a]-[46]. Identification of all redundancies in a suite of difficult benchmark circuits [47] has been achieved at a nominal computational expense [46].

BRGLEZ el al.: AUTOMATED SYNTHESIS FOR TESTABILITY 269

Cell-based netlist

Scan-based DFT audit violations

- t;p\ c

Testability F.C. an a I y s i s projections

I

patterns

I c

patterns

Exact

Reversed test pattern

compaction patterns

Fig. 10. The basic testability system.

B. Testability System Overview

The basic system consists of five modules, depicted in Fig. 10: audit to verify compliance with scan-based rules and to map the cell-based netlist into an acyclic graph of combinational logic, tap to assess random pattern testability and project fault coverage, mike to efficiently fault simulate random or user-supplied patterns and establish an exact fault coverage, dtpg to generate test patterns algorithmically for the faults that resist detection with random patterns, and xtp to further compact the test pattern set. All modules are written in “C” under Berkeley Unix 4.3.

1) Scan-Based Audit. The system supports a raceless flip- flop with normal data and scan data inputs which is controlled by a reset line and three clock lines. Only two nonoverlapping clock signals are active at any time: they shift either normal data or scan data. The scan-chaining of flip- flops takes place only after automatic placement and routing of standard cells by the VPNR place and route system [48]. One of the scan data inputs and one of the flip-flop outputs are designated as primary input and primary output of the scan chain. The following are violations of our scan-based design rules: presence of asynchronous feedback loops, gated clock and reset signals, ambiguous declarations of primary inputs and outputs, and wired logic. All of these violations can be corrected by well-known design transformations. In addition, we can automatically remove redundant logic associated with constant input signals such as VDD and VSS. We employ a

similar transformation during the redundancy removal process which is described in a separate section. The audit module is driven by a hierarchical, cell-based netlist that is compatible with the RNL simulator [5]; the netlist is either entered manually or is generated automatically, as discussed earlier.

2) Testability Analysis. The basic purpose of testability analysis is to project the cost of testing with random patterns. We use a probabilistic procedure, COP, introduced in [49] and benchmarked in [50] and [51]. Without the cost of exact fault simulation, this procedure estimates the number of patterns needed to achieve a high fault coverage. Extending this approach further, we can now generate better distributions of random patterns to significantly reduce the cost of random pattern testing [41], [44]. Alternatively, we can maintain a uniform distribution of random patterns but insert a minimal number of additional test points to reduce the number of random patterns.

3) Fault Simulation. The generic application of fault simulation in this system is to evaluate whether a new applied pattern will detect faults not detected by previously generated patterns. The implementation is based on processing 32 patterns in parallel and traversing the circuit graph in a highly efficient manner [43]. Often, to cover a comparable number of faults, the fault simulator will grade thousands of randomly applied patterns much faster than we can produce tests using a deterministic test pattern generator. The case in point is the 16-bit multiplier based on Fig. 3. This multiplier is highly random pattern testable; only 192 random trial patterns are required to cover 100 percent of all single stuck-at faults at a cost of 18 CPU seconds on a VAX 8650, and only 65 patterns are retained as the test set. However, fault simulation cannot resolve whether an undetected fault is redundant or merely resistant to random pattern testing. In such cases, we have no choice but to resort to deterministic test pattern generation.

4) Deterministic Test Pattern Generation. The deterministic test pattern generator in Fig. 10 is a stand-alone module, not integrated with the fault simulator. Typically, it takes advantage of the fast fault simulator that grades random patterns until the fault coverage no longer increases; consequently the fault set presented to the deterministic test pattern generator consists usually of only 5-10 percent of the full fault set. Faults in this remaining set either resist detection with random trials or are redundant. The deterministic generator resolves the faults as follows: it finds a test for the fault, it proves the fault redundant (no test exists), or it aborts on the fault due to the backtrack limit. The basic distinction between all test pattern generation algorithms lies in the number of backtracks that are required to either generate a test or prove the fault redundant. Our implementation is to a large extent based on the PODEM algorithm [34] and we found our backtracking performance on par with or better than the comparative results on PODEM in [35]. The difference may be attributed to our using probabilistic measures to guide the algorithm. While FAN [35] has shown performance advantages over PODEM, the relative simplicity of PODEM permits us to more readily explore the issues of hierarchical test pattern generation that are highlighted later.


f t

Select a Target Fault I

1 DTPG at rnodule/gate level.

Fig. 11. Hierarchical concept of deterministic test pattern generation.

5) Test Pattern Compaction. Test pattern compaction reduces the number of test patterns produced by fault simulation and deterministic test pattern generation while maintaining the same level of fault coverage. Compaction achieves this by repeating fault simulation on the combined set of patterns in reverse order. Because patterns are applied in the reverse order, faults that were detected last are now detected first. These patterns also detect many of the easy faults detected earlier. We observed a 25 to 50 percent reduction in the number of test patterns required.

C. Hierarchical Deterministic Test Pattern Generation The cost of test pattern generation increases with circuit and

fault list size. Both can be managed hierarchically to reduce the cost of test pattern generation. We have shown that even for circuits that contain a large proportion of EXOR modules relative to simpler gates, considerable savings in CPU can result-when compared to an equivalent circuit in which all EXOR modules are expanded into simple gate equivalents [9], [ 111. The argument for lower cost is not only smaller circuit and fault list size; combining gates into modules also collapses reconvergent fan-out nodes and hence reduces the complexity of the test pattern generation process.

This section highlights the most important principles that we applied to hierarchical test pattern generation; more details are given in [52].

I ) Leveraging Hierarchy. Our approach is illustrated in Fig. 11 . At the top level, there are two generic steps: 1)

selecting the target fault from a list of module/gate faults and a list of module interior faults and, 2) generating a test for the target fault at the module/gate level. The architecture of the module/gate-level deterministic test pattern generator is static; however, the netlist presented 'to the generator changes dynamically whenever a module is expanded to select an interior untested fault as a target. The strategy to leverage from hierarchical representation is twofold: 1) all untested module/gate faults are processed first and, 2) only a single module from the complete netlist is expanded at any given time to target the module interior faults. This strategy is generic and need not depend on the particular algorithm used in the implementation of the module/gate-level algorithm-as long as the algorithm and implementation support gate-level as well as module-level primitives.

In order to prove the concept as discussed above, we extended our gate-level implementation of the PODEM algorithm [9], [34]. In principle, more complex algorithms such as FAN [35] or its extension, SOCRATES [46], could be used as a basic framework. The framework as illustrated in Fig. 1 1 is different from the one proposed in conjunction with PODEM in [53]. We make use of compact cube notation similar to [53]; however, the context of the cubes and the calculus are different, as will be shown in sections that follow. The key to success in any framework is the consistent characterization of the complex module primitives beyond the traditional gate-level and a consistent strategy in making decisions at the mixed module/gate-level .

BRGLEZ et al.: AUTOMATED SYNTHESIS FOR TESTABILITY 27 1

1 - - 1 l o - -

‘A@ b GT 1

( x .... designates a redundant stuck-at fault ) -~

Fig. 12. An example of module/gate-level characterization for testability

2) Characterization of Complex Combinational Primi- tives. A hierarchical representation of a circuit will accelerate the test pattern generation process whenever the modules that characterize major subcircuits offer at least one, if not all, of the following attributes: 1) evaluation of the module’s function requires less effort than the multilevel gate evaluation of the subcircuit; 2) we can propagate faults across the boundaries of the module faster than with the multilevel gate evaluation of the subcircuit; and 3) we gather a better intelligence as to the early resolution of potential conflicts in fault propagation when compared with the local gate-by-gate decision making.

Currently, we characterize all required functions of the module in terms of a minimized, two-level sum-of-products representation. The functions are the traditional on-set and off- set as illustrated for several module primitives of the MAX unit in Fig. 4; in addition we generate an observability-set [9], [54] for every module input, illustrated for a simple circuit in Fig. 12.

The circuit in Fig. 12 represents a naive implementation of

a bitwise comparator. While this implementation illustrates the simplicity of generating a ‘ ‘greater-than-or-equal” function by reusing a “greater-than” and an “equal” module, the implementation is naive because it does not take into account that several redundancies may result from using such a straightforward approach. In fact, several backtracks are required to confirm the presence of redundant faults (marked with an “x”) when we try to generate a test at gate-level, using PODEM. However, if we approach the test pattern generation at the module level, we can discover the redundant faults on the module boundary without the need for backtracking. Consider, for example, the faults on the inputs of the module “greater-than.” In order to propagate these faults to the output, the OR-gate input from module “equal” must be held at 0. All data that we need are stored in the on-set, off-set, and observability-set shown in Fig. 12; we must form the bitwise intersection of the off-set from module “equal” with the observability-set from module “greater-than, ” resulting in the following sets of implicants for line values on a, b , c,

272

- 1 1 0 - 0 0 1 1 - 0 1 1 0 0 -

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 36, NO. 2, MAY 198)

w.r.t. 0, of ”greater than”

and d:

a b c d l

0 1 0 0 1 1 1 0

0 1 - 0 1 0 - 1 1 - 0 -

0 1 0 0 1 1 1 0

w.r.t. Ob of ”greater than”

w.r.t. 0, of ”greater than”

w.r.t. Od of ”greater than”

Implicant n o i -

We can readily see from the above covers that no patterns exist that would set either b to 0 or d to 1 and make them observable; hence faults b sal and d sa0 are redundant. Note also that a test for faults on both a and c can be found readily.

The on-set and off-set covers correspond to ‘‘primitive cubes of the function” as described in [55]. The observability functions are related to the “propagation D-cubes” [55], although we do not need to expand to D-notation and D- calculus. We are thus storing less information than we would with the D-notation; for example, consider an n-input EXOR

module where every input is observable, regardless of the values of other inputs. Once we establish that a fault is observable, i.e., it must have propagated to the module output, we obtain the parity of the fault simply by inspection of the good circuit simulation. Finally, upon expanding all two-level functions into their respective disjoint covers, we can readily evaluate probabilistic controllabilities and observabilities as defined in [56]. These signal probabilities are thus also evaluated hierarchically, first at module/gate level and second at module interior level. The signal probabilities are an important part of heuristic decision making during test pattern generation.

Having established a consistent functional representation common to both gate-level primitives and more complex modules, we next demonstrate a consistent strategy for making decisions at the mixed module/gate-level. When modules are simple gates, the decision making reduces to gate-level without changing the generic module-level procedures.

3) Forward Implication at Module/Gate Level. The current generation of test pattern generation algorithms that have been benchmarked on large circuits are based on simple AND/OR/NOT gates; the SOCRATES algorithm [46] adds an EXOR primitive gate. Common to all approaches is that unique lookup tables or sets of rules are associated with each gate primitive.

Our objective is to have a single generic forward implication procedure that readily accommodates both a simple gate and a complex module. We employ the on-set and off-set from the

Input 0 Signal 1 Value X

* 0 * 0 * * X X *


the forward implication on the output, we perform the set intersection of {Xl l } with the on-set implicants, the intermediate result being X . We continue intersecting with the off-set implicants to find that both off-set intersections are empty. Therefore, output = 1. Note that a gate-level implication would only have given output = X .

The set intersection operations can be implemented very efficiently on the computer and, because the circuit size at the module level is much smaller than the gate level, a CPU improvement is seen. More significantly, in many cases we also achieve an improved implication over what we would obtain at the gate level, as our example showed. In the general case, the module level implication will always produce a result that is equal to or more fully specified than at the gate level.

4: Line Justification at the Module/Gate Level. Just as with forward implication, our goal in line justification is to have a single generic backtrace procedure that readily accommodates both simple gates and complex modules. We describe the extension of the single backtrace procedure used in PODEM; the same principles apply to the multiple backtrace and to backward implication in FAN.

Consider the two-input OR gate of Fig. 4 and its two-level representation. Suppose an objective of out = 1 is to be transferred to an input of the gate. PODEM identifies this as a decision gate and selects the easiest of a or b to justify to 1. Alternatively, we consider the OR as a very simple module and refer to its two-level representation to do the backtrace. To satisfy out = 1 we look at the on-set covers of the module. We see that two covers, { 1 - } and { - l} , satisfy the objective, again indicating that either a = 1 or b = 1 will satisfy the objective. Because more than one cover will satisfy the objective, this is a decision module. We will select the easiest cover to justify. Had our objective been out = 0, PODEM would have identified this as an imply gate, requiring both a = 0 and b = 0 and would have selected the hardest of a or b to justify to 0. Similarly, at the module level we recognize that there is only one off-set cover for the OR module, and it is {OO}; therefore, this is an imply module for out = 0. Because the cover requires justification of both a and b, we select the hardest of a or b to justify.

When considering covers which will satisfy a module output objective, we first intersect the potential covers with the current input signals to rule out those with empty intersections, leaving a list of those covers which had an indeterminate intersection. We now summarize our approach as follows:

1) For an output objective of 1, we intersect the current input signals with the on-set covers to identify covers which will satisfy the output objective.

2) Using our guidance measures, we select the easiest cover to justify.

3) Within the selected cover, we select the hardest input to justify, based on the value required for it by the cover, and continue the backtrace along that signal line.

For an output objective of 0, we do the same except that we deal with the off-set covers. To complete the objective transfer, we establish the new objective value as the signal value required for the chosen input in the chosen cover.

It is important to note that the backtrace procedure is limited to selecting a cover from along the list of prime implicants provided to it. However, a minimal two-level representation does not necessarily contain all primes of the onset and offset. When it does not, we want to optimize backtrace decision making by considering these other prime implicants. For example, consider the MUX module of Fig. 4. Two on-set and two off-set covers suffice for the minimal two-level representation of this function, as used in forward implication. But we recognize that the primes - 11 in the on-set and -00 in the off-set also represent acceptable covers for satisfying output objectives of 1 and 0, respectively. In the event that one of these covers is easier to justify than either of the essential primes listed in the minimal set, we would prefer to make this choice. To exploit opportunities such as these, we augment our minimal two-level representation during backtrace decision making with any additional primes of the function not listed in the minimized sets.

As with forward implication, the additional complexities of the nine-valued calculus within the fault cone are overcome by the split-circuit model. A backtrace operation considers only the good or the faulty machine, but not both. Consequently, the procedure deals exclusively in three-valued calculus and is always conflict-free, yet implicitly accomplishes the same decision making of the nine-valued calculus in [ S I .

We thus have a backtrace procedure which is based on the module-level representation, which embodies the principles of the gate-level algorithm, and which reduces to the same decision making when a module is simply a gate-level primitive.

D. Redundancy Identification and Removal The importance of removing redundant faults to improve

testability while simplifying logic has been recognized for some time [60]. However, the algorithm proposed in [60] occasionally fails to identify some redundancies in the case of reconvergent fan-out. In contrast, redundancy identification based on the test pattern generation process does not have such an intrinsic limitation.

In principle, deterministic test pattern generation, accelerated by a fast fault simulator, will identify many redundancies at reasonable cost. As shown in Fig. 13, we have combined the components of our basic testability and synthesis systems [ 101 into a self-contained prototype that not only removes the redundant faults but also efficiently remaps a simplified netlist into a target technology.

The simple example in Fig. 14 illustrates the transformation that has taken place after applying the single redundancy removal procedure seven times to the circuit that initially contained six redundant stuck-at faults. It should be noted that the process of removing redundancies may create new ones; thus we may not always succeed in removing all redundancies. For the circuit in Fig. 14, we require from five to seven iterations before it becomes irredundant, depending on the choice of the target redundant fault. As a case of immediate practical importance, consider the example of Fig. 3, where redundancy removal techniques were applied to make the hierarchically synthesized n-bit multiplier fully testable.


I

c

Simulation 14-=

I yes I

Single Redundancy Removal

Technology Remapping

Fig. 13. Redundancy removal process.

4 -

xo - Xl - x 2 -

Wt-J 1 ;,;;;marked 1 a re redundant

Redundancy Removal I Process I

U

Fig. 14. Redundancy removal example.

We next outline the basic steps of the redundancy removal procedure. The presence of confirmed single stuck-at redundant faults introduces conditions that are similar to having a constant value, a “0” or a “1,” in the logic circuit. As a

during the netlist audit in order to simplify the existing netlist. The essential steps are summarized below:

1. target line redundant fault list target line value = 0 for stuck-at 0

1 for stuck-at 1 2. remove fanout-free region (FFR) driving

target line 3. if target line value controls the gate it drives

target line = gate output line if gate is inverting

goto step 2

remove this input from the gate if only one input remains

target line value = - (target line value)

else

replace gate with inverter or buffer

v. TESTABILITY OF SYNTHESIZED BENCHMARKS The purpose of this section is to highlight typical results

achieved for logic that has been primarily synthesized automatically. When synthesis takes place from a single prime and irredundant PLA specification, the result is consistently 100 percent testable logic. When a circuit is synthesized hierarchically, redundancies may be introduced. Typically, we identify and remove them as described in the preceding section. On the other hand, our examples show that hierarchical design capture can and does reduce the cost of test pattern generation. All of the CPU costs are quoted for a VAX 8650 under UNIX, unless noted otherwise.

A . A Controller Design with LOGIC-111 The main purpose of this example is to show that in a scan-

based design, the CPU cost of test pattern generation does not dominate the cost of the overall compilation from specification to layout. We choose the example of the CC main controller chip which is part of the Ray Casting machine designed at Duke University [61], [62]. The complete LOGIC-I11 program comprises about 500 lines of code. Following are some characteristics of the controller:

LOGIC-111 lines of code: 500. Inputs: 22. Outputs: 29. Product terms produced by LOGIC-111: 391. Product terms after minimization by espresso with the

single output option: 29 1. Standard cells generated by logic synthesis: 344.

CPU Costs on a VAX 8600.

Input compilation: 18.3 s. Logic minimization: 6.1 s. Logic synthesis: 263.6 s. Test pattern generation: 17.0 s. Standard cell place and route: 781.3 s.

B. Impact of Synthesis on Hierarchical DTPG We examine the impact of synthesis on testability with

respect to two sets of design benchmarks. The first set is - consequence, we can employ techniques similar to ones used derived from [47] as follows: we perform technology map-

BRGLEZ et al.: AUTOMATED SYNTHESIS FOR TESTABILITY

Gate-level I Cell-level

275

Reduction

T A B L E I TECHNOLOGY MAPPING BENEFITS FOR HIERARCHICAL D T P G

I386 I 4166 I 315

Circuit

C432M C880M

C1908M C2670M C3540M C5315M C7552M

ALU4.M chknM rnultl6 max63 1835 I 77 % 1 56 %

IC499 Max63

Max63

C1908M

C2670M

287 474 499 659 959 I468 2177

83 73 29 1

2111

-

- 534 26 - 99.49 - 55 4166 - - 100 - 2300 -~

- 1835 278 - LOO - 582

1060 - - 99.98 - 775 - - 153 907 - LOO - 516 154 - - 99.24 - 36 -

- 105 49 - 9 9 4 3 - 24 363 - - 95.73 - I12 -

927 7100

B

147 162 269 364 577 850 1080 39 38

20 1 1408

- I 218 I 145 11 - I 95.73 I - I 88 C3540M 1) 197 1 - I - 1) 95.79 1 - 1 133 1 -

53 % 220 48 % 837 31 %

C5315M

C7552M

25 % 66% 41 % 24 % 21 % 24 % 35 % 26 % I9 % IO % 23 ?G

- 118 79 - 95.79 - 110 513 - - 98.70 - 189 -

- 426 87 - 98.80 - I23 296 - 98.21 - 413 - -

M ~ l t l 6

t “Cell-level” circuit is C499 with fault collapsing done in inputs to EXOR cells.

- 215 81 98.26 - 294 52 - 47 - - 100

3 100 - 26

- -

- 44 -

ping, using McMap and the MCNC standard cell CMOS library. We then flatten the cell-based netlist back to gate-level for comparison: the results are shown in the top part of Table I. Note that the gate-level data of the circuits in Table I can and do differ in number and types of gates from the original in [47]. The circuits in the bottom part of Table I have different origins: Max63 and mult16 were captured in LOGIC-I11 and synthesized directly to cell level as discussed in the earlier section; circuit chknM originates from the PLA set in [20], and circuit ALU4 is based on the schematic of the familiar four-bit ALU181 from [63]. Interestingly, ALU4 contains four redundant faults when EXOR’S are expanded to gate level; these have been removed to produce ALU4M, which is now 100 percent testable. A single most important characteristic of dual representations of the same circuits in Table I is an average 47 percent reduction in primitives at cell level and an average 29 percent reduction in the size of fault lists at cell level. This in itself should assist in reducing the effort of test pattern generation at cell level, when compared with the traditional gate-level approaches.

Table I1 shows a more objective account of benefits that we gain from performing deterministic test pattern generation hierarchically. The main items in this table are cumulative fault coverages and CPU costs for two circuit representations: gate-level (flat) and cell-level (hier). In addition, the circuits are divided into two groupings, A and B. Circuits in group A have been exercised over their complete fault sets at the gate level and the cell level respectively. The results reported for gate-level circuits are based exclusively on a single step of deterministic test pattern generation, whereas the results reported for cell-level circuits have been generated in three steps: 1) deterministic test pattern generation at cell level until all faults on boundaries of the modules have been covered, 2) flattening the complete circuit to gate level and grading the resulting patterns for coverage of module-interior faults, 3) returning the list of undetected module-interior faults to the hierarchical test pattern generator and resuming the test pattern generation hierarchically as shown in Fig. 11. As shown in part A of Table 11, covering module faults covers most but not all of module-interior faults; however, the number of interior faults that must be covered is relatively low. As a consequence, the total effort (including flattening

TABLE I1 COST AND FAULT COVERAGE BENEFITS OF HIERARCHICAL D T P G

Faultset Size Cumulative Cost Circuit hierarchical Fault Coverage % (CPU sec) Name flat module 1 interior flat 1 hier flat I hier ALU4 287 I - I - 97.91 I - 6.6 I -

837

and the interim fault simulation) of hierarchical test pattern generation is still considerably less than the total effort required at gate level. Most notable gains in group A are for circuits C1355lC499 and Max63.

The results in group B show a more typical application of DTPG in a system environment. In these examples, we consider a relatively smaller subset of the total faults; only those faults that are not covered by a predetermined number of random trials graded by the fault simulator. Both the gate-level and the hierarchical test pattern generator now deal with identical numbers of faults and we no longer resort to grading patterns generated at module level for coverage of the interior module faults. Note that in these examples, the number of interior undetected faults approaches or exceeds the number of module-level faults and yet we still see an average cumulative CPU savings of 31 percent in the hierarchical case. This points out that the cost of module-at-a-time expansion and collapsing as shown in Fig. 11 is negligible relative to gate- level-only test generation. The maximum backtrack limit for results of test generation in Table I1 is 50.

A most unexpected result is with respect to the benchmark circuit Max63. Note that by using the hierarchical test pattern generator to cover all module-level faults and then grading the patterns with the fault simulator for coverage of interior faults we save CPU cost and improve coverage over the gate-level run that starts with grading random patterns using the fault simulator and switches to the gate-level deterministic test generator. We will experience similar results whenever the circuit under test requires an excessive number of random trials to generate a test.

A much smaller circuit with such characteristics is chknM,


TABLE 111 FAULT SIMULATION RESULTS FOR CIRCUIT “chkn”

Fault Simulation 11 DTPG applied 1 F.C. I CPU 11 F.C. I CPU I patterns 1 (%) 1 sec 11 1 s;; 1 15,000 67.9 25.8 25.8 30,000 72.2 44.1 45,000 75.2 61.2 60,000 80.0 76.0 100,000 80.7 96.1

which is another example of a synthesized circuit which is fully testable. It only has 29 inputs, seven outputs, 291 simple gates, and 927 faults; yet it is remarkably resistant to testing with random patterns. Consider the tabulated results in Table 111. This circuit cannot be fully tested even by grading several million uniform random trials. However, it can be fully tested at a relatively low cost by combining both fault simulation and deterministic test pattern generation.

VI. CONCLUSIONS We have presented a framework for automated design that

includes scan-based design for testability. We achieved this objective by partitioning the design process into four major steps: compiler-driven unified structural/functional specification, logic synthesis that maps Boolean specifications into a netlist of standard cells, scan-based test pattern generation, and fully automated standard cell layout. We have shown that routine application of high-level design specification and logic synthesis can significantly reduce the problem of test pattern generation. We have discussed the components of the modular testability system with emphasis on hierarchical test pattern generation and redundancy removal techniques. The set of benchmark results highlights the close coupling of a language- based design specification, logic synthesis, and testability.

Future work includes enhancements to the language-based design capture system, state assignment and minimization as an integral part of the logic synthesis system, and further exploitation of hierarchy in test pattern generation and redundancy removal procedures.

ACKNOWLEDGMENT

H. Abdalla and M. Wong have contributed to the develop- ment of the LOGIC-I1 and LOGIC-I11 language compilers. C. Gloster has been a most helpful user of the system. Some of the early work on testability was initiated as a class project in a design for testability course taught by Prof. T. Nagle and Dr. F. Brglez at North Carolina State University in the Fall of 1986. The fast fault simulator prototype was developed in part by cooperation with Dr. Schulz and Prof. Antreich from the Technical University of Munich.

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