An accurate analytical propagation delay model for high-speed CML bipolar circuits

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. I . JANUARY 1994 31

An Accurate Analytical Propagation Delay Model for High-speed CML Bipolar Circuits

Khaled M. Sharaf, Student Member, IEEE, and Mohamed I. Elmasry, Fellow, IEEE

Abstract- A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-speedhow-voltage- swing silicon and HBT CML circuits operating at medium or high current densities. The model is based on bipolar SPICE parameters file, and can be used to estimate the propagation delay time of CML circuits under different operating conditions. The detailed transient analysis accounts for delay components due to each element in the complete SPICE bipolar transistor model. The comparison to SPICE circuit simulation results show excellent agreement for a wide range of state-of-the-art technologies and circuit parameters. The new model predicts the delay time with less than 5% error in most cases. The influence of the finite slopes (slewing rate) of the input signal and the device dimensions is also investigated. The delay model determined the optimum current io (or load resistor R L ) for a transistor of a certain emitter area when driven by a source of a voltage swing (AI - ) and slew time ( t r ) . At a specified power dissipation, the delay model is used to optimally size the transistor emitter area for maximum switching speed. The model provides circuit and device guidelines to minimize the propagation delay time and improve the performance of high-speed CML circuits.

NOMENCLATURE

Current gain of common-base BJT. Forward, reverse current gain of common-emitter BJT. Average extrinsic base-collector capacitance. Average intrinsic base-collector capacitance. Average collector-substrate capacitance. Load capacitance. Voltage-swing in the CML circuit. BJT collector current in the absence of high-current effects. BJT collector, base, emitter currents. Bias current of the CML circuit. Forward knee current of the BJT. Saturation current of the BJT. SPICE parameter controlling transit-time dependence on current. Normalized majority base charge of BJT. BJT base, collector, emitter resistances. Load, linearized BJT emitter-base junction resistances.

Manuscript received January 8, 1993; revised August 31, 1993. This work was supported in part by the National Science and Engineering Research Council of Canada.

The authors are with the VLSI Research Group, Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ont. N2L 3G 1, Canada.

IEEE Log Number 9214023.

Slew-time of the input ramp. Time instant when the “OFF” BJT starts conduction. Time instant when input reaches 50% of the voltage-swing . Time instant at the end of the input ramp. Time instant when output reaches 50% of the voltage-swing. Time instant when the “ON’ BJT stops conduction. Low-current transit time of the BJT. Delay component due to transit-time/diffusion capacitance. Delay component due to substrate Capacitance. Delay component due to load capacitance. Delay component due to extrinsic base-collector capacitance. Delay component due to intrinsic base-collector Capacitance. Base-emitter, base-collector voltage of the BJT. SPICE parameter controlling transit-time dependence on Vbr. Reverse early voltage. Cut-in voltage of the linearized BJT. SPICE parameter controlling transit-time dependence on i,. Vb,.

Thermal voltage.

I. INTRODUCTION

UMEROUS digital high speed systems and subsystems N are based on CML and ECL circuits. For example, they are widely used in implementing multigigabit-per-second optical fiber transmission systems [ 11. The propagation delay of CML and ECL gates has been extensively used as a performance measure of bipolar and BiCMOS technologies, e.g., to demonstrate the load driving capability and analyze the effects of device scaling [ 2 ] .

Evaluating the delay of CML circuits and optimizing their performance can be simply obtained by running a circuit simulator such as SPICE many times which becomes very time consuming and impractical for large circuits. Moreover, physical insight into the crucial circuit and device parameters affecting gate performance is difficult to achieve when relying purely on circuit simulations. Therefore, an accurate analytical propagation delay model is a key to various optimization tasks

0018-9200/94$04.00 0 1994 IEEE

32 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29. NO. I , JANUARY 1994

at different design phases. Several attempts have been made in the literature to derive analytidclosed form delay expressions for CML bipolar circuits in order to provide an engineering insight into the relative importance of process, device, and circuit parameters [3]-[ 111.

In general, there are two approaches to determine the propagation delay and relate it to its circuit parameters. In the first approach [3]-[7], the delay expressions were developed analytically based on the device modeling equations and the CML circuit elements; RL, CL. Some approximations had to be applied to solve the nonlinear differential equations encountered in bipolar device model and its associated circuit.

In [3], [4] a rigorous analytical study of the transient response of CML and ECL gates under the conditions of low- level injection, unity fan-in, and zero fan-out (in CML case) was presented. The study assumed a step input waveform to predict the switching speed of the circuit which lacks a proper physical basis and tends to fail over a wide range of parameter variations. This failure is attributed to the nonlinear nature of the bipolar switching device which, in turn, causes a continuous dynamic change in the transfer function between input and output during the switching process. This has also been confirmed by simulations that show the dependence of the propagation delay on the slewing rate of the input waveform.

An analytical timing model based on the average branch current analysis and the parametric correction scheme has been developed in [5]. Both input slewing rate and output loading were considered. High-current effects were also considered in a simple form by assuming the transit-time increases linearly with the current. The reported agreements between the predicted analytical delay results and SPICE simulations, shown in [4], [SI, are based on approximate SPICE transistor models used in their delay analyses rather than the exact complete Gummel-Poon SPICE model.

In [7] the delay was calculated according to a definition proposed by Ashar [6] whereby it is tied to a network function reduced into a series of time constants. The network function was derived by adapting a set of linearized charge control equations to describe the bipolar transistor model. The delay expressions obtained by applying this technique to CML and ECL circuits are simple and straightforward. Nevertheless, the error produced by this approximate method should be considered when the performance of CML and ECL circuits of different technologies is compared.

All the models of this approach have assumed the following: 1) simplified bipolar transistor model which neglects the collector resistance T, or folds it into the load resistance, thereby both the collector-substrate and load capacitances are lumped together, 2) lumping both the extrinsic CCJz and intrinsic C,,, base-collector capacitances into one capacitance CJc: 3) decomposing the total base-collector capacitance C,, into two constant Miller capacitances; one at the internal base and the other at the collector. Each of these assumptions has to be examined and compared to the results obtained by using the complete bipolar transistor SPICE model (realistic simulations). In high-speed applications like transmission line drivers, multiplexers, demultiplexers and frequency dividers, the effective load resistance RL is usually chosen to be 50

f l to achieve good impedance matching or to minimize the load capacitance delay [l] . This low load resistance becomes comparable to the collector resistance T, of some state-of-the- art bipolar transistors. This means that T, should be modeled precisely in these relevant situations. Moreover, neglecting the distributed nature of the base-collector junction capacitance CJ, does affect the delay; especially if the circuit is driven by a voltage source of a significant output resistance. Consequently, replacing the lumped C,, with two Miller’s capacitances introduces a remarkable delay error over a wide range of parameter variation.

In the second approach as in [SI-[ll], the propagation delay is expressed as a linear summation of the circuit time- constants, with each time constant being weighted by a factor that was determined empirically from a sensitivity analysis of the circuit. This approach always assumes a chain of identical cascaded cells (i.e., same transistor sizing) to keep the number of time-constants reasonable since it tends to increase drastically in the case of different sizing. This is extremely important in multi-transistor high speed digital circuits (e.g., XOR, D-latch, MS-D-FF); where maximum speed requires individual optimization of both the current and area of each transistor [l], [ 2 ] . Further, this approach does not give enough information about the transient evolution of the output waveform. Therefore, in circuits of different sizing transistors, it does not offer an insight to the interaction process between various device and circuit parameters during the switching interval.

Our delay model, presented in this paper, has been developed according to the following methodology. First, the Gummel-Poon SPICE bipolar transistor model is linearized utilizing the features of CML circuits. Second, all the parasitics of SPICE bipolar transistor model are exactly considered except for the emitter-junction capacitance which can be neglected without remarkable error in the case of CML circuits. Third, the superposition principle is applied to predict the propagation delay. Namely, the contribution of each storing element is studied successively, one at a time then the circuit delay is obtained by summing all the delay components.

High-current effects have also been considered since in most high-speed applications the transistor has to operate at high current density to minimize the overall propagation delay. The model utilizes SPICE transistor parameters to calculate the CML propagation delay under different operating conditions.

The comparison to SPICE circuit simulation results shows excellent agreement for a wide range of circuit parameters. The new model has been used to predict the delay of high speed CML single gate realized in state-of-the-art silicon and AlGaAdGaAs technologies. The new model predicts the propagation delay time with less than 5% error in most cases. The influence of the finite slopes of input waveforms and the device dimensions is also investigated. The new model indicates that if a transistor of an emitter area ( A , ) is driven by a source of a voltage swing (AV) and slewing time ( t r ) , there is an optimal current i o (or load resistor E L ) to achieve a minimum propagation delay. At a specified power dissipation, the delay model is used to optimally size the transistor emitter area for maximum switching speed.

SHARAF AND ELMASRY: ACCURATE ANALYTICAL PROPAGATION DELAY MODEL

~

33

Fig. 1. Circuit diagram of the CML gate.

11. MODEL DERIVATION

A. The Investigated CML Circuit

The CML circuit which has been studied is shown in Fig. 1 under constant loading condition. Differential operation is assumed, which is the typical case in high speed applications. The load resistor RL is related to the dc current of the emitter coupled pair through the output voltage swing AV :

(ai (bi

Fig. 2. junction model.

(a) Linearized bipolar transistor model. (b) Linearized emitter-base

Second, the collector current-controlled current source is assumed to be a single-pole function at a frequency of f~ to account for the transit-time and the diffusion capacitance. Third, all the parasitics of the SPICE bipolar transistor model are precisely considered except for the base-emitter depletion capacitance which can be neglected with an error less than 1% in typical CML circuits. The simplified linear bipolar model is shown in Fig. 2, which is utilized in the subsequent transient analysis to evaluate the propagation delay time of a single CML cell.

111. TRANSIENT ANALYSIS

B. The Linearized Bipolar Transistor Model

The Gummel-Poon SPICE bipolar transistor model [ 121 is still considered the workhorse model for bipolar circuit simulation. It is commonly used by bipolar circuit designers since it is time-efficient and the model parameters are readily available for any technology. Because of the complexity and high nonlinearity of the model, it can be solved numerically with the aid of computer simulators. However, in CML and ECL high speed circuits, both high current and large voltage swing are avoided to gain higher switching speed. This can lead to a simplification in the Gummel-Poon SPICE model without any significant loss in the accuracy of the results achieved. First, the exponential i-v relation of the base emitter junction can be replaced with a linear diode model of a dc- voltage source v d and a bias-dependent diode resistance r d as shown in Fig. 2(b). Both v d and T d are optimized to give minimum mean square error between real exponential and approximate linear i-v relation. It is shown that a best fit occurs when ~d and v d are given by the following relations (see Appendix A).

where

2) T d is the linearized diode resistance. 3) VT is the thermal voltage. 4) io is the CML bias current. 5) v d is the cut-in voltage of linearized transistor model.

1) V b e m a x VT ln(iO/Is).

A. Preliminary

For proper operation of a CML gate, the load resistor, the dc current source and the dc-levels of the input voltage source should be appropriately set-up, The features of the linear bipolar transistor model are readily inspected by referring to Fig. 3, which shows the CML input and output waveforms using both the complete Gummel-Poon bipolar transistor model (SPICE) and our proposed linearized one (MODEL). The waveforms of the internal base and the coupled emitters are shown as well. The propagation delay error E between the two output waveforms, using the above two bipolar transistor models: SPICE and MODEL, stems from the linearization of the bipolar transistor model. However, it will be shown that by a proper superposition scheme, (32), the delay error t can be minimized. Once the CML circuit is linearized, the linear network theory can be directly applied to get analytical expressions for the waveforms at any node. Thus, the propagation delay can be calculated. Since there are five storing elements (capacitors) involving the transient evolution of the output, the characteristic nodal equation will be of the fifth-order which is impossible to solve analytically. Therefore, despite the linearity of the circuit, it is still practically unsolvable.

B. Superposition of Delay Times

The linearity of the delay expression obtained from sensitivity analysis in [8]-[ 111 was the incentive behind applying the superposition principle in our CML delay model. In addition, a sound theoretical formulation was suggested by Ashar [6], who defined the propagation delay of a linear network as the averaged time by which the response of the delta function

34

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IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 29, NO. I , JANUARY 1994

20.011 r

\

Vin2

'b2

Vout2 [MODEL] Vout2 [SPICE]

100 I I

I I 40 I I 4

1 2 3 4 5 6 7 8 Switch C u r r e n t i o ( m a l

CML propagation delay time versus current by different circuit techniques Fig. 4.

input is delayed. The delay formulas can be easily generated and result in a summation of network time constants with appropriate weighting factors. Ashar's method assumes linear

differential equations are involved in calculating the delay. Since there are five distinct storing elements, five separate cases should be independently analyzed to calculate the delay

networks with little or no overshoot, having time constants of the same order of magnitude. A more accurate but detailed and cumbersome technique would demand a complete transient analysis. This is essential especially in linearized CML switching circuits, where the circuit has two linear configurations corresponding to the two states; ON and OFF. By using this procedure, less than 5% error in the CML propagation delay is obtained even if the circuit and device time constants order of magnitudes are different. The delay model has been developed by applying the superposition principle whereby the contribution of each storing element is studied successively, then the circuit delay is obtained by adding the delay components in such a way that offers best accuracy. Using this technique, only first-order linear

in each respective case. In each case, the transient analysis has to be carried out in time segments, wherein transistor operating conditions are the same. A change in the input waveform, or the transistor state, means another time segment. Normally, two or three time segments are needed in each case to evaluate the associated delay. Fig. 4 shows a comparison of the CML propagation delay time, obtained by three different circuit techniques, to that using SPICE, i.e., the complete Gummel-Poon BJT SPICE model. These are:

1) Model, i.e., using our analytical linear model based on superposition of the delay components.

2) Lumped, i.e., modified BJT SPICE model where both extrinsic and intrinsic base-collector capacitances are lumped into one capacitor between internal base and internal collector.

SHARAF AND ELMASRY: ACCURATE ANALYTICAL PROPAGATION DELAY MODEL 35

rc D

(C) (d)

Fig. 5. Equivalent circuit for delay analysis due to (a) transit-time ~f (b) substrate capacitance C,, . (c) Extrinsic base-collector capacitance C , c r . (d) Intrinsic base-collector capacitance C,,, .

3 ) Miller i.e., modified BJT SPICE model where both extrinsic and intrinsic base-collector capacitances are lumped into one capacitor which is split up into two Miller’s input and output capacitors. Each capacitor is twice the original assuming unity gain (i.e., output voltage swing = input voltage swing).

It is clear that the last two models differ substantially from the referenced SPICE results, due to the error associated with the assumptions and approximations made in each one as pointed out in Section I.

C. Delay Analysis

Because of the symmetry of CML circuits, half of the circuit is enough to provide the required delay information. The equivalent circuit of the CML gate is shown in Fig. 5. Four different circuits (a)-(d) are used to calculate the corresponding delay components. These are:

1) t p d C d is the delay due to transit-time/diffusion capaci-

2 ) t p d C J s is the delay to collector-substrate capacitance; 3 ) tpdCJcz is the delay due to extrinsic base-collector

4) t p d C J c t is the delay due to intrinsic base-collector ca-

tance;

capacitance; and

pacitance.

Each of these delay components will be accurately derived based on linear network theory. The derivation of t p d C d and tCJs delay components shows a similarity because there is no coupling between the input and output in the respective equivalent circuits [see Fig. 5(a) and Fig. 5(b)]. The delay component due to the load capacitance defined as t p d C L is similar to that of t p d C J s except for different time constants. On the other hand, the delay components tpdCJ,-- and t p d C J c t

involve coupling between input and output giving rise to ovedundershoot phenomena which affects the delay differently [see Fig. 5(c) and Fig. 5(d)]. All parasitic capacitances CJs. C,,,. and C,,, are voltage-dependent as

where C(0) is the zero-bias capacitance, 4 and m are process- dependent coefficients, and Vr is the magnitude of the reverse bias across the parasitic propagation. These are available in the SPICE parameters file of any technology. For most CML circuits, the low and high logic levels of the input and output are the same so that C,,, and CTCz are reasonably correct if we use their zero-bias values in our delay calculations. On the other hand, C,, is greatly reduced from its zero-bias value when the substrate is reversely biased by the most negative supply voltage (i.e., V,. = VEE). 1 ) Delay Due to Transit-Time/Di#usion Capacitance:

The delay will be calculated while switching from the “OFF’ to the “ON” state. The propagation delay is defined as the time difference between the output and input waveforms when they reach the mid value of the “HIGH” and “LOW’ voltage levels (i.e., -AV/2). Fig. 6(a) shows the waveforms at the differential input, output, and internal base of Q2 during the switching process. The emitter voltage (Vcom) of the coupled emitter transistors is also shown, which is level-shifted by the constant cut-in voltage V d of the linearized base-emitter junction. Assuming an up-going input ramp starts at t = 0. these times will be defined and referred to in the following analyses for the sake of an easy reference:

t l

t 2

t 3

t 4

t 5

time when the “OFF’ transistor starts conduction; time when the input waveform is 50% of the voltage swing; time at the end of the up-going input ramp

time when the output waveform is 50% of the voltage swing; and time when the “ON” transistor stops conduction.

(= f 7 . ) :

Each of t 3 . t 4 . and t j can lead or lag the other two, according to the value of the input waveform slewing rate, transistor parameters, biasing conditions, and/or voltage swing. The propagation delay is given by

36 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. 1, JANUARY 1994

“in2 ‘b2

%Om+

Vout2

I I I I I I 1 I 1 I I I . P q 0 . 0 a . 0 I I . 8 P S l . l P 3 I . O P q I . O P 6 0 . 0 P -

(c) (d)

Fig. 6. capacitance C,,, . (d) Intrinsic base-collector capacitance CJct ..

Simulated waveforms of the CML circuit in presence of only (a) transit-time ~f (b) substrate capacitance CJs. (c) Extrinsic base-collector

Within each time segment, the starting time is taken as a reference. For instance, t , < t < t , ---f ti = t , - t,, for any i = 1 , 2 , 3 , j = 2 ,3 ,4 ,5 .

At tl , the current of transistor Q2 is zero, referring to Fig. 5(a):

(4b) Knz(t1) = Vb2(tl) = VCO, + Vd.

Before the time tl , transistor 4 2 is “OFF.” Therefore, there is no base current flowing into the input circuit. After t l . transistor Q2 starts conduction since Vzn2 exceeds Vb~( t ) , giving rise to base current flow. During the time interval between tl and t j , both Q1 and Q2 are in the “ON’ state. One is conducting more, while the other is conducting less, such that they carry the constant current i o ; a situation similar to any differential pair. This explains the constant unchanging voltage of their emitters in this interval. At t 2 the input Kn( t2 ) = -(AV/2), each transistor carries exactly half the current i o , which leads to an emitter voltage of

= -0.5AV 1 + ~ - V, . (4a) ( ( r d 1 3

Therefore, (4a) gives

From Fig. 6(a), it is evident that

As pointed out earlier, the development of the transient analysis during different time segments depends on the order of the three times t3, t 4 , and t5. The analysis scheme will be as follows:

0 For t > t l (t’ = t - t l ) The input ramp is represented by


where the first term is the initial value of the input during this time segment and the second term represents the linear time varying part. Applying K. V. L. to the input loop yields

Kn2(t’) = i b z ( t ’ ) Q + i e * ( t ’ ) ( T d + r e ) + v d + KO, .

Case 1: ( t s > t3) 0 t 3 < t < t5 ( t” = t - t 3 ) The input loop equation should be resolved again with

ViT22(t) = 0. Initial conditions have to be considered for proper and reliable results. The collector current becomes (6b)

Equating (6a) to (6b) and using (4b) leads to ic2( t”) = ic2(t3) exp (-t”/r’) + O.5AV 1 1

Time til is the time when i c2( t ; )R~ = -0.5AV. Using (8) to substitute for ic2(t3). we get The transistor base and emitter currents are related by

Applying Laplace transforms to solve the linear differential equation of (6c) give

AV ie2(t’) =

( r d f “‘e)tr

where r’ = rf (1 + [ r b / ( r d + re)]). The output voltage will be given as

AVr’RL VoutZ(f’) = - . [t’/r’ + exp (-t’/r’) - 11. (8)

t r ( r d + T P )

The propagation delay is

t p d C d = tl f t i + ty - 0.5tr = 0.5tr + ty. (12)

Case 2: ( t s < t 3 )

In this case, ie*( t ’ ) maintains its maximum value io no matter what the input is. The initial condition for the output voltage calculation is the value of the current ic2(t/j) which is given by the substitution of t/j. obtained from solving (7), in (8). The output will be

O t j < f < t 3 (t” = t - t j )

(13)

This transcendental equation is solved for t i at which L h t 2 ( t ” ) = -AV VOut2(ti) = -AV/2. The propagation delay will be

Then, time ti: becomes t p d C d = t l + ti - 0.5tr.

2ic2 ( t ‘ j ) Equation (8) represents the ramp response of a linear RC

t; = rf 111 ( 2 - 7). (14)

circuit. For t’ >> 7’. the response is always a ramp delayed by r’ but having a slope depending on both the input slewing

delay is simplified to

The propagation is

. (15) rate and the circuit gain. In this special case the propagation t r ( r d + r c )

t p d C d = t , + tk + t(i - 0 . 5 t ~ = tk + ty - 2RL

where Cd = r f / r d represents the diffusion capacitance of the conducting transistor. The delay in this particular condition agrees with that of [6], [7] indicating no dependence on the input slewing rate. However, examining CML circuits using typical parameters of the state-of-the-art high-speed bipolar transistors reveals that the above condition is often violated. This means that the transcendental equation in (8) has to be solved numerically and the input slewing-rate does have an

2) Delay Due to Collector-Substrate Capacitance: The waveforms shown in Fig. 6(b) show that time tl is same

as in ( 5 ) because of similar input loops up to t l . However, time t s always leads t 3 (i.e., t j < t3). Since ic(t) is always following i e ( t ) (a = 1). the internal base voltage Vb(t) will also follow and be equal to the input signal. This means that complete conduction ( i c = i o at t = t j ) has to occur before the end of the input transition ( t = t 3 ) for proper circuit operation.

.t > t l (t’ = t - t l ) The output voltage can be obtained directly as

impact on the delay. So, the delay in general becomes AVRLr, Voutz(t’) = - . (t’/r, + t xp (-t’/rJ) - 1) (16)

where rJ = (BL + rc)CJs. This transcendental equation is

(rd + r e ) t r (9)

t r ( r d + r e )

2RL t p d C d = ti -

solved for f l , when Vout2(tk) = -0.5AV. The propagation delay will be If (8) has no solution, this means that t& or t’j is less than

ti . Time tQ is obtained when i e 2 ( t k ) = L O which means that transistor &I is completely OFF after this time. Two cases arise upon comparing t’j to ti = t , .

t p d C J s = t l + ti - 0.5t, = t i - t r ( T d + r e ) , (17) 2RL

38 IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 29. NO. I , JANUARY 1994

If (16) has no solution, then the next time segment should be Time t:’ is calculated when considered.

.t > t j ( , I / = t - t j )

Solving the circuit gives

Therefore,


’ (20) ( r d + r e )

t p d C , s = tl + t; + f! - 0.5t, = t i + 0.5tr - R L

3) Delay Due to Load Capacitance:

previous one. All needed is to replace r, by T L

This delay calculations in this case is analogous to the

Two delay expressions like those in (17) and (20) are obtained under the same conditions. 4 ) Delay Due to Extrinsic 3ase-Collector Capacitance:

The presence of C,,, results in an overshoot in the output waveform shown in Fig. 6(c) when an up-going signal is applied to the input

.t < tl Transistor Q2 is “OFF” so that the output loop can be solved

directly.

where r, = ( R L + r,) . C,,, .t > tl (t” = t - t l ) Transistor Q2 starts conduction and the output now is

determined by two currents; collector current and current through C,,,. Neglecting the small drop on the base resistance ( i b 2 = 0 ) , i e 2 ( t ) can be written as

Determining the current through C,,, requires the initial value of the drop on CcJz at the start of this time segment. From (6) and (21), we get

Writing KVL from input to output, using (22) and (23), the current i through C,,, is calculated as

AV r, (RL + ~ c ) t r

i ( t ” ) = - [I - f x p (-f1/.,)

+ (1 + ( R L + “I) (1 - cxp ( -f”/r,)) . (24) (rd + r e ) 1


5 ) Delay Due to Intrinsic Base-Collector Capacitance: Overshoot calculation, when Transistor Q2 is OFF ( t < t l ) . needs to be calculated as an initial value for the next time segment, when Q2 switches to the ON state ( t > t l ) . as shown in Fig. 6(d).

.t < t l The transistor Q2 is OFF and the current through C,,, can

be obtained by solving the KVL from input to output loop. This gives

where R, = 7’b + T, + RL and rt = RtCJct. Transistor Q2 switches to the ON state at f l . when

V b 2 ( f ) = Kn(f) - (h( t ) = Vo, + Vd.

From (4a), (4b) and (27). If t > 3 or 4 times rt which is often a valid assumption in most cases, then

Note that t l given by (28) is different from the one used in other cases due to the presence of a significant voltage drop across Tb by the capacitor current i(t).

.t > tl ( , I r = t - t l ) Applying KCL to the two internal nodes of the circuit;

namely the internal base and the internal collector the expression for the output can be obtained as

where r, = (RL + r,)CJr,: therefore,



25

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5 15,;

2 0" 1 0 -

~

39

L e-.. - - -

0. - - - * _ _ - - ~

- - pd Cd

'i -

- _ _ - - I .

tpdCl pdCjc i

.-..-....--------- ............................................................................................................ 0 0 0 0 0

0 0

30 I

.:...r..dCj.s2.. .... ........ & ........ -.-... .

....... P ...............t.....------.---.--.-. pdCjcx

5 -

bCd Calculation of tpdCjs bCr Calculation of

41149). Eqn.(l2). or Eqn.(l5) E ~ ( l 7 ) Or EW(2O)

0 ' I 4 0 50 60 70 80 90 100 110 12C

Slew-time tr Ips)

(a)

Calculauon of bdCjcrr pdCjc.

Eqn.(26) and Eqn.(31)

50 . -5

,a , t ; pdCd

0

, . 6

- r o - SPICE1 1: MODEL

1

1 2 3 4 5 6 7 8 Switch Current 10 lml

(b)

Fig. 7. c u r r e n t I [ ) . .

CML delay c o m p o n e n t s versus (a) i n p u t s l e w - t i m e t , (b) s w i t c h

The delay can be rewritten as

which represent Miller's input and output equivalent capacitances, respectively. This means that Miller's principle can only be applied to the intrinsic part of the base-collector capacitance to calculate its associated delay component. On the other hand, the delay component associated with the extrinsic base-collector capacitance t p d C J c s in (26) is much smaller; since no Miller's action takes place. This explains the significant error in the delay models which combine the two capacitances and then apply Miller's principle in calculating the delay (see Fig. 4).

Fig. 7 compares the delay components, predicted by the developed model, as a function of the slew time ( t r ) and switch current (io). to SPICE simulation result for each case.

If, Pf 3 Ikf. 'If * Yf * l,f

i or RL , C L , A V s lr , Yr-area

I I

I I

This emphasizes the dependence of the first delay component t p d c C l on the input slew time and its dominant effect with respect to other delay components on this specific technology. Moreover, it verifies the accuracy of the derived delay component expressions.

Finally, the overall propagation delay time of a single CML cell, driven by an input signal, having a finite slewing rate is given by

In (32), the delay components are not superposed linearly since it was noticed that a constant delay error of 10-20% would happen. Therefore, the superposition expression in (32) is used in order to minimize this error. The vector magnitude (root- sum-of-squares) of t p d C d and f p d C J c i delay components results in a well agreement with the SPICE simulations. Among the five delay components, these are the only two which involve a significant input current through Q during the switching process. This is shown in Fig. 6(a) and Fig. 6(b) where the intemal base potential is different from the input ramp by the voltage drop 61.b on the base resistance. The implication of this on the linearized diode of Fig. 2 can be observed by looking at LTbC,( t ) = ~l(t)-V,,,,, in these two cases compared to the other cases. After t l . where Ijb, = V,. Vb, increasing nonlinearly as the input rises in the first two cases while it always increases linearly with time in the others. In other words, t p d C d and tpdCJc, delay components depend on both the input ( ~ b ) and output circuit parameters (RL . r r . rcl,rc). while the other delay components; t p d C j s . t p d C l . t p d ~ 3 c . r . involve only the output circuit parameters. This is why the first two delay components in (32) are combined differently than the rest. Moreover, in the case of a single CML circuit loaded by a fixed capacitance the slewing rates of the input and output are generally not the same unlike that in the case of cascaded CML circuits, e.g., ring oscillators, flip-flops where the output of one circuit is the input of the next; thus both slew at the same rate. The delay model has been implemented as a set of mathematical expressions according to the flowchart shown in Fig. 8.


I v . HIGH-CURRENT EFFECTS

In high-speed CML circuits, bipolar transistors operate at high collector-current densities to minimize the delay through the circuit [l]. As the transit-time is one of the most significant parameters characterizing the high-frequency properties ( f ~ -

2, curve) in bipolar transistors, a precise description of this parameter, at high-collector current densities j,. is crucial. At high current densities, high-current effects such as base push- out, lateral spreading, space-charge-limited current flow, and quasi-saturation increase the transit-time and hence decrease f~ . The transit-time deterioration in the high-current region depends on physical device parameters, geometry, collector current, and base-collector voltage. High-current effects are modeled in SPICE [12] by an empirical expression as

7 f (high-current)

= 7 j (1 + x*j exp (") 1.44V j (Ay) I,, + It j (33)

where X t f , Vtj. and I t j are SPICE fitting parameters controlling the total fall-off of f ~ . the change in f T with respect to base-collector voltage vb,. and the change in , f ~ with respect to current. I,, is the collector terminal current in the absence of the high-current effects which corresponds to that of Ebers-Moll model [12]. Despite its empirical nature, (33) can describe the high-current effects with good accuracy if optimizing schemes are used to extract high-current fitting parameters. This is quite feasible if operation is to be expected near the onset of high-current region which is the case in typical high-speed CML circuits. In CML circuits, I,, is related to the collector current 2, by (see Appendix B)

I k f is the forward knee current modeling the onset of the current gain 0 roll-off due to high-current effects. It is important to distinguish between I,, and i , before using (33) in the delay model. Fig. 9 plots the transit-time obtained from (33) versus i, using (34) for different transistor areas. On the same graph, the transit-time is calculated if i , and I,, are assumed equal. This illustrates the large error between the two cases which makes this assumption generally invalid. In addition, high-current effects start impacting the transit-time at current values earlier than I k f . This means that neglecting these effects based on operating at current levels below I k j is unreliable. However, in [14] and [15], no discussion between i , and I,,, has been mentioned in the delay analysis of high- speed BiCMOS circuits operating at high currents. It has also been found that estimating I k j by simple multiplication of the maximum current density and the emitter area is subject to error due to lateral electrons injection in the base region (lateral base-widening). The high-current effects are generally two- dimensional which are strongly dependent on the technology and the device structure. These remarks suggest that the inclusion of the high-current effects may become inevitable if accurate modeling is sought.

5 0 1 1

10

5 1 I I 0 2 4 6 8 10 1 2 14

COlleCtOr C"rre"t IC lml

Fig. 9. real ( i , # I,., ).

Transit-time versus current for two cases; approximate ( z c = Ice).

TABLE I DEVICE PARAMETERS

Parameter Unit BiCMOS Plessey HBT [I71 HBT 1181

Emitter pni X pm 0.8 x 8 1 x .j 2 x 5 2.5 x 4.5 Area

l'b !! I70 1 50 80 50 I', !! 60 15 36 42 I', ( 2 10 10 30 1.7 c,,, fF 28 13.8 0 0 c,, I fF 10 3.2 8.5 8.5 c, . fF 60 30 0 0 c, fF 100 100 100 100 Ii mA 10 I , J

,\-,J 7.50 - - -

t , Ps 50 50 30 20

[I61

T f ps 12 7.23 3.54 2

- - -

- - - mA 160 I;, V 2.5 - - -

In CML circuits, high-current effects impact the propagation delay through the heavily conducting ON-transistor (Q1 in Fig. 1 ) of the current switch. During the switching event, the current of this transistor changes from its maximum value io before switching to 0.520 at time t l where propagation delay is calculated [see Fig. 5(a), Fig. 6(a)]. Note that Vb is also time- dependent changing from AV before switching to -0.5AV at time t 4 . Therefore, according to (33) the transit-time becomes time-dependent and nonlinear differential equations arise in the delay calculations 1131. The situation is simplified by using an average value for the transit-time in the high-current region. The study showed that in typical CML circuits with low- voltage swing the average occurs when i, is about 0.8-0.920 and Vb, is zero. This is different from the case of ECL circuits where the magnitude of vbc is at least one diode drop because of the level-shifting done by the emitter-followers.

v. SPICE VERIFICATION AND MODEL APPLICATION TO CML CIRCUIT OPTIMIZATION

CML delay models are usually verified by SPICE simulations based on an approximate bipolar transistor model consistent with the respective model used in developing the CML delay expression. In other words, the reference bipolar


SPICE KODEL

8 1 4 5 t

J 50 60 70 80 90 100 110 120

40 ' Input Slew Time tr (pa)

4 0 50 5 0 7 60 10 80 90 100 110 120 130

Input slew Time tr Ips)

Fig. 10. (h) with high-current effects.

CML propagation delay time versus input slew-time t , at 10 = 1.2 .4 mA, Tr. area = 1 x 0.8 {rm x 8pm (a) without high-current effects;

loo 3 I \ \ "---I Lo 1

40 ' ' I 1 2 3 4 5 6 7 B

Svitch Current io la)

100 , *

7 4

7 0 8oL\\ J 1 1 2 3 4 5 6 7

switch Current i o ImAl

4 0 *

Fig. 11. CML propagation delay time versus current with high-current effects.

at t , = 50 ps, Tr. area = 1 , 2, 3 x 0.8 p m x 8 p m (a) without high-current effects; (b)

transistor model is not the complete Gummel-Poon SPICE model but it may be modified, as was explained in Section 11. Verifying CML delay models by this way is unreliable since it does not reflect a realistic comparison between the actual waveforms. The verification carried out for our delay model is based on the results of SPICE simulations using the complete built-in bipolar Gummel-Poon transistor model. The model has been tested in two cases: 1) without high-current effects and 2) with high-current effects. The electrical parameters used for calculating the delay are based on a generic 0.8 pm BiCMOS process and are listed in Table I.

The dependence of the total delay, predicted by the model on the input slew time, is illustrated in Fig. 10 for various collector currents. The load is assumed to be 100 fF, representing a fixed static capacitance. The graphs show the impact of the input slew-time on the circuit delay arising from the transistor

' diffusion capacitance. The CML propagation delay is strongly dependent on the switch current-source io. This is obvious in Fig. 11, where the delay versus current is calculated for different transistor areas. Whenever the transistor emitter area is recalled, it is assumed the emitter width is always kept at its minimum value which is the technological limit of the process (i.e., 0.8 pm for the given BiCMOS process). Therefore, an area of 1, 2 , 3 refers to 0.8 x 8, 0.8 x 16, and 0.8 x 24 pm *, respectively. In other words, it is the emitter length that is increased or reduced to change the transistor emitter area while keeping the minimum emitter with constant. The delay increases dramatically with the current for small area transistors as shown in Fig. I l(b) due to high-current effects. The delay behavior in Fig. 11 indicates that for a certain transistor area, there is an optimum current value at which the CML gate switching speed is maximum. This is a local

42 IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 29, NO. 1. JANUARY 1994

100

90

,

- MODEL ~ - 4 A S P I C E I

1 X J

z1

p 6 0 n e 6 5 0

m

a

I 0.6 0.8 1 1.2 1.4 1.6 1.9 2 2 2 2 . 4

Transistor area

4 0 '

180

- 160 a

2 140

- w - MODEL

E" e 9 : 6 100

0 8 BO

' 60 0.6 0 8 1 1.2 1 . 4 1.6 1 . 8 2 2 . 2 2 . 4

40

Tranris:ar area

(a) (b)

Fig. 12. CML propagation delay time versus Tr. area x 0.8 Iim x 8 pm at t o = 14 mA, 1 , = ,50 ps (a) without high-current effects; (b) with high-current effects.

Switching Switching speed

0.5

( d l (a) (b)

Fig. 13. CML switching speed (l/delay) versus current and Tr. area. (a) Without high-current effects; (b) with high-current effects.

minimum delay at a certain transistor area since the delay is area-dependent too.

Fig. 12 shows the delay as a function of the transistor emitter area at different values of current. The design space can then be represented in a three-dimensional plane to demonstrate the delay in a CML cell as a function of current and transistor emitter area. Both Fig. 1 1 and Fig. 12 are combined and plotted on a 3-D graph as shown in Fig. 13 to gain insight into the effect of the transistor emitter area and current together on the CML switching speed. The delay versus load capacitance is shown in Fig. 14 which indicates the linear increase in the CML delay with the load. The load sensitivity improves by operating at large currents. However, the degradation due to high-current effects should be considered if the circuit is designed to function under a specific loading margin. The model has been applied to a number of current technologies of silicon bipolar and GaAs HBT's. Fig. 15 displays the CML propagation delay for different technologies as a function of the current. The SPICE parameters of three other technologies are also listed in Table I which represent state;of-the-art silicon and HBT device parameters. The results of the model agree very well with that obtained from SPICE simulations under moderate loading conditions and low-voltage swing

(AV = 200 mV) which are typical conditions in high-speed applicztions; ring oscillators and frequency dividers. Note that different slew times are used to account for the difference in the inherent speed of the compared devices under the same loading conditions. It is clear from the comparison given in Fig. 15(a) that in silicon bipolar CML circuits, both the current and area interact nonmonotonically giving rise to a unique design point for minimum CML propagation delay. The situation is different in HBT CML circuits, where the CML delay tends to decrease almost monotonically by increasing the current for different transistor areas. Thus, high-speed HBT CML circuits generally operate at high currents [2]. The CML delay versus the current density of the four compared candidates is shown in Fig. 15(b) for devices of minimum emitter area corresponding to that of Table I. The HBT CML circuits are much faster; the delay is about one quarter that of silicon BJT (i.e., within the four process examples exhibited for our delay model verification). However, this comes at the expense of the process complexity, yield and cost considerations involved in HBT fabrication. On the other hand, silicon CML circuits utilize a low-cost mature process in addition to the availability of supporting high density CMOS and BiCMOS circuits on the same chip.


0

2 0 0

- a - ‘oa 150

E c > 4 U 100

c 0

01 x

5

H 53 J

I

1 - MODEL 0 SPICE

2 0 3

-s 150 C

- MODEL o S P I C E - MODEL o S P I C E

8 -s 150 - C

E

t (Y 1 0 0 -

8 x H 5 0 -

43

) O

Fig. 14. effects; (b) with high-current effects.

CML propagation delay versus load capacitance at Tr. area = 1 x 0.8 p m x 8 pm, t,- = 50 ps, i o = 1 . 2 . 1 mA (a) without high-current

2 J 4 1 E sw1tct. i u r r e r . r 13 lm;l

BiCMOS 0 0

1 current Density (m&/um^21

0.1

(a) (b)

Fig. 15. current density for the different technologies.

(a) CML propagation delay time versus current for different technologies and different emitter areas. (b) CML propagation delay time versus

VI. MODEL LIMITATIONS

The discrepancy between the delay results obtained by the proposed model and SPICE simulation based on Gum- mel-Poon complete bipolar transistor model, can be attributed to two fundamental factors. First, the delay model is based on a linearized bipolar transistor model which causes a finite error proportional to the voltage swing AV. This means that operating at low-voltage swings (200-300 mV single-ended or 400-600 mV differential) yields the best accuracy of the delay model. Fig. 16 shows the delay versus the current for different voltage swings. In the high current region, quasi- saturation starts degrading the delay with the increase of the voltage-swing due to the voltage drop on t , as shown in Fig. 16(a). Our delay model does not account for quasi- saturation since it is commonly avoided in typical high-speed CML circuits. However, the minimum delay point is always

within the coincident region which does emphasize the model accuracy in the parameter range of interest. Investigating the delay beyond that region is less important, since it increases sharply due to high-current effects. Second, the superposition technique may introduce additional error in the delay of CML circuits when exceeding the valid range of parameter variation. As a matter of fact, the delay model gives reliable results when the input slew time t , corresponds to the actual slew time present in CML circuits of fan-out 1 to 3.

It should be noted that the presented delay model is valid only for CML circuits loaded by a fixed static load (i.e., Fan-out = 0) and driven by a low output resistance voltage source. These are typical conditions for loads, as CMOS gates in BiCMOS environment or laser diodes in optical-fiber transmitters where the CML circuit is driven by an emitter- follower stage having a low output resistance. However,


120 , 120 . I

iin - MODEL 110 - MODEL - - *

- - i] SPICE 1 a SPICE [

I 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

Switch Current io IuAI

4 0 ' switch Current 10 ImAl

(a) (b)

Fig. 16. CML propagation delay time versus current for different voltage-swing 11. = 200.300.400 mV (a) without high-current effects; (b) . . . high-current effects.

the case of dynamic loads (i.e., fan-out > 0) and finite driver output resistance is discussed elsewhere [ 191 along with ECL circuit optimization. It should be emphasized that approximating dynamic loading conditions by static ones may be an erroneous technique due to the nonlinearity associated with the input stage of the CML switching circuit. This is different when a buffering stage is inserted between cascaded circuits as in the case of ECL, where the emitter-follower improves fan-out capability, thus static and dynamic loading conditions could be slightly different.

VII. CONCLUSION

An accurate CML propagation delay analysis has been carried out by accounting for all the important parasitics in SPICE bipolar transistor model. High-current effects are also included in the study. The model is based on bipolar SPICE parameters file and can be applied to high-speed silicon and HBT CML circuits. A linearization scheme has been adapted to predict the different delay components from simple transient analyses that consider the slew-time of the input signal. The comparison to SPICE circuit simulation results shows good agreement for a wide range of state-of-the- art technologies and circuit parameters. The model provides insight into the behavior of CML circuits and physical intuitive expressions for the delay. Further, it can be used to optimize the transistor current and area for maximum switching speed at certain operating conditions; input slew-rate, load capacitance, and maximum power dissipation. Thus, the model offers device and circuit guidelines to improve the CML circuit performance.

APPENDIX A

During the switching interval in the CML circuit the current has to increase or decrease all the way from its maximum value i o to approximately zero current value or vice versa. This is also true for the base-emitter dynamic diode resistance where it changes from a minimum value of VT/ZO to a maximum

with

value of thousands of ohms. We can define two regions within each one, the circuit will be linearized as follows:

Both 7'd and V , are evaluated when the square of the error d shown in Fig. 2(b) is minimum. This can be written as

The integration of (A2) is minimum when ( d d 2 ) / d V d = 0 which leads to (2a) and (2b).

APPENDIX B

According to the Gummel-Poon SPICE bipolar model [12], the collector current in the normal active region is defined as

Zc = ' ["p ( V b e / v T ) + qb /PR] . (B1) q b

In CML circuits, Vb, > 700 mV so the second term is dropped, giving

where

which represents the normalized majority base charge under the above conditions. Solving (B2) and (B4), then Icc can be expressed in terms of i,, written as (34). V b e / V ~ = 0.8(V)/5(V) which is a typical value in most high-speed bipolar transistors.


REFERENCES

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[ 3 ] J. M. Stork, “Bipolar transistor scaling for minimum switching delay and energy dissipation,” IEDM Tech. Dig., pp. 550-553, 1988.

[4] M. Y. Ghannam er al., “An analytical model for the determination of the transient response of CML and ECL gates,” IEEE Trans. Electron Devices, vol. 37, pp. 191-201, Jan. 1990.

[51 A. T. Yang and Y. Chang, “Physical timing modeling for bipolar VLSI,” IEEE J. Solid-State Circuits, vol. 27, pp. 1245-1254, Sept. 1992.

[6] K. G. Ashar, “The method of estimating delay in switching circuits and the figure of merit of a switching transistor,” IEEE Trans. Electron Devices, vol. ED-I 1, pp. 497-506, Nov. 1964.

[7] P. K. Tien, “Propagation delay in high speed silicon bipolar and GaAs HBT digital circuits,” Inr. J . High SpeedElectronics, vol. 1 , pp. 101-124, 1990.

[8] D. D. Tang and P. M. Solomon, “Bipolar transistor design for optimized power-delay logic circuits,” IEEE J. Solid-State Circuits, vol. SC- 14, pp. 679-684, Aug. 1979.

[9] E. F. Chor et al., “A propagation-delay expression and its application to the optimization of polysilicon emitter ECL processes,” IEEE J . Solid-State Circuits, vol. SC-23, pp. 251-259, Feb. 1988.

[IO] W. Fang et al., “Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits,” IEEE J. Solid-State Circuits, vol. SC-25, pp. 572-583, Apr. 1990.

[ I I ] W. Fang et al., “An analytical maximum toggle frequency expression and its application to optimizing high-speed ECL frequency dividers.” IEEE J . Solid-State Circuits, vol. 25, pp. 92e-930, Aug. 1990.

[ 121 P. Antognetti and G. Massobrio, Semiconductor Device Modeling with SPICE. New York: McGraw-Hill, 1988.

[ 131 K. M. Sharaf, “Studies on the propagation delay time of high-speed CMLECL bipolar circuit structures,” Univ. Waterloo, Waterloo, Ont., Canada, Internal Rep., 1992.

[I41 P. A. Raje et al., “Accurate delay models for digital BiCMOS,” IEEE Trans. Electron Devices, vol. 39, pp. 1456-1464, June 1992.

[ 151 W. Fang et al., “An accurate analytical BiCMOS delay expression and its application to optimizing high-speed BiCMOS circuits,” IEEE J . Solid-State Circuits. vol. 27, pp. 191-202, Feb. 1992.

[I61 S. Duncan etal., , “A I-jrm trench isolated high speed bipolar transistor,” presented at the VLSI Symp., San Diego, CA, 1988.

[ 171 T. Ishibashi et al., “High-speed frequency dividers using self-aligned AIGaAs/GaAs heterojunction bipolar transistors,” IEEE Electron Device Lett., vol. EDL-8, pp. 194-196, 1987.

[I81 Y. Yamauchi etal., “22 GHz 114 frequency divider using AICaAsEaAs HBTs,” Electron. Lett., vol. 23, pp. 881-882, 1987.

1191 K. M. Sharaf and M. I . Elmasry, “On the optimization of high-speed CML and ECL bipolar circuit structures,” IEEE J. Comput.-Aided Design, to be submitted.

Khaled M. Sharaf was born in Ismailia, Egypt, on February 22, 1962 He received the B Sc and M.Sc. degrees in electrical engineering from Ain- Shams University, Cairo, Egypt, in 1984 and 1989, respectively His research was involved in the effect of electronic feedback on semiconductor lasers and optical histability

Since 1990, he has been working ds a Research Assistant at the University of Waterloo, Ontario, Canada, toward the Ph.D degree His current in- terests include the design and optimization of high-

performance BiCMOS circuits to be used in optical fiber transmission systems

Mohamed I. Elmasry was born in Cairo, Egypt, on December 24, 1943. He received the B.Sc. degree from Cairo University, Cairo, Egypt, and the M.A.Sc. and Ph.D. degrees from the University of Ottawa, Ottawa, Ontario, Canada, all in electrical engineering in 1965, 1970, and 1974, respectively.

He has worked in the area of digital integrated circuits and system design for the last 27 years. He worked for Cairo University from 1965 to 1968 and for Bell-Northem Research, Ottawa, from 1972 to 1974. He has been with the Department of Electrical

and Computer Engineering, University of Waterloo, Waterloo, Ontario, since 1974, where he is a Professor and founding Director of the VLSI Research Group. He has a cross appointment with the Department of Computer Science where he is a Professor. He holds the NSERCBNR Research Chair in VLSI design at the same University since 1986. He has served as a consultant to research laboratories in Canada and the United States, including AT&T Bell Labs, GE, CDC, Ford Microelectronics, Linear Technology, Xerox and BNR, in the area of LSWLSI digital circuithbsystem design. During sabbatical leaves from Waterloo he was at the Micro Components Organization, Bur- roughs Corporation (Unisys), San Diego, CA, Kuwait University, Kuwait, and Swiss Federal Institute of Technology, Lausanne, Switzerland. He has authored and coauthored over 200 papers on integrated circuit design and design automation. He has several patents to his credit. He is editor of the IEEE Press books, Digital MOS Integrated Circuits, 1981 ; Digital V U 1 Systems, 1985; Digital MOS Integrated Circuits 11, 1991; and Analysis and Design of BiCMOS Integrated Circuits, 1994. He is also author of the book Digifal Bipolar Integrated Circuits (Wiley, 1983) and a coauthor of the books Digital BiCMOS Integrated Circuits (Kluwer, 1992), Optimal VLSI Architectural Synthesis (Kluwer, 1992), and VLSI Artificial Neural Networks Engineering (Kluwer, 1994).

Dr. Elmasry has served in many professional organizations in different positions, including the Chairmanship of the Technical Advisory Committee of the Canadian Microelectronics Corporation. He is a founding member of the Canadian Conference on VLSI, the International Conference on Microelectronics, and the founding president of Pic0 Electronics Inc. He is a member of the Association of Professional Engineers of Ontario and is a Fellow of the IEEE for his “contributions to digital integrated circuits.”

An accurate analytical propagation delay model for high-speed CML bipolar circuits

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