1

Abstract—In this paper, we propose an approach to

generate high-level test patterns from the arithmetic model

of an RTL circuit using a hybrid canonical data structure

based on a decision diagram. High-level simplified and fast

symbolic path activation strategy as well as input

justification is combined with test pattern generation for

circuits under consideration. The current approach has

been implemented for a range of small to large benchmark

circuits. The results clearly demonstrate that tests

generated using the proposed method have achieved high

fault coverage for known sequential circuit benchmarks in

very short CPU time and minimum memory usage.

Index Terms— Automatic Testing, Canonical

Representation, Test Pattern Generation, RTL Circuits.

I. INTRODUCTION

IGH fault coverage achievement has traditionally

been the main objective of the test development

techniques. As these techniques have matured and this

objective has been attained, other objectives have

become important. Decreasing test generation and

application time as well as test data volume are among

other such objectives being pursued. Although, design

flow is moving toward higher levels of abstraction,

automatic test pattern generation (ATPG) and also

design-for-testability (DFT) tools are based on gate-

level techniques. The use of DFT features, such as scan

and built-in-self-test, further exacerbates the problem.

In order to improve this problem, several ATPG

approaches have been proposed for detecting functional

faults. It is shown test generation is non-polynomial

(NP-complete) [1]. However, observations show that

the test generation complexity of practically encountered

combinational circuits is polynomial [2]. Also, different

techniques for solving the problem of generating tests

for functional faults have been proposed.

For simplification of test procedure some ATPG

approaches have been introduced based on Binary

Decision Diagram (BDD) tools [3]. Since these methods

require the design to be flattened into the bit level, they

cannot be used to deal with large industrial benchmarks

efficiently, either in terms of memory or run time.

Evolutionary algorithmic methods used in [4-6] are

better than the fully random-based method used in state-

of-the-art ATPG approaches. However, they are not

very robust methods for generation of test vectors to

achieve highest coverage. Although these methods can

get good coverage in small and medium designs, their

random nature made these methods so poor in large

circuits where the number of inputs and registers and

flipflops increases drastically.

In [7, 8] we proposed a method based on a hybrid

Boolean-word level canonical representation named

Horner Expansion Diagram (HED) [9] to alleviate the

above mentioned problems by generating high level test

vectors for combinational data paths and control parts.

In this paper, we show our polynomial based

approach in order to demonstrate robustness of this

method for applying it to register-transfer-level (RTL)

circuits as an automatic modeling and test generation

methodology. As illustrated in Fig. 1, we obtain a Finite

State Machine with Datapath (FSMD) model [10] from

the RTL code which helps us to extract the transition

and output polynomial functions (Section III). A fault

model at the behavioral level of abstraction is defined.

Following the proposed polynomial model, a process

that is similar to the time frame expansion is presented

which facilitates handling of fault propagation as well as

justification phases to generate test patterns at a higher

level of abstraction (Section IV). Finally, by considering

generated high-level test patterns as constraints and

passing them to a SMT-solver we are able to

automatically and efficiently generate gate-level test

patterns. Then a commercial gate-level fault simulator is

used to estimate gate-level fault coverage. Experimental

results show robustness and reliability of our method

compared to other approaches in terms of gate-level

fault coverage percentage and CPU time.

The rest of this paper is organized as follows. In

Section II, canonical data structure named Horner

Expansion Diagram is introduced to represent

polynomials in test generation process. Following the

A New Approach for Automatic Test Pattern

Generation in Register Transfer Level Circuits

Mohammad Mirzaei*, Mahmoud Tabandeh*, Bijan Alizadeh**, Zainalabedin Navabi**

M. Mirzaei and M. Tabandeh are with the Department of Electrical Engineering, Sharif University of Technology, Tehran, Iran

(E-mail: mohammadmirzaei@ee.sharif.edu; tabandeh@sharif.edu).

** B. Alizadeh and Z. Navabi are with the Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran

(E-mail: alizadeh@cad.ut.ac.ir; navabi@cad.ut.ac.ir).

H

2

proposed representation structure, we present a method

of obtaining set of polynomials to make a formal model

of an RTL circuit to extract the transition and output

polynomial functions in Section III. High-level test

pattern generation approach and conversion of patterns

to gate-level ones is demonstrated in Section IV in order

to estimate gate-level fault coverage. Experimental setup

and results and a brief conclusion are given in Sections

V and VI, respectively.

Fault Injection

Propagation/

Justification

SMT-Solver

Polynomial

Extraction

HED

Representation

High-level Test

Genration

Gate-level Test

Pattern

FSMD

Extrraction

Gate-level

NetlistRTL Description

Fault Simulator

Fig. 1 RTL automatic modeling and test generation methodology

II. HYBRID CANONICAL REPRESENTATION

In this section we introduce our graph-based

representation structure called HED [9] for functions

with a mixed Boolean and integer domain to integer

range for representing arithmetic operations at a high

level of abstraction. In HED, functions to be represented

are maintained as a single ordered, normalized and

reduced graph in strongly canonical form.

HED is a binary graph-based representation which

supports polynomial function by factorizing higher

orders of Taylor series expansion recursively as shown

in (1), where const is independent of variable X, while

linear is coefficient of variable X.

F(X,…)=F(X=0,…)+X×[F’(X=0,…)+…]=const+X×linear (1)

Definition 1: HED is a directed acyclic graph

G = (VR, ED) with vertex set VR and edge set ED.

While the vertex set VR consists of two types of

vertices: Constant (C) and Variable (V). The edge set

only indicates integer values as weight attribute. A

Constant node v has as its attribute a value val(v)Z. A

Variable node v has as attributes a variable var(v) and

two children const(v) and linear(v){V,C}.

According to the above definition, a vertex v in the

HED denotes an integer function fv that has been defined

recursively as follows:

1) If vC (is a Constant node), then fv=val(v).

2) If vV (is a Variable node), then fv=const(v)+

val(v)×linear(v).

To normalize the weights, any common factor is

extracted by taking the greatest common divisor (GCD)

of the argument weights. In addition, we adopt the

convention that the sign of the extracted weight matches

that of the const part. This assumes that GCD always

returns a nonnegative value. As long as all vertices are

created, the graph will remain in canonical form.

Example 1: Fig. 2 illustrates how f(X,Y,Z)=24-8×Z+

12×Y×Z-6×X2-6×X2×Z is represented by HED.

Let the ordering of variables be X>Y>Z. First, the

decomposition with respect to variable X is taken into

account. As shown in Fig. 2(a), after rewriting f(X,Y,Z)

based on (1), const and linear parts will be (24–8×Z+

12×Y×Z) and (-6×X–6×X×Z). The linear part is

decomposed with respect to variable X again due to X2

term. After that, the decomposition is performed with

respect to variable Y. By rewriting 24–8×Z+12×Y×Z=

(24–8×Z)+Y×(12×Z), it can be determined that the

const and linear parts of the left hand side Y node in Fig.

2(b) are 24–8×Z and 12×Z. Finally, the expressions are

decomposed with respect to variable Z and a reduced

diagram is obtained. To reduce the size of an HED,

redundant nodes are removed and isomorphic sub-

graphs are merged. For this purpose, the GCD of the

argument weights are taken to figure out isomorphic

subgraphs as well as redundant nodes. In Fig. 2(b),

24−8×Z, 12×Z, and −6−6×Z are rewritten by

8×[3+Z×(−1)], 12×[0+Z×(1)], and −6×[1+Z×(1)]. In

order to normalize the weights, GCD(8, 12) = 4 and

GCD(0,−6) = +6 are taken to extract common factors.

Finally, Fig. 2(c) shows the normalized graph where

GCD(4,−6) = 2 is taken to extract common factor

between outgoing edges from X node. In this

representation, dashed and solid lines indicate const and

linear parts, respectively. Note that, in order to have a

simpler graph, paths to 0-terminal have not been drawn

in Fig. 2(c).

(b)

Fig. 2 HED Representation of 24-8×Z+12×Y×Z-6×X2-6×X2×Z

X

24-8Z+12YZ -6X-6XZ

X

Y X

24-8Z 12Z -6-6Z 0

(a)

(c)

X

Y X

Z Z -1

3

2

1

3

Z

-1

-1

2

3 2

1

1

3

In this representation, basic arithmetic operators such

as adders, subtractors, multipliers, divisors, shifters, and

multiplexers are available that work for symbolic integer

variables. In order to represent Boolean functions,

logical bitwise operations including NOT, AND, and

OR have been provided [9].

III. POLYNOMIAL MODEL OF RTL CIRCUITS

In this section, we introduce a formal model for

describing RTL circuits. Polynomial Model of an RTL

circuit is a set of algebraic functions that describe a

given circuit based on its datapath or a finite state

machine with datapath (FSMD) model. The FSMD is

formally defined by a universal specification model,

proposed in [10], that can represent all hardware

designs. The objective of defining the FSMD model is to

save considerable front-end implementation effort since

translating from RTL to an FSMD is a well-known

synthesis-like process.

Definition 2: An FSMD is defined as an octet

M = f (PI,S,V,PO,U,AR,trans,func), where:

1) PI is the set of primary input signals

2) S is the finite set of control states

3) V is the set of storage variables

4) PO is the set of primary output signals

5)U={xe|x(POV) and eE} represents a set of

storage or output assignments and E={g(p,q,r,…)|

p,q,r,…(PIV)} represents a set of arithmetic

expressions of input and storage variables over PIV

6) AR={R(a,b)|a,bE; and R is any arithmetic relation}

represents a set of status signals as arithmetic relations

between two expressions.

7) trans: S×AR→S, is the state transition function.

8) func: S×AR→U, is the update function of the output

and the storage variables.

The state transition function, trans, is a high-level

expression which describes the next state variables with

respect to the present state and the primary input signals.

This function is modeled by a polynomial function so

that it can be easily represented with a decision diagram.

When we need to traverse the FSMD from primary

outputs to primary inputs, a pre-image computation is

necessary in order to compute which previous state is

reachable from a given present state. To do so, the next

state variable in the polynomial model is replaced by the

related value. Finally a simple polynomial equation

should be solved to find out the values of the present

state and primary input signals. Also, trans and func

functions should be expressed based on a set of

polynomial functions. For this purpose, each state SkS

is encoded by a polynomial Pn(PS,k) defined as follows.

Definition 3: Consider an FSMD which has n states,

S=(S0,S1,…,Sn-1). If one-hot encoding is used, each

present state PS≡SkS (0≤k≤n-1) can be described as a

polynomial Pn(PS,k) in (2). In other words, after

replacing PS in (2) by 2k, Pn(PS,k) is computed as 1 and

therefore we say that Pn(PS,k) represents the present

state Sk . If PS is replaced by 2m(0≤m≤n-1,m≠k), then

zero value for (PS-2m) in (2) will result Pn(PS,k)=0.

)2(

)22(

)2(

),(:)(1

0

1

0 kiwhere

PS

kPSSPSn

i

ik

n

i

i

nk P

According to the concept of definition 3, expression

of the transition function trans(PS, PI) as well as output

function func(PS, PI) are expressed in a summation of

polynomial functions as equated in (3) and (4), where

ft(PS,PI,k):S×PI×AR→U, fo(PS,PI,k):S×PI×AR→U

show operations in each state of the FSMD to generate

next state and output functions, respectively.

)4(),,(),(),(

)3(),,(),(),(

1

0

1

0

n

kn

n

kn

kPIPSfokPSPIPSfunc

kPIPSftkPSPIPStrans

P

P

Example 2: Consider the schematic depicted in Fig. 3,

the FSMD of which is shown in Fig. 4. To describe the

transition function trans and output function func in

terms of the present state PS and primary input PI, each

state is encoded based on an initial state. State diagram

of this state-machine is shown in Fig. 4. Based on

definition 3, each state has a one-hot code such as reset

for the initial state encoded by 1(0001), and sA, sB and

sC are encoded by 2(0010), 4(0100) and 8(1000),

respectively. Furthermore, by definition 2, we can

extract PI, S, V, PO, E, U, and AR, separately. Primary

inputs and outputs of a circuit can be found from port

declaration in the circuit’s description. Thus, we can

easily extract these parts, whereby, PI={X,Y,Z,c1,c2,i},

PO={SC_O} and S={reset,sA,sB,sC}. Moreover, we can

find storage variables which are temporary variables and

signals in the design as the set V={T,T1,T2,T4,T4,T5}.

Set of arithmetic expressions over primary input and

storage variables can be considered as E={X+Y,X–

Y,T3×Z, T3+Z}. Hence, U={T1:=X+Y,T2:=X–

Y,T4:=T3×Z, T5:=T3+Z} will be the set of storage and

output assignments. Furthermore, the set of status

signals and conditions as arithmetic relations between

two expressions can be considered as AR={(c1=0)OR

(c1=1),(c2=0)OR(c2=1),(i=0)OR(i=1)}. Now we can

compute func function as illustrated in equations (5)-

(11). It should be noted that T and Ti (1≤i≤5) in these

equations are temporary variables, i.e., based on

definition 2, they should be described as polynomial

functions as well.

4

+

-

-

X

Y

Z

C

c1

c2

i

x

clock

Reg_A

Reg_B

Reg_C

>

Mux1

Mux3

ADD

MUL

SUB1

SUB2>

>

out

Mux2

t0t0-1t0-2

Fig. 3 Schematic circuit of FSMD circuit - Example 2

Also, trans function is computed as illustrated in

equation (11). According to each present state defined

by Pn(PS,k), it is only necessary to determine the

appropriate next state value as ft part of equation. For

example, the third term in (12), i.e.,

Pn(PS,4)×[8×(i)+4×(1-i)], indicates that if the state

machine is in state sB (encoded by 4), the next state

depends on input i. If i=1, then sB has a transition to sC

(encoded by 8) and the result is 8. Otherwise, the result

will be 4 that indicates the next state will be sB (encoded

by 4).

)8()11()(1)(

34

)7()11()(1)(

)11(2113

)6(2

)5(1

cZYXcZYX

ZTT

cYXcYX

cTcTT

YXT

YXT

)11(})22)(22)(22(

)2)(2)(2(

),(_{

)10(22)11()(

21)()21()11(

)()21(1)(

25)21(4

)9()11()(1)(

35

231303

210

TPSPSPS

PIPSOSCfunc

cZccYX

ccYXcc

ZYXccZYX

cTcTT

ZcYXcYX

ZTT

)12()2()22)(22)(22(

)2)(2)(2(

))1(4)(8()22)(22)(22(

)2)(2)(2()4(

)22)(22)(22(

)2)(2)(2(

)2()22)(22)(22(

)2)(2)(2()},,(

)22(

)2(

{

)},,(),({),(

231303

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321202

310

312101

320

302010

321

3

,0

3

,03

0

3

0

PSPSPS

iiPSPSPSPSPSPS

PSPSPSKPIPSftrans

PS

KPIPSftransKPSPPIPStrans

kii

ik

kii

i

k

n

k

In this example we utilized a one-hot encoding method to

express the state machine with respect to the state variables.

It should be noted that other encoding techniques such as

gray encoding or integer encoding can easily be used as

well. For example, to use integer encoding, variables will

be rest=”00”=0, sA="01"=1, sB="10"=sA+1 and

sC="11"=sA+2. Although the polynomials for the next state

and output functions obtained from integer encoding

method are similar to those of the one-hot encoding

method, the processing time to compute the coefficients in

integer encoding is less than that of one-hot encoding.

Fig. 4 State diagram of FSMD circuit - Example 2

IV. HIGH LEVEL TEST GENERATION

1. High-level Fault Injection

After representing RTL circuits with algebraic

equations, in order to complete test generation procedure

we obtain a set of high-level test sequences using

various coverage metrics. The key point that has to be

appreciated in this decomposition is that linear part

indicates under what conditions the function will be

dependent on the related variable (see (1)). Now

suppose the top variable is a faulty variable named

FAULT as shown in (13), so linear portion expresses

conditions that cause the FAULT variable to be

observed at the output. This property completely covers

path sensitization, while no computation needs to be

performed.

f (FAULT, …) = const + FAULT × linear (13)

Obviously, the const part is equivalent to the fault-

free behavior, while linear is exploited as a set of test

vectors which are formally represented. Indeed, HED

representation has an inherent property of automatically

separating fault-free behavior from the faulty part of a

faulty design. We will point out how this property helps

us generating test vectors from the faulty specification.

2. High-level Test pattern Extraction

In contrast to other approaches of test generation, it

is not necessary to perform justification/propagation

phase, because HED is able to express primary outputs

in terms of primary inputs. If we can find some

conditions that reach the specified fault to one of the

primary outputs, according to the above-mentioned

if (c2) then SC_O=T3×Z

else SC_O=T3 - Z

SC_O=0

8

2

i=1

if (c1) then T3=X+Y

else T3=X-Y

sC

sA sB

4

SC_O=0

reset

1

SC_O=0

i=0

5

property, we have already fulfilled path sensitization as

well as justification phases all together. It should be

noted that if fault propagation needs to go through

storage variables, our method tries to symbolically

manipulate the transition function instead of duplicating

the circuit by applying time-frame expansion. In our

proposed high-level test generation behavioral

specifications (BS) in HDL as well as a fault list (FL)

are treated as inputs to the algorithm. Each fault in the

FL is characterized by the name of the affected signal,

the line of behavioral model, and the type of stuck-at

fault. We define a fault model that comprises two kinds

of faults: (1) bit failure including stuck-at less than (-

FAULT) and stuck-at greater than (+FAULT) the fault-

free value, (2) condition failure indicates that each

condition can be stuck-at true (causing to remove else

execution path) or stuck-at false (causing to remove then

execution path). It is worth noting that such a fault

model provides a good correlation with gate-level fault

models, i.e., stuck-at zero and one, while allowing a

faster and simpler analysis than gate-level approaches.

The test generation algorithm starts by selecting and

then injecting a fault into the behavioral specification

(BS). To do so, a variable FAULT is added to

(subtracted from) the fault-free symbolic value of the

related signal. After that, the highest order of variables

is set to the FAULT due to beneficial property of HED

representation discussed earlier. Finally during HED

representation of different outputs, they are checked to

see whether the linear child of FAULT variable is not

zero. As soon as we can find such an output, the

algorithm has succeeded to detect the fault. Hence the

linear child of variable FAULT is returned as a set of

test vectors that are formally represented in HED,

otherwise the fault is undetectable.

Example 3: Consider Example 2 again. The stuck-at

greater than faults (FAULT1, FAULT2, FAULT3 and

FAULT4), have been injected in ADD(X+Y), SUB(X-

Y), MULT(C×Z) and SUB(C-Z) operators. Fig. 5(a)

illustrates HED representation of the func variable as a

primary output in this example. The coefficients of

FAULTi(1≤i≤4) variables, i.e., linear child, express

conditions under which the specified fault can be

observed at the output func. It should be noted that the

const child of FAULT4 variable represents the fault-free

behavior of the circuit for this fault. Let the variable

ordering be FAULT1>FAULT2>FAULT3>FAULT4>

X>Y>Z>c1>c2>PS. After writing symbolic value of

func in terms of primary inputs and present state, (15),

replacing T3 from (14), we obtain (15).

)15(}42)3(()3)21(3{(

)22)(22)(22(

)2)(2)(2(

)14()11()2(1)1(3

231303

210

FAULTcZTFAULTcZT

PSPSPSfunc

cFAULTYXcFAULTYXT

func = FAULT1×(TP1)+FAULT2×(TP2)+FAULT3×(TP3)+ FAULT4× (TP4) + FFB (16)

In (16), TPi and FFB stand for TestPattern for

FAULTi and FaultFreeBehavior in func, respectively

and they are:

]21[)22)(22)(22(

)2)(2)(2(4

]2[)22)(22)(22(

)2)(2)(2(3

)]21()11(2)11[([)22)(22)(22(

)2)(2)(2(2

)]21(121[)22)(22)(22(

)2)(2)(2(1

231303

210

231303

210

231303

210

231303

210

cPSPSPS

TP

cPSPSPS

TP

ccccZPSPSPS

TP

ccccZPSPSPS

TP

)}21()]21(21[)]21(21))21(

)11(2)11(([{)22)(22)(22(

)2)(2)(2(231303

210

cZcccZYcccZc

cccZYXPSPSPS

FFB

The stuck-at zero and one faults (FAULT5 and

FAULT6) for input variable i have been injected into

trans. Let the variable ordering be FAULT5>FAULT6>

i>PS. We first describe the polynomial function of trans

in (17). Fig. 5(b) illustrates the HED representation of

trans according to (18), where TP5, TP6, and FIP_ns

stand for TestPattern for FAULT5, FAULT6, and

FaultIndependent-Part, respectively, and their equations

are given in (19). The coefficients of FAULT5 and

FAULT6 variables express conditions under which the

state machine has an incorrect transition.

)17()2()22)(22)(22(

)2)(2)(2(

)]1)(64())(58[()22)(22)(22(

)2)(2)(2(

)4()22)(22)(22(

)2)(2)(2()2(

)22)(22)(22(

)2)(2)(2(

231303

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321

PSPSPS

iFAULTiFAULTPSPSPS

PSPSPSPSPSPStrans

trans = FAULT5×(TP5) + FAULT6×(TP6) + FIP_ns (18)

)1()22)(22)(22(

)2)(2)(2(6

)()22)(22)(22(

)2)(2)(2(5

321202

310

321202

310

iPSPSPS

TP

iPSPSPS

TP

)19()2()22)(22)(22(

)2)(2)(2()]1(4)(8(

)22)(22)(22(

)2)(2)(2(

)4()22)(22)(22(

)2)(2)(2()2(

)22)(22)(22(

)2)(2)(2(_

231303

210

321202

310

312101

320

302010

321

PSPSPSii

PSPSPS

PSPSPSPSPSPSnsFIP

TP5 indicates that if the input variable i becomes 1,

while the present state is PS=4 (sB in Fig. 4), stuck-at-

zero on i will be detectable due to having a transition to

PS=4 instead of PS=8 (sC in Fig. 4). Each TPi in (16)

6

and (18) indicates that the injected faults will be

detected if at least one condition can be satisfied.

Otherwise, TPi becomes 0 and, therefore, that fault will

be undetectable.

Fig. 5 HED Fault Representation - Example 3

3. Gate-level Coverage Computation

Although functional tests generated at the behavioral

level are effective in traversing through much of the

control space of a digital circuit, exercising all values of

variables is not possible due to the large number of

possible values. Hence, for testing arithmetic operators,

a gate-level approach may be more effective in finding

values that exercise potential faults. We employ a gate

level ATPG to generate a test pattern targeting structural

faults in the corresponding functional unit. We use

functional methods based on the pre-image computation

techniques to compute justification sequences. We

assume that every FSMD has an initial state, and pre-

image computation is continued until the initial state is

reached. Note that we do not assume that the circuits

have synchronizing sequences. According to conditions

generated for this fault, we assign some values to the

related variables in each time slice to generate a

sequence of gate-level test vectors. Although we utilize

a PODEM-like algorithm, any other gate-level test

pattern generation algorithms can be applied. Moreover,

instead of using ATPG tools, we are able to take

advantage of SMT Solvers to solve a list of equations

extracted from the high-level test patterns [12].

Example 4: Consider behavioral test pattern TP1,

generated for FAULT1 in example 3. This test shows

that in order to detect fault behavior in ADD operation

which provides X+Y, it should satisfy one of the

following conditions:

1- (c1)≠0,(c2)≠0,(Z)≠0, and ((PS-1)(PS-2)(PS-4))≠0

2- (c1)≠0,(1-c2)≠0, and ((PS-1)(PS-2)(PS-4))≠0

According to Fig. 3 which depicted an RTL

schematic of the FSMD in Example 2, to extract gate-

level tests for condition 1, variables c1 and c2 should be

set to one and variable Z to a non-zero value at time

slice t0, while the state machine should be reached to a

state where (PS-1)(PS-2)(PS-4) ≠ 0. On the other hand,

according to the state encoding described in Section III,

(PS-1)(PS-2)(PS-4) ≠ 0 will be satisfied if PS is set to 8,

i.e., sC state in Fig. 4. On the other hand, in order to

reach this state from the initial state sA, we need to

recursively apply the pre-image computation to the state

transition function until the initial state, i.e., sA, is

reached. Therefore, to propagate FAULT1 to the primary

output func, at time slice t0+1, variables c2 and Z should

be set to one and a nonzero value, respectively, at time

slice t0. This way, Reg_C=Reg_b×Z is computed by the

MUL unit in Fig. 3. After doing the first pre-image

computation, the present state sB (Reg_B in Fig. 3) is

reached where the primary input i, i.e., the select bit of

Mux2, should be set to one at time slice t0−1. Performing

the second pre-image computation gets us to the initial

state sA while variable c1 should be set to one at time

slice t0−2. It causes the ADDER unit, the faulty

operation, computes Reg_A=X+Y. In this example, since

there is no constraint on X and Y variables, all

combinations of their values are applied to the ADDER

unit when the conditions for different time slices are

fixed. Note that, in contrast to the conventional methods

of sequential circuit test generation, in our method it is

not necessary to have different copies of a circuit for

different time slices as time frames.

V. EXPERIMENTAL SETUP AND RESULTS

In this section we report some experimental results

that show the robustness of the HED based test

generation compared to other methods. We have

implemented the algorithms in C++ and carried out on

an Intel® 933 MHz Processor and 256 MB of memory

running Windows XP. The effectiveness of the proposed

-16

26

-1

-11

1

trans

FAULT5

Next-State

Fault-Free

Behavior

i

FAULT6

i

PS

PS

PS

(b)

-1

FAULT1

TestPattern

(TP1)

func

Z

-1

FAULT1

c1

c2

-1

c1

c2

FAULT2

Z

c1

c2

c1

c2

-1

FAULT3

FAULT4

Fault-Free

Behavior

-8

(a) 1

PS

-7

14

PS

PS

7

approach has been evaluated on 1999 International Test

Conference VHDL benchmarks [13]. General

information about the benchmark circuits are given in

Table I. Column VHDL Spec provides the number of

lines in RTL representations. In columns GATE Level

Spec, an idea about size of the circuits, number of

primary inputs (PI), primary outputs (PO),

combinational gates (CG), flip-flops (FF), total faults

(TF), and collapsed faults (CF) are given. Experimental

results have been compared with ARTIST [4], ARPIA

[5] and RAGE99 [6] which are behavioral RTL ATPG

tools based on evolutionary and genetic algorithm.

ARTIST and RAGE99 were run on a Sun Ultra 5

running at 333 MHz with 256 MB of memory and

ARPIA was run on a Sun Enterprise 250 running at 400

MHz and equipped with 2 GB of memory. In order to

represent a design in HED, first of all we utilize GAUT

[11] as a high-level synthesis tool to obtain the FSMD

model of the design. After that, the data path and

controller parts of the design are represented in HED

based on the polynomial model defined in section III.

Table II reports the results of running HED package

for each benchmark. For this purpose, based on

statement and path coverage metrics, different high-level

faults are taken into account. Time, memory usage,

number of equations, and the number of variables

needed to generate high-level test patterns have been

reported in columns Time in seconds, Memory in

Mbytes, #EQ, and #Var respectively.

Test patterns generated by HED are simulated at the

gate level when the stuck-at faults are considered. Table

III summarizes the results of our method in comparison

with ARTIST, ARPIA and RAGE99. In this table,

columns F.C. and Time indicate the fault coverage and

the CPU time required by fault simulator to report the

related fault coverage. Although column #Test shows

the number of test vectors reported by methods in Table

III, this information was not accessible for ARPIA

approach.

Although HED package was run on Windows XP

and other methods were run on Sun platforms, in order

to have a fair comparison of their processing times we

have used the benchmarks in [14] which evaluate the

performance of different platforms. It is reported in [14]

that an Intel® 933 MHz processor running Windows XP

is about two times faster than other platforms mentioned

in this paper. For example, in circuit b05, ARTIST

achieved 33,393 seconds, ARPIA achieved 1,932.2

seconds and RAGE99 achieved 2,583.2 seconds, while

our method achieved 97.3 seconds which needs to be

multiplied by 2 since our platform is almost two times

faster than other platforms. Obviously, the run times

(columns Time in Table III) for test generation using

HED for all circuits reported in our experiment, are

almost two orders of magnitude lower than those of

reported using other methods. Therefore this gives us

ways to use the proposed approach to get coverage

driven high level test generation ability within practical

time.

VI. SUMMARY AND CONCLUSION

An arithmetic approach for modeling RTL circuits

with polynomial expressions using a hybrid canonical

data structure based on a decision diagram is introduced

in this paper. Models were modified to generate test

patterns at the behavioral level. Fault coverage at the

logic level is computed by converting the high level test

vectors to gate-level test patterns and applying them to

the related logic circuits. We have applied our approach

to some standard benchmarks which include Boolean

logic expressions as well as arithmetic expressions.

Experimental results show the efficiency of our method

even on large industrial circuits. A possible avenue for

future work would be to apply this method for inserting

optimal test points in the circuit in order to use it for

design for testability.

TABLE I

BENCHMARK CHARACTERISTICS FOR HED-BASED APPROACH

Bench-

mark

VHDL

Spec. GATE LEVEL Spec.

#lines #PI #PO #CG #FF #TF #CF

b01 110 2 2 49 5 260 114

b02 70 1 1 28 4 148 62

b03 141 4 4 160 30 872 386

b04 102 11 8 737 66 4,102 1,646

b05 332 1 36 998 34 5,732 2,440

b11 118 7 6 770 31 4,332 1,726

b12 569 5 6 1,076 121 6,306 2,856

b13 296 10 10 362 53 1,906 830

b14 509 32 54 10,098 245 58,348 22,634

b15 671 36 70 8,922 449 53,018 21,776

TABLE II

HED REPRESENTATION

Benchmark Time

(mSec)

Memory

(Mbytes) # EQ # Var

b01 120 0.25 36 55

b02 100 0.18 21 29

b03 80 0.15 43 93

b04 50 0.14 17 40

b05 100 0.22 39 71

b11 70 0.18 80 85

b12 110 0.28 167 227

b13 100 0.25 113 187

b14 190 0.33 179 253

b15 210 0.38 267 326

8

References

[1] P.Goel, “Test generation costs analysis and projections”, in Proc.

17th DAC, pp. 77-84, June 1980.

[2] M.R.Prasad, et.al., “Why is ATPG easy?”, in Proc. 36th DAC,

pp. 22-28, June 1999.

[3] M.K.Ganai, et.al., “Enhancing Simulation with BDDs and

ATPGs”, in Proc. of Design Automation Conference (DAC), pp.

385-390, 1999.

[4] F.Corno, et.al., “ITC’99 benchmarks and First ATPG Results”,

IEEE Design & Test of computers, Vol. 17, No. 3, pp. 44-53,

July-September 2000.

[5] G.Cumani, “High-Level Test of Electronic Systems”, PhD thesis,

Politecnico di Torino, 2003.

[6] F.Corno, et.al., “High Quality Test Pattern Generation for RT-

level VHDL Descriptions”, MTV99: 2nd Int. Workshop on

Microprocessor Test and Verification Common Challenges and

Solutions, Atlantic City (USA), September 1999.

[7] B.Alizadeh, M.Fujita, “High level test generation without ILP

and SAT Solvers”, in Int. Workshop on High Level Design

Validation and Testing (HLDVT07), pp. 298-304, 2007.

[8] B.Alizadeh, M.Fujita, “Guided gate-level ATPG for sequential

circuits using a high-level test generation approach,” in Proc.

Asia South Pacific-Design Automation Conference (ASP-DAC),

pp. 425–430, 2010.

[9] B.Alizadeh, M.Fujita, “HED: A Canonical and Compact Hybrid

Word-Boolean Representation as a Formal Model for

Hardware/Software Co-designs”, in 4th Int. Workshop on

Constraints in Formal Verification (CFV07), pp. 15-29, 2007.

[10] D. Gajski, et.al., "Introduction to high-level synthesis", in IEEE

Transactions on Design and Test of Computers, pp. 44-54, 1994.

[11] E. Martin, et.al., “GAUT: An architectural synthesis tool for

dedicated signal processors,” in Proceeding European Design

Automation Conference (EURO-DAC), pp. 14–19, 1993.

[12] B.Alizadeh, M.Fujita, “A Hybrid Approach for Equivalence

Checking between System Level and RTL Descriptions”, in Int.

Workshop on Logic and Synthesis (IWLS07), pp. 298-304, 2007.

[13] S.Davidson, ITC99 Benchmarks, 1999. Available:

http://www.cad.polito.it/tools/itc99.html.

[14] J. L. Henning, Standard Performance Evaluation Corporation

(SPEC), 2006. Available: http://www.spec.org/cpu

TABLE III

COMPARING FAULT COVERAGE OF HED METHOD WITH ARTIST, RAGE99 AND ARPIA

Benchmark

ARTIST RAGE99 ARPIA HED

F.C.

(%) #test

Time

(Sec)

F.C.

(%) #test

Time

(Sec)

F.C.

(%) #test

Time

(Sec)

F.C.

(%) #test

Time

(Sec)

b01 100 1,061 4,118 100 259 549.0 100 N.A. 78.8 100 315 77.5

b02 99.33 940 1,731 99.33 114 51.61 99.33 N.A. 39.1 100 175 3.6

b03 74.33 374 5,131 73.48 174 69.36 74.82 N.A. 1,089,9 75.72 146 32.5

b04 89.42 427 6,905 80.18 83 518.4 90.44 N.A. 1,627.8 99.95 107 72.5

b05 33.50 2,800 33,393 40.26 68 2,583.2 33.43 N.A. 1,932.2 89.95 216 97.3

b11 85.98 532 5,092 91.11 1,222 1,741.0 91.14 N.A. 34,837.1 99.95 114 70.1

b12 45.99 5,541 67,575 20.86 155 1,231.7 20.92 N.A. 7,890.2 89.98 756 350.8

b13 68.37 4,538 43,450 84.49 3,303 5,531.4 82.56 N.A. 2,801.8 99.88 896 487.1

b14 79.65 4,743 55,240 79.01 4,597 9,722.9 81.78 N.A. 473,741.9 99.99 1,023 1,172.5

b15 31.96 2,733 60,990 38.11 2,838 11,566.9 32.50 N.A. 590,611.3 79.99 840 1,807.8