A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter

1846 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006

A 14-bit 125 MS/s IF/RF Sampling Pipelined ADCWith 100 dB SFDR and 50 fs Jitter

Ahmed M. A. Ali, Member, IEEE, Christopher Dillon, Robert Sneed, Andrew S. Morgan, Scott Bardsley,John Kornblum, and Lu Wu

Abstract—This paper describes a 14-bit, 125 MS/s IF/RF sam-pling pipelined A/D converter (ADC) that is implemented in a0.35 m BiCMOS process. The ADC has a sample-and-holdcircuit that is integrated in the first pipeline stage, which re-moves the need for a dedicated sample-and-hold amplifier (i.e.,“SHA-less”). It also has a sampling buffer that is turned off duringthe hold clock phases to save power. To accurately estimate andminimize the clock jitter, a new jitter simulation technique wasused whose results were verified on silicon. The measured siliconresults indicate the highest published IF sampling performanceto date and prove the viability of the “SHA-less” architecture forIF/RF sampling ADCs. The ADC is calibration-free and achievesa DNL of less than 0.2 LSB and INL of 0.8 LSB. The SNR is75 dB below Nyquist, and stays above 71 dB up to 500 MHz. Thelow-frequency SFDR is about 100 dB, and stays above 90 dB up toabout 300 MHz. This is also the first ADC to achieve 14-bit levelperformance for input signal frequencies up to 500 MHz and tohave a total RMS jitter of only 50 fs.

Index Terms—analog-to-digital converter (ADC), A/D converter,buffer, IF sampling, jitter, pipeline, SHA-less.

I. INTRODUCTION

WIRELESS communication applications have been amajor driver for the development of high-speed and

high-resolution analog-to-digital converters (ADCs) with betterAC performance and IF sampling capability. The high ACperformance, in terms of signal-to-noise ratio (SNR) andspurious-free dynamic range (SFDR), enables wider cellularcoverage, more carriers, better quality and reliability. TheIF/RF sampling capability simplifies the system design by re-moving one or more mixers from the signal chain. Many otherapplications, such as instrumentation and imaging, also benefitfrom a higher-speed IF sampling ADC with high performance.

The main challenge in implementing such an ADC, besidesachieving the high AC performance at a high sampling rate(125 MS/s), is preserving that performance for high input fre-quencies. As the input frequency increases, the effect of anynonlinearity and mismatches in the input signal path becomesvery detrimental. This is especially true with large sampling ca-pacitors, which are needed to achieve the high SNR required.Moreover, the jitter in the clock path degrades the performanceat high frequencies significantly.

Manuscript received December 1, 2005; revised February 27, 2006.The authors are with Analog Devices, Inc., Greensboro, NC 27409 USA

(e-mail: [email protected]).Digital Object Identifier 10.1109/JSSC.2006.875291

Fig. 1. Block diagram of the pipelined A/D converter.

Therefore, the key to achieving the targeted IF/RF samplingperformance is to create a low-noise and low-distortion inputfront-end capable of handling those high-frequency signals, to-gether with a very low-jitter low-noise clock path. In this work,we present a 14-bit, 125 MS/s calibration-free pipelined ADCthat is designed to address these issues. Measured silicon resultsare discussed and indicate that the ADC indeed achieves a 14-bitlevel of performance for input frequencies up to 500 MHz.

II. DESIGN AND IMPLEMENTATION

A. Architecture

The ADC architecture is shown in Fig. 1. It consists of a dif-ferential switched input buffer followed by a pipelined ADC.Each pipeline stage is comprised of a flash ADC and a Multi-plying DAC (MDAC) [1]. The pipeline is composed of 3 bits inthe first stage, 3 bits in the second stage, nine 1.5-bit stages anda 3-bit back-end flash. There is a 1-bit overlap (redundancy) be-tween each two neighboring stages for digital error correction.This gives a total of 16 internal bits out of the digital error cor-rection block, of which only 14 bits are used. The two extra bitswere implemented to allow for calibration of the capacitor mis-match errors, if needed, to an accuracy of 0.25 LSB. However,silicon results indicated that the capacitor matching and linearityof the ADC are adequate (i.e., less than 1 LSB) without any cal-ibration. Therefore, the calibration feature was not needed andthe ADC as described is calibration-free.

The input sampling capacitors consist of 8 polysilicon capac-itors (constituting the first 3-bit MDAC) of 750 fF each, givinga total of 6-pF. The following pipeline stages are scaled downfor power efficiency as shown in Fig. 1. The ADC operates on adifferential analog input of 2 Vp-p and uses two supply voltagesof 5 V and 3.3 V.

0018-9200/$20.00 © 2006 IEEE

ALI et al.: A 14-bit 125 MS/s IF/RF SAMPLING PIPELINED ADC WITH 100 dB SFDR AND 50 fs JITTER 1847

Fig. 2. (a) Simplified schematic of the front-end. The buffer drives the capac-itances in the first MDAC (8C) and flash comparators (C). The flash consistsof 8 comparators with 8 sampling capacitances C/8 each. The clock �1 a isthe boosted and advanced sampling clock. The clocks �1 and �2 are out-of-phase and nonoverlapping. The grounds shown in the flash and MDAC are ACgrounds. (b) Ideal MDAC output showing the nine sub-ranges.

B. SHA-Less Front End

Traditionally, the sample-and-hold circuit in pipelined ADCs[1], [2] tends to consist of a sampling network and a sample-and-hold amplifier (SHA). The SHA is used to present a heldsignal to the first pipeline stage. It, however, consumes a sig-nificant amount of power, and contributes substantially to thedistortion and noise of the whole ADC. This is mainly becauseit is a front-end block that has to handle the full-swing inputsignal (and hence the impact on distortion) without any pre-vious amplification (and hence the impact on noise). To over-come these disadvantages, we employed a “SHA-less” architec-ture, in which the sample-and-hold (S/H) circuit is integrated inthe first MDAC, without a dedicated amplifier. This architec-ture, shown in Fig. 2(a), provides the same S/H operation to theuser, but saves power, improves distortion and reduces noise. It,however, creates two issues that must be addressed for the ar-chitecture to work properly.

The first issue of the SHA-less architecture is the need tomatch the input networks of the flash (sub-ADC) and the MDACof the first stage. Since the flash and the MDAC see the actualinput signal, and not a held signal, any mismatch between thebandwidths and/or the sampling instant of these two input net-works will result in a mismatch between the sampled values ofthe MDAC and the flash. This mismatch can be corrected by thedigital error correction as long as it does not exceed the redun-dancy correction range of the first pipeline stage. If it exceeds

that range, errors will go uncorrected causing significant perfor-mance degradation. To illustrate the required matching quanti-tatively, assume the input signal is a sine wave given by

(1)

Also, assume the bandwidths of the two input networks (of theflash and MDAC) result in propagation delays of and , andthe sampling instants are and . The difference betweenand represents the bandwidth mismatch, and the differencebetween and represents the skew in the sampling clocks.Then

where (2)

To achieve good high-frequency linearity, the sampling band-width needs to be much larger than the frequency of interest, aswill be seen in Section II-C. This allows us to neglect the differ-ences in amplitude and only look at the differences in samplingtime and phase error. That is

(3)

Using and 2 for the flash and MDAC in (3) and subtractinggives the mismatch error:

(4)

The worst case error happens near the zero crossing, where. Thus

where (5)

where is the total mismatch between the two input networksdue to the bandwidth mismatch and the clock skew. It is clearfrom (5) that the error is in the form of gain error and that asthe input frequency increases, the sensitivity to bandwidth andtiming mismatches increases too.

For correct operation, the total flash error must not exceed thecorrection range shown in Fig. 2(b). That is

therefore mV (6)

where is the full-scale range of the ADC (2 Vp-p) and isthe gain of the first stage . The total flash error is the ag-gregate of all sources of errors. Those include the inherent errorswhich exist even in the presence of an SHA and are caused bycomparator offsets, reference gain error, charge injection, etc.;and the mismatch errors caused by the SHA-less architecture as


discussed above. Allocating half the error budget to the inherenterrors leaves the other half for the mismatch errors:

mV (7)

Substituting in (5) for a 500 MHz input frequency gives

therefore ps (8)

That is, to handle a 2 Vp-p input signal with a frequency ofup to 500 MHz, the total timing mismatch between the flash andMDAC input networks must be less than 20 ps.

For example, we can divide this 20 ps budget equally betweentiming and bandwidth mismatches to have a maximum allowedtiming mismatch of 10 ps for each. Using (2), this will translateinto a maximum allowed bandwidth mismatch of about 5% for asampling bandwidth of about 800 MHz. It is interesting to notefrom (2) that the higher the flash and MDAC bandwidths are,the less sensitive they will be to mismatches. For example, ifthe bandwidth is doubled to 1.6 GHz, it can tolerate up to 10%mismatch while keeping the timing error less than 10 ps for a500 MHz signal. This high bandwidth, however, is undesirablefor noise purposes, and is difficult to achieve because of therouting parasitics.

The maximum allowed mismatches mentioned above repre-sent the worst-case design targets that must never be exceededwith variations in temperature, supply and process. To mini-mize the clock skew, the same sampling clock is used for theMDAC and the flash comparators. Moreover, careful routing ofthe clock to the two blocks ensures that the skew of the clocksampling edge is well below the allowed limit. As for bandwidthmatching, it is important to use similar sampling networks forthe MDAC and flash. The MDAC consists of eight capacitorsand the flash consists of eight comparators. The flash’s eightsampling networks are designed such that their time constantand bandwidth match those of a single MDAC capacitor. More-over, careful layout measures are taken to ensure that matchingis still within the above tolerance when parasitics are included.

The second issue of the SHA-less architecture is that itdecreases the time available for the settling of the first MDACbecause of the absence of a held signal. This causes the flashto consume a portion of the time that would normally beavailable for the MDAC’s settling, had there been an SHA,and requires a fast comparator to minimize the latching time.A BiCMOS comparator is used, as shown in Fig. 3, wherethe high gain–bandwidth product ( ) of the NPN bipolarjunction transistors (BJTs) (about 25 GHz) is utilized to reducethe regeneration/latching time. Nevertheless, at 125 MSPS, thetime available for the first MDAC settling becomes about 2ns, which is significantly less than the settling time that wouldhave been available had there been an SHA (about 3.5 ns). Sothe MDAC bandwidth must be increased accordingly. In spiteof that, the power saved by removing the SHA is more than theextra power needed to speed up the MDAC. In addition, the

Fig. 3. Simplified schematic of the BiCMOS comparator used. It consists ofa pre-amplifier and a latch. The BJTs Q2A and Q2B are used as regenerationdevices to make use of their high fT .

noise and distortion improve, which further justifies the use ofthe SHA-less architecture.

C. Switched Input Buffer

This ADC has a BiCMOS differential input buffer that is de-signed to achieve high linearity with IF sampling and to iso-late the ADC external driving network from the kick-back andcharge injection caused by the switching of the sampling ca-pacitances. The buffer, shown in Fig. 2 in a single-ended formfor simplicity, is composed of two cascaded sets of emitter fol-lowers separated by a bootstrapped switch. The first set is asingle follower that is always ON. The second set is comprisedof nine followers. Eight of which are driving the eight capacitorsin the MDAC and the ninth drives the eight comparators of thefirst flash. All nine of the second set of followers are switchedoff during the hold phase by AC grounding their bases and dis-abling their current sources, in order to allow the MDAC andflash to operate properly in the gain phase. The bootstrappedswitch is needed to allow the bases of the second followers to begrounded during the gain phase. Finally, the first follower iso-lates the input from this switching operation and the resultingcharge-injection.

During the gain/hold phase, the MDAC switches are con-nected to the positive or negative reference (Vrefp or Vrefn) ac-cording to the flash decisions. Disabling the current sources ofthe followers during the gain phase can be done by steering thatcurrent away from the follower. However, to reduce the powerconsumption, we chose to turn the current off completely (in-stead of steering it away) [3]. This approach saves a substantialamount of power (about 35% of the buffer power). To ensure thatthe switching is fast enough with minimum effects on perfor-mance, the nMOS switch (Msw) is inserted between the MOScurrent source and the NPN cascode. This enables fast switchingby keeping the gate and base voltages of the devices intact. Italso reduces the glitches on the sampling capacitor because ofthe isolation provided by the cascode BJT. The supply is de-coupled using large on-chip capacitors to attenuate the resultingglitches. Since the switched peak currents in the second fol-lowers are large (about 120 mA), attention must be paid in order


Fig. 4. Simplified schematics of some sampling networks. (a) Using a switchedfollower. (b) Using a bootstrapped nMOS switch.

to prevent any supply “ringing” that may be caused by the reso-nant network formed by the package inductors and the internalcapacitors. This is done by internal decoupling that is properlydetuned to prevent under-damped responses. Moreover, externaldecoupling with large capacitors is necessary to remove anyresidual effects of the switching on the power supply.

In addition, the input buffer structure is designed to achievebetter linearity relative to what can be accomplished using MOSbootstrapped switches, especially at high input frequencies. Thelarge trans-conductance and output impedance of the NPN fol-lower, coupled with the high output impedance of its cascodedcurrent source, are needed to achieve good linearity in the buffer[4]. Moreover, using an NPN (instead of an NMOS) as the cas-code device in the current source achieves a very high output re-sistance and low output capacitance of the current source. Thisis due to the high intrinsic gain and the low parasitic capacitanceof the NPN device compared to the nMOS device.

A major source of distortion is the variation of the circuitcomponent values (resistances and capacitances) with the inputsignal. For example, if we look at a typical sampling network asshown in Fig. 4, the resistance ( ) tends to be signal-dependent,and its contribution to the distortion is roughly proportional to

That is, the linearity degrades with increasing the fre-quency and/or the sampling capacitance; and improves by in-creasing the sampling bandwidth and/or decreasing the compo-nent’s input dependence. The relatively high of the NPNBJTs (about 25 GHz) allows us to achieve high gm (and hencesmall resistance ) with small variation and low parasitic ca-pacitances, if adequate current is used. Otherwise, to realizesuch a small with a 0.35 m nMOS switch, whosevalue is only a few gigahertz, would cause it to have relativelylarge parasitic capacitances. Those parasitics (which were ig-nored in the above example) would degrade the bootstrappingperformance, cause significant kick-back on the input and havetheir own voltage dependence that contributes to the distortion.

In addition, the emitter follower isolates the input from theeffects of charge injection and kick-back caused by switchingthe sampling capacitances, which in turn helps improve the lin-earity. This is even more important in an SHA-less architecturewhere the kick-back is nonlinear. It is important to note thatthe bootstrapped switch used between the two sets of followersbenefits from the isolation provided by the second follower. Theswitch’s capacitance load is the input capacitance of the secondset of followers, which is much smaller than the sampling ca-pacitors. Also, the currents flowing through it during tracking

Fig. 5. Simplified schematic of the low-jitter clock path.

and after the sampling switch is turned off (i.e., from charge in-jection) are much smaller than if there were no second follower.This relaxes the impact of that switch on distortion and sim-plifies its design. Moreover, the first follower isolates the ADCdriver from the effects of any kick-back because of this switchand the base currents of the second set of followers.

Attention is also paid in the layout to matching the differentialpaths and to capacitor matching in the first MDAC. The sam-pling switches are sized for good high-frequency sampling per-formance and the sampling clock is advanced. The inputbuffer consumes a total of about 100 mA from a 5 V supply.

D. Clock Jitter

The clock jitter causes degradation in the performance ofthe ADC that tends to be negligible for low input frequencies,but becomes more detrimental as the input frequency increases.Clock jitter can be periodic, random or a mixture of both. Peri-odic jitter causes harmonics and spurs in the output spectrum,while random jitter raises the noise floor. To achieve the tar-geted IF/RF sampling performance, both types of clock jitterneed to be very small. Coupling from periodic and noise sourceson the clock path contributes to both types of jitter, and can beminimized by layout isolation, shielding and decoupling tech-niques. In addition, the noise generated by the devices in theclock signal path itself contributes to the random jitter. Thiscontribution needs to be accurately simulated and minimized inorder to reduce the overall jitter.

To set a design target for the random jitter, it is imperativeto quantify its impact on the ADC noise. The ADC jitter noisevoltage is given by [5]

(9)

where is the RMS amplitude of the input signal, is theinput frequency, and is the RMS jitter. The total ADC noiseis given by , and the resulting total SNRis given by

(10)

Therefore, the RMS clock jitter is given by

(11)


Fig. 6. Jitter simulation results using Spectre-RF. (a) The output “sampling clock” time-waveform in Fig. 5 using the PSS analysis, (b) The RMS noise voltageversus frequency of the periodic noise analysis performed using an ideal sampler at the shown sampling instant. The resulting simulated jitter is 50 fs, whichmatches the silicon result.

For example, if the low frequency dB, and we needthe SNR to stay above 70 dB up to 500 MHz input frequencyfor a 2 Vp-p signal, then

fs (12)

That is, the maximum allowed total RMS jitter must be lessthan 83 fs. This includes the internal jitter from the ADC itselfand the external jitter from the signal generators. Since the bestavailable signal generators known to the authors have a totalrandom jitter of about 50 fs (obtained by bandpass filtering asynthesized signal generator such as the HP8644B or the Rohde& Schwarz SMA), the maximum jitter allowed in the ADC canbe found using

(13)

This results in an ADC jitter requirement of less than 66 fs,which is about 50% lower than the state-of-the-art in ADC jitterperformance [6]. Moreover, the state-of-the-art was achievedusing a complimentary bipolar sampler [6] which utilizes a fullydifferential clock all the way up to the sampling circuit. In ourcase, just like in most other CMOS samplers, the input differen-tial clock must be internally converted into a single-ended clockto drive the nMOS sampling switch. Once single-ended, it be-comes more susceptible to noise from the substrate, supply and

ground bouncing. Thus, in addition to lowering the noise gen-erated in the clock path, attention must be paid to the isolationof the clock path from substrate, ground and supply coupling.

To simulate the random jitter due to the noise generated bythe devices in the clock path, strobed (sampled) periodic noiseanalysis is used. In this method, the periodic operating point isfound using Spectre-RF’s Periodic Steady-State analysis (PSS),then the periodic noise analysis is performed around this peri-odic operating point to account for the periodic time-varying na-ture of this noise (i.e., cyclostationary noise). Moreover, sincethe impact of the clock jitter on the ADC takes place only at thesampling edge, and not throughout the whole clock cycle, wesample the output clock at the sampling instant using an idealsampler. Integrating the resulting noise spectral density, at theoutput of the ideal sampler, up to the Nyquist frequency and di-viding by the slope of the sampling edge gives an estimate ofthe jitter. That is, the RMS jitter is given by

(14)

where is the noise power spectral density obtained usingthe strobed (sampled) periodic noise analysis. This method issimple to run and accurately models the cyclo-stationary na-ture of the system. It is used in the current work to optimizethe design of the clock path, which is shown in Fig. 5. Theinput clock buffer is a differential low-noise BiCMOS buffer,


Fig. 7. Simplified schematic of the MDAC amplifier. Two common-mode feed-back loops control the common-mode voltages of the two stages.

Fig. 8. Simplified schematic of the reference circuit.

followed by a differential-to-single-ended converter. This is fol-lowed by a chain of gates that perform the duty-cycle stabiliza-tion and nonoverlap clock generation. The clock circuit usesa 3.3 V supply and burns about 30 mA. Simulation results ofthe clock path using the above method and a differential sinu-soidal input clock of 2 Vp-p, indicated an RMS noise voltage of4.2 mV and a slope of 84 V/ns as shown in Fig. 6. Using (14), weget a simulated jitter estimate of about 50 fs. As will be shownin Section III, the jitter simulation result indeed closely matchesthe measured silicon results in a consistent manner.

To minimize the other sources of jitter, careful substrate iso-lation is employed. This was done using substrate contacts andN-well isolation. The clock was also carefully shielded, and thesupply heavily decoupled.

E. Pipeline

The first MDAC amplifier is a two-stage Miller-compensatedBiCMOS amplifier as shown in Fig. 7. Bipolar transistors areused as cascodes in the first stage and form the differential pairin the second stage. The two stages are separated by emitterfollowers for buffering and level-shifting. Two independentswitched-capacitor common-mode feedback (CMFB) loops areused for the two stages [2]. The amplifier has a gain of about120 dB and a closed loop bandwidth of about 750 MHz. Thisis needed to settle with better than 0.25 LSB accuracy in theavailable settling time of 2 ns as discussed in Section II-B. Thelater pipeline stages are scaled down gradually after the firststage to save power, as shown in Fig. 1.

Fig. 9. Die photomicrograph.

Fig. 10. Worst-case histogram of the first-stage residue for a full-scale 510MHz input frequency measured on the chip. The residue is reconstructed usingthe digital outputs of the following pipeline stages (i.e., stages 2 and beyond).The x axis is the value of the residue represented digitally and as a ratio of thefull-scale. The y axis represents the sub-range in which the residue exists as de-termined by the digital output of the first flash. The shades/colors represent thenumber of samples (density). So those 9 segments can be thought of as the topview of 9 bell curves. The limits of the correction range are between �1 and 1on the x-axis. The measured histogram shown above indicates that the residue isalways within the correction range, which indicates that the matching betweenthe flash and MDAC sampling networks is good enough up to 500 MHz. We canalso see that the worst mismatch happens in the middle sub-ranges (i.e., near thezero crossings of the input) as expected.

The reference circuit, partially shown in Fig. 8, consists ofa bandgap circuit that generates a single-ended reference. Thisgoes to a single-ended-to-differential amplifier that generatesthe differential references. That differential output is externallydecoupled to minimize noise and then passes to a bipolar buffer(two emitter followers) that generates the pipelined references.The ADC pipeline and the reference circuit operate from a 3.3 Vsupply and consume a total current of about 300 mA.


TABLE ISUMMARY OF MEASURED SILICON RESULTS. ALL MEASUREMENTS GIVEN

BELOW ARE DONE AT �1 dBFS INPUT SIGNAL. IT IS INTERESTING TO NOTE

THAT THE SNR AND SNDR ARE ALMOST THE SAME. THIS IS BECAUSE OF

THE LOW DISTORTION OF THE ADC (I.E., HIGH SFDR), WHICH MAKES THE

CONTRIBUTION OF THE HARMONICS TO THE SNDR NEGLIGIBLE

III. MEASURED RESULTS

The ADC is fabricated in a 0.35 m BiCMOS process withtwo polysilicon layers and three metal layers. The die area isabout 70 mm and the die micrograph is shown in Fig. 9. All theresults mentioned below are based on silicon measurements.

To measure the matching between the MDAC and flash sam-pling networks, as discussed in Section II-B, the output residueof the first stage is reconstructed using the digital outputs of thefollowing pipeline stages (i.e., stages 2 and beyond). The residuehistogram is measured on silicon and shown in Fig. 10. It showsthat the residue is always within the correction range, which in-dicates that the matching between the flash and MDAC samplingnetworks is good enough up to 510 MHz.

The ADC performance is summarized in Table I and shownin Figs. 11–15. It has a baseband SNR of 75 dB and SFDR of100 dB. The SFDR stays above 90 dB up to 300 MHz, and theSNR above 71 dB up to 500 MHz. The DNL is 0.2 LSB and INLis 0.8 LSB. It is important to note that, the capacitor matchingachieved was in the order of 15-bit accuracy, which removed theneed for any digital calibration. This matching was calculatedfrom the measured INL and DNL at low sample rates.

The jitter is calculated using the measured SNR at high fre-quencies (at 400 and 500 MHz) and (11). From there, we can seethat the total system jitter of the ADC and the signal generatorsis about 70 fs. The total jitter of the signal generators is measured

Fig. 11. Measured DNL of the ADC at 125 MS/s and 10 MHz input frequency.

Fig. 12. Measured INL of the ADC at 125 MS/s and 10 MHz input frequency.

to be about 50 fs, which, when subtracted from 70 fs using (13),indicates the ADC jitter is about 50 fs. This agrees closely withthe simulation results, which confirms the accuracy of the simu-lation method. In fact, jitter measurements at different clock andbiasing conditions have consistently matched the correspondingsimulation results. Moreover, this result indicates the effective-ness of the layout isolation and decoupling techniques used tominimize the other sources of jitter, which were not included inthe noise simulation.

A comparison between the performance of the ADC de-scribed in this paper and the closest state of the art [6] issummarized in Table II and Figs. 14–16. It is clear that theADC surpasses the state of the art in its IF sampling perfor-mance. To evaluate the efficiency of the ADC, the figures ofmerit (FOMs) are calculated using

(15)

where SNDR is the signal-to-noise-plus-distortion ratio, andBW is the bandwidth of the input signal over which the usedSNDR value holds. The power used in this calculation is the totalpower. Obviously, the smaller the FOM, the more efficient theADC is. Although the FOM_1 formula tends to be more com-monly used, FOM_2 is more technically sound especially forhigh-performance ADCs whose power is limited by their SNR.It accurately captures important interactions such as the effectsof decimating the digital output, using parallel ADCs or scaling


Fig. 13. Measured FFT results at different conditions.

Fig. 14. SFDR of this work compared to prior art [6].

the capacitances to increases the SNR, etc. However, for com-pleteness, we used both formulae. The FOM results are shownin Fig. 16 and indicate that although this ADC is less efficientat low input frequencies, it becomes significantly more efficientthan prior art at high frequencies. This demonstrates the IF/RFsampling focus and effectiveness of this ADC design.

IV. CONCLUSION

This paper describes a 14-bit 125 MS/s IF/RF samplingADC. The converter is calibration free and surpasses thestate-of-the-art in its IF sampling performance. It achieves alow frequency SFDR of about 100 dB, and preserves a 14-bitlevel of performance for input frequencies up to 500 MHz.

Fig. 15. SNR of this work compared to prior art [6]. The impact of the lowjitter of this work on preserving the SNR with frequency, compared to prior art,is clear.

TABLE IIA COMPARISON WITH THE STATE OF THE ART

This is enabled by designing a high-linearity low-noise inputfront-end, and a very low jitter clock path that is better thanthe-state-of-the-art by more than 60%. Moreover, meticulouslayout was necessary for good capacitor matching, bandwidthmatching, substrate isolation, shielding and decoupling.

This work also demonstrates the viability of the SHA-less ar-chitecture for high input frequencies up to 500 MHz, the possi-bility of turning currents off at high sample rates to save powerwithout degrading performance, the feasibility of very low clockjitter using single-ended CMOS sampling and finally the effec-tiveness of the strobed periodic noise analysis in accurate jittersimulation.


Fig. 16. FOMs, using (15), of this ADC compared to prior art [6]. It is clear thatalthough this ADC is less efficient at low frequencies, it becomes significantlymore efficient at high input frequencies. This illustrates the IF/RF sampling na-ture of this work.

ACKNOWLEDGMENT

The authors would like to acknowledge the contributions ofJ. Greene, C. Block, G. Boles, P. Durant, D. Combs, C. Shelton,M. Crawford, R. Kranz, B. Rigsbee, and R. Wright, and the restof the HSC-ADC product line.

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[2] W. Yang et al., “A 3-V 240 mW 14-b 75-Msample/s CMOS ADC with85-dB SFDR at Nyquist input,” IEEE J. Solid-State Circuits, vol. 36,no. 12, pp. 1931–1936, Dec. 2001.

[3] I. Ahmed and D. Jones, “A 50 MS/s (35 mW) to 1 kS/s (15 mW) powerscaleable 10 b pipelined ADC with minimal bias current variation,” inIEEE ISSCC Dig. Tech. Papers, 2005, pp. 280–281.

[4] P. Wambacq and W. Sansen, Distortion Analysis of Analog IntegratedCircuits. Norwell, MA: Kluwer Academic, 1998, p. 386.

[5] M. Shinagawa et al., “Jitter analysis of high-speed sampling systems,”IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 220–224, Feb. 1990.

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Ahmed M. A. Ali (M’99) received the B.Sc. andM.Sc. degrees, with distinction and highest honor(summa cum laude), in electronics and communica-tion engineering from Ain Shams University, Cairo,Egypt, in 1991 and 1994, respectively. He receivedthe Ph.D. degree in electrical engineering from theUniversity of Pennsylvania, Philadelphia, in 1999.

He is currently a Senior Staff Design Engineer withthe High Speed Converters Group (ADCs), at AnalogDevices, Greensboro, NC. Before joining Analog De-vices, he was with Texas Instruments Incorporated,

Mixed-Signal R&D Labs and Wireless Infrastructure Business Unit, where heworked on developing high-speed pipelined ADCs and other mixed-signal cir-cuits and systems. His past industrial experience also includes design positionswith Anacad/Mentor Graphics, and Siemens AG. He has been an Adjunct Assis-tant Professor at the University of Pennsylvania since 2001. He is the principalauthor of 22 refereed papers, and has 14 patents (some of which are pending),in the fields of high-speed converters, analog IC design, signal processing andmixed-signal processing for speech recognition.

Dr. Ali received the S.J. Stein award for an “outstanding Ph.D. in the fieldof electronics” from the University of Pennsylvania. He is also the recipient ofthe George Stephenson Foundation award, the Catalyst Foundation fellowshipaward, the University of Pennsylvania fellowship, and several academic excel-lence awards from the Ministry of Education in Egypt.

Christopher Dillon received the B.S.E.E. degreefrom North Carolina State University, Raleigh, in1997.

After graduating, he joined Analog Devices in theHigh Speed Converter group as a Mixed Signal De-sign Engineer. He has spent his entire career to datedesigning and developing a wide range of circuits forhigh-speed high-resolution A/D converter products.He has done most of his design work in BiCMOSprocesses and enjoys the flexibility and challengesthese processes offer in switched capacitor designs.

He holds several U.S. patents related to high-speed circuit design, with morepending.

Robert Sneed received the B.S. degree from the Uni-versity of Tennessee at Knoxville in 1994.

He joined Analog Devices in 1995 and worked onhard disk drive amplifiers. He continued this work atAdaptec and STMicroelectronics between 1999 and2000. He returned to Analog Devices in 2000 as aDesign Engineer in the High Speed Analog to DigitalConverter group. He continues work in the convertergroup focusing on modeling and verification.

Andrew S. Morgan was born January 18, 1980. Hereceived the B.S.E.E. degree in December 2002 fromNorth Carolina State University, Raleigh. Workingunder the direction of Dr. Paul D. Franzon, he thenfocused his studies in analog and high-speed digitalcircuit design. He completed his thesis work and re-ceived the M.S.E.E. degree from North Carolina StateUniversity in May 2004.

He has worked on high-speed, high-resolutionADCs since joining Analog Devices, Greensboro,NC, in July 2004.

Scott Bardsley was born in Miami, FL, on April26, 1962. He received the B.S.E.E. degree from theUniversity of Florida, Gainesville, in 1985 and tookclasses toward the M.S.E.E. degree from the FloridaInstitute of Technology, Melbourne, before leavingMelbourne.

From 1985 to 1999, he worked at Harris Semicon-ductor, Melbourne, FL, first as a Product Engineer onRAD hard military products until 1992, and then asa Design Engineer in the mixed signal product devel-opment group working on a variety of products in-

cluding ADCs, synthesizers, modems, and wireless LAN radios. Since 1999,he has been with Analog Devices, Greensboro, NC, in the high-speed convertergroup where he has worked on high-speed 12 and 14 bit pipeline ADC con-verters in both BiCMOS and CMOS technologies. He holds seven patents inthe area of mixed-signal and pipeline ADC design.


John Kornblum received the B.S.E.E. degree fromthe University of South Florida, Tampa.

He has over 20 years experience in IC design. He iscurrently a Senior Design Engineer and group leaderwith Analog Devices, Greensboro, NC. He holds fivepatents.

Lu Wu received the B.E. degree in micro-electronicsengineering from Beijing Institute of Technology,China, in 1997.

He joined Analog Devices Inc. in 2000, and cur-rently he is a Design Engineer for the digital tech-nology team in Greensboro, NC.

A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter

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