04782178

354 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 56, NO. 1, FEBRUARY 2009

Development of Binary Readout CMOS MonolithicSensors for MIP Tracking

Yavuz Degerli, Member, IEEE, Auguste Besson, Gilles Claus, Michel Combet, Andrei Dorokhov,Wojciech Dulinski, Mathieu Goffe, Abdelkader Himmi, Yan Li, and Fabienne Orsini

Abstract—Recently, CMOS Monolithic Active Pixels Sensors(MAPS) have become strong candidates for pixel detectors used inhigh energy physics experiments. A very good spatial resolutionlower than 5 � can be obtained with these detectors. A recentfast MAPS chip, designed in AMS CMOS 0.35 � Opto processand called MIMOSA16 (HiMAPS2), was submitted to foundry inJune 2006. The chip is a 128 32 pixels array where 8 columnshave analog test outputs and 24 columns have their outputsconnected to offset compensated discriminator stages. The pixelarray is addressed row-wise. The array is divided in four blocksof pixels with different charge-to-voltage conversion factors and iscontrolled by a serially programmable sequencer. The sequenceroperates as a pattern generator which delivers control signals bothto the pixels and to the column-level discriminators. Discrimina-tors have a common adjustable threshold. This chip is the basis ofthe final sensor of the EUDET-JRA1 beam telescope which will beinstalled at DESY in 2009. In this paper, laboratory tests resultsusing a ��

�� source together with beam tests results obtained atCERN using Minimum Ionizing Particles (MIPs) are presented.

Index Terms—Active pixel sensor, charged particle detector,CMOS sensor, discriminator, MAPS, MIP, position sensitivedetector, tracking.

I. INTRODUCTION

O NE of the goals of the EUDET-JRA1 project (DetectorR&D towards the International Linear Collider) is to pro-

vide a test beam area with a high precision telescope throughan upgrade of an existing facility at DESY near Hamburg, Ger-many [1]. An optimal determination of the spatial resolution ofthe device under test is among the most important tasks in thisconcept. To this end, a high precision beam telescope with upto six measurement planes and one plane for a device under testwill be constructed (Fig. 1). Each measurement plane will beequipped with CMOS Monolithic Active Pixel Sensors (MAPS)that allows fully evaluation of the tracking properties of newdetectors. For each plane, a spatial resolution better than 5and a very high readout speed (integration time inferior than100 /frame for 576 rows) are required. The telescope can bealso operated inside a solenoid magnetic field of up to 1.2 T.

Manuscript received November 26, 2007; revised September 05, 2008. Cur-rent version published February 11, 2009. This work was supported in part bythe Commission of the European Communities under the 6th Framework Pro-gram “Structuring the European Research Area” (Contract RII3-026126).

Y. Degerli, M. Combet, Y. Li, and F. Orsini are with CEA Saclay, IRFU/SEDI, 91191 Gif-sur-Yvette Cedex, France (e-mail: [email protected]).

A. Besson, G. Claus, A. Dorokhov, W. Dulinski, M. Goffe, and A. Himmi arewith IPHC, IN2P3/ULP, 23, 67037 Strasbourg, France.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNS.2008.2009985

In the past, the first fast MAPS with on-chip signal discrim-ination designed for charged particle detection, the MIMOSA8(HiMAPS1) chip, has exhibited very encouraging performances[2], [3]. The Temporal and Fixed Pattern Noises of the sensorhave been largely reduced thanks to the double sampling ar-chitecture integrated inside each pixel. The input referred Tem-poral noise was only about 10 . The first step towards finalon-chip data sparsification has been achieved by column levelcomparators which digitalize analog pixel signals into a 1-bitdigital code. The readout speed has been reached 13 /frame

on analog outputs and 20 /frame (50000frames/s) on digital outputs for a pixel array of 128 rows 32columns. With the 5 GeV electron test beam of DESY, per-formed in 2005, detection efficiency for Minimum Ionizing Par-ticles (MIPs) was above 98% for both analog and digital out-puts [3]. A spatial resolution of on binary outputs wasmeasured at CERN later with 180 GeV pions, corresponding to

.All these encouraging results demonstrate that the circuit ar-

chitecture of MIMOSA8 chip was a good candidate for high en-ergy experiments where high speed and good spatial resolutionare necessary. However the S/N of the central pixel was quitesmall in beam tests . The reason was that the MIMOSA8chip was implemented in TSMC 0.25 digital process, wherethe estimated thickness of epitaxial layer was only about 6.5

. The total charge collected with this epitaxial layer wassmall and it limits the maximum signal value.

To improve the amount of total charge, a CMOS process withthicker epitaxial layer has to be used. As a result, a new pro-totype, MIMOSA16 (HiMAPS2), using the same architectureas MIMOSA8, but with improved pixels has been designed inAMS 0.35 OPTO process, with an epitaxial layer of about14 . Moreover, in order to study the influence of the thicknessof epitaxial layer on detection performance, another version ofMIMOSA16 has been fabricated in the same process but withan epitaxial layer of about 20 .

These chips are the basis of the final sensor of the EUDET-JRA1 beam telescope. We notice that the final sensors will haveat least 500000 pixels and integrated zero suppression circuits.

II. ARCHITECTURE OF THE CHIP

As the main purpose of MIMOSA16 is to test and improvethe performances of the architecture of MIMOSA8 by using aCMOS process with thicker epitaxial layer, only minor modifi-cations in the architecture have been made. The diagram of theglobal architecture of the chip is shown in Fig. 2(a). The MI-MOSA16 chip is an array of 128 rows by 32 columns of which

0018-9499/$25.00 © 2009 IEEE

DEGERLI et al.: DEVELOPMENT OF BINARY READOUT CMOS MONOLITHIC SENSORS FOR MIP TRACKING 355

Fig. 1. Sketch of the EUDET-JRA1 beam telescope.

8 columns have analog test outputs and 24 columns are dis-criminated binary outputs with a common adjustable threshold.Analog outputs are used to evaluate the performance of differentpixels. The pixel size is 25 25 . Three versions of thischip (M16_1, M16_2 and M16_3) have been submitted for fab-rication. M16_1 and M16_2 have been fabricated at the sametime on an engineering run, while M16_3 has been fabricatedlater on a different MPW (multi-project wafer) run. Each chip isdivided in sub-arrays with four types of pixels (S1–S4) with dif-ferent charge collecting diode sizes and amplifier types. Table Isummarizes the differences between these three versions of fab-ricated MIMOSA16 chips. The only difference between M16_1and M16_2 is the thickness of their epi-layers. The pixels of S3(M16_1 and M16_2) have been designed with ionizing radiationtolerant design rules in order to study the radiation tolerance.

The digital part generates and distributes the control signalsnecessary for the analog part. The timing patterns are loadedinto the chip during the initial phase of programming thanks tothe programmable sequencer. The outputs of 24 column-leveldiscriminators are multiplexed by the serializer block.

The column level discriminators and the programmabledigital sequencer described in [2] have been translated in AMS0.35 Opto process with only minor modifications. Forexample, MOS capacitors used in column-level discriminatorshave been replaced with poly-poly capacitors that offer betterlinearity. The description of these blocs can be found in [2].

III. PIXELS

The success of pixel design strongly depends on the efficiencyof noise reduction. While the influence of shot noise is smallthanks to high readout speed, the classical 3 transistors pho-todiode pixel suffers from the Reset Noise, Temporal readout

Noise and pixel-to-pixel FPN (Fixed Pattern Noise). All thesenoises have to be reduced in the pixel in order to perform columnlevel discrimination. To reduce the influence of the Temporalreadout Noise, an amplifier has to be added and be placed veryclose to the detection diode. Moreover, the FPN results fromthe offset of the mismatches among the transistors and its re-duction is also crucial for on-chip data sparsification. Each tran-sistor implemented on the analog signal path contributes to thepedestal variations. Considering the small signal level, specialcare is needed to remove these offsets while maintaining thetarget readout speed.

A. Pixel With Basic CS Amplifier

The pixel architecture is shown in Fig. 3(a). A CS (CommonSource) pre-amplifying stage is placed very close to the chargedetection diode. The amplifier is based on a common sourceNMOS transistor with a diode connected NMOS transistor load,both saturated in strong inversion. The voltage gain is the ratioof the transconductances of these two transistors. The DC cur-rent bias of the amplifier is determined by the voltage across thecharge collecting diode. A double sampling circuitry is com-posed of this CS preamplifier, a serially connected capacitor(MOSCAP) and two reset switches. The first switch (RST1) isused to reset the detection diode and the second one (RST2) isused to memorize on the capacitor the offset of the preamplifierand the reset level of the diode. A SF (Source Follower) and arow select switch are used to output the signal on the commondata bus. RD and CALIB are column level commands and areused to memorize the output signal level and the reference levelof the pixel output stage, respectively. The timing diagram andmore details on this pixel can be found in [2] and [3].


Fig. 2. (a) Architecture of MIMOSA16 CMOS sensor, (b) microphotography of the chip.

TABLE IDESCRIPTION OF FABRICATED MIMOSA16 CHIPS

While the damage of non ionising radiation can not be re-duced by applying special layout design rules, the ionising radi-ation damage can be reduced by using enclosed geometry tran-sistors and by using guard-rings. The enclosed geometry tran-sistor thins down the field oxide to reduce the charge created byionization. The guard-ring cuts the path of surface leakage cur-rent induced by positive charge build-up on oxide after irradia-tion. In the pixels of sub-array S3 (M16_1 and M16_2) of MI-MOSA 16, only poly-layer guard-ring structure has been usedto remove the thick oxide around the detection diode. The domi-

nant leakage current being generated by the diode, enclosed ge-ometry transistors are not used in this chip.

B. Pixel With Enhanced CS Amplifier and Feedback

In this pixel, the reset transistor is replaced by a diode.The charge sensitive element is a two diode system, with ann-well/p-epi diode, collecting the charge available after particleimpact, and a p+/n-well diode, providing a constant reversebias of the first one.


Fig. 3. Schematics of the pixel used in the MIMOSA16 chip, (a) pixel with basic Common Source amplifier, (b) pixel with enhanced CS amplifier and feedback.

In order to maximize signal-to-noise ratio (S/N) of the pixel,the gain of the amplifier should be increased as much as pos-sible. The performances of the basic CS amplifier used in thefirst pixel can be improved using additional transistors [4]. Inthis pixel, a negative feedback loop is used to polarize the chargecollecting diode and to stabilize the operation of point of the am-plifier, which makes the circuit more resistant to CMOS varia-tions. More details on the amplifier used in this pixel can befound in [4] and [5]. This pixel also uses a CDS circuit with aserially connected clamping capacitor, a switch and a SF likethe first pixel (Fig. 2(b)).

In the sub-array S4 of M16_3, an additional SF is introducedbetween the amplifier and the MOS capacitor (MOSCAP) tobetter polarize this capacitor. However, this additional SF atten-uates the signal by and introduces additional noise, alsoone need to add a current source for the source follower, so thecircuit becomes more complex.

IV. LABORATORY TEST RESULTS

In order to determine the basic performances of the chip(Temporal Noise, FPN, Charge-to-Voltage conversion Factorand Charge Collection Efficiency), laboratory tests have been

performed on analog test outputs and discriminated binaryoutputs, with and without a source (5.9 keV peak).

A. Analog Outputs

Fig. 4 shows the input referred rms Temporal and Fixed Pat-tern Noises measured without source on a M16_2 chip as a func-tion of the clock frequency up to 170 MHz. At high operatingfrequencies, the dominant noise being generated by the elec-tronics and the kTC noise of the charge collecting diode beingsuppressed, no significant differences exist between the outputnoise levels of S1–S3. For the pixels with basic CS amplifier, theinput referred noise is lower for the smallest diode (S1). The in-crease of the Temporal Noise at low frequencies is probably dueto the increase of low-frequency noise; and the increase of FPNabove 100 MHz is due to the reduced time available to chargethe auto-zeroing capacitors. Note that the chip is optimized towork at . The FPN remains well below theTemporal Noise, as it is needed for on-chip data sparsification.The noise results obtained for M16_1 and M16_3, which arevery close to the results of M16_2, will not be reported in thissection. However, the noise levels of the sub-arrays with bestperformances in terms of S/N will be given in the beam testssection together with other measured parameters. Note that the


Fig. 4. Measured (a) Temporal Noise and (b) FPN versus clock frequency for the 4 sub-arrays of M16_2 chip.

lowest input referred Temporal Noise levels are measured on S1of M16_1 and M16_2 , and the highest noise level onS3 of M16_3 .

Using a source, calibration peaks, cluster peaks (for3 3 pixels) and Charge Collection Efficiencies (CCE) havebeen evaluated. The distribution of hits for only one pixel,obtained at with a significant number ofevents recorded, is given in Fig. 5 for two sub-arrays of M16_2.The calibration peak of the source is clearly seen ( ADCUnits for S2 and ADC Units for S4), but correspondsto relatively rare events, when photons deposit all their energy(5.9 keV) on a single diode or very near. The Charge-to-Voltageconversion Factors (CVFs) obtained for these two sub-arraysare and respectively.

In order to study main events of charge deposition, the chargedistribution around a central pixel (where the charge is a max-

imum), has been analyzed. Fig. 6 shows the total charge collec-tion peak for clusters of 3 3 pixels for a M16_2 chip.

The ratio of the position of total charge collection peak overthe position of calibration peak gives the Charge Collection Effi-ciency (CCE). The CCEs measured on M16_1 and M16_2 chipsas a function of the clock frequency are given in Fig. 7. For thechip M16_2, this parameter has been measured up to

and no significant change hasbeen observed. CCE varies from 8% for S1 up to 52% for S4(Fig. 7(a)); and for M16_1 chips, from 7% for S1 up to 66% forS4 (Fig. 7(b)).

Note that the CCE is higher for M16_1 whose epi-layer thick-ness is smaller (14 ). In fact the epi-layer of this type ofsensor is not fully depleted. In spite of more charges generated inthe 20 epi-layer option (M16_2), more charges are diffusedto neighboring pixels and less charge is collected in a cluster of


Fig. 5. Signal distribution for one single pixel (number of hits versus signalamplitude) at a clock frequency of 100 MHz with the �� source, (a) for theS2 sub array (M16_2), and (b) for the S4 sub array (M16_2) (1 ADC Unit �� ).

3 3 pixels. The position of the calibration peak remaining un-changed, the CCE of M16_2 is lower for clusters of 3 3 pixels.

From these laboratory measurements, the estimated S/N ratiowith MIP’s for S1–S3 is lower than 10. It is clear that the diodesizes of these sub-arrays are too small for this process and verylittle charge is collected. The diode size of S4 being much larger,its CCE is higher.

To explore the simple amplifier circuit (like in S1–S3), a thirdchip, M16_3, has been submitted to fabrication with simple am-plifier and bigger diode sizes (see Table I). The sub-array S2 ofthis chip is identical to the S2 of M16_1 to get a reference. Un-fortunately this chip has been fabricated by mistake on a lightlydoped non-epitaxial substrate. As a consequence, lower CCEshave been observed on this chip with respect to M16_1 results:

for S1, for S2, and for S3.

B. Binary Outputs

The transfer curves for the global performance have been ob-tained using a dedicated data acquisition system. One transfercurve is related to one pixel and the corresponding column-leveldiscriminator. The transfer curves give the noise performance

Fig. 6. Signal distribution obtained with a �� source in a cluster of 3� 3pixels at the clock frequency of 100 MHz (a) for the S2 sub array (M16_2), and(b) for the S4 sub array (M16_2) (1 ADC Unit � �� ).

for both pixels and column level discriminators. Limited by thespeed of the data acquisition system, the measurements havebeen performed at . The curves have been ob-tained without input signal by varying the external thresholdvoltage in a certain range. For each pixel, the average of 1000events has been calculated for each threshold value. Fig. 8 showsthese normalized curves obtained on the whole pixels of twosub-arrays (S3 of M16_3 and S4 of M16_1). From these curves,one can estimate the mean systematic offset, the temporal noiseand the FPN of the analog signal path (pixels & discriminators).Note that the Temporal Noise is smaller for S4 of M16_1 thanthe noise for S3 of M16_3.

During beam tests, the threshold value applied is very im-portant because it influences the detection efficiency and thefake hit rate (see Section V). When there is no input signal,the random responses of a discriminator could be either “1” or“0” and the “1” is obviously caused by noise in this case. Byraising the threshold voltage, the probability of “1” caused bynoise can be reduced but the minimum input signal level will begreater on the other hand, reducing the sensitivity of the discrim-inator. Thus, the detection efficiency will be drawn down. On theother hand, if the threshold value is too small, the unwanted “1”caused by noise increases and leads to an increase of fake hit


Fig. 7. Charge Collection Efficiency versus clock frequency for the 4 sub-ar-rays of (a) M16_2 (� �� for S4,� �� for S3,� �� for S2 and� �� forS1), and (b) M16_1 (� �� for S4, � �� for S3, � �� for S2 and � ��

for S1). Clusters of 9 pixels were used.

rate. A compromise has to be found between the noise perfor-mance and the sensitivity of the discriminator. A preliminarystudy of different threshold values as a function of the pixelsresponses has been carried out. As an example, the responsesof three sub-arrays (S2, S3, S4) for M16_1 atare shown in Fig. 9 with and without source (100 kEvents wererecorded). We notice that with this threshold value, very fewpixels are activated by noise and more hits are recorded on S4(S4 having highest CCE).

V. BEAM TESTS RESULTS WITH MIPS

The three chips of MIMOSA16 series have been testedwith a 120 GeV/c positive pions beam in September 2007at CERN. The set-up used and the types of measurementsperformed are already described in [3]. The measurements havebeen performed at , due to the limitations ofthe acquisition system. A C++ based analysis software usingROOT interface under LINUX environment has been used toanalyze the experimental data. This software, called “MAF”(Mimosa Analysis Framework), has been developed by IPHCsince 2003. No survey has been done to make any preliminaryalignment corrections, so the final alignment has been made

Fig. 8. Normalized number of counts versus discriminator threshold voltagefor (a) S3 of M16_3, and (b) S4 of M16_1. The offset and the noise of the pixel& discriminator chain can be derived.

Fig. 9. Events (number of hits for each pixel) recorded on M16_1 (S2-S4)(a) Without source, (b) With source. (� � �� , Threshold voltage� �� ). 100 kEvents were recorded in each case.

by software using particles tracks. The alignment procedureis a simple minimization algorithm based on the assumption


Fig. 10. Temporal Noise measured in beam tests conditions for (a) S4 sub-arrayM16_1, (b) S3 sub-array of M16_3. The mean values are 14.7 � and 19.1 � ,respectively.

that the particle trajectory is a straight line. After the align-ment procedure of the MIMOSA16 chip with the 8 X and Ymicro-strip reference planes, the performances of the chip canbe calculated offline.

As it is impossible to show all the results for the 12 sub-ar-rays (3 chips 4 sub-arrays), only the 2 best sub-arrays (S4 ofM16_1 and S3 of M16_3) are illustrated in the continuation.

The first result concerns the noise level: the typical TemporalNoise obtained in beam test conditions are shown in Fig. 10 forS4 of M16_1 (a) and S3 of M16_3 (b). Noise level is very similarto those obtained in laboratory for the two chosen sub-arrays(14.7 and 19.1 respectively).

For the other M16_1 and M16_2 sub-arrays, the TemporalNoise is between 12 and 15 ; and for the other M16_3sub-arrays, between 13 and 20 . The Temporal Noise isslightly higher for the sub-arrays of M16_3 chip than the othersbecause the sizes of the diodes chosen for this chip are larger,and this increases the equivalent capacitance of the diode andthus the input referred noise. Anyway, this noise level is stillvery good.

One of the most important parameter for these chips is theS/N ratio, which has to be as great as possible. It should be atleast than 10, preferably greater than 15 for an efficient detec-tion of MIPs. This parameter has been improved with these newchips, compared to MIMOSA8 results [3]. This is mainly dueto the thicker epitaxial layer in MIMOSA16 and the increased

Fig. 11. Seed pixel S/N distribution obtained on analog test outputs with MIPsat � � �� : (a) S4 sub-array M16_1, (b) S3 sub-array of M16_3. TheMPVs are �� and �� , respectively.

in-pixel amplifier gain. Fig. 11 illustrates this improvement; theMost Probable Value of the S/N ratio is for S4 of M16_1and for S3 of M16_3. The results, in terms of S/N ratio,obtained with S4 of M16_1 (14 epi-layer) are very encour-aging.

One remark concerns the S/N results obtained with M16_2(20 epi-layer): the S/N ratio is equivalent to those obtainedwith M16_1, in spite of a thicker epi-layer for M16_2. Inprinciple, a thicker epitaxial layer chip should provide a highersignal because the particle is crossing a larger amount of sen-sitive material. But on the other hand, being a diffusion basedsensor, this could also result in a greater spread of the charge inneighboring pixels and in a lower charge collection efficiencybecause of charge recombination effect. This is also true for thenon-epitaxial option. Indeed, we notice a spread of the chargein the neighboring pixels in M16_2 and M16_3. For example,the total charge in a cluster of 3 3 pixels is higher in thecase of M16_2 than for M16_1 ( for a S4 cluster ofM16_1, and for same S4 cluster size of M16_2), butkeeping always the same charge inside the seed pixel (this isnot illustrated here with figures), which proves that increasingthe epi-layer thickness in this process is not necessarily a goodsolution. But increase of in-pixel amplifier gain is probably thebest solution with this process to improve the S/N ratio.

Another important parameter is the Detection Efficiency toMIPs, which is , with a Fake Hit Rate for


Fig. 12. Binary outputs Detection Efficiency as a function of the externalthreshold voltage of discriminators: (a) M16_1, (b) M16_3.

a discriminator threshold of (S4 of M16_1). This effi-ciency decreases only to 99.88% with a fake hit rate offor a discriminator threshold of (Figs. 12 and 13). Thisresult proves that we are able to provide a chip with a verygood MIP detection efficiency on a large range of discriminatorthreshold.

The hit multiplicity per pixel is also an important parameterfor the digital part. To give an order of magnitude for S4 ofM16_1, we found only of clusters with one pixel and

of clusters with one pixel for a discriminator thresholdof and respectively. Working at high discrim-inator thresholds, without degrading the detection efficiency isrecommended.

Finally, the Spatial Resolution, without multiple scattering, isstudied as a function of the discriminator threshold (illustrationof the results on Fig. 14). In spite of a pixel pitch of 25 , thesingle point resolution obtained is for S4 of M16_1 and

for S3 of M16_3 for a discriminator threshold of 5–6mV. This value is well below the binary resolution reflecting the25 pitch (7.2 ). This result can probably be explained bythe important charge collected in the pixels with this processand thus the barycenter of the CoG (Center of Gravity) methodis known with better precision.

Fig. 13. Digital Fake Hit Rate as a function of the external threshold voltageof discriminators: (a) M16_1, (b) M16_3.

Table II summarizes the most important parameters measuredat laboratory and at CERN for the best two sub-arrays for adiscriminator threshold value of .

VI. CONCLUSIONS

A higher Detection Efficiency and better Spatial Resolutionthan MIMOSA8 have been obtained with the MIMOSA16 chippresented in this paper. The column parallel architecture worksvery well and on-chip digital-to-analog coupling is well con-trolled.

Best results have been obtained with sub-array S4 of M16_1which has been fabricated on substrates with 14 epi-layer.With these results, we have been checked that at least onepixel sub-array fully satisfies EUDET-JRA1 Beam Telescoperequirements: A spatial resolution better than 5 , a readoutspeed of /frame (for 128 rows), and a very good detec-tion efficiency with low fake hit rate.

In the case of 20 epi-layer option (M16_2), the chargesdiffuse more laterally on neighboring pixels (well beyond theseed pixel) and then the spatial resolution is slightly degraded.For the third prototype M16_3, in spite of the lightly doped non-epitaxial substrates used by mistake, very good performances


TABLE IISUMMARY OF THE PERFORMANCES WITH MIPS FOR TWO SUB-ARRAYS ��

Fig. 14. Binary outputs Spatial Resolution as a function of the externalthreshold voltage of discriminators: (a) M16_1, (b) M16_3.

have been obtained on the sub-array S3 thanks to its pixel archi-tecture. In the future, its performances should be better whenfabricated on substrates with 14 epi-layer.

Another very important conclusion of the work on this chipis that the increase of in-pixel amplifier gain improves S/N ratioand consequently the spatial resolution. In the near future, otherchips will be designed developing this point. In the AMS CMOS0.35 Opto process, diodes sizes bigger than haveto be used to get a reasonable CCE.

Following the very encouraging results of MIMOSA16, alarger chip (MIMOSA22) with an active surface of(576 128 pixels), smaller pitch (18.4 ), with more op-timized pixels, JTAG, and more testability was submitted tofoundry at end of October 2007. This chip (IDC: IntermediateDigital Chip) is the last prototype before the final sensorsof EUDET-JRA1. The tests results were published at IEEENSS’2008 [6].

REFERENCES

[1] T. Haas, “A pixel telescope for detector R&D for an international linearcollider,” Nucl. Instrum. Methods Phys. Res. A, vol. A569, no. 1, pp.53–56, Dec. 2006.

[2] Y. Degerli et al., “A fast monolithic active pixel sensor with pixel levelreset noise suppression and binary outputs for charged particle detec-tion,” IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 3186–3193, Dec. 2005.

[3] Y. Degerli et al., “Performance of a fast binary readout CMOS activepixel sensor chip designed for charged particle detection,” IEEE Trans.Nucl. Sci., vol. 53, no. 6, pp. 3949–3955, Dec. 2006.

[4] A. Dorokhov et al., “NMOS-based high gain amplifier for MAPS,”presented at the 5th Int. Meeting Front-End Electronics, Perugia, Italy,May 17–20, 2006.

[5] A. Dorokhov et al., “Optimization of amplifiers for monolithic ac-tive pixel sensors,” in Proc. Topical Workshop Electronics for ParticlePhysics, Prague, Czech Republic, Sep. 3–7, 2007.

[6] M. Gelin et al., “Intermediate digital chip sensor for the EUDET-JRA1high resolution beam telescope,” in IEEE Nuclear Science Symp. Conf.Rec., Dresden, Germany, Oct. 19–25, 2008.

04782178

Documents

Transcript of 04782178