Post on 16-Jan-2023
3D chip-stackingtechnology withthrough-silicon viasand low-volume lead-free interconnections
K. SakumaP. S. AndryC. K. TsangS. L. Wright
B. DangC. S. Patel
B. C. WebbJ. Maria
E. J. SprogisS. K. Kang
R. J. PolastreR. R. Horton
J. U. Knickerbocker
Three-dimensional (3D) integration using through-silicon vias(TSVs) and low-volume lead-free solder interconnects allows theformation of high signal bandwidth, fine pitch, and short-distanceinterconnections in stacked dies. There are several approaches for3D chip stacking including chip to chip, chip to wafer, and wafer towafer. Chip-to-chip integration and chip-to-wafer integration offerthe ability to stack known good dies, which can lead to higheryields without integrated redundancy. In the future, with structureand process optimization, wafer-to-wafer integration may providean ultimate solution for the highest manufacturing throughputassuming a high yield and minimal loss of good dies and wafers. Inthe near term, chip-to-chip and chip-to-wafer integration may offerhigh yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3Dintegration after using a chip-to-wafer assembly process using 3Dchip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled andcharacterized using lead-free solder interconnections that were lessthan 6 lm in height. The average resistance of the TSV includingthe lead-free solder interconnect was as low as 21 mX.
Introduction
The refinement of integrated circuits has been doubling
the number of devices per chip area every two years,
following Moore’s Law. However, physics-based
constraints will force many changes in materials,
processes, and device structures as the industry moves
down to 32 nm and below. Consequently, it is
increasingly difficult to sustain this growth rate and
implement each successive generation of chip technology.
Three-dimensional (3D) integration technology is
expected to make it possible to extend the density growth
rate by stacking chips rather than by simply shrinking
device dimensions. Moreover, 3D integration makes it
possible to stack heterogeneous technologies or different
subsystems such as microelectromechanical systems,
radiofrequency devices, nanodevices, or sensors [1, 2], in
addition to processors and memory [3]. A processor chip
can be stacked on top of multiple memory chips by using
3D integration technology. Processors and memory
would be electrically connected through multiple vertical
interconnections.
Three types of 3D stacks are now emerging: wire-
bonded chip stacks, package on package, and package in
package. While these approaches allow known-good-
device testing prior to stacking devices, the disadvantages
include long connection lengths and limited connections
between chips. To overcome these wiring connectivity
problems, 3D chip-stacking technology using through-
silicon vias (TSVs) is attractive because it offers a way to
solve interconnection problems while also offering
integrated functions for higher performance [4–6]. Some
of the key technologies needed to enable chip stacking
include wafer bonding, wafer thinning, chip alignment,
and fabrication of TSVs with high-density lead-free
solder interconnects. Figure 1 shows a configuration of
face-to-back 3D chip integration. Each layer is electrically
�Copyright 2008 by International Business Machines Corporation. Copying in printed form for private use is permitted without payment of royalty provided that (1) eachreproduction is done without alteration and (2) the Journal reference and IBM copyright notice are included on the first page. The title and abstract, but no other portions, of thispaper may be copied by any means or distributed royalty free without further permission by computer-based and other information-service systems. Permission to republish any other
portion of this paper must be obtained from the Editor.
IBM J. RES. & DEV. VOL. 52 NO. 6 NOVEMBER 2008 K. SAKUMA ET AL.
611
0018-8646/08/$5.00 ª 2008 IBM
connected through the TSVs and high-density low-
volume lead-free solder interconnects. One approach uses
lead-free interconnections that have either a binary or a
ternary eutectic composition that gives a good bonding
yield and later forms a joint with a melting temperature
greater than 2508C.
In this paper, we describe a 3D chip-stacking
technology and investigate a joining process using low-
volume lead-free interconnects. We also present results of
fabrication and characterization of a 3D chip-stacking
test vehicle using chip-to-wafer technology.
3D chip integration technology
Three-dimensional chip integration is an attractive
technology to meet future performance needs of
integrated circuits [7–13]. Advantages can be realized in
power consumption [14], latency, area, and packaging
density, and the short vertical interconnects replace long
two-dimensional wires. For 3D chip integration, there
are different approaches under development. They
include chip-to-chip, chip-to-wafer, and wafer-to-wafer
approaches. Each has benefits and limitations.
Comparisons of 3D integration technologies are
summarized in Table 1.
Chip-to-chip and chip-to-wafer approaches
Chip-to-chip and chip-to-wafer integration may be
performed using high-precision flip-chip bonding. In
general, die sizes will be different when various different
technologies are used for assembling. Chip-to-chip and
chip-to-wafer integration technologies make it possible to
stack multiple known good dies (KGDs) with different
die sizes in layers [15, 16]. However, when chips are
bonded as arrays on a wafer, the process has to be
repeated as many times as the number of laminated chips
in the array. If precise alignment accuracy is required, the
process time for stacking each layer increases further [17].
Thus, because of the low expected fabrication
throughput, chip-to-chip and chip-to-wafer bonding
techniques may not ultimately be cost effective. These
technologies can be used when high yield or dies of
different sizes are needed for 3D integration.
Wafer-to-wafer approaches
Wafer-to-wafer integration technology may provide an
ultimate solution for the highest manufacturing
throughput if high yield and a minimal loss of good dies
and wafers can be realized [18–22]. Using wafer-to-wafer
integration technology would require raising the yield
much higher than currently possible. In addition, all
layers must be the same diameter size with the same or
similar technologies because all layers must be aligned at
the wafer level. Material and geometries become complex
because mismatches of thermal gradients between stacked
wafers will cause displacements during their bonding
process. The total yield of 3D integration using wafer-to-
wafer technology is determined by multiplying the yield
of each wafer in the stack [23]. Therefore, the compound
chip yield exponentially decreases as the number of
Thin
silicon
Back end of the line
MOSFET
Metal-oxide semiconductor
field-effect transistor
(MOSFET)
MOSFET Thin
silicon
Thick
silicon
TSV
Low-volume
lead-free
solder
interconnect
Figure 1
Three-dimensional chip stacking using the face-to-back approach.
ChipC4 solder interconnect Chip
Substrate
Low-volume lead-free
solder interconnect
<6 m
Silicon substrate
(a) (b)
80 m
Substrate
�
�
Chip
Chip
Intermetallic
compounds
Figure 2
Comparison between (a) C4 solder interconnect and (b) low-
volume lead-free solder interconnect.
K. SAKUMA ET AL. IBM J. RES. & DEV. VOL. 52 NO. 6 NOVEMBER 2008
612
stacked layers increases. However, this technology could
be used if the chip yield of each wafer is very high.
Key technologies for 3D chip stackingTo realize the chip-to-wafer 3D chip-stack technology,
our study focuses on the development of key technologies
such as multilevel 3D chip assembly and lead-free
interconnects. We describe these key technologies in more
detail in the following sections.
Low-volume lead-free solder interconnects
Materials composed of Sn/Pb have been widely used for
soldering as package-to-board or chip-to-substrate
interconnects. However, the use of lead-containing
solders is increasingly restricted because of environmental
concerns and related legislation [24]. In addition, because
of the need to minimize the wiring length between chips,
to increase the heat dissipation, and to shrink the design
rules in silicon, low-volume lead-free solder interconnects
are more desired than controlled-collapse chip connection
(C4) interconnects for 3D integration. Figure 2 compares
a C4 solder ball joint with a low-volume lead-free solder
interconnect. C4 solder interconnects need a larger
spacing between balls and higher joint gaps than low-
volume lead-free solder interconnects [8, 25]. Low-volume
lead-free solder interconnect, direct Cu-to-Cu bonding,
and conductive adhesives are the main candidates for
bonding materials for 3D integration. Cu-to-Cu bonding
is desirable since Cu has advantages such as high thermal
conductance and low electrical resistivity [26–29].
However, Cu-to-Cu bonding is achieved at a high
temperature since Cu has a high melting temperature.
High pressure and high co-planarity are also required. In
contrast, lead-free solder interconnects such as Sn or In
can be joined at a relatively low temperature and form an
intermetallic phase with a melting temperature much
higher than the low bonding temperature [30–32]. For
example, the melting point of In is 1568C and the melting
point of the resulting Cu/In intermetallic compound
(IMC) is expected to be more than 4008C, higher than the
standard solder reflow temperature (2608C) in the
subsequent bonding. This is a desirable feature for 3D
chip-stack processes because high thermal stability is
needed to allow repetition of the same bonding process
steps for subsequent chip-stack assemblies. In addition, a
low-temperature bonding process has the potential to
overcome issues such as wafer or chip warpage during
bonding. In this work, Cu/Sn, Cu/Ni/In, and Cu/In were
evaluated as lead-free solder interconnect material
candidates for 3D chip stacks.
Reliability of low-volume lead-free solder
interconnects
The test vehicles were fabricated using a standard
lithography process to investigate the mechanical reliability
of the lead-free solder interconnects. The pad structures
on the silicon substrates contained an outermost layer of
Ni, followed by a thin layer of immersion Au. As lead-
free solder interconnects, bumps with less than 6 lmin thickness and 100 lm in diameter on a 200-lmpitch with a 4-mil-on-8-mil spacing (1 mil ¼ 25.4 lm)
were fabricated on the silicon chip. Cu (3 lm)/Sn,
Cu (1 lm)/Sn, Cu/Ni/In, and Cu/In formed uniformly by
an evaporation process were about 3 lm/3 lm, 1 lm/3 lm,
3 lm/0.5 lm/2 lm, and 3 lm/1.5 lm height, respectively.
Mechanical shear tests were done at room temperature
on the bonded samples to determine the shear strength
per bump. The chips were initially cleaned after dicing
before bonding experiments. The cleaning prior to
bonding improved bonding yield and joint strength of the
Cu/Ni/In alloy composition.
The relationship between shear strength per bump and
bonding temperature is shown in Figure 3(a). The shear
strength of Cu/In is found to be lower than the strength
of both Cu/Sn and Cu/Ni/In. In addition, there were
optimal bonding temperatures to achieve maximum shear
strength per bump for both Cu/Ni/In and Cu/In, but the
shear strength of the Cu/Sn joints was relatively
unchanged by the bonding temperature. A possible
explanation for the increase in shear strength per bump
with temperature is that increasing the temperature also
increases the reaction rate, so more IMC is formed during
the chosen bonding time. When the joints are bonded
above the optimal bonding temperature to achieve
maximum shear strength for a chosen bonding time, a
Table 1 Features of 3D integration technologies.
Chip to chip and chip to wafer Wafer to wafer
Alignment required Die size Wafer scale
Yields High (select known good die) Low (multiplying the yield of each wafer)
Throughput on stacking Low High
Suitable for Both common size and dissimilar size Common size
IBM J. RES. & DEV. VOL. 52 NO. 6 NOVEMBER 2008 K. SAKUMA ET AL.
613
thicker nonductile intermetallic layer is probably formed,
causing the interconnections to be less resistant to shock.
Figure 3(b) shows the relationship between shear
strength per bump and bonding temperature. The shear
strength ofCu (3lm)/Sn is higher than that ofCu (1lm)/Sn,
but there is little change in shear strength as the bonding
times vary. The mechanism determining an optimal
bonding time to achieve maximum shear strength for a
chosen bonding temperature is still unclear, since for all
bonded samples the shear strength remained fairly
constant. This seems to suggest that 90 seconds is enough
time to sufficiently form the IMCs, and the shear strength
of each sample changes little when the bonding time is
extended to 300 seconds.
Electronic devices are especially prone to failure due to
mechanical shock. To characterize the joint reliability of
these lead-free solder interconnects for a potential heat
sink to be attached to the top of the stacked chips,
mechanical shock tests were conducted with the bonded
samples. Cu/Ni/In and Cu/Sn chips were bonded with
optimal bonding parameters. In addition, the samples of
eutectic Pb/Sn C4s were bonded to the same substrates
with the same pitch for comparison. Bonded chips were
glued on metal carriers, which were mounted on support
pins with screws at a fixture. The reliabilities of different
chips were studied using simulated heat sinks with two
different weights of 27 g/cm2 and 54 g/cm2. These were
attached to the top of the chips with epoxy. Various
shock loading conditions, such as a peak deacceleration
of 100 multiples of gravity (G) for 2-ms duration, 200 G
for 1.5-ms duration, and 340 G for 1.2-ms duration, were
used in accordance with JESD22-B110 Service Condition
C, D, and E [33]. The components were subjected to five
shock pulses of the peak level. The impact shock results
are shown in Table 2. The results showed that the samples
of eutectic Pb/Sn met all of the targets in the impact
shock tests. However, the samples of Cu/Sn did not meet
the targeted impact shock test objectives with the
simulated heat sinks of 27 g/cm2 and 54 g/cm2. In the
same tests, the samples of Cu/Ni/In met the targeted
impact shock testing objectives for 27 g/cm2. The
Cu/Ni/In chips, formed without IMCs throughout the
pad volume, had better resistance to impact shocks than
the Cu/Sn samples with brittle IMCs formed at the
interface.
The lead-free interconnects such as Cu/Ni/In, Cu/In,
and Cu/Sn were cross-sectioned and characterized by
scanning electron microscope (SEM) and energy-
dispersive x-ray spectroscopy (EDX) to analyze the
IMCs, as shown in Figure 4. Figure 4(a) shows that the In
solder reacted with Cu and Au and formed an IMC in
very small areas, not all over the pad surface. It is possible
to form Cu/In IMCs in this structure because Cu will
diffuse through the Ni, even at room temperature. For
Cu/In IMCs, there are about three IMCs in the phase
diagram (gamma, eta, and phi phases) between 30 and 50
atomic percent In. The percentage of In present and the
temperature determine the phase of the Cu/In alloy, and
the physical characteristics are different based on each
phase of the alloy. In order to investigate the effects of the
Ni layer, a Cu/Ni/In interconnect was fabricated since the
Ni layer prevents the formation of the Cu/In intermetallic
layer over the entire surface of the pad. Figure 4(b) shows
that the Cu/In IMC formed throughout the pad volume,
although the soldered area to the substrate pad was
limited. Figures 4(c) and 4(d) show that Cu/Sn
interconnects formed an IMC throughout the pad volume
with good wetting. In Figure 4(c), the Cu/Sn IMC would
be mostly Cu6Sn5 with some alloy additions of Ni and Au
as the thickness of Au and Ni used is very small compared
Cu/Ni/In Cu/In Cu (3 m)/Sn Cu (1 m)/Sn
0
20
40
60
80
100
50 100 150 200 250 300
Bonding time (s)
(b)
Str
eng
th p
er b
um
p (g
ram
-fo
rce)
0
20
40
60
80
100
100 150 200 250 300 350 400
Bonding temperature (°C)
(a)
Str
eng
th p
er b
um
p (
gra
m-f
orc
e)
� �
Figure 3
Shear strength per bump: (a) as a function of bonding temperature
for interconnect metallurgy candidates. Cu/Ni/In and Cu/In, with
bonding conditions of 2.9 Kgf/cm2 and 150 seconds and Cu/Sn, with
bonding conditions of 4.1 Kgf/cm2 and 90 seconds; (b) as a function
of bonding time for interconnect metallurgy candidates. Cu/Ni/In
and Cu/In, with bonding conditions of 1808C and 2.9 Kgf/cm2 and
Cu/Sn, with bonding conditions of 3508C and 4.1 Kgf/cm2.
K. SAKUMA ET AL. IBM J. RES. & DEV. VOL. 52 NO. 6 NOVEMBER 2008
614
with the thickness of Cu and Sn. If Cu3Sn is formed, it
would be in a small amount. Two different thickness
ratios of Cu and Sn were tested to investigate the
relationship between Cu/Sn IMC and Cu thickness. All of
the Cu reacted with the Sn and Au when the Cu thickness
was 1 lm. It seems that the Cu/Ni/In had better resistance
to mechanical shock than the Cu/Sn chips with IMC
formation in the interface.
TSV/3D chip fabrication
The TSV is one of the key 3D integration-enabling
technologies for replacing wire bonding because it can
provide vertical area-array connections and address many
of the limitations of current chip-stacking methods. In
general, the fabrication of TSVs has the following process
steps: via formation, sidewall insulation, filling the via
with conducting material, and connecting to terminals or
wires. For low contact resistance and high reliability, the
filled via must be void-free. A variety of structures and
processes have been demonstrated using copper,
tungsten, and other materials. Each process flow in the
fabrication of TSVs has its own challenges, and the
structure as well as the choice of materials for filling the
via depend on the specific application of the 3D
integration [34, 35]. In this work, tungsten-filled annular
vias with gaps of 4 lm and diameters of 50 lm were
exclusively used to form the 3D interconnects [8, 36–38].
The fabrication sequence is summarized below.
Figure 5 shows the TSV process flow for both top chips
with wiring links and TSV-only stackable chips with vias
and pads. In order to reduce the metal volume within the
via and to diminish the effects of the coefficient of thermal
expansion (CTE) mismatch between the metal conductor
and silicon, annular vias instead of the standard
cylindrical vias were fabricated. The annular vias are
formed by Bosch-type deep reactive-ion etching [39],
after which they are insulated by thermal oxidation and
filled with chemical vapor deposition (CVD) tungsten,
followed by standard polishing. Since the CTE of
tungsten (5 ppm/8C) is close to bulk Si, there is less plug
displacement during repeated thermal cycles to 4008C
compared with copper (17 ppm/8C). Once the via filling is
completed, a single damascene Cu pad is added on top of
the vias. As shown in Figure 5, this is a branch point in
the process. The top chip wafers continue along the
standard route where another BEOL (back-end-of-line)
Cu level of wiring with conventional Cu damascene steps
is used to build the links that will complete the chains.
The stackable wafers, which have topside pads but no
wiring links, are sent for electroless Ni/Au deposition.
Both kinds of wafers rejoin the same process stream
where glass handling wafers are attached for mechanical
support during wafer grinding. All of the wafers are
thinned to a desired thickness by mechanical grinding and
chemical-mechanical polishing (CMP). The bottoms of
the tungsten-filled vias are exposed, followed by an
insulation process on the backsides using plasma-
enhanced CVD and a final CMP step to expose the via
metal. The final wafer-level processing step is deposition
of the bottom pad and lead-free joining metal by
evaporation through an aligned mask.
3D chip-stack assembly and reliability
Fundamental characteristics of the 3D chip stacks were
demonstrated. Stacks of multilayer thin silicon that
were up to six chips high with annular tungsten TSVs and
Table 2 Results of impact shock test for three interconnect metallurgies. The bonding conditions for Cu (3 lm)/Sn were 3508C,
150 seconds, and 4.1 Kgf/cm2, and the bonding conditions for Cu/Ni/In were 2858C, 150 seconds, and 2.9 Kgf/cm2.
Test sample Input gravity/time
duration (G/ms)
Simulated heat sink
No mass (pass/fail) 27 g/cm3 (pass/fail) 54 g/cm3 (pass/fail)
Cu (3 lm)/Sn 110/2.19 Pass Fail Fail
168/1.65 Pass * *
346/1.25 Pass * *
Cu/Ni/In 109/2.20 Pass Pass Fail
181/1.65 Pass Pass *
321/1.26 Pass Pass *
Eutectic Pb/Sn 101/2.21 Pass Pass Pass
179/1.65 Pass Pass Pass
322/1.26 Pass Pass **
* denotes no test; ** denotes glue failure.
IBM J. RES. & DEV. VOL. 52 NO. 6 NOVEMBER 2008 K. SAKUMA ET AL.
615
Cu/Ni/In lead-free solder interconnects on silicon
substrates were assembled using the test vehicles. A
detailed description of the test-vehicle structure and
electrical characterization of stacked chips is presented in
the following subsections.
Test-vehicle structure and assembly
To test the 3D chip stacks, primary electrical test vehicles
including a top-link chip, a TSV carrier, and a substrate
were designed. The top-link chip and the substrate
contained the Cu wiring links to form via chains in the
module, while the TSV carrier contained only top-side
pads, TSVs, and lead-free solder interconnects. Cu/Ni/In
was chosen as the interconnect material because of its
superior mechanical shock test results. Tungsten is used
as a conductor in TSVs. Each layer was fabricated using
CMOS technology and can be prepared separately for
stacking. Both the top-link chip and the TSV carrier had
24 subdie arrays. The size of a subdie arraywas 1237.5mm,
and each array contained 60 rows3 36 columns of
4-mil-on-8-mil-spaced TSVs, pads, and backside lead-free
metallurgy. The matching silicon substrates contained the
Cu wiring with electroless Ni and immersion Au as the top-
surface metallurgy. A number of shorter chains ranging
from 4 to 20 links in each module were made for electrical
measurements, and long chains with 204 links were made to
Pt1Pt2Pt3
Pt4 Pt5Pt6
Pt7
Chip
Substrate
Pt1 � Cu
Pt2 � Ni
Pt3 � In, Au, Ni
Pt4 � In, Au, Cu
Pt5 � In
Pt6 � Ni
Pt7 � Cu
Chip
Substrate
Pt1
Pt2Pt3
Pt4
(b)
Pt1 � Cu
Pt2 � Cu, In
Pt3 � Ni, Au
Pt4 � Ni, P
Pt5 � Cu Pt5
Chip
Substrate
Pt1Pt2
Pt3
Pt4
(d)
Pt1 � Cu, Sn, Au
Pt2 � Sn
Pt3 � Ni, P
Pt4 � Cu
Chip
Substrate
Pt1
Pt2
Pt3Pt4
Pt5
Pt6Pt7
(c)
Pt1 � Cu
Pt2 � Cu, Sn
Pt3 � Ni, Cu, Au, Sn
Pt4 � Ni, Cu, Au, Sn
Pt5 � Ni, P (dark
region P rich —
depletion of Ni)
Pt6 � Ni, P
Pt7 � Cu
(a)
1 m�
2 m�
1 m�
1 m�
Figure 4
Cross-section scanning electron microscrope and energy-dispersive
x-ray spectroscopy analysis for (a) Cu/Ni/In with bonding
conditions of 1808C, 150 seconds, and 2.9 Kgf/cm2, (b) Cu/In,
with bonding conditions of 1808C, 150 seconds, and 2.9 Kgf/cm2,
(c) Cu (3 lm)/Sn, with bonding conditions of 3508C, 90 seconds,
and 4.1 Kgf/cm2, and (d) Cu (1 lm)/Sn, with bonding conditions of
3508C, 90 seconds, and 4.1 Kgf/cm2. (Parts [a], [c], and [d] �2007
IEEE. Reprinted with permission from Reference [8].)
Tungsten via
Copper pad
Silicon
Glass handler Glass handler
Wiring links
Joining metal
Ni/Au pad
Joining metal
Figure 5
Annular metal TSV process flow. Following common TSV etch
and metal fill steps, two styles of 3D test chips were fabricated: top
chips with wiring links (left) andTSV-only stackable chips withNi/Au
pads (right).
K. SAKUMA ET AL. IBM J. RES. & DEV. VOL. 52 NO. 6 NOVEMBER 2008
616
measure the electrical resistance and yield of the TSVs and
lead-free solder interconnects.
To stack the individual chips, as in the chip-to-chip or
the chip-to-wafer approach, the wafers for the top-link
chips and TSV carriers were diced for the required
dimensions. The thinned silicon chips with glass handler
intact were joined to the silicon substrates after careful
alignment using a precision flip-chip bonder, after which
the laminated glass was removed. The Ni/Au top-surface
metallurgy pads of the TSV-only chips mirrored the
substrate pads, and the top-link chips were stacked and
joined in the same way. The 3D chip integration is done
by repeating this sequence. In this face-to-back 3D
integration process, each layer is stacked in the same
orientation as the bottom silicon substrate that acts as the
supporting material.
Electrical characterization
The multilayer chip-stack samples were fabricated to
evaluate the yield and average electrical resistance of each
TSV and lead-free solder interconnect using the test-
vehicle variable length chains. Figures 6(a) and 6(b) show
a SEM image and a nondestructive x-ray image,
respectively, of a six-layer chip stack on a supporting
silicon substrate. The pads on the surface of the
supporting substrate are used for contact with the
backside bump interconnects to the chip stack and also
for probe testing. Figure 6(c) shows the cross-sectional
SEM image of a 3D chip stack. The six layers are
vertically stacked and connected by TSVs and bumps.
The stacked chips appear to be in good alignment and the
annular vias are completely filled with tungsten. Each
stacked chip thickness is approximately 70 lm, and the
Cu/Ni/In lead-free solder interconnects are 100 lm in
diameter and 5.5 lm in thickness.
Figure 7 shows the direct current resistance of the link
chains in the 3D chip-stacking test vehicles. The measured
total resistance of the link chains is indicated by the left
axis, and the resistance of a single TSV plus lead-free
solder interconnect by the right axis. The total resistance
of the link chains includes the TSVs, bump interconnects,
and link wiring. A total of six different locations were
measured for each sample. The resistances of the one-
layer, three-layer, and six-layer chip stacks on supporting
silicon substrates are shown with total average resistances
of 1.16 X, 1.24 X, and 1.38 X, respectively. This shows
that shorting defects did not occur in the link chains and
that the total resistance of the link chains increases as a
function of the number of links chains. Since the Cu
wiring links are the dominant component, the resistances
are comparable. These results show that the average
resistance of a single TSV plus a lead-free solder
interconnect is approximately 21 mX, an acceptably low
value.
(a)
(b)
(c)
70 m � 6
Six-layer TSV
chip stack
Si substrate
�
�
Lead-free solder
interconnect
Annular
TSV
Au/Ni pad
Si substrate
Annular
metal TSV
Lead-free
solder
interconnect
70 m
Silicon
Figure 6
A 3D chip-stack sample: (a) Scanning electron microscope (SEM)
image and (b) nondestructive x-ray image of stacked six-layer chip
on a silicon substrate using chip-to-wafer integration process. (c)
Cross-sectional SEM image of a chip stack. The annular vias are
filled with tungsten.
IBM J. RES. & DEV. VOL. 52 NO. 6 NOVEMBER 2008 K. SAKUMA ET AL.
617
To evaluate the thermal reliability of the
interconnections, deep thermal cycling from �558C to
1258C based on the JEDEC standard [33] with two cycles
per hour was performed using eight different 204-link
chains in a one-layer stack on a silicon substrate sample
without underfill. The resistance of each chain was
monitored up to 1,200 cycles with no failures occurring in
any of the link chains. This result indicates that the
interconnections including the tungsten annular vias and
the Cu/Ni/In interconnects have good thermal cycling
performance. Other reliability tests including
electromigration, temperature, and humidity bias testing,
high-temperature storage, and shock and vibration
testing are underway.
Summary and conclusionsThree-dimensional integration is emerging as an
approach to achieve high bandwidth, high performance,
and high functionality and to reduce the complexity of
interconnects. In this paper, a 3D chip integration
technology and characterization of low-volume lead-free
interconnections and TSVs were described. Three
different lead-free solder interconnect metallurgies were
studied in detail. Cu/Sn shows good thermal stability and
exhibits the strongest shear strength per bump of all the
metallurgies studied, but it did not pass the impact shock
test when simulated heat sinks with masses of 27 g/cm2
and 54 g/cm2 were attached. In contrast, the Cu/Ni/In
chips passed the impact shock test for a simulated heat
sink mass of 27 g/cm2. In addition, we fabricated a 3D
chip-stacking test vehicle using chip-to-wafer technology
and demonstrated the fundamental characteristics of the
3D chip stacks. Some six-layer chip stacks on silicon
substrates were produced. Electrical resistance
measurements on the daisy chains revealed a combined
single TSV plus lead-free solder interconnect resistance of
approximately 21 mX.
Future work on 3D chip-stacking technology will
include the assessment of thermal management, fine-pitch
low-volume lead-free interconnect, high precision
alignment, robust thin chip handling for backside
processing, mechanical reliability, high-frequency signal
characterization, and active circuit integration for
advanced 3D integration.
AcknowledgmentsWe acknowledge the support given by R. Sirdeshmukh,
D. Dimilia, and M. Farinelli, Central Scientific Services
Group; Microelectronics Research Laboratory at the
IBM Thomas J. Watson Research Center; K. Sueoka, F.
Yamada, K. Matsumoto, and A. Horibe, IBM Tokyo
Research Laboratory; Y. Orii and Y. Oyama, IBM
Systems and Technology Group in Kyoto; and G.
Advocate, F. Dicesare, J. Rosa, C. McCarthy, M. Griffin,
E. Kastberg, and G. Embler, Analytical Group, IBM
Systems and Technology Group in East Fishkill, New
York. We acknowledge management support and
encouragement from H. Yamaguchi, K. Kawase, N.
Morimoto, T. Chainer, D. Seeger, and T.-C. Chen during
this research.
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0.0
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Three-layer stack on substrate (via:6, bump:6)
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Figure 7
Electrical resistance of one-layer, three-layer, and six-layer chip
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Received January 9, 2008; accepted for publication
Katsuyuki Sakuma IBM Research Division, IBM TokyoResearch Laboratory, 1623-14 Shimo-tsuruma, Yamato-shi,Kanagawa-ken 242-8502, Japan (sakuma2@jp.ibm.com).Mr. Sakuma is a Research Staff Member in the Electronic andOptical Packaging Group. He holds B.S. and M.S. degrees inmechanical engineering from Tohoku University, Japan. He iscurrently pursuing his Ph.D. degree in advanced science andengineering from Waseda University, Japan. He joined the IBMTokyo Research Laboratory in 2000 working on the research anddevelopment of a liquid crystal display source driver. Following anassignment in the IBM Research Division, Thomas J. WatsonResearch Center, New York, he returned to the Tokyo ResearchLaboratory and is now the leader of 3D chip-stacking research. Hisresearch interests include high-density, low-volume solderinterconnections, system-on-package, wafer-level packaging, and3D integration technologies. He is an author or coauthor of morethan 22 conference and journal publications and holds seven issuedor pending patents. He was an associate editor of the Institute ofElectronics, Information and Communication Engineers (IEICE)from 2003 until 2005. He is a member of the IEICE, the JapanSociety of Applied Physics, and the Japan Institute of ElectronicsPackaging.
Paul S. Andry IBM Research Division, Thomas J. WatsonResearch Center, P.O. Box 218, Yorktown Heights, New York10598 (andry@us.ibm.com).Dr. Andry is a Research Staff Memberat the IBM T. J. Watson Research Center. He joined IBM in 1997,working in the Advanced Display Technology Laboratory on avariety of projects including prototypes of the world’s highestinformation content display, as well as the world’s first a-Si-drivenOLED (organic light-emitting diode) display. After serving asTechnical Assistant to the Vice President of Science andTechnology, he returned to technical work in the System-on-Package Group where he has been working on development of key3D technology elements and applications of silicon-carriertechnology. He is a coeditor of the book Thin Film Transistors,author or coauthor of more than 35 professional publications, andholder of more than 30 issued or pending patents. Dr. Andryreceived his B.Sc. degree (1986) in physics from the University ofWaterloo, Ontario, Canada, his M.Sc. degree (1990) in physicsfrom the Universite de Sherbrooke, Quebec, Canada, and hisPh.D. degree (1997) in materials science from the University ofVermont, Burlington. He has received two Outstanding TechnicalAchievement Awards, two Technical Group Awards, one ResearchDivision Award, and eight IBM Invention Plateau Awards.
Cornelia K. Tsang IBM Research Division, Thomas J. WatsonResearch Center, P.O. Box 218, Yorktown Heights, New York10598 (cktsang@us.ibm.com). Ms. Tsang is a Senior Engineer atthe IBM T. J. Watson Research Center. She joined the IBMResearch Division in 2001 and has worked since then in theSystem-on-Package Group on novel process development andintegration of silicon-based packages. Her research interestsinclude through-silicon via technology, silicon-carrier integration,3D integrated circuits, chip stacking, and various types of chip-and wafer-level assembly and bonding. She is an author orcoauthor of more than 17 professional publications and holder of16 issued or pending patents. Ms. Tsang received her B.S. and M.S.degrees in materials science and engineering from theMassachusetts Institute of Technology in 2000 and 2001,respectively.
Steven L. Wright IBM Research Division, Thomas J. WatsonResearch Center, P.O. Box 218, Yorktown Heights, New York10598 (wrightsl@us.ibm.com). Dr. Wright is a Research StaffMember in the System-on-Package Group within the Electronic
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March 3, 2008; Internet publication October 24, 2008
and Optical Packaging Department. He received B.S. and M.S.degrees in electrical engineering from the University of Colorado in1975 and 1978, working in the area of liquid-phase epitaxialgrowth of III–V compound semiconductor heterojunctions. Hereceived a Ph.D. degree in electrical engineering from theUniversity of California, Santa Barbara in 1982. His doctoratework involved the first successful growth of GaP on Si bymolecular beam epitaxy, as well as fabrication of a heterojunctionbipolar transistor with a wide bandgap emitter. Since the start ofhis career at IBM in 1982, he has worked in the areas of materialsscience and device physics of III–V compound semiconductorheterojunctions, liquid-crystal amorphous Si flat panel displaytechnology, development and marketing of high-resolutionvisualization technology, and silicon-carrier packaging technology.He is currently focusing on test and reliability issues for silicon-carrier technology. Dr. Wright has received six IBM InventionAchievement Awards and three Research Division Awards, and hehas contributed to more than 150 publications.
Bing Dang IBM Research Division, Thomas J. WatsonResearch Center, P.O. Box 218, Yorktown Heights, New York10598 (dangbing@us.ibm.com). Dr. Dang is a Research StaffMember in the System-on-Package/3D Integration Group. He hasworked on various research projects including compliant wafer-level packaging, fine-pitch flip-chip, 3D chip-stacking andintegration, and thermal management technologies. He received hisPh.D. degree in electrical and computer engineering at GeorgiaInstitute of Technology in 2006. He also holds three M.S. degreesin electrical and computer engineering, materials engineering, andmetallurgical physical chemistry. He received his B.S. degree inmetallurgical physical chemistry at the University of Science andTechnology, Beijing, China, in 1995. He has authored andcoauthored more than 40 publications in international conferencesand journals in the field of integrated circuit packaging. He hascontributed to eight patent applications. Dr. Dang received a BestInvited Paper Award at the IEEE 2007 Custom Integrated CircuitsConference and an Outstanding Paper Award at the IEEE 2007Electronic Components and Technology Conference. He is amember of the IEEE.
Chirag S. Patel IBM Research Division, Thomas J. WatsonResearch Center. Dr. Patel is a Research Staff Member in theScience and Technology Department at the IBM T. J. WatsonResearch Center. He holds B.S., M.S., and Ph.D. degrees, all inelectrical engineering, from the Georgia Institute of Technology. In2001, he joined the IBM Research Division, where he continues towork on the design and characterization of advanced andexploratory systems based on silicon handler technology. He is anauthor or coauthor of more than 50 technical papers.
Bucknell C. Webb IBM Research Division, Thomas J. WatsonResearch Center, P.O. Box 218, Yorktown Heights, New York10598 (bcwebb@us.ibm.com). Dr. Webb is a Research StaffMember working in the System Measurement and Test group. Hereceived a B.A. degree in physics from Harvard University and aPh.D. degree in physics from Cornell University for studies on thefar-infrared reflectivity of valence-fluctuating compounds,primarily CePd3. He joined IBM in 1988, working initially withoptical imaging and the high-frequency (100-MHz) magneticresponse of magnetic thin films such as in disk drive recordingheads. In 1992, he and his group began work on what wouldbecome the self-servo-writing process used to create the servo dataon disk drives. In 2002, Dr. Webb shifted to working on thermaland thermomechanical problems in microelectronics, with a focuson technology and applications of silicon interposers. He is anauthor of more than 24 scientific papers and 33 U.S. patents.
Joana Maria University of Illinois Urbana–Champaign,201 Materials Science and Engineering Building, 1304 W. GreenStreet, Urbana, Illinois 61801. Miss Maria holds a B.S. degree inengineering physics from the New University of Lisbon, Portugal,and an M.S. degree in physics from the University of IllinoisUrbana–Champaign. She joined the Professor John A. Rogersgroup at the University of Illinois at Urbana–Champaign in thesummer of 2003 to pursue her Ph.D. degree in materials scienceand engineering. In the summer of 2006, she did an internship atthe IBM Thomas J. Watson Research Center where she worked onchip stacking with lead-free interconnect solders.
Edmund J. Sprogis IBM Systems and Technology Group,1000 River Street, Essex Junction, Vermont 05452(u6474@us.ibm.com). Mr. Sprogis holds the B.S.E.E. degree fromWorcester Polytechnic Institute and the M.S.E.E. degree from theUniversity of Vermont. He joined IBM in 1978 performingelectrical characterization and defect diagnostics in various logictechnologies. He then moved into DRAM technology developmentand worked on advanced cell structures, architectures, anddesigning novel test vehicles for the characterization of 4-Mb to1,284-Mb generation DRAM cells. In 1994, he served as leadengineer for several packaging development projects ranging fromstacked die packages to silicon cubes. He is currently a SeniorEngineer and, since 2002, has been developing and qualifying TSVtechnology for high-performance 3D applications.
Sung K. Kang IBM Research Division, Thomas J. WatsonResearch Center, P.O. Box 218, Yorktown Heights, New York10598 (kang@us.ibm.com). Dr. Kang is a Research Staff Memberin the Electronic and Optical Packaging Department. He holds aB.S. degree in metallurgical engineering from Seoul NationalUniversity, Korea, and a Ph.D. degree in materials science andmetallurgy from the University of Pennsylvania. He has worked onmicroelectronic interconnection technologies and materials, andrecently on conducting adhesives and lead-free solderingtechnologies. He received an IBM Outstanding Quality TeamAward, IBM Research R&D Award, and two IBM ResearchExternal Honors Awards. He is an author or coauthor of 115technical papers and holds 36 U.S. patents. Dr. Kang is a seniormember of the IEEE.
Robert J. Polastre IBM Research Division, Thomas J. WatsonResearch Center, P.O. Box 218, Yorktown Heights, New York10598 (polastr@us.ibm.com). Mr. Polastre is an Advisory Engineerworking in the System-on-Package Group. He joined the IBMResearch Division in 1983. He holds a B.S. degree in electronictechnology from LaSalle University. He received two IBMOutstanding Technical Achievement Awards and an IBMCorporate Award for his work on array testing of thin-filmtransistors. He is the author or coauthor of several papers onautomated and thermal testing and is a coinventor of severalpatents in these areas.
Raymond R. Horton IBM Research Division, Thomas J.Watson Research Center, P.O. Box 218, Yorktown Heights,New York 10598. Mr. Horton is a Staff Engineer. He is a memberof the System-on-Package Group and is responsible for bonding,assembly, and testing of interconnections. His work experienceincludes flat-panel display assembly and test and packaging. He isthe coauthor of numerous technical publications and patents.Mr. Horton is the recipient an IBM Outstanding TechnicalAchievement Award.
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John U. Knickerbocker IBM Research Division, Thomas J.Watson Research Center, P.O. Box 218, Yorktown Heights,New York 10598 (knickerj@us.ibm.com). Dr. Knickerbocker is anIBM Distinguished Engineer. He is Manager of theSystem-on-Package/3D Integration Group. He holds a Ph.D.degree in engineering from the University of Illinois. He worked inIBM Microelectronics at East Fishkill, New York, from 1983 to2003 where he held a series of engineering and managementpositions leading to director of IBM worldwide packagingdevelopment. In 2003, he joined the IBM Research Division, wherehe has led the development of next-generation 3D siliconintegration including die stacking and silicon packaging, eachwith TSVs, thinned silicon, and fine-pitch interconnection.Dr. Knickerbocker has received an IBM Corporate Award, threeDivision Awards, and 39 Invention Plateau awards. He hasauthored or coauthored 150 patents or patent applications andmore than 40 technical papers and publications. He serves as amember of the Sematech 3D working group. He has been amember of the IEEE, IMAPS, and is a Fellow of the AmericanCeramic Society.
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