Thermomechanical Reliability of Nickel Pillar Interconnections Replacing Flip-Chip Solder Without...

IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 31, NO. 4, OCTOBER 2008 341

Thermomechanical Reliability of NickelPillar Interconnections Replacing Flip-Chip

Solder Without UnderfillAnkur O. Aggarwal, P. Markondeya Raj, Baik-Woo Lee, Myung Jin Yim, Member, IEEE, Mahadevan Iyer,

C. P. Wong, Fellow, IEEE, and Rao R. Tummala, Fellow, IEEE

Abstract—Interconnect technologies between ICs and packagesor boards have a significant impact on the IC performance andpackaging density. Today, the interconnections are typically ac-complished with either wire bonding or flip-chip solders. Whileboth of these technologies are incremental, they also run intoeither electrical or mechanical barriers as they are extendedto higher density of interconnections. Downscaling traditionalsolder bump interconnect might not satisfy the thermomechanicalreliability requirements at very fine-pitches. Alternate intercon-nection approaches such as compliant interconnects typicallyrequire lengthy connections and are therefore limited in terms ofelectrical properties, although expected to meet the mechanicalrequirements. This paper reports fine-pitch interconnection tech-nologies using nano-structured nickel as primary interconnectionmaterial. The nano-grained nickels are produced by electro-plating process. The primary nano-structured interconnects areassembled with different bonding methods to provide organiccompatible low-temperature fabrication. Au–Sn and Sn–Cu areused for solder-based assembly of nano-nickel interconnections.Low modulus anisotropic conductive films (ACFs) are also usedas an alternate bonding route of the solders. No underfilling isused in all the interconnect structures evaluated in this paper.Assembly are accomplished on different coefficient of thermalexpansion (CTE) substrates including FR-4 with 18 ppm C,advanced organic substrates with 10 ppm C, novel low CTE(3 ppm C) substrates based on Carbon–Silicon Carbide (C–SiC).The thermomechanical reliability of all the nano-interconnectsassembled on different CTE substrates with different bonding ap-proaches is evaluated by thermal shock testing and finite-elementanalysis. Nano-nickel interconnects bonded with the ACF showedthe highest reliability withstanding 1500 cycles. In all cases, noapparent failure was observed in the primary nano-nickel metalinterconnects. This technology is expected to be easily downscaledto submicrometer and nano-scale unlike the current solder tech-nologies leading to true nano-interconnections.

Index Terms—Anisotropic conductive film (ACF), failure anal-ysis, fine-pitch interconnects, nano-structured interconnect, solder,thermomechanical reliability.

Manuscript received October 15, 2007; revised April 22, 2008. This work wasrecommended for publication by Associate Editor E. Perfecto upon evaluationof the reviewers comments.

A. O. Aggarwal, P. M. Raj, B.-W. Lee, M. Iyer, and R. R. Tummala are withthe Packaging Research Center, School of Electrical and Computer Engineering,Georgia Institute of Technology, Atlanta, GA 30332-0560 USA.

M. J. Yim and C. P. Wong are with the School of Materials Science and En-gineering, Georgia Institute of Technology, Atlanta, GA 30332-0560 USA.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TEPM.2008.2001974

I. INTRODUCTION

S HORT and reliable interconnections are becoming verycritical for mixed-signal wireless applications. Thinner

modules with embedded actives are beginning to drive theneed for less than 30- m pitch interconnections [1]. Otherapplications are the new need for computer and communicationtechnologies for highest aggregate system performance suchas by multicore processors, aggregately providing highest datarates at the lowest power. These multicore architectures arepushing the I/O density to more than 10 000/cm and pitch toless than 50 m [2], [3]. Traditional solder interconnectionsmay not satisfy the thermomechanical and electrical reliabilityrequirements in these applications. Semiconductor companiesare addressing this problem by a variety of techniques suchas immersion soldering and thermode bonding [4], gold studbumping, and thermo-compression bonding [5], [6]. In addi-tion, some of these companies have announced copper pillartechnologies combined with solder bonding to address theelectromigration and reliability issues at fine pitch [7], [8].The copper bump enables easier processing, minimizes thethermomechanical concerns, distributes the current densityuniformly over the interconnection, and also lowers the bumptemperature to mitigate several reliability issues. While thereis a general opinion that lead-free solders even with underfillmay not withstand the high stresses and strains at fine pitch,there is no ideal solution for fine-pitch interconnections thatcan address bonding and assembly at low temperatures and atlow cost while providing the required reliability. This problemis further complicated because of the difficulty in underfillingshort interconnections at fine pitches for larger die sizes.

The Packaging Research Center (PRC) of the Georgia Insti-tute of Technology has been working on novel interconnectiontechnologies to achieve ultrafine-pitch wafer-level packaging bybringing nano-materials and processes [9]. The central themeof this research is the replacement of solders with advancedinterconnection materials such as nano-structured copper andnickel, novel bonding and barrier layers to provide both relia-bility, and down-scalability to ultrafine pitches of 10–20 m.The intrinsic properties of nano-materials enable several ordersof magnitude higher interconnection densities with the best me-chanical properties for the highest reliability and yet providehigher current and heat transfer densities. For example, Cu in-terconnections when fabricated in nano-crystalline grain sizes(10-50 nm) have been shown to possess dramatically enhanced

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342 IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 31, NO. 4, OCTOBER 2008

Fig. 1. Schematic of nano-structured nickel interconnection with (a) Sn–Cu orAu–Sn bonding layers and (b) ACF bonding layer.

resistance to fatigue and fracture without large increase in elec-trical resistance [10]. Similarly, nano-structured nickel has anextremely high strength of above 800 MPa and much higher fa-tigue resistance compared to most solders, making it an attrac-tive interconnection material. Nano-structured interconnectionsprovides the ability to package ICs with ultrathin-film fine-pitchinterconnections to enable advanced analog/digital testing, reli-ability testing, and burn-in at wafer level.

In this paper, novel nano-interconnections consisting of nano-structured nickel primary interconnection and low temperatureassembly routes that are compatible with organic substrates aredemonstrated. This paper describes all the process includingfabrication of nano-structured nickel primary interconnects, for-mation of Sn–Cu and Au–Sn bonding interface on the primaryinterconnects, assembly of the primary interconnects with var-ious bonding layers including Sn–Cu solder, Au–Sn solder, andthin anisotropic conductive films (ACFs). For all the fabricatednano-interconnects, thermomechanical reliability is evaluatedby experimental thermal shock tests and finite-element mod-eling analysis.

II. EXPERIMENTS

Fig. 1 shows the schematic of nano-structured nickel inter-connections with different bonding layer approaches. The nano-structured nickel interconnections are realized by wafer-levelnickel bumping, the formation of bonding layers, substrate fab-rication and assembly. The baseline process for the fabricationof nano-structured nickel interconnections is shown in Fig. 2.

A. Chip Fabrication

Chips were fabricated on 4-in silicon wafers. First, a1- m-thick silicon oxide layer was deposited by plasma-en-hanced chemical vapor deposition (PECVD). Metal pads werethen made by sputtering titanium and copper sequentially,whose thicknesses are 0.03 and 2 m, respectively. Finally, apolymide layer (PI 2771, HD Microsystems) was applied onthe chip as a pad passivation layer. The thickness of passivationlayer was approximately 4 m. Nano-structured nickel bumpsare plated on the pads of these chips on wafer level. The chipsize was 5 5 mm and the interconnection pitch was 200 m.

B. Nano-Structured Nickel Interconnects

For the fabrication of nano-structured nickel interconnects,the wafer was sputtered with a layer of Ti/Cu/Ti that serves as aseed layer for electroplating nickel. Before sputtering, the waferwas dipped in a 10% H SO solution to remove any copper

Fig. 2. Baseline Process for Fabrication of nano-structured nickel interconnec-tions with solder caps. For ACFs, solder and barriers are not needed.

oxide formed on the pad surface during the polyimide passi-vation curing process. This step was extremely critical in orderto maintain a clean conducting path for the interconnects, andthus the wafers were transferred to the sputter as soon as theoxide cleaning step is finished to minimize the copper oxidationfrom air. The sputtered seed layer comprises of 2.4- m titanium,0.25- m copper, and 0.6- m titanium. The last titanium layerwas deposited to prevent the underlying copper from being at-tacked by the developing agent used for the plating photoresist.

In order to fabricate the nano-structured nickel interconnec-tions, electroplating mold was first formed by using a negativeworking, polymer dry film photoresist (WBRT50, DuPont Elec-tronic Materials). This photoresist has been developed for in-viaand mushroom electroplating bumping applications and is also

AGGARWAL et al.: THERMOMECHANICAL RELIABILITY OF NICKEL PILLAR INTERCONNECTIONS 343

suitable for photo stenciling applications. The photoresist hasa strong heat resistance and a high-resolution capability withwide processing latitude. In addition, this photoresist is compat-ible with a variety of surfaces, including silicon, silicon nitride,sputtered copper, sputtered gold, and sputtered titanium. For theplating of our nickel interconnections, two 50- m-thick filmswere stacked together to get the required 100- m photoresistthickness. The electroplating mold could be obtained by lithog-raphy process. Then, the top Ti seed layer was etched away bydry plasma etching. The dry plasma etching process providedbetter results in removing the Ti layers in the deep trenchesof the mold than a typical Ti wet etching process. The plasmaetching process was well controlled not to have any effect on thephotoresist and the copper layer under the Ti layer.

A nickel sulfamate electroplating chemistry (Nickel HT-2,Technic, Inc.) was used for plating the nano-crystalline nickel.This chemistry has been known to produce ultrafine-grainedlow-stress deposits of nickel. The plating time to deposit about70- m height of nano-nickel interconnects was about 3 h witha current density of 13.5 mA cm , resulting in an approximatedeposition rate of 0.3 m . To avoid over plating, the waferwas taken out and inspected periodically with a profilometer andmicroscope.

The nano-structure of the plated nickel materials was char-acterized by X-ray diffraction (XRD) and field-emission scan-ning electron microscopy (FESEM). XRD analysis was carriedout using a Philips Power Diffractometer with a Cu tube. Thewavelength of Cu K radiation is 1.5418 . Each diffractionpeak profile was obtained at a slow scan rate of 0.002 s .

C. Bonding Layers

Once the nickel interconnects are formed by the electro-plating, the next step is to form bonding layers on the top ofthe nickel interconnects that will serve as the bonding interfacebetween the interconnections and the substrate pads. In thisstudy, two different solder materials including Sn–0.7Cu andAu–20Sn and anisotropic conductive film (ACF) were eval-uated for the bonding layers. For the solder bonding layers,about 20–25- m-thick solder was deposited in both cases. Forthe ACF bonding layer, solder deposition is not needed.

1) Sn–Cu Bonding Layer: The Sn–0.7Cu system has beenconsidered as a promising candidate for wave-soldering appli-cation in the mass production of consumer products, since itis cheaper than other lead-free solders including Sn–Ag–Cusystem solders, and offers the longest thermal fatigue lifeamong all the lead-free solder evaluated [11], [12]. Therefore,Sn–Cu eutectic solder was selected as one of the bonding in-terfaces of nano-structured interconnects. The Sn–0.7Cu alloywas formed by sequential plating of Cu and Sn, followed by areflow process to dissolve the Cu in Sn, as shown in Fig. 3. Re-flow of the solder was done around 250 C in a nitrogen reflowoven. The amount of Cu and Sn that had to be deposited wascalculated to get the caps of required shape and composition.

For the tin plating of Sn–Cu bonding layer, a commer-cially available sulfate-based pure tin electroplating chemistry(Ronastan EC, Rohm and Haas Electronic Materials) was used.This plating chemistry produces smooth, fine-grained, satindeposits over a wide plating range. For the copper plating

Fig. 3. Plating steps and reflow process for formation of Sn–Cu solder cap.

of Sn–Cu bonding layer, a high-acid copper electroplatingchemistry (Copper Gleam 125-EX, Rohm and Haas ElectronicChemicals) was used, which could produce ultra-fine grainedequi-axed copper.

2) Au–Sn Bonding Layer: Eutectic Au–20Sn solder has longbeen recognized as offering superior high temperature perfor-mance, excellent electrical and thermal conductivity, high me-chanical strength, and fluxless soldering. It has been used forhigh power electronic and optical device packaging over lastdecade [13]. The Au–Sn solder was selected as another solderbonding interface for nano-structured interconnects. Similar tothe formation of Sn–Cu alloy, Au–Sn solder was formed by elec-troplating of Au and Sn in successive process steps followed bya reflow step during which the eutectic solder cap was formed.Reflow of the solder was done around 300 C in a nitrogen re-flow oven. The reflow leads to an even bump surface and pre-vents the bumps surface from oxidizing. Tin for Au–Sn solderbonding layer was plated by the same plating process as theSn–Cu bonding layer. For the gold plating of Au–Sn solder, aready-to-use cyanide-free stabilized gold sulfite electroplatingsolution (TSG-250, Transene Company) was used.

3) Post Plating Process: Once all the electrolytic plating iscomplete, the photoresist for electroplating mold was strippedin a Tetra-Methyl-Ammonium Hydroxide (TMAH)-based so-lution. TMAH solution slowly dissolves the cured photoresistfilm, and it typically takes a few hours to lift off the photoresistmold. The TMAH solution does not attack the surface of thephotoresist, and rather attacks the vertical walls of the photo-resist openings to lift off the resist. Therefore, it is importantnot to over-plate or mushroom-plate through the photoresist, asin this case the photoresist removal becomes problematic. Then,the seed layers were removed where the titanium seed layer isremoved with a mild HF solution. The copper seed layer is thenselectively etched and again followed by the bottom Ti layer.Once the etching process is complete, the wafer is thoroughlywashed with DI water to remove any acidic residues. The waferis subsequently singulated into individual dies to be assembledon to substrates.

4) ACF Bonding Layer: Thin conducting polymeric adhesivefilms were also investigated as the bonding layers of nano-struc-tured nickel interconnects. ACF is one of typical conductingpolymeric adhesive films, which is a lead-free and environmen-tally friendly epoxy system that has been used for almost 30years in the flat-panel display industry to make the electricaland mechanical connection from the device electronics to theglass substrates of the displays [14]. In this study, we formu-lated 50- m-thick ACF with gold/nickel coated polymer parti-cles of 4 m in diameter dispersed in epoxy-based polymer ma-trix with latent hardener. The concentration of conductive filler


Fig. 4. Two—dimensional plane stress finite-element models for half ofnano-structured interconnects with (a) Sn–Cu or Au–Sn solder and (b) ACF asbonding layers.

TABLE IMATERIAL PROPERTIES FOR NANO-NICKEL USED IN THIS STUDY

was 6 wt% in the ACF material. The film was coated on the car-rier film by doctor blading method. The typical cure conditionfor the ACF was 180 C for at least 20 s under the bonding pres-sure of 100–200 MPa.

D. Substrate Fabrication

The substrates were fabricated using three core materialswith different CTEs. The high CTE control substrates used ahigh FR-4 laminate core (16–18 ppm C). Medium CTEsubstrates (8–11 ppm C) used MCL-E-679F laminates fromHitachi Chemical, consisting of PTFE dielectrics reinforcedwith Cu–Invar–Cu cores and. C–SiC core (2-3 ppm C) wasused as an alternative of low CTE organic substrates.

Design of 200- m-pitch test vehicle substrates involved asingle metal layer structure with bonding pads of 110- m di-ameter and 100- m lines for escape routing the daisy chain teststructures. The metal trace definition on the substrates involvedthinning down the copper clad from 20 m to 4–5 m, followed

TABLE IIMATERIAL PROPERTIES OF SUBSTRATES MODELED IN THIS STUDY

TABLE IIIMATERIAL PROPERTIES OF BONDING MATERIALS USED IN THIS STUDY

by depositing a photoresist mask on the substrates. High-res-olution liquid photoresist (Shipley Eagle NT-90) and dry filmRiston photoresist were used for the lithography. Thereafter, asubtractive process was used to etch the metal on the substrates,followed by removal of photoresist mask in an organic solvent.The substrate pads were finished using electroless nickel andimmersion gold surface finish.

In case of the C–SiC substrate fabrication, a 25- m high-tem-perature polyimide film (from DuPont) was laminated on eachside of the C–SiC core before copper cladding. The polyimidelamination was done on both sides of the core to minimize theeffects of pits that initially exist after the core fabrication andto balance the thermomechanical loads on each side, potentiallyminimizing the substrate warpage.

E. Assembly of Nano-Structured Nickel Interconnects

A flip-chip bonder machine (Fineplacer, Finetech, Germany)was used for the assembly of all nano-structured nickel in-terconnects, which is able to provide m in placementaccuracy. Three different types of nano-structured nickel in-terconnections were made by reflowing Sn–Cu, Au–Sn solder


Fig. 5. Equivalent plastic strain at the nano-structured nickel interconnects withSn–Cu bonding layer on different CTE substrates. (a) C–SiC. (b) MCL-E-679F.(c) FR-4.

bonding layers or thermocompression bonding with ACF.The Au–Sn bonding process did not need any flux, while theSn–Cu bonding process required a flux. No-clean NR 2000 flux(Alpha Metals) was used for the nano-structured interconnectassembly with Sn–Cu bonding layer. The reflow peak temper-atures for Sn–Cu and Au–Sn bonding interfaces were 250 Cand 300 C, respectively, which are slightly higher than eacheutectic temperature (227 C and 280 C [15]). For the ACFbonding layer process, the ACF film was first laminated to thesubstrate (2–3 kgf cm , 3–5 s at 80 C), followed by tackingthe chip to the film (1 kg cm , 50 C). The thermocompressionbonding was finally applied (180 C with a load of 100 MPa

Fig. 6. Thermal cyclic plastic strain at the nano-structured nickel interconnectsassembled on different CTE substrates with Sn–Cu solder as bonding layers.

or 100 g/bump for 5 min), permanently curing the epoxy andattaching the chip to the substrate.

F. Thermal Shock Tests

Thermal shock tests in the range from 25 C to 125 C withdwell time of 10 min and heating and cooling rate of 30 C minwere performed for all the nano-nickel interconnects bondedon the three different CTE substrates [C–SiC (2–3 ppm C),MCL-E-679F (8–11 ppm C), and FR-4 (16–18 ppm C)] withdifferent bonding interface: Sn–Cu, Au–Sn, and ACF. Failureanalysis was performed based on these thermal shock test re-sults, FEA results, and observation of failed sites. The electricalresistance was measured through the daisy chains every 25 or100 cycles.

III. FINITE-ELEMENT ANALYSIS FOR NANO-STRUCTURED

INTERCONNECTS

Nano-interconnection assembly consists of silicon, substrate,nano-nickel representing the primary interconnects and bondinginterface materials used to assemble the interconnection ontothe substrate. These newly introduced interconnect structuresincorporate materials with different thermal and mechanicalproperties. In order to evaluate thermomechanical reliability ofthe nano-structured interconnection structures, finite-elementanalysis (FEA) was performed, especially focusing on thebonding area of interconnects assembled onto the substrates ofvarious CTE values including the three fabricated substrates.

Fig. 4 shows the FEA models for two different geometries ofnano-interconnections depending on bonding layers. Becauseof symmetry, only half of the models were simulated. Theflip-chips modeled here have a peripheral row of interconnec-tions. When a 2-D symmetric cross-section is taken, only asingle interconnection is incorporated into the model. Thus,the half-symmetry was applied along the diagonal so as tocapture the interconnection furthest from the center of package.Two-dimensional four-noded plane stress elements were used.The finite-element models consist of 1369–1713 nodes and1250–1584 elements depending on bonding methods in the


Fig. 7. Distribution of von Mises stress at the nano-structured nickel inter-connects with Au–Sn bonding layers on different CTE substrates. (a) C-SiC.(b) MCL-E-679F. (c) FR-4.

interconnects. The mesh was highly refined in the primarynickel interconnects and bonding area so that their deformationcould be described accurately.

The material properties for all the constituents of the in-terconnects were obtained from literature (Tables I and III)[14]–[22]. Since the temperature-dependent material propertiesfor nano-nickel are not currently known, temperature-depen-dent material properties of bulk-nickel were used in the models

Fig. 8. Maximum von Mises stress at the nano-interconnects assembled on dif-ferent CTE substrates with Au–Sn solder as bonding layers.

Fig. 9. Maximum von Mises stress at the nano-structured nickel interconnectsassembled on different CTE substrates with ACFs as bonding layers.

(Table I). For the purpose of understanding the behavior ofinterconnections with low, medium, and high CTE substrates,various substrates were chosen to have different CTE values inthe ranging from 2.5 ppm C to 16 ppm C (Table II). Threebonding methods were evaluated, which include Sn–0.7Cusolder, Au–20Sn solder material and ACF (Table III). ForSn–0.7Cu solder, Sn–0.7Cu-3.8Ag solder properties have beenused. Sn–0.7Cu solder and Au–20Sn solder were considered tobe temperature-dependent, elastic–plastic materials and ACF tobe temperature-dependent elastic material. All the constituentswere modeled as isotropic except the orthotropically modeledFR-4 substrate. These nano-interconnection models were sub-jected to three cycles of thermal loading between 25 C and125 C. The FEA models were assumed to be in a stress-freestate at 25 C and to have a uniform temperature throughout


Fig. 10. FESEM micrograph of electrodeposited nano-crystalline nickel.

the analysis. A commercial finite-element code, ABAQUS, wasused for modeling [23].

A. Bonding With Sn–Cu Solder

Solder bonding layers were plastically deformed in all thenano-interconnect structures assembled on different CTE sub-strates, as shown in Fig. 5. Especially, large plastic deformationwas concentrated at the corners of solder bonding layers. Theplastic strain increases as the CTE of the base substrate deviatesfrom that of Si (Fig. 6). In the investigated set of substrates, FR-4showed the highest plastic strain range while a basesubstrate made up of C-SiC showed the least straindue to a Si-matched CTE.

B. Bonding With Au–Sn Solder

To see the effect of the Au–Sn solder materials as the bondinginterface, the solder material in the previous model was replacedwith Au–Sn material. Since Au–Sn is a very strong material withyield strength of 275 MPa as compared to 30–40 MPa for typ-ical lead-free solders, the Au–Sn bonding layers did not haveany plastic deformation in all the interconnects assembled ondifferent CTE substrates. Instead, the stresses were concentratedon either chip pad or substrate pad (Fig. 7). Thus, the maximumvon Mises stresses in the chip or substrate pads are plotted tosee the effects of substrate CTEs on the thermomechanical reli-ability of nano-interconnection joints (Fig. 8).

As the CTEs of the substrate decrease and approach that of Si,the overall stresses at the nano-interconnection joints decrease.However, large stresses on the substrate pads of C-SiC and AlNsubstrates are noticeable in spite of their very low CTEs below4.5 ppm C. Thermal stress in a fully restrained bar can besimply expressed as , in which , , and areelastic modulus, CTE, and temperature difference, respectively.Considering both contributions of elastic modulus and CTE tothermal stress, the large stresses on the pads of the two substratescan be ascribed to their much higher elastic moduli (350 GPa for

Fig. 11. XRD of micro-crystalline and nano-crystalline nickel.

C-SiC and 320 GPa for AlN) than other substrates having elasticmoduli from 28 to 54 GPa.

In the case of Au–Sn solder as bonding layers, the shift offailure sites is expected from the interconnection to the chip padsor substrate pads, since the strength of the nano-interconnectionjoints is considerably high. Therefore, the modeling stronglysuggests that the interfaces of pads with chips or substrates haveto be very robust in order to get reliable interconnection assem-blies using Au–Sn bonding layers.

C. Bonding With ACF

For ACF bonding layers, the solder bonding interface wasreplaced with a polymeric adhesive material of ACF. A smalllayer m of ACF between the nano-interconnection andthe substrate bonding pad, in which conductive particles of ACFare trapped, is introduced to provide an electrical connection be-tween the two electrodes. The filler loading of these conductiveparticles in the ACF polymer material is less than 1 vol.% andhence the material properties of the ACF material is assumed tobe the same as the polymer used to make the ACF.

Maximum von Mises stresses in the nano-interconnectionjoints are plotted for each of the substrates as shown in Fig. 9.Since there is no rigid joint between the primary interconnectsand the substrate pads and also the polymer material servesas a stress buffering layer, the von Mises stresses in this caseare much lower as compared to the rigid bonding approachesdiscussed earlier. In addition, compared to Au–Sn bondinglayers, the stresses on chip pads increase only marginally withincreasing substrate CTEs. This also demonstrates that ACFpolymer materials have significant influence on distributingthermomechanical stresses along the polymer layer.

The stresses are higher on chip pads than on substrate pads forall the interconnects, indicating that the interconnects are mostlikely to fail at the chip pads. Robust chip/pads interfaces areagain expected to enhance the thermomechanical reliability ofthe interconnects with ACF bonding layers. Compared to highCTE substrates such as FR4, larger stresses are observed on thepads of C-SiC and AlN substrates. This can be explained with


Fig. 12. FESEM micrographs of electrodeposited nano-crystalline copper (a) before and (b) after thermal annealing.

the same reason as in the case of Au–Sn bonding layers. Thehigh elastic modulus of the substrates contributes to the padstresses.

IV. RESULTS AND DISCUSSION

A. Nano-Structured Nickel Interconnect

The electroplating with patterned photoresist molds success-fully produced the nickel interconnect posts. The interconnectposts were formed in tapered shape due to the undercut in thedeveloped electroplating molds. Mushroom or over-plating wasprevented. The interconnect height was 70 m and its diameteron the top surface was about 84 m. Fig. 10 shows a FESEMmicrograph of a Ni deposit produced by DC electrodeposition.However, the grain was too small to directly measure its sizefrom the FESEM image. As an alternative, the XRD methodwas used. Fig. 11 shows an XRD pattern of a dc-plated nano-crystalline nickel deposit compared to micro-crystalline nickel.The XRD data of micro-crystalline nickel was obtained fromhot-rolled nickel sheet that has typically micro-sized grains. Thegrain sizes of nano-crystalline nickel deposits were estimatedby applying the well known Scherrer formula [24] for the (111)peak. The micro-crystalline nickel sample was used as a refer-ence sample to get rid of the instrumental broadening and todetermine the broadening caused by nano-crystallization. Thegrain size was calculated using the Scherrer’s formula to be16 nm.

It is also important to know the thermal stability of the nano-crystalline nickel at higher temperatures during various pack-aging operations. The nano-crystalline nickel deposits were an-nealed at 100 C and 300 C and no change in their grain sizeswas observed. A similar behavior of nano-crystalline nickel athigher temperatures was also reported by Wang [25] and Kle-ment [26]. The thermal stability of nano-crystalline nickel canbe compared to that of nano-crystalline copper that has beenalso widely explored for nano-structured interconnects [9], [27].

Fig. 12(a) shows a FESEM image of a nano-crystalline copperdeposit (38 nm in grain size) produced by dc electrodeposition.This nano-copper was annealed at 120 C for 1 h in a nitrogenatmosphere. It was observed as seen in Fig. 12(b) that the grainsgrew to an average of 1 m in size after heat treatment. There-fore, nano-crystalline nickel becomes a very obvious choice as ahigh-strength interconnection material that retains its character-istic mechanical properties even after undergoing the rigorousthermal exposures during the package reflow operations.

B. Bonding Layers

For bonding interfaces, the plated stacks of Cu/Sn and Au/Snon the nickel interconnects to form eutectic Sn–Cu and Au–Sncompositions, respectively, were subjected to thermal reflowtreatments to allow the each alloy to inter-diffuse. The energydispersive X-ray analysis (EDX) was used to obtain spatial con-centration maps of the alloy compositions in both bonding inter-faces. The EDX results showed that there were strong inter-dif-fusions of each alloy element in both eutectic Sn–Cu and Au–Snsystems (not shown here). The eutectic solder composition for-mation was also confirmed in both bonding layers: 99.37Sn–0.63Cu and 80.67Au–19.33Sn.

C. Assembled Nano-Structured Interconnections

The chips were assembled on three different CTE substratesusing three different bonding interfaces: Sn–Cu, Au–Sn andACF. Fig. 13 shows the nano-structured interconnection on theFR-4 substrates with different bonding interfaces. For the othertwo substrates (C-SiC and MCL-E-679F), similar bonding inter-face shapes were obtained. It can be seen from Fig. 13(a) and (b)that the Sn–Cu solder flows easily on a horizontal pad surface,while the Au–Sn does not. This leads to lower interconnectheight in Au–Sn bonding interface than Sn–Cu interface. Theheight difference of these two interconnects is thought to be dueto the differences of surface tension or wetting angle betweenthe solders and the landing pads. Fig. 13(c) shows the small gap


Fig. 13. Nano-structured nickel interconnects with (a) Sn–Cu, (b) Au–Sn and(c) ACF as bonding layers.

between the interconnects and the landing pads, in which smallmetal-coated polymeric particles that can provide electrical in-terconnection are expected to be entrapped. The electrical con-

Fig. 14. Change in dc resistance during thermal shock tests for nano-struc-tured interconnects with different bonding layers. The interconnects with Au–Snbonding layers on MCL-E-679F and FR-4 substrates failed right after assembly.

tinuity was confirmed for all the interconnections by an LCRmeter.

D. Reliability Performances of Nano-Interconnects

Fig. 14 shows the change in dc resistance of daisy chainsduring thermal shock tests for nano-structured interconnectswith different bonding layers. Assembled chips were consid-ered to have failed when the initial contact resistance of singleinterconnects is larger than 50 m , which can correspond toaround 4400 m in the resistance measurements of our daisychain having 88 nickel pillar interconnects, assuming the con-tribution of wide Cu–metal trace to the measured daisy chainresistance is negligible compared to that of all the intercon-nects. Thus, we defined the failure criteria as the daisy chainresistance larger than 4400 m . Thermal shock test results forour three interconnects were summarized in Table IV.

1) Sn–Cu Bonding Layer Interconnects: The nano-intercon-nects assembled on FR-4 and MCL-E-679F substrates failedafter 25 and 50 cycles, respectively, while the one assembledon C-SiC substrates failed only after 400 cycles. It is to benoted that no underfill was used in any of these test vehicles.It is expected that using an underfill will significantly improvethe thermal shock life of the test vehicles. Fig. 15 shows thefailure sites at the nano-structured interconnects bonded on dif-ferent CTE substrates with Sn–Cu bonding layers. It was ob-served that there was no apparent fracture in the nano-nickelmetal interconnections.

For the nano-interconnects on the low CTE substrate[Fig. 15(a)], it was confirmed that the failure occurred on theunder bump metallurgy (UBM). This failure was not predictedfrom our FE results of Fig. 6. It might be related to the localCTE mismatch between the die (2.6 ppm C) and the Ni-in-terconnection (12.5–13.8 ppm C), leading to the increased


TABLE IVTHERMAL SHOCK TESTING RESULTS OF NANO-STRUCTURED NICKEL INTERCONNECTS

thermal mismatch stresses and then failure. However, thebonding layer region did not show any failure or cracks, whichwas consistent with the FE results of Fig. 6 that showed verylittle plastic deformation occurred at the Sn–Cu bonding layerof the interconnects on the C-SiC substrate.

The primary failure mode observed in nano-interconnectsbonded on high CTE substrate was cracking of the bulk Sn–Cusolder, as shown in Fig. 15(d). Considering the FE result[Fig. 7(c)] showing that large plastic deformation occurs atthe upper right corner or the lower left corner of the bondinglayers, it is expected that cracks are initiated at these cornerregions and propagated into the Sn–Cu solder. This is in goodagreement with other previous studies to report the crackinitiation and propagation within bulk solder as a typical failuremode of Sn–Cu solder [28], [29]. In this solder system, such anintermetallic as Cu, Ni Sn formed in the interface betweenthe solder and Ni/Au finished pads are known not to affectthermal fatigue life [29], [30].

The interconnects bonded on intermediate CTE substratesshowed both failure characteristics of low CTE and high CTEsubstrates. They failed at either UBM on the die side or throughthe bulk of the Sn–Cu solder, as shown in Fig. 15(b) and (c).However, it is not clear which of these failure modes determinedthe thermal fatigue cycles of nano-interconnects on the interme-diate CTE substrate.

2) Au–Sn Bonding Layer Interconnects: The interconnectsbonded on the C-SiC substrate with Au–Sn bonding layer failedafter 100 thermal shock cycles, while the ones assembled onFR-4 and MCL-E-679F substrates failed during cooling fromthe reflow temperature. A great improvement in thermal fatiguelife was not achieved by using low CTE substrate. All the fail-ures of nano-interconnects with Au–Sn bonding layers occurredat the UBM of die side, as shown in Fig. 16. This supports the FE

results of Fig. 9 showing that thermal mismatch stresses are con-centrated on either UBM of die side or the substrate pads. Thefailures of interconnects on the intermediate and high CTE sub-strates suggest high reflow temperature induced high residualstresses at the interconnects. The FE results in low CTE sub-strate of Fig. 8 shows thermal stress is higher on the substratepads than the chip pads. However, the failure was observed onlyat the UBM of the chip in thermal shock cycle tests. This indi-cates the adhesion between Au–Sn solder and substrate pads isbetter than that between the nickel interconnects and the UBM.No failures in the nano-nickel interconnects were found.

3) ACF Bonding Layer Interconnects: With nano-nickel in-terconnections assembled using ACFs, no failures were detectedon C-SiC and FR-4 substrate even after 1500 thermal cycles.However, with intermediate CTE substrate, some failures wereseen at 700 cycles, even though the FE results suggested thelonger thermal cycle fatigue life in the intermediate CTE sub-strate than in high CTE substrate. The primary failure modeobserved in the interconnects with ACF on the intermediateCTE substrate was crack formation and propagation at the in-terface between the ACF epoxy materials and the substrate pads(Fig. 17). Considering the crack was initiated at the interface be-tween the ACF epoxy materials and the substrate, it is thoughtthat the adhesion at the interface is not as good as C-SiC or FR-4substrate. In addition, the FE results indicate the thermal stressat the substrate pads helped the crack propagation.

From the thermal shock test results summarized in Table IV,the best thermomechanical reliability was obtained at the nano-nickel interconnects with ACF bonding layers. In addition, thehigh strength of nano-nickel precluded any failures in the pri-mary interconnections. It is, however, worth comparing cur-rent carrying capability of ACF bonding layer with two metallicbonding layers such as Au–Sn and Sn–Cu. Fig. 14 indicates that


Fig. 15. Failures in nano-structured nickel interconnects bonded with Sn–Cu layer on (a) C-SiC, (b) and (c) MCL-E-679F, and (d) FR-4 substrates during thermalshock testing.

the initial daisy chain resistances in metallic bonding intercon-nections are about 400 m , while those in ACF bonding inter-connections are about 1000 m . The daisy chain resistance ofACF bonding layer increases more than that of metallic bondinglayers during thermal shock reliability tests. Thus, this less cur-rent-carrying capability of ACF bonding layers should be con-sidered when choosing ACF as bonding layers.

It is expected that the nano-interconnections assembled withACF having nano-particles ( 20–30 nm in size) are scalable tovery fine-pitch interconnects. In addition, the use of nano-parti-cles in ACF films can increase the number of captured conduc-tive particles between pads, leading to higher current-carryingcapability in fine-pitch interconnects.

V. CONCLUSION

A novel nano-interconnection scheme consisting ofnano-structured nickel primary interconnects and variouslow-temperature assembly routes was successfully demon-strated. The primary nano-structured metal interconnects were

fabricated by electroplating nickel within patterned photoresistmolds. The thermal stability of the nano-crystalline structurewas also confirmed. The nano-structured interconnects wereassembled on various substrates having different CTEs withthree different lead-free bonding layer approaches: Sn–Cu,Au–Sn, and ACFs. No underfilling was used in any of theinterconnect structures evaluated in this study. The thermo-mechanical reliability of the nano-interconnects with differentbonding interface was investigated by finite-element analysisand thermal shock tests. Nano-nickel interconnects with Au–Snbonding layer showed the lowest thermomechanical reliability,as predicted from the FE modeling results. The nickel inter-connects assembled with Sn–Cu showed severe plastic strainsin the solder and failed within 400 cycles even on low CTEsubstrates. Based on all the reliability test results, it was foundthat nano-structured nickel interconnects bonded with thinanisotropic conductive films (ACF) showed the highest thermalcycling reliability. The improved reliability performance ofACF bonding layer comes from both effects of underfill andcompliance. The polymer matrix in the ACF films redistributed


Fig. 16. Failures in nano-structured interconnects bonded with Au–Sn layer on (a) C-SiC, (b) MCL-E-679F, and (c) FR-4 substrates during thermal shock testing.

Fig. 17. Failure in nano-structured interconnects bonded with ACF on MCL-E-679F substrate after 700 cycles.

the stresses and strains, and could act as an underfill. The thinmetal coated polymer particles to provide conduction pathin ACF could make compliant interconnections between ICsand substrates. High-strength nano-nickel interconnectionscombined with ACF can potentially provide the mostly reliableinterconnection solution at ultrafine pitch for high electricalperformance interconnections. The nano-structured nickel

interconnects with Sn–Cu and Au–Sn bonding layers will needunderfill for their better thermomechanical reliability.

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Ankur O. Aggarwal received the B.Tech. (honors)degree in ceramic engineering from Banaras HinduUniversity, Varanasi, India, and the Ph.D. degree inmaterials science from the Georgia Institute of Tech-nology, Atlanta.

He is a Process Engineer in the C4 Group, LogicTechnology Development (LTD), Intel Corporation.His interests are in novel packaging technologies fornext-generation microprocessors. He has authoredthree U.S. patents and several publications in ref-ereed journals and conferences.

Dr. Aggarwal has been a recipient of the Undergraduate Research Fellowshipfrom the Indian Academy of Sciences and several best paper awards in the fieldof microsystems packaging.

P. Markondeya Raj received the B.S. degree fromthe Indian Institute of Technology, Kanpur, in 1993,the M.E. degree from the Indian Institute of Science,Bangalore, and the Ph.D. degree in ceramic engi-neering from Rutgers University, New Brunswick,NJ, in 1999.

He is an Assistant Research Director at thePackaging Research Center, Georgia Institute ofTechnology, Atlanta. His research expertise spansfrom functional thin films (sensors, capacitors,antennas, and inductors), MEMS components

(tunable capacitors), packaging substrates, thermomechanical reliability, anddevice and system integration. He managed and led several government- andindustry-funded programs in these areas. He coauthored three books and 100publications and has four patents pending.

Dr. Raj received seven Best Paper awards for his conference and journal pub-lications, which include the Distinguished Scholar Award from the MicrobeamAnalysis Society and the IEEE TRANSACTIONS ON ADVANCED PACKAGING

Commendable Paper Award, IEEE Outstanding Technical Paper Award, andthe Philips Best Paper Award.

Baik-Woo Lee received the B. S. degree fromKyungpook National University, Taegu, Korea, in1998, the M. S. degree from Seoul National Uni-versity, Seoul, Korea, in 2000, and the PhD degreein material science and engineering from SeoulNational University in 2004.

He is a Research Engineer at the PackagingResearch Center, Georgia Institute of Technology,Atlanta. His research focuses on system-on-package(SOP) technology, which includes chip-last em-bedded ICs, 3-D chip stacking technology, and

embedded capacitors. He has authored two U.S. patents and over 30 publica-tions in refereed journals and conferences.

Myung Jin Yim (M’04) received the B.S., M.S., andPh.D degrees in material science and engineeringfrom the Korea Advanced Institute of Science andTechnology (KAIST), Taejon, Korea, in 1995, 1997,and 2001, respectively.

During the Ph.D degree, he was a Visiting Re-searcher at the IBM T. J. Watson Research Center,Yorktown Heights, NY, from September 2000 toFebruary 2001 and was involved in the project onPb-free solder and intermetallic compound study.From 2001 to 2004, he worked at Telephus, Inc.

as a Senior R&D Researcher in charge of the development of ACFs/ACPsfor flat panel displays and semiconductor packaging applications. He wasa Postdoctoral Research Associate at the Center for Electronic PackaingMaterials (CEPM), KAIST, from September 2004 to December 2005, andthe Department of Materials Science and Engineering, Georgia Institute ofTechnology, Atlanta, from February 2006 to September 2007, respectively. Heis now a Senior Packaging Engineer at Numonyx, Inc, Chandler, AZ. He haspublished more than 50 technical papers and holds seven U.S. patents in the areaof electronic packaging. His research interest are the polymer nano-compositepackaging materials for flip-chip, RFID Tag, 3-D, MEMS, bio-packaging,image sensors, LED devices, and system-in-package (SIP) integration throughdesign, fabrication, performance and reliability testing, and modeling works.

Dr. Yim is the 2007 IEEE/CPMT Outstanding Young Engineer Award winnerand a member of the CPMT, IMAPS, SMTA, and American Chemical Society(ACS).

Mahadevan Iyer, photograph and biography not available at the time ofpublication.


C. P. Wong (SM’87–F’92) received the B.S. degreein chemistry from Purdue University, West Lafayette,IN, and the Ph.D. degree in organic/inorganic chem-istry from Pennsylvania State University, UniversityPark.

He is a Regents Professor and the CharlesSmithgall Institute Endowed Chair at the School ofMaterials Science and Engineering, Georgia Instituteof Technology, Atlanta. After his doctoral study, hewas awarded a two-year postdoctoral fellowship withNobel Laureate Professor Henry Taube at Stanford

University, Stanford, CA. He joined AT&T Bell Laboratories in 1977 and be-came a Senior Member of the Technical Staff in 1982, a Distinguished Memberof the Technical Staff in 1987, and was elected an AT&T Bell Lab Fellow in1992. Since 1996, he has been a Professor at the School of Materials Scienceand Engineering, Georgia Institute of Technology. He was named a RegentsProfessor in July 2000, elected the Class of 1935 Distinguished Professor in2004 for his outstanding and sustained contributions in research, teaching, andservices, and named holder of the Georgia Tech Institute Endowed Chair in2005. His research interests lie in the fields of polymeric materials, materialsreaction mechanism, IC encapsulation, in particular, hermetic equivalentplastic packaging, electronic manufacturing packaging processes, interfacialadhesions, and nano-functional material syntheses and characterizations. Heholds over 50 U.S. patents, numerous international patents, has published over600 technical papers.

Dr. Wong received the AT&T Bell Labs Fellow Award in 1992, the IEEECPMT Society Outstanding and Best Paper Awards in 1990, 1991, 1994, 1996,1998, and 2002, the IEEE CPMT Society Outstanding Sustained Technical Con-tributions Award in 1995, the Georgia Tech Sigma Xi Faculty Best ResearchPaper Award in 1999, the Best M.S., Ph.D., and Undergraduate Theses Awardin 2002 and 2004, respectively, the University Press (London) Award of Excel-lence, the IEEE Third Millennium Medal in 2000, the IEEE EAB EducationAward in 2001, the IEEE CPMT Society Exceptional Technical ContributionsAward in 2002, and the IEEE CPMT Field Award in 2006. He is a Fellow of AICand AT&T Bell Labs and a member of the National Academy of Engineering.He was the Technical Vice President (1990 and 1991) and the President of theIEEE CPMT Society (1992 and 1993).

Rao R. Tummala (M’88–SM’90–F’94) received theB.E. degree in metallurgical engineering from the In-dian Institute of Science, Bangalore, and the M.S. de-gree in metallurgical engineering and the Ph.D. de-gree in materials science and engineering from theUniversity of Illinois, Chicago, in 1969.

He is a Distinguished and Endowed Chair Pro-fessor, and Director of NSF ERC, Georgia Instituteof Technology (Georgia Tech) Atlanta, pioneeringsystem-on-package (SOP) vision. Prior to joiningGeorgia Tech, he was an IBM Fellow, pioneering

such major technologies as the first flat panel display based on gas discharge, the first and next three generations of multichip packaging based on 35-layer alumina and 61-layer LTCC with copper and copper–polymer thin film,and materials for ink-jet printing and magnetic storage. He has published375 technical papers and holds 71 patents and inventions. He authored thefirst modern packaging reference book Microelectronics Packaging Handbook(Van Nostrand, 1988) and the first textbook Fundamentals of MicrosystemsPackaging (McGraw Hill, 2001).

Dr. Tummala received numerous awards including Industry Week’s Awardfor Improving U.S. Competitiveness, IEEE’s David Sarnoff and Major Edu-cation awards, Dan Hughes Award from IMAPS, the Engineering MaterialsAchievement Award from DVM and ASM-International, the Total Excellence inManufacturing Award from SME, the John Jeppson’s Award from the AmericanCeramic Society as well as the Distinguished Alumni Awards from the Univer-sity of Illinois, the Indian Institute of Science, and Georgia Tech. He is a Fellowof IMAPS and the American Ceramics Society, and a Member of the NationalAcademy of Engineering. He was the President of the IEEE CPMT Society andthe IMAPS Society.

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