IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 6, JUNE 2011 833

3-D Wafer-Level Packaging Die StackingUsing Spin-on-Dielectric Polymer Liner

Through-Silicon ViasYann Civale, Deniz Sabuncuoglu Tezcan, Harold G. G. Philipsen, Fabrice F. C. Duval, Patrick Jaenen,

Youssef Travaly, Philippe Soussan, Bart Swinnen, and Eric Beyne

Abstract— In this paper, we report on the processing andthe electrical characterization of a 3-D-wafer level packagingthrough-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporarycarriers. A Cu/Sn micro-bump structure is integrated in theTSV process flow and used for realizing a two-die stack. BeforeTSV processing, the Si wafers are bonded to temporary carriersand thinned down to 50 µm. The actual TSV and micro-bumpprocess uses 3 masks, two Si-deep-reactive ion etching steps and apolymer liner as a dielectric. The dimensions of the TSV structureare: 35 µm ∅TSV, 5 µm thick polymer liner, 25-µm-∅ Cu TSV,50 µm deep TSV, and a 60 µm TSV pitch.

Index Terms— Integrated circuit fabrication, integrated cir-cuit interconnections, integrated circuit packaging, integratedcircuits, packaging.

I. INTRODUCTION

THROUGH-SILICON VIA (TSV) is a key technologyfor enabling the benefits of 3-D integration, such as

reduction of package size and power consumption and mul-tifunctionality [1]–[3]. 3-D integration of electronic systemscan be addressed in many different ways, and a large varietyof TSV technologies are being proposed [4]–[6]. All theseapproaches can be categorized by the position of the 3-Dinterconnects in the interconnect hierarchy and basically fallinto two categories: 3-D-TSV interconnects at the level of on-chip electrical wiring, and 3-D-TSV interconnects at the bondpad level [7], [8]. This first type (3-D-stacked IC or 3-D-IC)typically uses approaches that integrate the TSV processingin the wafer fabrication and are generally referred to as via-first or via-middle TSVs [9]. The corresponding process flows

Manuscript received July 28, 2010; revised February 7, 2011; acceptedFebruary 13, 2011. Date of publication May 12, 2011; date of currentversion June 10, 2011. Recommended for publication by Associate EditorY.-S. Lai upon evaluation of reviewers’ comments.

Y. Civale, D. S. Tezcan, H. G. G. Philipsen, Y. Travaly, P. Soussan,and B. Swinnen are with the Interconnect and Packaging Department,Interuniversity Microelectronics Center, Leuven 3001, Belgium (e-mail:Yann.Civale@imec.be; Deniz.SabuncuogluTezcan@imec.be; Harold.Phi-lipsen@imec.be; Youssef.Travaly@imec.be; philippe.soussan@imec.be;Bart.Swinnen@imec.be).

F. F. C. Duval and P. Jaenen are with the Department of Lithography,Interuniversity Microelectronics Center, Leuven 3001, Belgium (e-mail: fab-rice.duval@imec.be; Patrick.Jaenen@imec.be).

E. Beyne is with the Department of Process Technology, Interuni-versity Microelectronics Center, Leuven 3001, Belgium (e-mail:Eric.Beyne@imec.be).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2011.2125791

address small-diameter TSVs, generally below 30 μm, andcombine typically a silicon oxide-based dielectric liner withcopper (Cu) or tungsten (W) metallization. The second type,referred to as via-last, allows for postprocessing of the TSVstructure, combining the TSV processing with redistributionwiring and microbumping, hence the name 3-D-wafer levelpackaging (3-D-WLP) [10]. A key challenge for the 3-D-WLP approach is to fabricate cost-effective TSVs withoutcompromising the quality and the reliability of the ICs, whilethe process temperatures are kept below the 200–300 °C range.

In particular, for building complex heterogeneous integratedsystems made of dedicated logic, DRAM, Flash, or RF tech-nology components stacked to each other, the TSV capacitanceto the substrate is the most important electrical parameter. TheTSV capacitance can be approximated, to the first order, to acoaxial capacitance

CT SV ≈ 2π K Hsi

ln(

1 + T∅TSV

) (1)

where K is the dielectric constant, HSi the substrate thickness,∅TSV the diameter of the metal fill in the TSV, and T theTSV isolating liner thickness. The expected TSV capacitanceis plotted in Fig. 1 for a 50-μm-thick Si substrate as a functionof the via diameter ∅TSV and for different thicknesses T of theinsulating liner. In this graph, it is further normalized by usingan equivalent oxide thickness Tox,eq = (4 × T/Kr ). The mostcommonly used insulating layer for TSVs is a silicon dioxideliner deposited by chemical vapor deposition. The thicknessis typically in the range of 100 nm to 1 μm, where thethicker ranges are more difficult to obtain on the vertical TSVsidewalls with good quality, particularly at low temperature.For via-last applications, this also results in more complexprocessing steps, such as the opening of the (thick) oxide linerat the bottom of a via to make contact to the chip circuits. Ascan be seen from Fig. 1, TSV capacitance for via-last TSVwith oxide liners will typically be in the 200 nF to 1 pF range.

In this paper, we report the processing and electrical char-acterization of a via-last TSV flow, using a polymer dielectricliner and Cu-filled TSV processed on thinned wafers bonded totemporary carriers. This technology realizes the TSVs startingfrom the backside of a thinned Si wafer and connecting tothe first metal layer (M1), avoiding the etching through theback-end-of-line on chip–chip interconnect layers. This TSV

2156–3950/$26.00 © 2011 IEEE

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ie (

fF)

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r = 4

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kr = 1 k

r = 1

Si thickness � 50 µm

Equivalent oxidethickness in nmT

ox,eq � (4/k

r)T

0.10.20.30.6123610

30Diameter Cu fill TSV (µm)

40 50

Fig. 1. TSV capacitance as a function of Cu TSV diameter and linerthickness.

carrier

Temporary glue and carrier wafer

300 nm Cu

SiC

Sn

Cu

Ti/Cu seed

50 µm Si

45 µm

35 µm

25 µm

11 µm Dielectric

SiO2

SiNx

Fig. 2. Schematic cross-section and specifications of imec via-last TSV.

technology uses a spin-on dielectric polymer to fill a 5-μm-wide liner trench around a 25-μm-diameter Cu TSV [11].The TSV pitch is 60 μm for a final wafer thickness of50 μm (Fig. 2). The 5-μm-thick polymer liner is equivalentto an oxide thickness of 6–8 μm. As can be seen fromFig. 1, this results in a TSV capacitance of 20–30 fF fora 25-μm-diameter Cu TSV in a 50-μm-thick Si device.A further advantage of using a polymer dielectric liner of afew micrometers thickness is that it can absorb some of thestress induced by the coefficient of thermal expansion (CTE)mismatch between the Cu in the TSV and the surroundingSi. The overall process fabrication and the results of electricalcharacterization, including reliability, are addressed in detailin the sections below.

II. 3-D-WLP TSV FABRICATION

A. TSV Process Flow

The schematic process flow of the 3-D-WLP TSVs is givenin Fig. 3. TSVs were fabricated in an imec 200 mm clean-room facility. A single-metal layer test vehicle, consistingof a Cu/oxide damascene layer on a regular CMOS pre-metal dielectric (PMD) stack made of silicon carbide (SiC),

Carrier

(b)

Carrier

(c)

Carrier

(d)

Carrier

(e)

Carrier

(f)

Carrier

(g)

Carrier

(h)

Carrier

(i)

(a)

Fig. 3. Schematic cross-section of the via-last TSV process flow. (a) Waferhaving received FEOL/BEOL processing. (b) Wafer bonding and thinning.(c) Ring-shaped trenches etched through 50-μm-thin Si. (d) Polymer dielectricliner spin coating. (e) Polymer patterning and central Si block deep-Si etching.(f) Contact to M1 pad etching (dry or wet). (g) Barrier and seed (Ti/Cu)deposited by PVD. (h) Thick negative-tone plating resist patterning. (i) TSVECD Cu filling, resist stripping, and barrier seed removal.

borophosphosilicate glass (BPSG) has been used. The singledamascene layer was capped with a thin SiC layer and aregular oxide/nitride passivation layer.

1) Wafer Thinning: First the wafers are edge-trimmed. Thisis done by dicing the edges of the wafer front-side downto a depth of 120 μm, in order to avoid sharp Si waferedge breakage resulting from backside wafer processing [12].Si wafers were then glued onto a carrier substrate using athermoplastic glue material before thinning down to a finalthickness of 50 μm by grinding. Both glass and Si carriersubstrates are used in this study. Glass substrates present theadvantage of being transparent in visible light but large gapfront- to back-side alignment strategy is then required, whereasthe alignment to the wafer front-side pattern requires infraredalignment capability when Si carriers are used. The groundside is thoroughly cleaned and recess etched after thinning inorder to remove particles and residual stress induced by thegrinding process steps.

2) TSV Processing: Ring-shaped trenches of 5 μm widthwere patterned on the wafer backside and etched throughthe thinned Si substrate to the back end of line pre-metaldielectric stack using a SF6/C4F8-based deep-reactive ionetching (DRIE) process. The stopping layer at the bottom ofthe circular trenches is the BPSG layer. Some overetchingis required to accommodate wafer-level thickness and etchnonuniformity. Indeed, the total thickness variation of the Siwafer after backside grinding on a silicon carrier is typically inthe range of 2 μm. Combined with the Si etch nonuniformityacross the wafer, this may result in the so-called notching

CIVALE et al.: 3-D WAFER-LEVEL PACKAGING USING SPIN-ON-DIELECTRIC POLYMER LINER TSVs 835

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Fig. 4. Cross-section SEM micrographs showing the impact of HF 0.55% wetetch on sidewall cleanliness after DRIE. We can see (a) the scallops directlyafter DRIE of the TSVs. A thick polymer layer, induced by the Bosch process,is covering the TSV sidewall and (b) TSV scallops, free of polymer after HF0.55% cleaning for 30 s.

dielectric

Si

10 µm

Fig. 5. Cross-section SEM micrograph showing the ring trenches filled withpolymer dielectric by spin coating. The polymer was cured at 175 °C, andthe smooth topography of the wafer surface indicates a low variation of filmthickness (below 1 μm), which enables direct patterning of the top surfacedielectric without an extra resist mask.

phenomenon, broadening of the etched trench close to thebottom, potentially causing poor polymer filling and dif-ficulties in TSV Cu metallization. To avoid the notch-ing phenomenon, a “soft-landing” step was introducedinto the DRIE sequence, during which the SF6/C4F8ratio is decreased so that polymerization, and thus pro-tection of the trench sidewalls, is enhanced when reach-ing the bottom of the trenches and landing on BPSG.The polymer layer deposited on the Si sidewalls during DRIEneeds to be removed after etching and before any furtherprocessing. A wet cleaning solution composed of 0.55% HFwas successfully applied using a spray etch tool (Fig. 4).The ring-shaped trenches were then filled with an epoxy-based polymer dielectric by spin coating. A large number ofpolymers were tested for this particular application and thedetails of this paper are reported in [13] and [14]. Severalmaterials were shown to enable void-free filling of the ringtrenches. In this paper, the polymer deposition consists of twodistinct steps, during which polymer materials with differentviscosities are used in order to achieve, first, an optimal wet-ting of the ring sidewalls and, second, a reduced topography onthe surface. The topography of the polymer above the trenchafter polymer deposition is sufficiently smooth to enable thedirect patterning of the dielectric without adding additionalresist and RIE steps (Fig. 5). The dielectric liner is used as anegative-tone hard mask to expose the TSV Si core and allows

(a) (b)

Fig. 6. Top-view optical micrographs showing a 25-μm-wide opening in thepolymer (a) before DRIE and (b) after DRIE and PMD etching at the TSVbottom.

(b)

20 µm

(a)

Fig. 7. (a) FIB image of the Cu/Sn filled via-last TSV. (b) Top viewmicroscope image of the ECD Cu resist pattern.

for its subsequent removal using a second Si DRIE sequence,which lands on the PMD stack (Fig. 6).

After TSV Si core DRIE, the BPSG layer is etched at thebottom of the TSV to allow contacting to the M1 pad. This canbe done either by RIE or wet chemical etching. When usingchemical etching, some limited lateral underetch of the poly-mer liner can occur. This has to be well controlled to allow fora successful barrier/seed physical vapor deposition (PVD) inthe next step. In this paper, a 70-nm-thick Ti adhesion/barrierlayer and a 500-nm-thick Cu layer were deposited by PVD onthe TSV cavity of aspect ratio 2:1, resulting in a continuousseed layer for electrochemical deposition (ECD). Before theCu fill plating process, an 11-μm-thick negative-tone resistmask layer is applied in order to form the Cu fill in the TSVand the Cu/Sn microbump on top of the TSV. The use of anegative resist is preferred in order to avoid patterning issues inthe TSV cavity [Fig. 7(b)]. The ECD was performed on NEXXSystems Stratus 300 using a current density of 5 mA/cm2, theresults of which are shown in Figs. 7(a) and 8. The platingoptimization is reported in [15] and more details on the platingchemistry can be found in [16]. In Fig. 7(a), the focused ionbeam (FIB) cross-section after Cu fill is presented, and tworegions with different Cu grain sizes are observed. At the top

836 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 6, JUNE 2011

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(a) (b)

(c) (d)

Fig. 8. FIB images of a series of partially filled vias, (a) 15 min, (b) 30 min,(c) 45 min, (d) 60 min of Cu deposition. In all cases, the current density was5 mA/cm2. The photosensitive resist mask is still present at the wafer surface.For preparation reasons, a small stripe of tungsten has been deposited on theCu top surface to encapsulate the material during FIB cross sectioning [wellvisible in (d)]. The chemistry used results in a in a void-free “bottom-up”filling.

of the via, the grain size is much smaller than at the bottom.Even a well-defined interface is visible. Experiments show thatthe incorporation of additives has a strong effect on the Cugrain size especially the incorporation of the leveler (JanusGreen B) leads to smaller Cu grains [17]. A 4-μm-thick tin(Sn) layer is then deposited directly after filling of the TSVswith Cu. The possible presence of voids in the filled TSVwas investigated by slanted cross-sectioning, which enabledoptical microscope inspection at different depths on multiplesuccessive vias. In the schematic Fig. 9(a), the white dot inthe Cu matrix depicts a filling defect, i.e., a void. Cross-sections are made in the “vertical” plane. When a row of vias ispolished under a small angle, which is depicted by the slopingline, one obtains information on the filling quality at differentlevels in the structure. For instance, for cross-section I, thepolymer liner (outer ring, “green”), the Cu (“orange”), and Sn(center dot, “pink”) are visible. Via II, III, and V are sectionedin the defect-free part of the Cu above and below the defect,respectively. For via IV, the cavity shows up. The results onthe Cu-filled TSV samples are shown in Fig. 9(b) and indicatea void-free TSV Cu filling. After stripping the plating resist,the Ti/Cu seed layer is selectively removed in presence ofSn bumps using a modified Cu etchant and HF-based Ti-etchchemistry. This completes the TSV and microbump fabricationprocess.

Eventually, the plating process can be modified to perform aconformal Cu ECD redistribution lines RDL, which implies inthat case the processing of another layer of dielectric polymerand Sn bump processing.

Further process integration proceeds with die stacking:TSV wafers were singulated into 5 × 5 mm2 single dice by

(I) (II) (III)

(a)

(b)

(IV) (V)

Fig. 9. (a) Schematic representation of slanted cross-sections from a rowof five TSVs that are not completely filled with Cu. (b) Optical microscopeimages showing the electroplated Cu at several depths in the imec TSV. FromD0 (bottom of the TSV) to D5 (top of the TSV), no voids were found in theCu regions. On D5, the cross section stops at the level of the Sn bumps.

(b)

(a)

Fig. 10. (a) SEM micrograph showing a 50-μm-thin TSV die bonded on afull thickness landing die. (b) Tilted microscope image of the stacked dies.

traditional dicing and then each TSV die was bonded to alanding die using Cu/Sn micro-bump transient liquid phasebonding TLP technology. The bonding process is done in aflip-chip bonder at 260 °C. A cleaning agent, such as flux-IF8300, is put on the dice prior to bonding. Then a pressureof 5 MPa is applied to bond the two dice during whichflux is squeezed and uniformly re-distributed across the gap.The bonding time was approximately 20 min. Eventually, thecarrier was removed after die bonding. Scanning electron andoptical microscope images of the Cu-filled TSVs and stackeddice are shown in Fig. 10. More details of this stacking processcan also be found in [18].

CIVALE et al.: 3-D WAFER-LEVEL PACKAGING USING SPIN-ON-DIELECTRIC POLYMER LINER TSVs 837

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1401301201101009080706050403020100

Sorted Sample Number

min

mean

max

extracted from 15-TSV daisy chain measurementextracted from 32-TSV daisy chain measurement

0 5 10 15 20 25 30 35 40

Fig. 11. Single TSV chain element resistance obtained from the measurementof 15 and 32 TSVs in series daisy chains. The values are sorted (from smallerto large larger).

III. ELECTRICAL CHARACTERIZATION AND RELIABILITY

A. Metallization Mask Layout

The test vehicle includes routing lines on the wafer backsidebetween TSVs, and between TSVs and probe pads. This allowsfor the electrical characterization (four-point probe) of TSVdaisy chains with 15 and 32 TSVs connected in series. Thesedaisy-chain test structures are interlaced to allow for bothcontinuity and isolation measurements [Fig. 7(b)].

After die stacking, additional test structures between bothdies can be measured. These include Cu meanders for Curesistivity measurements and four-point Kelvin structures forsingle TSV resistance measurements and TSV daisy chains.The characterization results are discussed in the next sections.

B. Test Chip Metal Resistivity

The sheet resistance of the Cu damascene interconnect onthe test chip was extracted from meander test structures andfound to be approximately 77 m�/square.

1) Interlaced TSV Daisy-Chain Resistance: Using the as-described TSV as a building block, peripheral interlaced daisychains of different lengths were successfully fabricated andelectrically characterized. The electrical tests were performedon a wafer prober with a temperature-controlled chuck, heldat 25 °C during the measurements. Four-probe resistancemeasurements were performed on the (unstacked) 15 and 32TSV daisy chains. The measurements are normalized to singleTSV chain element resistance (Rsingle element TSV) and shownin Fig. 11. An average value of about 75 m� per single TSVchain element was obtained with a limited spread.

The contribution of the top and bottom Cu wires, ensuringthe electrical continuity of the daisy chains, i.e., RWIRING, canbe calculated using the sheet resistance values extracted fromthe meander test structures. This wiring resistance is subtractedfrom the measured daisy-chain resistance in order to obtain thesingle TSV chain element resistance as

Rsingle element TSV = (RM − RWIRING)

N. (2)

Sing

le T

SV r

esis

tanc

e (m

Ohm

)

30

25

20

15

10

5

0

Sorted Sample Number

min

I V

mean

maxTSV1 TSV2 TSV3

0 5 10 15 20 25 30

Fig. 12. Single TSV resistance measured on bonded stacks. The value of theresistance also includes the resistance of the Cu/Sn intermetallic. The valuesare sorted (from smaller to large larger). The inset shows a schematic crosssection of the Kelvin-like structure used for the measurement of a single TSVresistance.

In (2), RM is the measured daisy chain resistance, and Nthe number of single TSV chain elements in the measureddaisy chain.

The extracted resistance values Rsingle element TSV includesthe resistance of the Cu TSV plug, RCuTSV, the Sn bumpresistance RSn, and the resistance corresponding to the topand bottom Cu metal pad RCu PAD, top and RCu PAD, bottom,

respectively, as given by relation (3)

Rsingle element TSV = RCu TSV + RSn + RCu PAD, top

+ RCu PAD, bottom. (3)

For the single TSV chain element resistance extraction, thethickness of the bottom damascene Cu metal was measuredby cross-section FIB and found to be about 280 nm, whereasthe thickness of the top Cu pad was 11 μm. The resistanceof the damascene Cu metal contributes about 80% to the TSVresistance measurement.

2) Kelvin TSV Resistance: In the case of stacked samples,the landing die layout also includes Kelvin test structures forsingle TSV resistance measurement, for which the contributionof the top and bottom Cu pad resistance is minimized. Mea-surement results and a schematic of the Kelvin TSV measure-ment structure are shown in Fig. 12. The resistance of a singleCu TSV and a Cu/Sn intermetallic microbump was measuredto be in the range of 10–24 m�. The resistance correspondingto the Cu/Sn intermetallic has been separately characterizedand is estimated to 3–4 m� [18]. Theoretically, the 25-μm-wide 50-μm-long Cu plugs correspond to a resistance of2–3 m�. The measured resistance also contains a spreadingresistance contribution in the top and bottom contact pads. Asthe sheet resistance of these Cu damascene M1 layer is about77 m�/square, these spreading resistances may amount to tensof milliohms. In combination, these contributions correspondwell with the measured values. The measured resistance of asingle Cu TSV and a Cu/Sn intermetallic microbump presentedin Fig. 12 shows a rather large range of values. There area couple of reasons for this, and the contact to M1 BEOLis one of them. The BPSG layer is etched at the bottom

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0.96

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Sample Number

T0−5%

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after 100 TCafter 500 TCafter 750 TCafter 1000 TC

10 12 14 16 18 20

Fig. 13. Effect of thermal cycling on the daisy-chain TSV resistancemeasured on each of the nine dies after 100, 500, 750, and 1000 thermalcycles. No impact has been electrically observed, the daisy chains remaincontinuous, and the interlaced daisy chains stay isolated.

of the TSV to contact Cu M1 pad. This is done by eitherwet or dry etch and it is time-controlled. This means that thenonuniformity of this etch step affects the contact resistance ofthe Cu plug to the M1 pad. As the contact area is affected, thiswill influence the resistance introduced by current constriction(the smaller the contact area, the higher the constriction).Another reason is the variability of the M1 damascene processitself across the wafer. The variations in the microbumpstructures and small variations in the metallization are alsoexpected to slightly contribute to the spreading of the measuredvalues.

3) Reliability: Due to the high CTE mismatch between Siand the conducting material (Cu in this case) in the vias,thermomechanical reliability is a major concern [19]. In orderto assess this issue, thermal cycling was performed on the15- and 32-TSV daisy-chain test structures. Up to 1000 times1-h thermal cycles between −40 and +125 °C were per-formed. The measured daisy-chain resistance values are shownin Fig. 13. The TSV samples were also analyzed by scanningelectron microscopy. Stable resistance values and no electricalfailures were observed even after 1000 thermal cycles.

IV. CONCLUSION

We reported on a via-last TSV technology combinedwith wafer-level redistribution and microbumping. The TSVprocess flow uses a polymer dielectric as liner material,which reduces the capacitive coupling to the Si by an orderof magnitude. The electrical characterization of 15- and32-TSVs in series daisy chains gave an average value ofabout 75 m� per single TSV chain element. This valueincludes the resistance of the Cu plug plus the Sn microbumpand the contribution of the top and bottom Cu pad, the latterrepresenting about 80% of the total measured value. Moreover,single TSV resistance measurements where the contributionof M1 pad is minimized indicated a resistance in the rangeof 10–25 m� per TSV. The nature of the process flow, whichdoes not require lithography at the bottom of the TSV, and theconsistent and reliable electrical results reported in this paper

make this via-last Cu-filled TSV approach a versatile buildingblock for complex heterogeneous 3-D integrated systems.

ACKNOWLEDGMENT

The authors would like to thank R. Verbeeck for generalassistance in processing and scanning electron microscopeimaging. Thanks are also due to R. Agarwal and P. Limayefor assistance in die-to-die stacking.

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[9] J. Van Olmen, A. Mercha, G. Katti, C. Huyghebaert, J. VanAelst, E. Seppala, Z. Chao, S. Armini, J. Vaes, R. C. Teixeira,M. Van Cauwenberghe, P. Verdonck, K. Verhemeldonck, A. Jourdain,W. Ruythooren, M. P. Broeck, A. Opdebeeck, T. Chiarella, B. Parvais,I. Debusschere, T. Y. Hoffmann, B. De Wachter, W. Dehaene, M. Stuc-chi, M. Rakowski, P. Soussan, R. Cartuyvels, E. Beyne, S. Biesemans,and B. Swinnen, “3-D stacked IC demonstration using a throughsilicon via first approach,” in Proc. IEEE Int. Electron Dev. Meet.,San Francisco, CA, Dec. 2008, pp. 1–4.

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[11] Y. Civale, D. S. Tezcan, H. G. G. Philipsen, P. Jaenen, R. Agarwal,F. Duval, P. Soussan, Y. Travaly, and E. Beyne, “Die stacking using3-D-wafer level packaging copper/polymer through-si via technologyand Cu/Sn interconnect bumping,” in Proc. IEEE Int. Conf. 3-D Syst.Integr., San Francisco, CA, Sep. 2009, pp. 1–4.

[12] W. C. Chiou and C. H. Yu, “Production worthy 3-D interconnecttechnology,” in Proc. 3rd Int. Microsyst., Packag., Assembly CircuitsTechnol. Conf., Taipei, Taiwan, Oct. 2008, pp. 371–374.

[13] F. F. C. Duval, Y. Civale, C. Okoro, P. Soussan, and E. Beyne,“Polymer filling of silicon trenches for 3-D through silicon viasapplications,” IEEE Trans. Comp. Packag. Technol., to be published.

[14] F. F. C. Duval, “Evaluation of photosensitive spin-on-dielectrics for3-D wafer level packaging,” in Proc. 14th Symp. Polym. Microelec-tron., May 2010.

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CIVALE et al.: 3-D WAFER-LEVEL PACKAGING USING SPIN-ON-DIELECTRIC POLYMER LINER TSVs 839

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Yann Civale received the M.Sc. degree from theEcole Centrale Marseille, Marseille, France, in 2003,after the completion of his thesis with PhilipsResearch Laboratories, Eindhoven, The Netherlands,on the development and characterization of thermo-electric microgenerators for autonomous microsys-tems.

He joined the faculty of Electrical Engineering,Mathematics, and Computer Science, Delft Uni-versity of Technology, Delft, The Netherlands, in2004, where he conducted research toward the Ph.D.

degree on an innovative sub-500 °C crystalline silicon growth techniquefor forming ultrashallow abrupt junctions. Since 2008, he has been withthe Interconnect and Packaging Department, Interuniversity MicroelectronicsCenter (imec), Leuven, Belgium, where he is in charge of process integrationof various through-silicon via technologies.

Deniz Sabuncuoglu Tezcan received the Ph.D.degree in electrical and electronics engineeringfrom the Middle East Technical University, Ankara,Turkey, in 2002.

She joined the Interuniversity MicroelectronicsCenter (imec), Leuven, Belgium, in 2003, wherespecializes in process development and integrationof various components including 3-D stacking ofwafers, through-silicon vias, high-performance visi-ble and infrared imagers, and various microelectro-mechanical systems and microfluidics components.

She is currently the Leader of the Packaging Modules Component IntegrationTeam. She is the author/co-author of more than 80 technical publications inthe field.

Harold Philipsen received the M.Sc. degree inchemistry from the University of Utrecht, Utrecht,The Netherlands, in 2003, on the subject diffu-sion of hydrogen in yttrium and palladium thinfilms, studied with electrochemistry. He receivedthe Ph.D. degree in the subject of electrochemistryof anisotropic wet-chemical etching of silicon in2007. Part of the work was done at the EcolePolytechnique, Paris, France, where in situ infraredspectroscopy was used to investigate the kineticsof anodic oxidation of Si(111) in alkaline solution.

Together with the University of Twente, Enschede, The Netherlands, hestudied the dynamics of the morphology of Si(110) using in situ opticalmicroscopy. With the University of Nijmegen, Nijmegen, The Netherlands,he conducted experiments at the European Synchrotron Radiation Facil-ity, Grenoble, France, where the effects of various wet-chemical etchingtreatments on the Si(111) surface morphology were studied using in situX-ray diffraction.

He has been with the Interuniversity Microelectronics Center (imec), Leu-ven, Belgium, since 2008, focusing on the development of electrochemicaldeposition processes, such as for the 3-D program (metallization of through-silicon vias) and the development of metallization processes for solar cells.

Fabrice F. C. Duval received the M.Sc degree inchemistry from Paul Sabatier University, Toulouse,France, in 1999, and the Ph.D. degree from CranfieldUniversity, Bedfordshire, U.K., in September 2000,for his thesis entitled “PZT thick films for high-frequency transducers.”

He was a Post-Doctoral Research Officer work-ing on piezoelectric microelectromechanical systems(MEMS) devices at Cranfield University, where hewas involved in the fabrication and characteriza-tion of MEMS actuators. He moved to the Institut

d’Electronique, de Microélectronique et Nanotechnologie, Centre National dela Recherche Scientifique, Lille, France, where he worked on the developmentof piezoelectric micromachined ultrasonic transducers. In August 2007, hejoined the Interuniversity Microelectronics Center (imec), Leuven, Belgium,where he currently works on photosensitive spin-on dielectric polymers for3-D packaging and integration technologies.

Patrick Jaenen received the Graduate degreein chemical engineering from the TechnischeHogeschool DENAYER, Mechelen, Belgium, in1984.

He is currently a Senior Litho Process Engineer atthe Interuniversity Microelectronics Center (imec),Leuven, Belgium, where he is working in the lithogroup on 248- and 193-nm (dry and immersion)process development. He is also working on lithog-raphy for through-silicon via 3-D wafer integrationprocess.

Youssef Travaly received the Ph.D. degree in mate-rials science combined with the M.B.A. degree ingeneral management.

He has more than 16 years of cumulative workexperience in managing research and developmentprojects & programs aiming at providing insight andsolutions to industrial actors. He is currently withthe Interuniversity Microelectronics Center (imec),Leuven, Belgium, managing the industrial affiliationprogram on 3-D system integration. He has authoredor co-authored more than 100 research papers pub-

lished in journal and conference proceedings in the field of semiconductors,biomaterials, and ab initio calculations.

Philippe Soussan was born in France in 1976. Hereceived the M.Sc. degree in mechanical engineer-ing from the École Nationale Supérieure d’Arts etMétiers, Paris, France, in 1999. He received theMasters degree in material sciences from the EcoleNationale Supérieure des Mines de Paris, Paris, in2000.

He joined the Interuniversity MicroelectronicsCenter (imec), Leuven, Belgium, as a TechnologyResearcher for multichip modules. Since 2007, hehas been leading the Packaging, Microsystems, and

Hybrid Technology Group at imec. The group deals with complex processintegration using 3-D interconnects, advanced packaging, and microfabricationof scaling and non-scaling driven components. He has authored or co-authoredmore than 100 publications and holds several patents in this field. Hiscurrent research interests include interaction between processes and materialproperties, technology integration in advanced packaging, and microsystems.

840 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 6, JUNE 2011

Bart Swinnen received the Ph.D. degree in solid-state physics from the University of Leuven, Leuven,Belgium, in 1997.

He was a Post-Doctoral Fellow with the Universityof Leuven. He was a member of the Abstract StateMachine Language Engineering Team, Eindhoven,The Netherlands, where he developed stepper align-ment strategies for processed wafers. He joinedthe Interuniversity Microelectronics Center (imec),Leuven, Belgium, in 2003, where he first worked asa Program Manager for the wafer-level packaging

(WLP) Research Program. Later, he managed both the 3-D-WLP and 3-D-stacked integrated circuit programs. He is now the Director of the Interconnectand Packaging Department at imec.

Eric Beyne received the M.Sc. degree in electricalengineering and the Ph.D. degree in applied sciencesfrom Katholieke Universiteit Leuven, Leuven, Bel-gium, in 1983 and 1990, respectively.

He has been with the Interuniversity Micro-electronics Center (imec), Leuven, since 1986.Currently, he is a Scientific Director of AdvancedPackaging and Interconnect and a Program Directorof imec’s 3-D System Integration AffiliationProgram.

Dr. Beyne is a Strategic Director for Region 8(Europe) of the IEEE Components, Packaging and Manufacturing TechnologySociety, President of the International Microelectronics and Packaging Society(IMAPS) Benelux Committee, and a member of the IMAPS Europe LiaisonCommittee.