Z-Axis Interconnects Using Fine Pitch, Nanoscale Through-Silicon Vias: Process Developmeint

Silke Spiesshoefer, Leonard Schaper, Susan Burkett, Gowtham Vangara, Ziaur Rahman, Parthiban Arunasalam University of Arkansas

High Density Electronics Center Fayetteville, Arkansas 72701

479-575-3967, E-mail: sspiess@uark.edu

Abstract A through-silicon via (TSV) process provides a means of

implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today’s advanced MCMs. This technology overcomes the RC delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and 3-D stacking technology have the potential to significantly reduce the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. However, even though TSVs have great potential, there are many fabrication issues that must be considered.

The rationale for systems based on TSVs, and a fabrication process development plan for the creation of these structures, was presented at the 2003 ECTC conference [l]. The development plan included five main areas for TSV fabrication: formation of the blind vias, deposition of the insulation and seed layers, copper plating, wafer thinning, and wafer backside processing. The project goal is to create high aspect ratio vias four to six microns in diameter on 20-micron pitch in wafers that are subsequently thinned to a thickness of 15 to 20 microns. This paper will discuss the results obtained during the TSV fabrication in detail and explain the process development decisions that were made.

Introduction The aim of this research is to examine the fundamental

limitations and process challenges in providing fine pitch TSVs (Through Silicon Vias), with the goal of developing a robust process for the creation of these structures in a manner compatible with IC fabrication technology. Extremely dense electronics can be created by stacking thin silicon chips with interconnections in the z-axis. The creation of a robust TSV process is one enabling technology for the stacking of thin silicon ICs so as to provide heterogeneous integration and a potential increase in the physical density of some electronic systems functions by a factor of 100. By dramatically increasing the area interconnect capability of a given IC, also by a factor of 100 over today’s flip chip dimensions, this technology enables potential architectural configurations for true “vertical integration” among multiple IC layers. Moreover, long line RC limited interconnect delays can be dramatically reduced by opening up interconnect in three dimensions instead of two [ 21.

The approach includes parallel development of both standard reactive ion etching (RIE) and inductively coupled plasma (ICP) processes for the formation of the vias.

Depending on the resulting sidewall slope, chemical vapor deposition (CVD) of silicon dioxide can be used to deposit an insulating layer, followed by sputtering of barrier and plating seed layers. The vias are then fully filled with electroplated copper. Wafers are attached front side down to a carrier wafer, mechanically ground, and spin etched, to expose the blind vias. Additional insulator and metal deposition forms pads on the backside of the thin wafer, allowing subsequent attachment of singulated ICs in a 3-D stack.

This work is part of the larger DARPA VISA program (Vertically Integrated Sensor Arrays) whose goal is to provide per-pixel image processing by attaching a stack of :several silicon processing elements to the back of a large image sensor, resulting in extremely dense signal processing hardware.

Via Formation The first step in creating TSVs in a completed IC wafer,

or in a test wafer as is currently being used, is to create a via structure that is 4-6 um in diameter and 15-20 microns deep in the silicon. There are three critical areas during this via formation step: maintaining feature size, minimizing undercutting, and providing proper sidewall taper as shown in Figure 1.

Undercut /

Insulating Layer I

Potential Void Region /

+ Taper

Figure 1. Via profile

Since a 2 micron feature size is near the minimum resolution of the lithography tool, tight control is needed during exposure and development, since the mask feature must be smaller than the required via diameter. Oxide is used as a hard mask during via formation, therefore undercutting must be minimized during wet etching, since this could result in copper plating difficulties. Therefore, an intermediate hard bake step is added to control over etching. This step allows the photoresist to act as a protection layer during the final wet etching process, as shown in Figure 2.

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The CVD process was carried out in a PlasmaTherm SLR 730 using the parameters as follows: SiH4 85 sccm, NzO 450 sccm, Nz 450 sccm, Power 55 W at 13.5 MHz. Deposition at 325°C for 5.5 minutes resulted in a uniform layer of SiOz .5 pm thick.

A metal layer consisting of a barriedadhesion layer and a copper seed layer is then deposited. Physical vapor deposition (sputtering) is used to deposit these layers. Sputtering has proven effective if the via geometry is properly controlled, as shown in Figures 4 and 5. The barrier layer consisted of a lOOOA layer of titanium, and was produced in an XM-8 sputtering system with Argon at 5mT and 2500 watts of power for 11 seconds. The seed layer is 3150 A of copper deposited in the same sputtering system using 3000 watts of power and 5mT pressure for 20 seconds.

Figure 2. Photoresist protection layer. ‘Two methods are being studied to form properly shaped

blind vias: conventional reactive ion etching (RIE), and Inductively Coupled Plasma (ICP) utilizing the Bosch process. The desired via must have slightly tapered sidewalls, so that subsequent deposition of the oxide insulator and metal barrier and seed layers will achieve uniform coverage. However, the vias must not taper too much, which would create too small a via at the bottom and could limit the desired depi:h, as shown in Figure 3a.

Figure 4. Insulation and seed deposition cross-section.

Figure 3. Via Etch Profiles. (a) too much sidewall taper, (b) good taper.

‘The ICP process development is at a very early stage, due to equipment bringup issues. Normally, ICP is used to produce absolutely straight side walls, but published papers have indicated that tapered sidewalls can be produced by appropriate modification of process parameters during the etch step [3,4].

Meanwhile the RIE process has produced reasonably good vias, as shown in Figure 3b. These vias were produced using a PlasmaTherm SLR 720 system (currently kown as Unaxis) with the conditions as follows: SF6 40 sccm, 02 35 sccm, power 180 W, pressure 100 mT, and time 30 minutes.

Insulation and Seed Layer Deposition . ‘Following via creation, chemical vapor deposition (CVD) is used to deposit Si02 in order to insulate the subsequent via meh1 from the surrounding silicon. Ideally, coverage over the entire via structure should be uniform, just like insulation on a wire. Yet the large aspect ratio of the via hole can be a prohlem, requiring careful optimization of deposition parameters. It is also critical to control stresses in the insulating layer, to ensure structural integrity under subsequent processing and operating conditions. Measuring the I hickness is done by careful cross sectioning.

’

Figure 5. Insulation and seed deposition SEM.

Copper Plating Following seed layer deposition, the via is plated with

copper until solid, with no voids that would entrap the plating solution and cause subsequent failures when the device is heated above the boiling point of the trapped liquid. The basic issue is one of mass transport of the necessary constituents in the plating solution, and the difficulty of moving those constituents to the bottom of a high aspect ratio via hole. Reverse pulse plating, which is used in the circuit board industry for the uniform plating of high aspect ratio through holes, is required. In this technique, copper is not deposited continuously; plating current is applied in short pulses to give plating bath constituents time to reestablish an adequate concentration at the plated surface. Periodically, reverse current pulses are applied to remove material from more thickly plated regions. Careful control of bath chemistry,

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pulse current, time, and frequency are used to optimize results. [5]

In order to ensure that plating solution continuously reaches the sidewall area of the vias, a form of fountain plating is used. A special “shower head” has been designed to direct many jets of plating solution directly at the surface to be plated. The streams of plating solution pass through a perforated anode before impinging on the wafer surface, as shown in Figure 5.

In the eventual case of plating many thousands of vias in a silicon wafer, plating uniformity across the wafer is a major concern. Both optical and mechanical measurements of plating thickness at several locations in many vias are needed. Careful control of the current distribution over the wafer also helps to achieve the necessary spatial plating uniformity.

Feature sizes greater than 10 microns have been realized with the current system as shown in Figure 6 . However, when the via size is less than 10 microns, the via closed at the top before plating was completed, as shown in Figure 7.

Figure 6. 10 um plated via.

Figure 7. 7 um plated via with voids.

Adjustments were made to the reverse pulse plating program which resulted in a bottom-up fill without closure at the top. This is shown in Figure 8.

Figure 8. 7 um plated via with bottom up filling. The plating solution used is a sulfuric acid and copper

sulfate based solution obtained from Enthone Inc., called CUBATH SC. It contains 33.5 average oz/gal of copper sulfate and 8.5 average oz/gal of copper upon delivery. Additives, also obtained from Enthone, are added to the solution in the amount of 10 mL/L as specified by Enthone [61. The anodes used are 99.99% pure copper with 0.04 to 0.06%; phosphorous.

Once the anodes are conditioned, they are placed in the plating bath with the wafer and are ready to plate. The current density used is 2.0mA/cm2. The plating profile is as follows: 30ms forward / 1.5 ms reverse / 30 ms off.

Wafer Attachment After forming the solid copper via plugs, the processed

wafer must be attached to a carrier wafer and made ready for mechanical grinding. Initially, a 150 pm thick thermal release tape was used to attach the front of the processed wafer to the carrier wafer. The tape offered excellent attachment between the process wafer and sacrificial wafer, with no voids or air bubbles. It endures the wafer thinning process, which includes abusive procedures such as wafer lapping, grinding and polishing. It also survived further reduction in the thickness using the spin-spray etch device which uses Hydrofluoric acid as the primary etchant, and finally CMP for finer polishing. However, when subjected to a temperature of more than 60°C the CTE mismatch between the tape and the thinned silicon caused internal stresses which cracked the thinned wafer. Since nominal processing temperatures of 120°C and above are required, this method proved to be unsatisfactory and other methods were explored.

We attempted to use photoresist as a bonding agent. Positive A24330 resist was used to attach the two wafers together. The resist is spin coated on and then is soft bilked at 90°C for 3 minutes to drive all the solvents away before the wafers are brought into contact with each other. They are then subjected to hard bake at temperature close to 100°C for 30 minutes. Grooved sacrificial wafers were used in order to provide escape paths for the gasses that are released during the hard-bake. Scanning Acoustic Microscope (SAM) was used to scan the intermediate layers to examine the bonding results. Figure 9 shows a wafer bonded using photoresist and close examination of the picture shows around 10% unbonded area.

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Figure 9. SAM Image, Photoresist Bonding These unbonded areas are generated due to the trapped

residual gasses trying to escape. Since void free bonding is absolutely necessary for further processing of the wafers, the alternative process of plasma bonding was investigated.

Before performing plasma bonding, the front surface of the wafer must be flat. A thick layer (4um) layer of silicon dioxide is PECVD deposited on the front-side of. the processed wafer. The topology of the deposited oxide follows the pattern of the metal underneath, and is then polished on the lapping machine using Colloidal Silica on an Oxide Polishing Chem-cloth. Initial results show that lum of oxide is siiccessfully removed in 30 minutes from a bare silicon wafer having an initial oxide thickness of 4 um. This polishing technique has also been used on dummy wafers having metal features under the oxide and yielded good results.

The ICP-RIE system is used in performing plasma bonding where the surfaces of the wafers to be bonded are exposed to oxygen plasma. Plasma bonding, in contrast to many high temperature bonding processes, uses temperatures as low as room temperature. The parameters used are a chamber pressure of 40mTorr, oxygen flow-rate of 48 sccm, RF power of 15W, coil power of 800W and an exposure time of 2 minutes. Following exposure to the oxygen plasma, the wafers are rinsed in DI water, dried and brought into contact at room temperature. Figure 10 shows the SAM scan obtained from bonding silicon to silicon after 24 hrs from the time of contact.

7Nhen the wafers are brought into contact after plasma immersion and DI-water dip, they bond to each other with hydrogen bonds between the adsorbed water and hydroxyl groups. During storage of the bonded wafer at room temperature, the surface energy increases due to the formation of S i-0-Si bonds according to the following reaction:

SiOH + HOSi + Si-0-Si + H20

The bond obtained is bubble-free in the center but shows some bubbles or improper bonding at the edges. This is beca.use of the use of razor blades between the wafers to

Figure 10. SAM Image, Si-Si Plasma Bonding. allow the air from the center to exit along the radius of the wafer. This process proved successful: however we need a bonding process between oxide and silicon, since the top of the wafer will be covered with planarized silicon dioxide.

Plasma bonding between silicon and silicon dioxide surfaces has also been implemented using the same process described above. Initial results are promising, but process refinement is continuing.

Wafer Thinning Once it has been successfully attached to the carrier wafer,

the wafer is ready to be thinned. After attachment the wafer was ground from 380 pm to 70 pm using 9 pm Alumina powder for 2 hours. Then the thinned wafer was polished using 0.3 pm Alumina powder for 1 hour, and the final thickness was 60 pm. The planarity obtained is f 4 pm. We are working to improve the bonding technique to obtain better planarity of the stacked wafers, so the planarity of the thinned wafer will also improve. Using this technique, the wafer can be thinned to 30 - 40 pm with k 4 pm variation. But to release the mechanical stress of the thinned wafer (-30 pm) spin spray etching or RIE is necessary. When the wafer becomes this thin, it becomes flexible, as shown in Figure 11.

Figure 11. Flexibility of a Si wafer thinned to 30 um.

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The spin spray objective was to develop a process for fine removal of material for the thinning process. The desired final thickness is 15 microns with the wafer planarity within +2 microns. The spin spray etch machine used was the Laurel1 WS-400A-GTFM-FULL. The initial results using the system as shipped showed poor planarity. The center of the wafer was very thin compared to the edges of the wafer. To improve the planarity of the wafer, a new showerhead was designed and installed in the system. The showerhead is shown in Figure 12. The results obtained using the new showerhead showed the center of the wafer was now thicker than the edges, which is the exact opposite of what was initially seen. This allowed us to define the range for the system. To solve this problem, a redesign of the showerhead is in process.

Figure 12. Wafer etch showerhead.

Another problem with spin spray etching is the pits that are produced all over the wafer, as shown in the SEM photos in Figure 13 and 14. With the use of the AFM, the pits at the center showed to have a greater depth (maximum 3.073 pm and in average 355 nm) and also a greater density, than the pits at the edges (maximum depth 535 nm and average 88 nm). Redesigning the showerhead should also solve this problem.

Figure 13. SEM of thinned wafer using spin spray etching (center region)

Figure 14. SEM of thinned wafer using spin spray etching (at the edges)

The goal of wet etching is to reduce the thickness of the wafer to within a few microns of the blind vias. Then the wafer is again placed in the STS system and silicon is removed by RIE. Because of process selectivity, the vias, coated with silicon dioxide, are left standing proud of the surface. The wafer is then ready for backside processing.

Backside Processing and Testing The backside processing steps create via connection pads

to allow for eventual system assembly. After the wafer has been thinned, it is placed in the PECVD system where an oxide layer is deposited. Using photolithography and wet etching, the bottoms of the vias are exposed. Copper pattern plating over a seed and barrier layer is then used to create the bottom connecting pads as shown schematically in Figure 15.

Figure 15. TSV Schematic with bottom connecting pads.

To determine the performance, yield, and via integrity of the TSV process, wafers will be probed from the backside. Initial measurements will be done on process development samples. The via isolation and resistance can be determined from this initial test, if appropriate metalization patternL, c- were applied to the front of the wafer. Additional masks for front and back side metal will be used to define final test structures that will allow for a complete study of the interconnect. These test structures will be used to measure via chain continuity and resistance, four point probe via resistance, and via isolation at DC. These tests can be made with the wafer still attached to the carrier wafer.

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Conclusions This paper has described the process development under

way for TSVs as a means to perform Z-axis interconnection among several stacked silicon slices. The TSV process is elaborate, and is not yet completely worked out, but it shows great promise as a way to achieve architectures in silicon impossible with any other method.

Acknowledgements This material is based upon work supported by DARPA

under Award Number N66001-02- 1-894 1. Any opinions, findi ags, and conclusions or recommendations expressed in this paper are those of the authors and do not necessarily reflect the views of DARPA.

References [ l ] S. Spiesshoefer, L. Schaper, “IC Stacking Technology

Using Fine Pitch, Nanoscale Through Silicon Vias,” 2003 ECTC Proceedings, pp. 631 - 633.

[2] I,. Schaper and S. Spiesshoefer, “System Architecture Iinplications of 3-D Interconnect Technologies,” Proc. Int. Conf. On Advanced Packaging and Systems, pp. 33 - 37, 2002.

[3] A. Ayon, R. Bayt, and K. Breuer, “Deep reactive ion etching: a promising technology for micro- and nanosatellites. Smart Materials and Structures, pp. 1 135- 1144. E. Chow, “Electrical Through-Wafer Interconnects and h‘licrofabricated Cantilever Arrays Using Through-Wafer Silicon Etching,” Electrical Engineering Dissertation at Stanford University, 2001. S’tephen Kenny and Kai Matejat, “HDI Production Using Pulse Plating with Insoluble Anodes,” CircuiTree, February 21,2001. Enthone, CUBATH SC Data Sheet, Enthone Inc., 2001.

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