Unified Compact Modeling of Emerging Multiple-Gate MOSFETs

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Unified Compact Modeling of Emerging Multiple-Gate MOSFETs Xing Zhou, Guan Huei See, Zhaomin Zhu, Shihuan Lin, Chengqing Wei, Guojun Zhu, Guan Hui Lim School of Electrical and Electronic Engineering, Nanyang Technological University 50 Nanyang Avenue, Singapore 639798. [email protected] Abstract - A generic double-gate (DG) MOSFET follows a generalized voltage equation from the first integral of Poisson equation and Gauss' law applied at the two gates, which is implicit and, in general, non-integrable when the silicon film is doped. Only DG with undoped body can be solved with implicit surface-potential solutions, or approximate surface-potential solutions for doped symmetric-DG (s-DG) structures. The most challenging task in DG compact modeling is the surface-potential solutions for the generic asymmetric-DG (a-DG) doped-body device: scalable over oxide thickness (from DG to SOI), body thickness and doping (from ultra-thin-body/fully-depleted to bulk-like/partially-depleted), and gate bias (from s-DG and common-gate a-DG to independent-gate a-DG). Once it is conquered, the model will be able to cover different structures and operations with seamless transitions. Another challenge is extension of a DG model to multiple-gate (MG) such as tri-gate (TG) and silicon nanowire (SiNW) devices, or a unified model that encompasses all different configurations. In this paper, we present solution methods towards such a unified MOS compact model based on the unified regional modeling (URMVI) approach. Index Terms - compact model, double gate, FinFET, MOSFET, multiple gate, silicon nanowire, SOI, surface potential, ultra-thin body, unified regional modeling. I. INTRODUCTION With four decades of continued scaling of conventional bulk and silicon-on-insulator (SOI) CMOS technologies, nonclassical MOSFET structures have been emerging, ranging from earlier (planar) partially-depleted (PD) or fully-depleted (FD) ultra-thin body (UTB) SOI MOSFETs, to emerging (vertical) symmetric/asymmetric double-gate (s-DG/a-DG) or tri-gate (TG) FinFETs, either on SOI or bulk-Si with common or independent gate biases, and to recent surrounding-gate (SRG) silicon-nanowires (SiNW) such as omega-gate (OG) or gate-all-around (GAA) MOSFETs, all implementable with compatible CMOS technologies. Structural, process, and material parameters of these devices include gate workfunction, gate insulator thickness and dielectric constant, silicon body thickness and doping, source/drain contact type and doping, in addition to conventional device geometries such as channel length and width that, depending on device structure, are determined by lithography in planar devices or by process in vertical devices such as FinFET's height and width or SiNW's diameter. In this paper, we review various device structures and their inter-relationships as well as corresponding formulations. We present various approaches and solution methods towards such a unified MOS compact model based on the unified regional modeling (URM) approach. Regional/explicit solutions are available for the generic doped-body a-DG in accumulation, depletion, weak/volume-inversion regions, and approximate solutions in strong-inversion region for the two gate's surface potentials. The unified solutions are obtained with smoothing functions, which contain the essential physics captured in the regional solutions that are otherwise impossible to obtain, and can be applied to terminal current/charge models with physical layer thickness and doping scalability. The selected results demonstrate a first step towards unification of MOS compact models for the existing bulk/SOI and emerging MG MOSFETs with seamless transitions and selectable accuracy. II. GENERIC MULTIPLE-GATE MOSFET A. Generic Multiple-Gate Structure A generic DG/SO1 n-channel MOSFET is shown in Fig. 1, with the physical and material parameters labeled, in which the subscripts '1' and '2' are associated with gates 1 and 2, respectively. The channel voltage Vcr(y) is equal to Vsr at the source end (y = 0) and Vdr at the drain end (y =L). V1 is a reference voltage that is taken as the lowest voltage in the silicon body (it is equal to Vb if there is a body contact biased at Vb as for bulk-MOS; or Vs when there is no body contact as for SOI/DG). The source/drain junction depth (Xj) can be smaller than the body thickness (Tsi) as in bulk/PD-SOI MOSFETs or equal to Tsi as in DG/TG FinFETs. Fig. 1. Generic MG MOSFET structure and coordinate. 1-4244-1098-3/07/$25.00 c2007 IEEE 3 1 IEDST 2007

Transcript of Unified Compact Modeling of Emerging Multiple-Gate MOSFETs

Unified Compact Modeling of Emerging Multiple-Gate MOSFETs

Xing Zhou, Guan Huei See, Zhaomin Zhu, Shihuan Lin, Chengqing Wei, Guojun Zhu, Guan Hui Lim

School of Electrical and Electronic Engineering, Nanyang Technological University50 Nanyang Avenue, Singapore 639798. [email protected]

Abstract - A generic double-gate (DG) MOSFET follows ageneralized voltage equation from the first integral of Poissonequation and Gauss' law applied at the two gates, which isimplicit and, in general, non-integrable when the silicon film isdoped. Only DG with undoped body can be solved with implicitsurface-potential solutions, or approximate surface-potentialsolutions for doped symmetric-DG (s-DG) structures. The mostchallenging task in DG compact modeling is the surface-potentialsolutions for the generic asymmetric-DG (a-DG) doped-bodydevice: scalable over oxide thickness (from DG to SOI), bodythickness and doping (from ultra-thin-body/fully-depleted tobulk-like/partially-depleted), and gate bias (from s-DG andcommon-gate a-DG to independent-gate a-DG). Once it isconquered, the model will be able to cover different structuresand operations with seamless transitions. Another challenge isextension of a DG model to multiple-gate (MG) such as tri-gate(TG) and silicon nanowire (SiNW) devices, or a unified modelthat encompasses all different configurations. In this paper, wepresent solution methods towards such a unified MOS compactmodel based on the unified regional modeling (URMVI) approach.

Index Terms - compact model, double gate, FinFET,MOSFET, multiple gate, silicon nanowire, SOI, surface potential,ultra-thin body, unified regional modeling.

I. INTRODUCTION

With four decades of continued scaling of conventional bulkand silicon-on-insulator (SOI) CMOS technologies,nonclassical MOSFET structures have been emerging, rangingfrom earlier (planar) partially-depleted (PD) or fully-depleted(FD) ultra-thin body (UTB) SOI MOSFETs, to emerging(vertical) symmetric/asymmetric double-gate (s-DG/a-DG) ortri-gate (TG) FinFETs, either on SOI or bulk-Si with commonor independent gate biases, and to recent surrounding-gate(SRG) silicon-nanowires (SiNW) such as omega-gate (OG) orgate-all-around (GAA) MOSFETs, all implementable withcompatible CMOS technologies. Structural, process, andmaterial parameters of these devices include gateworkfunction, gate insulator thickness and dielectric constant,silicon body thickness and doping, source/drain contact typeand doping, in addition to conventional device geometriessuch as channel length and width that, depending on devicestructure, are determined by lithography in planar devices orby process in vertical devices such as FinFET's height andwidth or SiNW's diameter.

In this paper, we review various device structures and theirinter-relationships as well as corresponding formulations. Wepresent various approaches and solution methods towards such

a unified MOS compact model based on the unified regionalmodeling (URM) approach. Regional/explicit solutions areavailable for the generic doped-body a-DG in accumulation,depletion, weak/volume-inversion regions, and approximatesolutions in strong-inversion region for the two gate's surfacepotentials. The unified solutions are obtained with smoothingfunctions, which contain the essential physics captured in theregional solutions that are otherwise impossible to obtain, andcan be applied to terminal current/charge models with physicallayer thickness and doping scalability. The selected resultsdemonstrate a first step towards unification of MOS compactmodels for the existing bulk/SOI and emerging MGMOSFETs with seamless transitions and selectable accuracy.

II. GENERIC MULTIPLE-GATE MOSFET

A. Generic Multiple-Gate Structure

A generic DG/SO1 n-channel MOSFET is shown in Fig. 1,with the physical and material parameters labeled, in whichthe subscripts '1' and '2' are associated with gates 1 and 2,respectively. The channel voltage Vcr(y) is equal to Vsr at thesource end (y = 0) and Vdr at the drain end (y =L). V1 is areference voltage that is taken as the lowest voltage in thesilicon body (it is equal to Vb if there is a body contact biasedat Vb as for bulk-MOS; or Vs when there is no body contact asfor SOI/DG). The source/drain junction depth (Xj) can besmaller than the body thickness (Tsi) as in bulk/PD-SOIMOSFETs or equal to Tsi as in DG/TG FinFETs.

Fig. 1. Generic MG MOSFET structure and coordinate.

1-4244-1098-3/07/$25.00 c2007 IEEE 31 IEDST 2007

Osl = (0(0, y) and ¢s2 =A(Tsi, y) are the surface potentialsalong the channels of the two gates, which are the solutions ofthe voltage equations (first integral of Poisson equation plusGauss' law applied at the two gates). We define the "zero-field" potential A) _ /(X0, y) where XO is the location alwayshaving O'O = do(X0, y)/dx = 0. In s-DG, 0, is always located inthe middle of the body (XO = TsJ12) and OslI = Os2, and incommon-gate a-DG (ca-DG) (Vgl = Vg2 and OsI :# ¢s2)A )0 isusually located inside the body. For independent-gate a-DG(ia-DG), however, 0O can be located outside the body (i.e., nozero-field inside the body). Since it is known [1] that the firstintegral of Poisson equation cannot be obtained for the generica-DG with doped body, we will treat the generic a-DG byextending the s-DG solution as two coupled solutions of theindividual MOSFETs with their own ¢)o and ¢)o2B. Generic Voltage Equation

Like for bulk-MOS model formulation, generic DG-MOSvoltage equations for the surface-potential solutions can beobtained from the first integral of Poisson equation and Gauss'law applied to the two gates. Poisson equation under gradual-channel approximation (GCA), together with Boltzmannstatistics for (non-equilibrium) carriers, is written as

in which 9s1 = ¢)sI Vth, 9oI = VollVth 9fFp = /Fp Vth, andvcr= Vcrlvth are the normalized (to thermal voltage, vth) surfacepotential, zero-field potential, hole imref, and channel voltage,respectively. sgn(x) is the sign function. The boundaryconditions (at x = 0 and x = Xol) are:

(4a)

and x = Xj is always defined as the zero-field location withEoj = -0¢)1= O (assuming due to Vgl alone). Applying Gauss'law at gate 1,

(5)q=-;1 = + £oxl Vgf l 1slesi Toxl

where Ve = Vgrl - VFBI is the flatband-shifted gate voltage, itgives one (input) voltage equation for gate 1:

Vgf I - (qsl = sgn (9p51 ) f1Qf, (9p5i , oil, Vcr)

where Vgfl = VgfllVth, Coxj = c,,IIToxj = K0xl0lToxl,

)'I = 'Y1+ hI -Y = /2q8,,NA /Coxl ,

(6)

(7)

p q(p-n+ND NA ) = q (n-P +NA ND )

esi esi esi

q Ln e(0-0Fn)IVth _ n e-(O-FW)Ivth + n e0Fp I," - n e-OF, /Vh

i~±cSi ~ ~

qNA Le(o AF,)I -ee ±1 e (sF + Fp) Vh

= qNA Le(0hFp Ir)/Vh _ e-IV h ±1 e (2 FP+V- ) ]Vlh

G(75,L/r)cSi

in which

in which NA niexp(9Fp).Similar sets of equations can be obtained by changing all

subscripts '1' to '2' for the respective expressions assumingdue to Vg2 alone, as if the two MOSFETs are independent and

(1) in parallel, each having its own surface potential (q)sl, ¢)s2) andzero-field potential (o0,1, )0,2). For s-DG (Vgl= Vg2= Vg),O5sI = 1s2 =Os and Ool = 5o2 = )o- This formulation alsoconverges to bulk-MOS solutions in which ol = (o2 = 0, since(6) converges to the conventional voltage equation for bulk-MOS, in which (3a) is given by

(8)

f ((9p Vb ) =e2 V,) (N ) eP -) 9

'cr OFn OFp (2)

is the electron-hole quasi-Fermi potential difference (imrefsplit) as a result of the voltages applied at the source/drain(and bulk) terminals. The first integral of (1) gives thenormalized surface field at gate 1:

Fs ((sl,(ol, cr) tG (0 cr)do]E2

V2qNA / -Si

sg ((P,I ) ;;h ,e 0(e e )(pl(l)

+ (e-'Pl - e-)1)±+ (yp - (ol ) =- sgn (y51 ) Vf ((sl RoI,Vcr)

fy (9si, 9o0,l Vcr) fo (0sl,qol,VFr)/Vth

=e 2 +VI',)(e`, ( ND) (p)it + e e ) ( A ())n7) (ND () (NA )

C. Generic Surface-Potential Solutions

For generic a-DG MOSFETs, the relations between qs5 andqj (j = 1, 2) can be obtained from regional solutions. Whenthe sum of the two maximum depletion widths (Xdml, Xdm2) byeach individual gate is smaller than the body thickness, thetwo MOSFETs are indeed in parallel and independent. Whenthe sum of the two (individual) depletion widths is larger thanTsi, the key link between Os, and qs2 iS to find the "full-depletion" gate voltages (Vgl,FD, Vg2,FD) that satisfies thecondition

Xdl,FD (Vgl,FD ) Xd2,FD (vg2,FD)) (9)

For s-DG, the above condition becomes XdFD(VgFD)= Ts12.Regional solutions with full-depletion approximation can beobtained to derive the "full-depletion voltage" (Vgj,FD) [2].

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dx2dX2

0(0,y) = 0SI (y), Ex (0, y) = ESI (y) = -Os', (y) .

O(X.J.y)=O,jy), E.(X.I,y)=E.jy): -01, (y), (4b)

0.5cls

0)A-

a)0

na)cJ

cnr0.0

0.5 1.0 1.5

Gate-Source Voltage, Vgfl (V)

Fig. 2. Explicit and implicit surface-potential solutions in a-DGwith channel-voltage variations. The inset shows the errors withrespect to the implicit solutions.

E

V

ci)

a)

C.

100

50

0

depletion to volume inversion, (6) is solved with only theregional solution in depletion up to full-depletion voltage; andin strong inversion, (6) is solved with the electron andacceptor terms in (3a), similar to bulk-MOS [2].

E. Solutions in Cylindrical Coordinate

For SiNWs, most of which having circular cross-sections ofthe channel, are more appropriately and easily described incylindrical coordinate. Similar voltage equation and surface-potential solutions are obtained [4] for undoped NWs, whichcan be solved iteratively. However, these solutions are mostsuitable for small-diameter NWs, which may not beextendable to large dimensions. On the other hand, a TG/OGFinFET is best described in Cartesian coordinate forlong/wide/thick device which, when scaled down, willapproach circular-shape cross-section, and short-channel/narrow-width/thin-body effect will have to beconsidered.

F. Surface-Potential-Based Drain Current

For undoped DG devices, the key to formulating a drain-current expression is to obtain the integral of inversion charge(Qi) across the channel

Id, = Q (V)dV (10)

analytically, where Qj(V) is related to the surface potentialsvia Gauss' law:

(V) dx x=O dx=tsi(1 1)

1.5 2.0

Drain-Source Voltage, Vds (V)

Fig. 3. Modeled output characteristics of the explicit model,compared with Medici data for four values of gate voltages. Thecalculated saturation voltages are shown by the crosses.

For undoped DG MOSFETs, second integral of Poissonequation is possible, and a generic implicit surface-potentialequation can be solved iteratively, e.g., by Newton-Raphson(NR) algorithm with a good initial guess [3]. Approximateexplicit solutions have also been derived [3].

D. Unified Regional Surface-Potential Solutions

The essence of the URM approach [2] is to solve thevoltage equation (6) regionally, and unify the regionalsolutions with smoothing functions. In accumulation, thesolution is a Lambert W function when only the hole term in(3a) is considered; in depletion, it is the simple square-rootfunction when only the NA term in (3a) is considered; from

For doped DG devices, URM approach is adopted and similarsurface-potential-based Ids equation as bulk-MOS can be used,in which the physics are mainly contained in the surface-potential solutions.

III. RESULTS AND DISCUSSION

This section presents some selected results for differentdevices with various approaches, details of the relatedformulations are presented elsewhere.

A. Implicit/Explicit Solutionsfor Undoped a-DG

Implicit surface-potential solutions by iteration for undopeda-DG have been presented [3], together with approximateexplicit solutions and used in closed-form Ids expressionderived based on the unified regional modeling approach. Fig.2 shows the explicit surface potentials of an a-DG MOSFETcompared with the numerical solutions of the same device(inset) at two channel voltages. These solutions are evaluatedin the explicit Ids model [3] at the source and drain ends, as

shown in Fig. 3 with excellent match to the Medici data.

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Symbols: Model (implicit) Toxl2 -2 nm, TSi -20 nmLines: Model (explicit) v , v v

v ....Vccr= 0.1 V

E ~4

0u0 4 s2LU

0.0 0.5 1.0 1.5

Vgl()(Vgf2 = 0)

0.0 0.5 1.0

).0

B. Iterative/Analytical Solutionsfor Undoped SiNW0-o- R =1nm

R= 10nmR 20nm

T 2nmL - 10 nm

v -o - 1013cr 10-4

10-210-3

>-, 10-4-, 10-8

, 10-610-710-8

0.0

0.0 0.5

Lines: Model (Xsim) An implicit surface-potential solution for undoped SiNW(or GAA) transistor has been derived under cylindricalcoordinate [4] and solved iteratively by NR algorithm with a

Absolute error in Medici very good initial guess. Fig. 4 shows one sample result in

.......comparison with numerical data that shows increased error atincreasing device size (inset), due to the grid density. Acompact drain-current model is also obtained [4], whichprovides a truly surface-potential-based long/wide-channelmodel scalable with wire radius, oxide thickness, and all

Vgs (V) terminal biases. Figs. 5 and 6 show the modeled SiNW0.5 1.0 1.5 2.0 characteristics in different regions as well as their derivatives,

all matching well (without fitting) to the corresponding1.0 1.5 2.0 numerical data.

Gate-Source Voltage, Vgs (V)

Fig. 4. Modeled/numerical surface potentials and their diffi(inset) in SiNW, showing increased "error" in numerical solutilarger radius due to grid density.

I--

10-4

10-510-6

10-710-8 -

10-9 -

10-10

1 -1011

10-12_

10-13

10-14

10-15

1 0-1 6 _

0.0 0.5 1.0 1.5 2.0

Gate-Source Voltage, Vgs (V)

Fig. 5. Modeled transfer characteristics in saturation in '

showing volume inversion (log-scale) and strong inversion (Iscale), compared with Medici data.

1.0

t 0.8-Un

a) 0.6-C)

0U:

I-

C:

~v v/

vVLa

0.0 _ fi

0 - gs= 1 V Symbols: Mediciv ......Vgs = 1.5 V Lines: Model (Xsim)

---Vgs =2V

erenceC. Unified Regional Solutionsfor Doped s-DG

ons at The regional 0, solutions in an s-DG MOSFET [2] is plotted

in Fig. 7 together with the unified Qseff solution and compared7 to the Medici numerical solution of the same device (without

any fitting), and the corresponding derivatives are shown inFig. 8. The transition from (bulk-like) depletion to volume

5 inversion is well and smoothly modeled by the solution inr depletion (q5dep) and that from depletion to volume inversion

4 (qd,). Scaling with channel doping is shown in Fig. 9 for the0tt' surface potentials and their derivatives (inset), and validated° with Medici data.

2 in The unified regional surface-potential model is applied toour surface-potential-based drain-current model similar tobulk-MOS formulations, and the results for the transfer

0 characteristics are shown in Figs. 10 and 11 for the linear andsaturation currents and transconductances, respectively, whichdemonstrate excellent match in all regions as compared to thesame numerical device without any fitting.

SiNW,linear-

4

R= 10nmTox = 2 nm

L = 10 nmci)

3 < 9

_.

t

C)-1 (D

D n

1.0

0.5

0.0

0

0.0 0.5 1.0 1.5 2.0

Drain-Source Voltage, Vds (V)

Fig. 6. Modeled output characteristics and drain conductance inSiNW, compared with Medici data.

-2 -1 0 1 2

Gate-Source Voltage, Vgs (V)

Fig. 7. Modeled surface potentials in s-DG and their regionalcomponents, compared with Medici data.

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0.e

0.6

0.4

0.2

0.C

en

a)m

cJ

cn

.qx/mhr)lc- Unriiri

9

80(

E 60E,a) 400

0

v 2000enCX om 0

-0.5 0.0 0.5 1.0

Gate-Source Voltage, Vgs (V)

Gate-Source Voltage, Vgs (V)

Fig. 8. The corresponding derivatives of the surface potentials inFig. 7, compared with Medici data.

1.0

en

C/)

a)

a)

co

0.5

0.0

-0.5

-1.0

-2 -1 0 1

Gate-Source Voltage, Vgs (V)

Fig. 9. Modeled surface potentials in s-DG and the derivatives(inset) with channel-doping variations, compared with Medici data.

1.0

Symbols: MediciLines: Model (Xsim)

0.8 o Vds = 005V

Vds = 1.2V

0.6 Nch 101 3-5 Tsi 50 nm

Tox= 3nm

1 0.4 L = 1 pm

C 0.2

0.0 T3 e-

-0.5

log(lds)

Ids

0.0 0.5 1.0

Gate-Source Voltage, Vgs (V)1.5

--2

;-3)-4-5 C-6-7

cn-8

I-I

--9 0)

-10--11 C-12-13 -

C-)

-14-15 -F-16 D-17-18

Fig. 10. Linear and saturation currents in on linear/logarithm scalesusing the modeled surface potentials, compared with Medici data.

Fig. 11. Linear/saturation transconductances on linear/logarithmscales using the modeled surface potentials, compared with Medicidata.

IV. SUMMARY AND CONCLUSIONS

In summary, various device types and operations foremerging generic multiple-gate MOSFETs have beenreviewed and the corresponding surface-potential equationsand solution methods outlined. Sample results for undopedasymmetric-DG and silicon nanowire devices have beenpresented, which are based on iterative (implicit) or

approximate (explicit) surface-potential solutions. The unifiedregional approach is applied to the surface- and zero-fieldpotential solutions of a generic DG MOSFET with dopedbody, which can be viewed as two coupled "half' DG linkedby a full-depletion voltage that determines the onset of volumeinversion. The formulation resembles (and includes) bulk-MOS expressions and can be extended to independentasymmetric-DG/SOI devices. The demonstrated results forthe symmetric-DG show a one step closer towards unificationof an MOS core model for all different device types andoperations.

ACKNOWLEDGEMENT

Our team has been supported by various sponsors in the pastyears, including the grant from Semiconductor ResearchCorporation through Chartered Semiconductor ManufacturingLtd, the Institute of Microelectronics under Agreement forResearch Collaboration through A*STAR TSRP project, theNTU-Atomistix Asia Pacific Pte Ltd Research CollaborationAgreement, as well as the Microelectronics Center andNanocluster at Nanyang Technological University.

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35

1.5

1.0

0.5

I--

u)

>)70

Symbols: MediciLines: Model (Xsim)

0 Ps- Pseff

lvi 0 CPstrPaccPds

0~

0.0

-2 -1 0

-2-3 E

-5 U)

61-7 D)-8 0)

10 8-11 C

12 t-13 v-14 C

0-15 0)-16 a-17 m

-18

2

1.5

1

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