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Dynamic performance of graded channel DG FD SOI n-MOSFETs for minimizingthe gate misalignment effect

Rupendra Kumar Sharma, Ritesh Gupta, Mridula Gupta, R.S. Gupta *

Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110 021, India

a r t i c l e i n f o

Article history:Received 6 October 2008Received in revised form 28 March 2009Available online 25 April 2009

a b s t r a c t

Double gate MOSFET has been regarded as the most promising candidate for future CMOS devices, forexcellent short channel effects (SCEs) immunity and high current drivability due to double gate coupling.The alignment between the top and bottom gates should be concern to fully realize the benefits of thedouble-gate configuration, as gate misalignment causes degradation in the device performance. Use ofgraded channel architectures somehow reduces the effect of gate misalignment. We scrutinize thathow the misalignment affects the small signal behavior and device characteristics like conductances,capacitances and cut-off frequency, for uniformly doped and graded channel double gate architectures.Considering the fact that gate misalignment can occur on any side of the gate, extensive simulations havebeen carried out using high–low (H–L), low–high (L–H) and low–high–low (L–H–L) doping profiles forboth source (DGS) and drain side (DGD) gate misalignment.

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1. Introduction

Double gate (DG) structures fabricated on silicon-on-insulator(SOI) wafers have been utilized in CMOS technology due to theirexcellent scaling capability, outstanding short-channel effects(SCEs) immunity and high current drivability owing to excellentcontrol of both top/bottom gates through coupling [1–13]. Whilethe DG devices have many advantages, the fabrication process isusually more complicated than that of its single-gate MOSFET(both bulk and SOI) [14]. In particular, a self-aligned top-gate(TG) and bottom-gate (BG) structure is required to fully realizethe benefits of the double-gate configuration [15,16]. Howeverdue to technological restrictions, the alignment between top andbottom gates may not be perfect, especially for the shortest gatelengths. Widiez et al. [17] provides the slightly oversized back gateis a promising solution for gate misalignment, if a 10% loss in dy-namic performance can be tolerated. FinFETs are also a promisingsolution for misaligned DG MOSFETs. However, the use of FinFETsfor rf applications needs to be considered carefully, as they main-tain a higher parasitic capacitance, which is extremely difficult tominimize due to the 3D fin structure as reported by Kranti andArmstrong [18]. Extensive simulations and analytical work havebeen carried out by many authors on uniformly doped (UD) archi-tecture to analyze the effect of gate misalignment. Sun and Kuo[19] have reported the increases in threshold voltage for misalign-ment varying from 0% to 50%. Yin and Chan [20] also considered

the misalignment from 0% to 100% for UD DG devices and analyzethe gate misalignment effect on surface potential, drain inducedbarrier lowering (DIBL), drain current, capacitance, etc. and foundthat for 100% gate misalignment DG behave like single gate.

‘‘Laterally asymmetric channel” devices also known as gradedchannel (GC) MOSFET have been reported [21–23], to overcomeproblems such as hot electron degradation, threshold voltageroll-off and parasitic bipolar effects exhibited by UD DG devices.In our previous study [24] we have established that for UD archi-tecture, misalignment causes degradation in device characteristicssuch as increase in threshold voltage by 49.7% and decrease indrain current and transconductance by 54.56% and 43.21%, respec-tively with the increase in misalignment by 50%. High–low (H–L)doping profile reduces the gate misalignment effect towards drainside (DGD), whereas aggravates the misalignment effect on sourceside (DGS). With the increase in the misalignment by 50% for DGDconfiguration of H–L doping profile, we can not achieve significantincrease in threshold voltage that we obtained for uniformly dopedarchitecture for 25% gate misalignment. To reduce the effect of gatemisalignment on source side, low–high (L–H) doping profile hasbeen considered, but this profile increases the misalignment effecttowards drain side. Since, misalignment can occur on any side ofthe gate, the low–high–low (L–H–L) doping profile has been con-figured in order to reduce/eliminate the gate misalignment effectfor both DGD and DGS configurations of DG FD SOI n-MOSFET.

Although significant analysis has been done to demonstrate theimportance of graded channel architecture in DG MOSFET for min-imizing/eliminating the effects of gate misalignment, but the anal-ysis is limited to the dc characteristics of the device. It is of interestto understand that the performance of integrated circuits depends

0026-2714/$ - see front matter � 2009 Elsevier Ltd. All rights reserved.doi:10.1016/j.microrel.2009.03.023

* Corresponding author. Tel.: +91 011 24115580; fax: +91 011 24110606.E-mail addresses: rupendra1984@gmail.com (R.K. Sharma), rsgu@bol.net.in (R.S.

Gupta).

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not only on the dc characteristics, but also on the ac characteristics.As far as analogue circuits are concern, the most important param-eters are the transconductance (gm), output conductance (gd), ter-minal capacitances, i.e. gate-to-source capacitance (CGS) and gate-to-drain capacitance (CGD) and cut-off frequency (fT). In this paper,extensive simulations using ATLAS 3D device simulator [25] havebeen carried out for UD, H–L, L–H and L–H–L doping profiles toanalyze the gate misalignment effect on capacitive behavior andhence cut-off frequency of the device for both DGD and DGSconfigurations.

2. Structure description and simulation

Basic device structure of misaligned DG MOSFET used for ana-lyzing various graded channel architectures, shown in Fig. 1, con-sists of a silicon film (tsi = 60 nm) doped with p-type impurityconcentration. Silicon film is sandwich between gate insulator[SiO2 (�ox = 3.9, tox = 7 nm)] of equal thickness followed by poly-sil-icon gates (Npoly = 1.65 � 1019 cm�3, L = 200 nm) on both side ofgate insulator. Source/Drain electrode are considered to be verticalat the end of N+ region (1020 cm�3). N+ regions are well thought-outto be of sufficient length so that gate misalignment can vary above50% of gate length. For graded channel architecture high doping isassumed to be 5 � 1017 cm�3 and low doping is considered to be5 � 1016 cm�3 and 5 � 1015 cm�3, respectively. The doping profileis considered to be step doping profile as shown in Fig. 2. H–L andL–H doping regions are assumed to be equally spaced (L1 =L2 = 100 nm), whereas for L–H–L doping profile, the length of low/high/low doped region is 50/100/50 nm, respectively. To have thegeneralized analysis, wide range of gate misalignment (0–50%) onboth source and drain sides have been considered.

All simulations have been performed using ATLAS 3D [25] de-vice simulation software. The models activated in simulation com-prise the inversion layer Lombardi CVT mobility model that takesinto account the effect of parallel and perpendicular fields alongwith doping dependent and temperature dependent parts of themobility. Shockley–Read–Hall (SRH) and Auger recombinationmodel for minority carrier recombination have been used. Further,we chose Gummel’s method (or the de-coupled method) alongwith Newton’s method (or the fully coupled method) to solve theequations included in the CVT model.

3. Results and discussion

The simulated results for threshold voltage (Vth), maximum va-lue of transconductance (gm(max)), maximum value of output-con-ductance (gd(max)), maximum value of total capacitance (CT(max))[CT = CGS + CGD] and cut-off frequency (fT(max)) are tabulated in Ta-bles 1–4. The threshold voltage is considered to be that value ofgate voltage for which drain current approaches 10�7 A/lm atVDS = 50 mV. The gm(max), CT(max) and fT(max) are taken atVDS = 1.0 V, whereas gd(max) is taken at VGS = 1.0 V.

The threshold voltage variation with gate misalignment for var-ious device configurations is shown in Tables 1–4 and Fig. 3a and bfor VDS = 50 mV. In uniformly doped architecture, as misalignmentincreases from 0% to 25%, Vth is raised up to 11.34% and 11.66% forDGD and DGS configurations, respectively. H–L doping profile lim-

Fig. 1. Schematic structure of GC DG MOSFET with gate misalignment of ma for L = 200 nm, L1:L2 = 1:1.

Fig. 2. Doping profile of GC (L–H–L) DG SOI along the channel length for L = 200 nm,L1:L2:L3 = 1:2:1.

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its the increase in Vth just by 0.05%, with the increase in misalign-ment from 0% to 25% for DGD configuration, whereas it aggravatesthe Vth variation up to 25% for DGS configuration. Similar increasein misalignment for L–H doping profile increases the Vth by 24.47%and 0.05% for DGD and DGS configurations, respectively. It is foundfrom the analysis that H–L doping profile is beneficial for DGD con-figuration while L–H doping profile is the better alternative for DGSconfiguration. Considering the fact that we cannot predict to whichside misalignment may occur, we proposed the L–H–L doping pro-file. In this profile, increase in misalignment from 0% to 25% in-creases the Vth by 2.33% and 2.46% for DGD and DGSconfigurations, respectively. This confirmed that L–H–L dopingprofile should be fabricated in order to reduce the gate misalign-ment for both DGD and DGS configurations.

Tables 1–4 further show the variation of gm(max) with gatemisalignment for various misaligned DG structures. In UD devices

with the increase in misalignment from 0% to 25%, the gm(max) de-creases by 40.44% and 36.08% for DGD and DGS configurations,respectively, whereas in H–L doping profile, gm(max) decreasesby 9.5% and 37.57% for these configurations. Similar increase inmisalignment for L–H doping profile decreases the gm(max) by41.89% and 37.57% for DGD and DGS configurations, respectively.However, L–H–L doping profile limits the decrease in gm(max) by17.69% and 24.82% for DGD and DGS configurations, respectivelywith the increase in misalignment by 25%. This further emphasisthat L–H–L doping profile is more beneficial for both DGD andDGS configurations in comparison to other profiles discussed.

As previously discussed, misalignment causes degradation indevice performance, i.e. increase in threshold voltage and decreasein transconductance. On the contrary, misalignment causes de-crease in the total capacitance of the device which is a desirabletrait for enhanced device performance. However, with the increase

Table 4Device parameters for L–H–L doped DG devices analyzed in the present work for L = 200 nm, L1:L2:L3 = 1:2:1, tsi = 60 nm, tox1 = tox2 = 7 nm (a) N1 = 5 � 1015 cm�3,N2 = 5 � 1017 cm�3, N3 = 5 � 1015 cm�3 (b) N1 = 5 � 1016 cm�3, N2 = 5 � 1017 cm�3, N3 = 5 � 1016 cm�3.

Channel doping (cm�3) Misalignment ma (%) Vth (V) gm(max) (lS) ga(max) (lS) CT(max) (fF) fT(max) (GHz)

DGD DGS DGD DGS DGD DGS DGD DGS DGD DGS

(a) N1 = 5 � 1015; N2 = 5 � 1017; N3 = 5 � 1015 ma = 0 0.2279 0.2279 701 701 1010 1010 1.87 1.87 63.3 63.3ma = 12.5 0.2280 0.2280 669 613 952 951 1.83 1.75 65.1 63.4ma = 25 0.2332 0.2335 577 527 775 773 1.74 1.73 59.6 59.5ma = 50 0.3384 0.3488 369 394 500 499 1.56 1.60 37.7 48.5

(b) N1 = 5 � 1016; N2 = 5 � 1017; N3 = 5 � 1016 ma = 0 0.2325 0.2325 694 694 966 966 1.87 1.87 62.8 62.8ma = 12.5 0.2327 0.2327 657 600 903 902 1.83 1.76 64.2 62.5ma = 25 0.2386 0.2394 553 513 699 696 1.74 1.74 57.2 58.4ma = 50 0.3457 0.3557 364 389 474 474 1.57 1.60 37.3 48.2

Table 1Device parameters for UD DG devices analyzed in the present work for L = 200 nm, tsi = 60 nm, tox1 = tox2 = 7 nm and NA = 5 � 1017 cm�3.

Channel doping (cm�3) Misalignment ma (%) Vth (V) gm(max) (lS) ga(max) (lS) CT(max) (fF) fT(max) (GHz)

DGD DGS DGD DGS DGD DGS DGD DGS DGD DGS

NA = 5 � 1017 ma = 0 0.2814 0.2814 643 643 756 756 1.87 1.87 59.0 59.0ma = 12.5 0.2836 0.2848 559 510 578 573 1.82 1.78 56.0 55.8ma = 25 0.3133 0.3142 383 411 399 399 1.73 1.75 36.6 50.7ma = 50 0.4212 0.4257 336 362 346 346 1.56 1.60 34.7 46.7

Table 2Device parameters for H–L doped DG devices analyzed in the present work for L = 200 nm, L1:L2 = 1:1, tsi = 60 nm, tox1 = tox2 = 7 nm (a) N1 = 5 � 1017 cm�3, N2 = 5 � 1015 cm�3 (b)N1 = 5 � 1017 cm�3, N2 = 5 � 1016 cm�3.

Channel doping (cm�3) Misalignment ma (%) Vth (V) gm(max) (lS) ga(max) (lS) CT(max) (fF) fT(max) (GHz)

DGD DGS DGD DGS DGD DGS DGD DGS DGD DGS

(a) N1 = 5 � 1017; N2 = 5 � 1015 ma = 0 0.1868 0.1868 716 716 1090 1090 1.94 1.94 658 65.8ma = 12.5 0.1868 0.1958 694 564 1090 793 1.88 1.84 68.7 62.5ma = 25 0.1869 0.2335 648 447 971 600 1.78 1.80 66.6 54.2ma = 50 0.200 0.3475 451 386 706 509 1.59 1.64 53.1 47.1

(b) N1 = 5 � 1017; N2 = 5 � 1016 ma = 0 0.1918 0.1918 710 710 1050 1050 1.93 1.93 65.3 65.3ma = 12.5 0.1919 0.2027 685 561 997 766 1.88 1.84 67.8 62.1ma = 25 0.1920 0.2379 630 445 896 574 1.77 1.79 65.0 54.2ma = 50 0.2135 0.3540 413 384 615 488 1.58 1.63 47.5 47.4

Table 3Device parameters for L–H doped DG devices analyzed in the present work for L = 200 nm, L1:L2 = 1:1, tsi = 60 nm, tox1 = tox2 = 7 nm, N1 = 5 � 1015 cm�3, N2 = 5 � 1017 cm�3.

Channel doping (cm�3) Misalignment ma (%) Vth (V) gm(max) (lS) ga(max) (lS) CT(max) (fF) fT(max) (GHz)

DGD DGS DGD DGS DGD DGS DGD DGS DGD DGS

N1 = 5 � 1015; N2 = 5 � 1017 ma = 0 0.1845 0.1845 685 685 1090 1090 1.83 1.83 61.8 61.8ma = 12.5 0.1909 0.1845 605 618 801 1050 1.80 1.69 58.9 62.7ma = 25 0.2302 0.1846 398 545 601 970 1.72 1.67 40.0 60.7ma = 50 0.3443 0.1993 362 455 510 707 1.56 1.58 37.1 56.1

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Fig. 3. Variation of threshold voltage with gate misalignment for different doping profiles – UD (L = 200 nm, NA = 5 � 1017 cm�3) doping profile; H–L (L = 200 nm, L1:L2 = 1:1,N1 = 5 � 1017 cm�3, N2 = 5 � 1015 cm�3) doping profile; L–H (L = 200 nm, L1:L2 = 1:1, N1 = 5 � 1015 cm�3, N2 = 5 � 1017 cm�3) doping profile; L–H–L (L = 200 nm,L1:L2:L3 = 1:2:1, N1 = 5 � 1015 cm�3, N2 = 5 � 1017 cm�3, N3 = 5 � 1015 cm�3) doping profile: (a) DGD configuration; (b) DGS configuration.

Fig. 4. CGS + CGD–VGS and fT–VGS curves for UD DG with various gate misalignments at VDS = 1.0 V: (a) DGD configuration; (b) DGS configuration. CGS + CGD–VGS and fT–VGS

curves for H–L doping profile with various gate misalignments at VDS = 1.0 V: (c) DGD configuration; (d) DGS configuration.

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in misalignment, the maximum value of cut-off frequency de-creases. In UD architecture, with the increase in misalignmentfrom 0% to 25%, CT(max) decreases by 7.49% and 6.42% for DGDand DGS configurations, respectively as shown in Fig. 4a and b. Thisis due to the fact that increase in misalignment causes increase inlength of ungated region. Capacitance in the ungated region is dueto the fringing electric field, and is always lesser in comparison tothe gated region capacitance. The combination of the ungated andgated region capacitance decreases the overall transcapacitance ofgate misaligned device in contrast to the aligned device. The vari-ation in transcapacitance is larger in DGD case while relating it toDGS case.

Fig. 4a and b also show the variation of cut-off frequency withgate voltage for various misaligned UD DG structures. For zero mis-alignment case (ma = 0%), fT(max) is found to be 59.0 GHz. With theincrease in misalignment by 12.5%, fT(max) decreases by 5.09% and5.42% for DGD and DGS configurations, respectively. The fT(max)decreases by 37.97% and 14.07% for DGD and DGS configurationswith the increase in misalignment by 25%. Further increase in mis-alignment by 50%, fT(max) decreases by 41.17% and 20.85% for DGDand DGS configurations, respectively.

H–L doping profile reduces the effect of gate misalignment forDGD configuration and is further explained through variation ofcapacitance and cut-off frequency with gate voltage in Fig. 4cand d. In H–L doping profile, with the increase in misalignmentby 25%, CT(max) decreases by 8.25% and 7.22% whereas fT(max)varies by 1.22% and 17.63% for DGD and DGS configurations,respectively. This shows that CT(max) of H–L doping profile de-creases in almost similar proportion for both DGD and DGS config-urations, as in UD devices. However, H–L doping profile showsnegligible variation in fT(max) for DGD configuration which clearlyindicates that variation in fT(max) follows the transconductancebehavior.

Fig. 5a and b shows the variation of total capacitance and cut-offfrequency with gate voltage for various misaligned L–H dopingprofiles. With the increase in misalignment by 25%, CT(max) de-creases by 6.01% and 8.74% for DGD and DGS configurations,respectively, whereas fT(max) decreases by 35.27% and 1.78%. Thisshows that L–H doping profile is beneficial for reduction of gatemisalignment effect on source side (DGS). Considering the fact thatwe cannot predict on which side gate misalignment could occur,we are proposing the lightly doped region on both source and drain

Fig. 5. CGS + CGD–VGS and fT–VGS curves for L–H doping profile with various gate misalignments at VDS = 1.0 V: (a) DGD configuration; (b) DGS configuration. CGS + CGD–VGS andfT–VGS curves for L–H–L doping profile with various gate misalignments at VDS = 1.0 V: (c) DGD configuration; (d) DGS configuration.

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side irrespective of which side gate misalignment can happen.Fig. 5c and d shows the variation of total capacitance and cut-offfrequency with gate voltage for various misaligned L–H–L dopingprofiles. With the increase in misalignment by 25%, CT(max) de-creases by 6.95% and 7.49% for DGD and DGS configurations,respectively. For zero misalignment, the fT(max) is found to be63.3 GHz. With the increase in the misalignment by 25%, thefT(max) decreases by 5.85% and 6.0% for DGD and DGS configura-tions, respectively. This emphasis that L–H–L doping profile is alsobeneficial for gate misalignment effect on both sides as far as dy-namic performance of the device is concerned.

When misalignment occurs, the effective gate length of the de-vice has been changed thus results in change of short channel ef-fects. This can be explained through the variation of outputconductance (gd) with drain bias (VDS) for various misaligned DGstructures in Figs. 6 and 7. In UD DG devices, with the increase inthe misalignment by 25%, the gd(max) decreases by 47.22% for bothDGD and DGS configurations as shown in Fig. 6a and b. The use ofH–L doping profile in Fig. 6c and d show that with the increase inthe misalignment by 25%, gd(max) decreases by 10.92% and 44.94%for DGD and DGS configurations, respectively. Fig. 7a and b showsthe variation of gd with VDS for various misaligned structures of L–

H doping profile. As we increase the misalignment by 25%, gd(max)decreases by 44.86% and 11.0% for DGD and DGS configurations,respectively. However, in L–H–L doping profile, with the increasein misalignment by 25%, gd(max) decreases by 23.27% and23.47% for DGD and DGS configurations, respectively. This furtheremphasis that the L–H–L doping profile is the best suitable profilefor device design as it reduces the gate misalignment with im-proved short channel effects. A comparison between the resultsobtained using drift-diffusion method with energy-balance solvingmethod is shown in Fig. 8. Results clearly emphasis that there is nonotable deference between the two methods which assured thatthe simulation results are realistic.

Comparative study has also been done through Tables 1–4 forUD, H–L, L–H and L–H–L doping profiles for both DGD and DGSconfigurations. This shows that L–H–L doping profile is more ben-eficial than other profiles discussed for both configurations. More-over, for L–H–L doping profile all the device characteristics showsimilar behavior owing to the uniformity of the structure on bothsource and drain side, except the applied drain bias. For two GC(H–L) doping profiles as shown in Table 2a and b, it can be seenthat greater is the difference between high and low doping greateris the enhancement offered. This can further be seen through the

Fig. 6. Variation of output conductance (gd) with drain voltage for UD DG with different gate misalignments at VGS = 1.0 V: (a) DGD configuration; (b) DGS configuration.Variation of output conductance (gd) with drain voltage for H–L doping profile with different gate misalignments at VGS = 1.0 V: (c) DGD configuration; (d) DGS configuration.

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comparison between the two L–H–L doping profiles in Table 4aand b.

4. Conclusion

The gate misalignment effect on dynamic performance of vari-ous misaligned DG structures has been analyzed using ATLAS 3Ddevice simulator. In UD devices, misalignment causes degradationin the device characteristics like increases in threshold voltage, de-crease in drain current and transconductance. On the contrary,misalignment causes decrease in the total capacitance of the de-vice which is a desirable trait for enhanced device performance,whereas with the increase in misalignment, fT(max) decreases.The graded channel profiles like H–L, L–H and L–H–L reduces/elim-inate the effect of gate misalignment on threshold voltage, draincurrent and transconductance in comparison to UD devices,whereas with the increase in misalignment, capacitance of GC de-vices decreases in same proportion as in UD devices. Misalignmentaffects the transconductance much more than capacitance of thedevice, thus cut-off frequency follows the conductive behavior.As far as dynamic performance is concerned, H–L and L–H dopingprofile reduces the gate misalignment effect for DGD and DGS con-figuration, respectively. Considering the fact that we cannot pre-dict on which side misalignment would occur, L–H–L doping

Fig. 7. Variation of output conductance (gd) with drain voltage for L–H doping profile with different gate misalignments at VGS = 1.0 V: (a) DGD configuration; (b) DGSconfiguration.Variation of output conductance (gd) with drain voltage for L–H–L doping profile with different gate misalignments at VGS = 1.0 V: (c) DGD configuration; (d)DGS configuration.

Fig. 8. Comparison of drift-diffusion with energy-balance solving method throughcapacitance and cut-off frequency variation with gate voltage of UD DG atVDS = 1.0 V.

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profile should be considered in order to reduce gate misalignmenteffects with improved short channel effects for both DGD and DGSconfigurations.

Acknowledgement

The authors are grateful to Defence Research and DevelopmentOrganization (DRDO), Ministry of Defence, Government of India,for the necessary financial assistance.

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