Spartan-3 5m Protoboard - baixardoc

OPERATIONAL MANUAL

FOR

SPARTAN-3 FG900 PROTOBOARD MODEL : MXS3FK- 5M

Rev : 002

MECHATRONICS TEST EQUIPMENT (I)PVT.LTD. B-3,MAYUR COMPLEX, OPP. BHELKE NAGAR,

NEAR YASHAVANTRAO CHAVAN NATYAGRUH,

KOTHRUD, PUNE- 411038

PHONE : +91-20-25386926 FAX : +91-20-25386930 EMAIL : [email protected] URL : www.mte-india.com

TABLE OF CONTENTS

PREFACE .......................................................................................................................................1

About Thi s Manual.......................................................................................................................1

Manual Contents ......................................................................................................................... 1

CHAPTER 1 ....................................................................................................................................2

Introduction...................................................................................................................................2

1.1 Features ................................................................................................................................ 2

CHAPTER 2 ....................................................................................................................................5

High Speed Synchronous SDRAM..............................................................................................5

2.1 Address Bus Connection ........................................................................................................ 5

2.2 Bank Address Selection ......................................................................................................... 6

2.3 Dat a Bus Connection ............................................................................................................. 6

2.4 Dat a Mask Lines Connection .................................................................................................. 7

2.5 Control Lines Connection ....................................................................................................... 7

CHAPTER 3 ....................................................................................................................................8

USB Interface ...............................................................................................................................8

3.1 Dat a Bus Connection ............................................................................................................. 9

3.2 Control Lines: ........................................................................................................................ 9

3.3. FTDI Driver Inst allation.......................................................................................................... 9

CHAPTER 4 ..................................................................................................................................11

Serial Interface........................................................................................................................... 11

4.1 RS- 232 Int erf ace..................................................................................................................11

4.2 RS- 422 Int erf ace..................................................................................................................12

CHAPTER 5 ..................................................................................................................................13

PS/2 Mouse/Keyboard Interface................................................................................................ 13

5.1 PS/2 Keyboard .....................................................................................................................14

5.2 PS/2 Mouse..........................................................................................................................15

5.3 Control Signal Connection .....................................................................................................16

CHAPTER 6 ..................................................................................................................................17

Switches And LEDs ................................................................................................................... 17

6.1 DIP Switches ........................................................................................................................17

6.2 Key Switches ........................................................................................................................17

6.3 LEDS ...................................................................................................................................17

CHAPTER 7 ..................................................................................................................................19

Seven Segment LED Di splay .................................................................................................... 19

CHAPTER 8 ..................................................................................................................................21

VGA In terface............................................................................................................................. 21

8.1 VGA Display Theory ..............................................................................................................22

8.2 VGA signal TI MING...............................................................................................................24

CHAPTER 9 ..................................................................................................................................25

LCD Interface ............................................................................................................................. 25

9.1 Dat a Lines Connection..........................................................................................................26

9.2 Control Line Interf ace: ...........................................................................................................26

CHAPTER 10 ................................................................................................................................27

10/100 Non PCI Ethernet Interface ........................................................................................... 27

10.1 System Address Bus Connection .........................................................................................28

10.2 System Data Bus Connection ..............................................................................................28

10.3 Control Signals Connection..................................................................................................29

CHAPTER 11 ................................................................................................................................32

Connector Details....................................................................................................................... 32

11.1 I O Connectors ....................................................................................................................32

11.2 Stackable Connect or ...........................................................................................................36

CHAPTER 12 ................................................................................................................................39

Clock and Reset Sources .......................................................................................................... 39

CHAPTER 13 ................................................................................................................................40

SPARTAN-3 Configuration Details............................................................................................ 40

13.1 Boundary Scan mode: .........................................................................................................40

13.2 Master Serial Mode .............................................................................................................40

13.3 Jumper Setting....................................................................................................................40

CHAPTER 14 ................................................................................................................................43

Power Supplies.......................................................................................................................... 43

14.1 Voltage Regulators ..............................................................................................................43

APPENDIX A.................................................................................................................................44

Consolidated UCF For The Complete Board ............................................................................ 44

APPENDIX B.................................................................................................................................58

Operating Inst ruction To Start A New Design ........................................................................... 58

B.1 Starting The ISE Sof tware: ....................................................................................................58

B.2 Design Flow.........................................................................................................................58

B.3 Design Desc ription ...............................................................................................................59

B.4 Truth Table of Half adder ......................................................................................................59

B.5 VHDL Code f or Half adder ....................................................................................................59

B.6 Steps to implement the Half adder in the FPGA using Xilinx iSE(8.1i) ......................................60

APPENDIX C.................................................................................................................................74

ASCII Table 5 X 7 LCD Display ................................................................................................. 74

APPENDIX D.................................................................................................................................75

ADC–DAC Add On Card ............................................................................................................ 75

APPENDIX E.................................................................................................................................81

Video ADC – DAC Add On Card ............................................................................................... 81

F.1 Video ADC int erf ace .............................................................................................................81

F.2 VIDEO DAC .........................................................................................................................82

F.3 SYNC SEPERATOR .............................................................................................................83

F.4 Consol idated UCF f or All Mother Boards: ...............................................................................85

LIST OF TABLES

Table 1 Address Bus Interface to SPARTAN-3 FPGA ...................................................................6

Table 2: Bank Address Selection Interface to SPARTAN-3 FPGA ................................................6

Table 3 Data Bus Interface to SPARTAN-3 FPGA.........................................................................6

Table 4: Data Bus Interface to SPARTAN-3 FPGA........................................................................7

Table 5: Control Lines Interface to SPARTAN-3 FPGA.................................................................7

Table 6: Data Bus Interface to SPARTAN-3 FPGA........................................................................9

Table 7: Control Lines Interface to SPARTAN-3 FPGA.................................................................9

Table 8: RS232 Interface to SPARTAN-3 FPGA..........................................................................11

Table 9: RS422 Interface to SPARTAN-3 FPGA..........................................................................12

Table 10: PS/2 Connector Details.................................................................................................13

Table 11: PS/2 Bus Tim ing...........................................................................................................13

Table 12: Common PS/2 Keyboard Commands..........................................................................15

Table 13: LED Status....................................................................................................................15

Table 14: PS/2 Interface to SPARTAN-3 FPGA...........................................................................16

Table 15: DIP switch Interface to SPARTAN-3 FPGA .................................................................17

Table 16: KEY switch Interface to SPARTAN-3 FPGA ................................................................17

Table 17: LED Interface to SPARTAN-3 FPGA............................................................................17

Table 18: Seven Segment Di splay Interface to SPARTAN-3 FPGA............................................20

Table 19: VGA Interface to SPARTAN-3 FPGA...........................................................................22

Table 20: VGA signal timing..........................................................................................................24

Table 21: Data Line Interface to SPARTAN-3 FPGA...................................................................26

Table 22: Control Line Interface to SPARTAN-3 FPGA...............................................................26

Table 23: Address Bus Interface to SPARTAN-3 FPGA..............................................................28

Table 24: Data Bus Interface to SPARTAN-3 FPGA....................................................................28

Table 25: Synchronous Bus Interface to SPARTAN-3 FPGA ......................................................30

Table 26: Asynchronous Bus Interface to SPARTAN-3 FPGA ....................................................30

Table 27: M iscellaneous Signal s Interface to SPARTAN-3 FPGA ..............................................31

Table 28: IOCON1 Connector Interface to FPGA ........................................................................32




Table 32 IOCON5 Connector Interface to FPGA .........................................................................34





Table 37: Stackable Connector Interface to FPGA ......................................................................36

Table 38: IO Clock-Reset Interface to FPGA ...............................................................................39

Table 39: Mode Selection Jumper Settings..................................................................................40

Table 40: Mode Selection Table...................................................................................................40

Table 41: Power Supply Details....................................................................................................43

LIST OF FIGURES

Figure 1: Block Diagram..................................................................................................................3

Figure 2: FPGA – SDRAM Interface...............................................................................................5

Figure 3: FPGA – USB Interface.....................................................................................................8

Figure 4: FPGA – RS232 Interface ...............................................................................................11

Figure 5: FPGA – RS422 Interface ...............................................................................................12

Figure 6: PS/2 Connector..............................................................................................................13

Figure 7: PS/2 Timing Diagram.....................................................................................................14

Figure 8: PS/2 Keyboard with scan codes....................................................................................14

Figure 9: Data fo rmat for PS/2 mouse interface...........................................................................16

Figure 10: Seven Segment Di splay ..............................................................................................19

Figure 11: FPGA –VGA Interface .................................................................................................21

Figure 12: CRT Di splay Tim ing.....................................................................................................23

Figure 13: VGA Tim ing..................................................................................................................24

Figure 14: LCD Interface to SPARTAN-3 FPGA ..........................................................................25

Figure 15: LAN 91C111 Interface to SPARTAN-3 FPGA.............................................................28

Figure 16: Positional Details of On Board Connectors.................................................................38

Figure 17: JTAG Mode Selection..................................................................................................41

Figure 18: JTAG Connector Details..............................................................................................42

1

PREFACE

A bout This Manual

This manual gives operational details for all the interfaces.

Manual Contents

This manual contains following chapters:

• Chapter 1, “Int roduction” • Chapter 2, “High Speed Synchronous SDRAM ”

• Chapter 3, “USB Interface” • Chapter 4, “Serial Interface”

• Chapter 5, “PS/2 Mouse/Keyboard Interface”

• Chapter 6, “Switches And LEDs” • Chapter 7, “Seven Segment LED Display”

• Chapter 8, “VGA Interface”

• Chapter 9, “LCD Interface” • Chapter 10, “10/100 Non PCI Ethernet Interface”

• Chapter 11, “Connector Detail s”

• Chapter 12, “Clock And Reset Sources” • Chapter 13, “SPARTAN-3 Configuration Details”

• Chapter 14, “Power Supplies” • Appendix A Consolidated UCF for the complete Board

• Appendix B Operating Inst ruction to Start a New Design • Appendix C ASCII Table 5x7 LCD Di splay • Appendix D ADC DAC Add – On Card Detail s

• Appendix E VIDEO ADC DAC Add – On Card Details

2

CHAPTER 1

Introduction

SPARTAN-3-FG900 Development Board (MXS3FK-5M) provides an easy to use development platform for realizing various desi gns around SPART AN-3 FPGA.

1.1 Features Figure 1 shows the SPARTAN-3 Development Board, which includes the following components and features:

• Spartan-3 family is building on the successor Spartan-IIE family by increasi ng the amount of logic resources, the capacity of internal RAM, the total no of I/O’s and overall level of perfo rmance as well as by improving clock management functions.

• Revolutionary 90 nm process technology

• Very low cost, high performance logic solutions for high volume consumer–oriented application

• Densities as high as 74,880 logic cell s’

• Upto 326 MHz system clock rate

• Three separate power supplies fo r the core (1.2), I/Os(1 .2 to 3.3), and special function(2.5V) • Select I/O signalling • Abundant, flexible logic cells with regi sters, wide multiplexer, dedicated 18x18 multiplier,

• Up to 1872 Kbits of total block RAM • Up to 520 Kbits of total dist ributed RAM

• Digital clock manager (up to four DCM) • Eight global clock lines and abundant routing.

• Fully supported by Xilinx ISE development system

• Unlim ited reprogram ability. • Very low cost.

• Platform Flash: 16 Mbit Xilinx XCF16P in-system configurable platform flash for configuration th rough PROM in VO 48 package.

1.8V supply voltage Serial or parallel FPGA configuration interface (up to 33 MHz)

Available in small-footprint VO48, VOG48, FS48, and FSG48 packages Design revi sion technology enables storing and accessing multiple design revi sions for

configuration. Built-in data decompressor compatible with Xilinx advanced compression technology

• SDRAM : 4 Meg x 32 M icron SDRAM MT48LC4M32B2 as a high speed synchronous

memory interface in TSOP-86 package PC100 functionality Fully synchronous; all signal s regi stered on positive edge of system clock

Internal pipelined operation; column address can be changed every clock cycle Internal banks fo r hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page

Auto Precharge, includes concurrent Auto precharge, and Auto Refresh Modes Self Refresh Mode 64ms, 4,096-cycle refresh (15.6µs/row) LVTTL-compatible inputs and outputs

Single +3.3V ±0.3V power supply Supports CAS latency of 1, 2, and 3

3

Figure 1: Block Diagram

• USB Controller: Cost effective, easy to use USB FIFO IC FT245BM from FTDI in LQFP-32 package to t ransfer da ta to / f rom FPGA and host PC at upto 1Mbyte per second. Single Chip USB ó Parallel FIFO bi-directional Data Transfer Transfer Data rate to 1M Byte / Sec - D2XX Drivers

4

Transfer Data rate to 300 Kilobyte / Sec - VCP Drivers Simple to interface to MCU / PLD/ FPGA logic with a 4 wire handshake interface Entire USB protocol handled on-chip, no USB-specific firmware programming required 384 Byte FIFO Tx buffe r / 128 Byte FIFO Rx Buffe r for high data throughput . Integrated 3.3V regulator fo r USB IO Integrated Power-On-Reset circuit Integrated 6MHz – 48MHz clock multiplier PLL USB Bul k or Isochronous data t ransfer modes

• Ethernet Controller: 10/100 Non PCI single chip Ethernet controller LAN 91c111 f rom SMSC in QFP package. Supports full duplex switched Ethernet. Supports burst transfer. 8 Kbytes of internal memory for receive and t ransmit FIFO buffers. Optional configuration th rough serial EEPROM Supports 8, 16, 32 bit CPU accesses.

Single 25 MHz Clock fo r both PHY and MAC. Fully integrated IEEE 802.3 / 802.3 u -100 Base –TX/ 10 Base-T physical layer.

• VGA display Port: 12 bit, 512 colours VGA di splay port.

• RS232 Serial Interface: 9 pin two channel serial interfaces. DB9 9-pin female connector (DCE connector)

RS-232 t ransceiver/level t ranslator using MAX3223 in SSOP package. Uses straight-th rough serial cable to connect to computer or workstation serial port.

• RS422 Serial Interface: 10 pin two channel serial interfaces. 10 pin berg connector.

RS-422 dual differential drivers and receivers SN65C118 in TSSOP package

• PS/2 Interface: PS/2-style mouse/keyboard port.

• Seven Segment Display: Four-character, seven-segment LED display.

• DIP Switches: Eight DIP switches.

• LEDs: 13 onboard LEDS 8 user LEDs (RED) Single configuration status LED (GREEN) 4 Power on indicator LEDs(RED)

• Push Button Switches: Four momentary-contact push button switches.

• LCD interface: 16 character 2 row LCD .

• Mictor Connector: Facilitates provision for Logic Analyzer interface.

• Stackable Connector: Facilitates provision fo r interface of ADD ON Boards

• Free IOs: 289 f ree IOs.

• Clock Oscillator: 40 MHz crystal clock oscillator. Socket for an auxiliary crystal oscillator clock source.

• JTAG port: 10 Pin FRC male connector fo r JTAG download cable (parallel III) interface that connects to the parallel port of host PC.

• Pow er Supplies: 5 volts regulated power supply provided along with the board. On board 3.3V, 2.5V, 1.8V, 1.2V regulators. On board generation of -5V supply.

5

CHAPTER 2

High Speed Synchronous SDRA M

SPARTAN-3 Development Board has a single 4 Meg x 32 high speed synchronous SDRAM (MT48LC4M32B2), surface mounted on top side of the board. A detailed interface is as shown in Figure 2.

Figure 2: FPGA – SDRAM Interface

This SDRAM i s internally configured as quad bank DRAM with synchronous interface (all

signals regi stered on positive clock edge). The SDRAM provides for p rogrammable READ or WRITE burst lengths of 1, 2, 4, o r 8 locations, or the full page, with a burst te rminate option. An auto precharge function may be enabled to provide a self-timed row precharge that i s initiated at the end of the burst sequence.

2.1 Address Bus Connection

• SDRAM has a 12 bit address bus interface with FPGA.

• A0–A11 are sampled during the ACTIVE command (row-address A0–A10) and READ/WRITE command (column-address A0–A8 with A10 defining auto precharge) to

select one location out of the memory array in the respective bank. A10 i s sampled during a PRECHARGE command to determ ine if all banks are to be precharged (A10 [HIGH]) o r bank selected by BA0, BA1 (LOW). The address inputs al so provide the op-code during a

LOAD MODE REGISTER command.

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