Regenerative medium-voltage AC drive based on a multicell arrangement with reduced energy storage...

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 1, FEBRUARY 2005 171

Regenerative Medium-Voltage AC Drive Based on aMulticell Arrangement With Reduced

Energy Storage RequirementsMarcelo A. Pérez, José R. Espinoza, Member, IEEE, José R. Rodríguez, Senior Member, IEEE, and Pablo Lezana

Abstract—Multicell power circuit topologies have proved to bean effective alternative to medium-voltage ac drives. The main ad-vantage is the improved power quality at both the ac system andthe motor sides. However, several drawbacks are present in theseconfigurations, such as a lack of sustained regenerative operatingmode, uncontrolled input reactive power, and a large second cur-rent harmonic that is injected by the load into the dc link of eachcell, which leads to a bulky electrolytic capacitor. This paper pro-poses to replace the input diode-based front-end rectifier with anactive front-end rectifier in all cells of the topology and a novel con-trol strategy in order to overcome the aforementioned drawbacks.In fact, the active front-end rectifier allows the topology to regen-erate and the control strategy handles the reactive input power andreduces the large second current harmonic from the dc-link ca-pacitor, thus reducing its size. These features are achieved withoutany penalties in the quality of both the ac input current and themotor voltage waveforms. Experimental results confirm the theo-retical considerations.

Index Terms—Energy storage reduction, multilevel converter,regenerative cell.

I. INTRODUCTION

MULTICELL power circuit topologies have provedto be an effective alternative to medium-voltage ac

drives [1]. Commercial units are built up based on modularunits, namely, cells, which are composed of a three-phasediode-based front-end rectifier, a dc-link electrolytic capacitor,and a single-phase full-wave inverter (Fig. 1). The main advan-tage is the improved power quality at both the ac system andthe motor sides as in multilevel converters [2], [3]. However,1) the normal operation of the inverter in each cell generatesa large second current harmonic that is injected back into thedc-link capacitor, thus, a very large electrolytic capacitor has tobe used in order to reduce the voltage ripple; 2) the diode-basedrectifier does not provide control over the reactive input currentcomponent; and 3) the diode-based rectifier does not providethe regenerative operating mode as required, for instance, bydownhill belt conveyors in mining applications, where this

Manuscript received December 31, 2003; revised February 20, 2004. Ab-stract published on the Internet November 10, 2004. This work was supported bythe Chilean Fund for Scientific and Technological Development (FONDECYT)under Projects 101 0096–103 0368. This paper was presented at the 2002 IEEEInternational Symposium on Industrial Electronics, l’Aquila, Italy, July 8–11.

M. A. Pérez and J. R. Espinoza are with the Departamento de Ingeniería Eléc-trica, Facultad de Ingeniería, Universidad de Concepción, Concepción, Chile(e-mail: [email protected]).

J. R. Rodríguez and P. Lezana are with the Departamento de Electrónica,Universidad Técnica Federico Santa María, Valparaíso Chile.

Digital Object Identifier 10.1109/TIE.2004.841095

operating mode is the normal one as several megawatts arerequired to be taken back by the ac drive. This paper proposesto replace the diode-based rectifier with an active front-endrectifier allowing the control of the active and reactive inputcurrent components and a novel control strategy that allowsthe topology to regenerate active power into the ac systemand to reduce the size of the dc-link electrolytic capacitor byreducing the second current harmonic that circulates into it.These features are achieved without any penalties in the qualityof the overall waveforms.

The remainder of this paper is organized as follows. Section IIpresents the currently used converter circuit topology and showsits drawbacks. Section III, shows the proposed topology andpresents the theoretical background. Section IV shows exper-imental results of a nine-cell converter that confirm the theoret-ical considerations. Finally, the conclusions are given in Sec-tion V.

II. MULTICELL POWER CIRCUIT TOPOLOGY

A commercial multicell power circuit topology is shownin Fig. 1(a). This structure uses three symmetrical cells [asshown in Fig. 1(b)] connected in series to form one motorphase voltage. The actual number of series-connected cells isdetermined by the required load voltage, as each cell is builtup of off-the-shelf, thus, standard, components. The phase loadvoltages [Fig. 1(f)] are the summation of the single-phase volt-ages generated by each cell [Fig. 1(e)]. In order to maximize theload phase voltages, the ac voltages generated by the cells con-nected in series feature identical and synchronized fundamentalcomponents. On the other hand, the voltage waveform gener-ated by each cell is a pulsewidth-modulation (PWM) voltagewaveform [Fig. 1(e)] which contains unwanted harmonicslocated at frequencies given by the modulating technique thatis used. In fact, if a carrier-based modulating technique is used,some of these harmonics are not present in the total phase loadvoltage if the carrier signals of each series-connected cell areproperly phase shifted. It is shown that the phase shift should be360 , where is the number of series-connected cells [4].

The ac supply current of each cell is a six-pulse type of currentas shown in Fig. 1(d) which features harmonics at

. Similarly to the motor side, the ac supply currents ofeach cell are combined in a multipulse transformer [Fig. 1(a)]so as to achieve overall high-performance supply currents.

From the previous description, it can be concluded that eachcell cannot regenerate active power into the ac system as the

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172 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 1, FEBRUARY 2005

Fig. 1. AC drive based on a multicell power circuit topology. (a) AC drive topology. (b) Power cell topology. (c) Supply input current. (d) Input ac cell current.(e) Output ac cell voltage. (f) Load ac phase voltage.

diode-bridge rectifier does not allow the dc current to reverse itspolarity. This can be considered as a drawback in applicationswhere regeneration is the normal operating condition. This is thecase of downhill belt conveyors in mining applications, where alarge amount of active power (several megawatts) must be takenback by the ac drive. Additionally, the ac output power in anyof the cells is given by , where could be ( isthe row number, then 1, 2, or 3, for 3 series-connected cells,and is the motor phase, then , , or ), and could be

( is the motor phase, then , , or ), as depicted inFig. 1(a). If the output voltage and current ripples are neglected,then, the output voltage can be simplified toand the output current to , where is themotor synchronous frequency and is the motor powerfactor. Thus, the output instantaneous power becomes

(1)

If the inverter stage of the cell is assumed lossless, then, the in-stantaneous power entering the inverter stage of any cell, whichis given by [Fig. 1(b)] is equal to and, therefore, thecurrent in the cell is given by

(2)

As expected, the input current at the dc side of the inverter inany cell contains a dc component and a large second harmonic(with respect to the motor operating synchronous frequency).This harmonic is partially absorbed by the dc-link capacitor andit would also tend to circulate through the diode-based rectifierand, thus, through the ac system. This will lead to a deteriorationof the dc-link voltage and a poor current harmonic cancellationperformance of the multipulse transformer. It should be notedthat the design of the dc-link capacitor in order to provide a pathfor the second current harmonic requires a large capacitor value,specifically if the drive operates at frequencies lower than thenominal synchronous value.

PÉREZ et al.: REGENERATIVE MEDIUM-VOLTAGE AC DRIVE BASED ON A MULTICELL ARRANGEMENT 173

Fig. 2. Proposed power cell topology.

III. PROPOSED CELL CIRCUIT TOPOLOGY

AND CONTROL STRATEGY

In order to allow the regenerative operating mode in the powercell, its diode-based rectifier should be replaced by an activefront-end rectifier. Because the single-phase inverter of each cellneeds a voltage source as a dc link, a voltage-source rectifier ischosen (Fig. 2). At first, it would be expected that sinusoidal acinput currents in each cell should provide an optimum operation;moreover, if unity displacement power factor is required, the acinput current should additionally be in phase with the phase volt-ages. However, sinusoidal and in-phase ac input currents willdemand the circulation of the second current harmonic injectedback by the operation of the inverter into the dc-link capacitor,just as in a cell that uses a diode-based rectifier.

In order to prove the previous statement, the ac supply phasevoltages in any given cell are assumed to be

(3)

where , , and could be , , and , respectively (is the row number, then 1, 2, or 3), and assuming the acsupply currents sinusoidal and in phase with the phase voltages,then

(4)

where , , and could be , , and , respectively ( isthe row number, then 1, 2, or 3). Hence, the input power ofthe cell is given by

(5)

which cannot be equal to the instantaneous output power of thecell that is given by (1) and. therefore, the dc-link capacitor hasto absorb the difference. In other words, it has to provide a pathfor the second current harmonic injected back by the operationof the inverter stage of the cell. In order to reduce the effect ofthe second current harmonic, the size of the capacitor could be

increased up to a value such that the dc-link voltage ripple isconsidered acceptable.

Instead, this paper proposes to impose an ac input currentwaveform in each cell such that both output and input instan-taneous powers are equal, which will lead to a dc-link capac-itor average voltage mainly constant. This will result in reducedstorage requirements for the dc-link capacitor. To determine thedesired ac input current waveforms in any cell, two control loopsare proposed. First, the instantaneous power theory [5] isused to obtain the ac input current required to assure that boththe active and reactive powers of the motor side are provided bythe ac side of the cell (the equalizer control loop) and second,a linear controller is used to modify the active power absorbedfrom the ac supply by the cell in order to regulate the dc-linkaverage voltage (the dc-link average voltage control loop). Thisscheme is also proposed in [6] using a feedback linearization;however, this work proposes instead a linear proportional plusintegral (PI) controller that guarantees its stability which can beproved by means of passivity theory.

A. PQ Equalizer Control Loop

Considering the ac output of a cell as an unbalanced three-phase system, then, the instantaneous components of thecurrents at the motor side of any cell are given by

(6)

where and,

similarly, the components of the voltages at the motor sideof any cell are given by

(7)

Because the instantaneous power at the motor side of any cell[5] is

(8)

then, the instantaneous active power is and the instanta-neous reactive power is zero.


Fig. 3. Proposed control strategy.

Considering that no zero sequence is present in the ac inputof the cell (because no grounding is considered), the followingexpression holds for the input instantaneous power [5]:

(9)

where , , and , are the instantaneous componentsof the voltages and currents, respectively, at the ac input of anycell, that are calculated as

(10)

and

(11)

where

Forcing the instantaneous input and output powers to be thesame ( , ), the expression for the desired ac inputcurrent is obtained from (8) and (9) as

(12)

The previous expression can be written in the frame consid-ering that as

(13)

where is the peak phase voltage and thus is the squareof the line rms voltage. It is possible to note that the currentreferences have a fundamental component given by the supplyvoltage, in (13), that modulate a second harmonic(referred to the output frequency) given by the output powerterm in (13).

TABLE IPARAMETER VALUES OF A CELL FOR EXPERIMENTAL RESULTS

Considering constant and as in actual implemen-tations that are synchronized with the ac supply, from (12) theinput current references in the frame become

(14)

The previous expression shows that just the direct current ref-erence is restricted by the equalization of the input and outputinstantaneous power. In order to have control over the input re-active power, an arbitrary term is added to the reactive cur-rent reference. Thus, the total input current reference becomes

(15)

The additional term allows to modify the input reactive powerwithout altering the active power required by the load [8].

B. DC-Link Average Voltage Control Loop

If the converter is lossless then (15) would define the totalrequired input current in order to guarantee that the active andreactive instantaneous motor powers are supplied by the acside of the cell and, therefore, the dc-link voltage should beconstant. However, the conduction and switching losses of the


Fig. 4. Supply voltage and input ac currents for the overall converter and one cell with unity displacement power factor but the power equalization control loop.(a) Waveforms. (b) Frequency spectrum.

power valves and the losses due to parasitic components of thecell finally result in deviations of the dc-link average voltage.It is proposed to use a standard PI controller to generate theadditional ac current references in phase with the phase supplyvoltages. Thus, additional active power is taken from the acsupply in order to compensate for the overall losses of thecell. The additional active power reference is given by theoutput of the PI according to

(16)

where the gains and should be obtained to assure anacceptable performance of the dc link average voltage dynamic.Hence, the additional current reference is given by

(17)

C. Overall AC Current References

The total current references is the summation of the refer-ences given by (15) and (17), which are

(18)

The complete control strategy block diagram for one cell isshown in Fig. 3 and can be implemented following the dis-tributed structure given in [7]. In particular, the block “outputpower correction” in Fig. 3 generates the desired ac input cur-rent using (16). In the block “output instantaneous power” theadditional reference is generated using (14). It is noted that theoutput voltage is not sensed as it is built up by multiplying

Fig. 5. Direct current reference, and actual direct and quadrature currents.

the modulating signal sent to the inverter (fundamental com-ponent of the desired ac output voltage) and the dc link voltage

, this avoids the troubles of sensing a PWM voltage as theactual ac output voltage of the cell and then filtering it out toobtain the fundamental component.

D. Ideal Overall AC Current

If the converter is lossless, then , thus, the desiredac currents at the input of the cell , using (13) are given by(19)–(21) for phases , , and , respectively

(19)


Fig. 6. DC-link voltage, output voltage, and output current for one cell. (a) Waveforms. (b) Frequency spectrum.

(20)

(21)

Such expressions have been obtained considering sinusoidalsupply voltages as in (3), and sinusoidal motor waveforms asused to obtain (2). Clearly, the desired input currents contain afundamental component which is in phase with the ac supplyvoltages and unfortunately, unwanted harmonics at frequencies

and . In fact, the current given by (22) isthe line current in the cell , and (23) is the line currentin the cell , all of which feature harmonics at frequencies

and , but 240 out of phase

(22)

(23)

However, these harmonics are cancelled out by the combinedoperation of the cells that belong to the same row (which areconnected to the other phases of the motor) and the multipulsetransformer. In fact, the total contribution to the phase of the

first row of cells ( , , and ) is the summation of thecurrents given by (19), (22), and (23), which comes to be

(24)

As expected, the resulting ac input current does not contain theharmonics at frequencies and , moreover, it issinusoidal and in phase with the supply voltage. Similar expres-sions are obtained for the phases and . Thus, the operation ofa single row of cells guarantees an input overall ac current freeof unwanted harmonics which are due to the proposed controlstrategy.

IV. EXPERIMENTAL RESULTS

For the experimental results a nine-cell prototype converterwas implemented. The parameters used throughout the experi-ments are given in the Table I. A small dc-link capacitor is usedin order to show clearly the influence of the second harmonic inthe dc link. Several static and dynamic tests were implementedin order to characterize the overall performance of the topologyand control strategy.

A. Test 1: Unity Displacement Power Factor

Figs. 4–6 show the results as the reference for the quadraturecurrent is set to zero, to obtain a unity displacement input powerfactor, and the power equalization control loop is off. Fig. 4shows that the input current for one cell has the switchingcharacteristic harmonics while the converter input currentfeatures smoothed harmonics.

Fig. 5 shows the reference for the direct ac supply currentgiven by the dc-link voltage controller, the actual direct current,and the actual quadrature current. Both actual components aremainly dc as the power equalizer control loop is off, leading tosinusoidal ac input currents.



Finally, Fig. 6 shows the dc-link voltage that features alarge second harmonic at the output frequency (40 Hz). It canbe also seen that the output voltage for one cell presentslow-order harmonics corresponding to the third (60 Hz) and fifth(100 Hz) of the output frequency and high-order harmonics lo-cated at the switching frequency. The output current is alsohighly distorted, mainly due to the low order harmonics presentin the output voltage. These results confirm that operating thecell with sinusoidal ac input currents requires the dc-link ca-pacitor to sink the dc-link current harmonics.

B. Controlled Rectifier With Enabled Equalization Power Loop

Figs. 7–9 show the results as the power equalization controlloop is turned on. Fig. 7 shows that the input current of eachcell has a fundamental component at Hz and twomodulated components at Hz and Hz. These twolast components are eliminated at the input transformer stage bymeans of the contribution of the other cells located at the samerow level in the topology as stated in (24) and seen in the overallinput current in Fig. 7(a).

Fig. 8 depicts the direct current reference given by thepower equalization loop. It is not mainly dc; on the contrary, it isnow mimicking the output power waveform. The direct currentpresents a tracking error due to the current controller parameterssettings and the quadrature current presents a small dynamiccoupling. These reference waveforms are reducing the injectionof the second current harmonic into the dc-link capacitor byinjecting it back into the ac system.

Fig. 9 shows that the dc voltage ripple is reduced and thelow-order harmonics in the output voltage are also dramat-ically reduced; moreover, the output current is nearly sinu-soidal [Fig. 9(a)].

Fig. 8. Direct current reference, actual direct and quadrature currents.

C. Reactive Power Compensation Capabilities

Figs. 10–12 are the results of the converter being forced to op-erate with a capacitive quadrature current. This operating modeis preferred in industrial facilities where the overall power factoris of concern. Usually, a minimum overall power factor is re-quired that can be accomplished by contributions of reactivepower from drives as the proposed. Specifically, Fig. 10 showsthat it is possible to operate with a capacitive overall current

, while the features obtained by the power equalization loopare maintained. These are a small dc-link voltage ripple, smalllow-order harmonics in the output voltage, and a nearly sinu-soidal output current, Fig. 11.

Fig. 12 shows the actual direct and quadrature currents, andthe reference. Clearly, the actual dc component of the


Fig. 9. DC-link voltage, output voltage, and output current for one cell. (a) Waveforms. (b) Frequency spectrum.

Fig. 10. Supply voltage and input current for the converter and one cell withoutthe power equalization loop.

Fig. 11. DC-link voltage, output voltage for one cell, and output current.

Fig. 12. Direct current reference, actual direct and quadrature currents.

Fig. 13. DC-link voltage ripple without/with power equalization.

quadrature current is positive confirming the capacitive oper-ating condition of the drive.



D. DC-Link Voltage Dynamic and Output Overall Voltage

Fig. 13 depicts the dc voltage dynamic response when theequalization power loop goes from the off to the on stage. It ispossible to note that the ripple is reduced to half of the orig-inal, and the average value is the same due to the dc voltageclosed-loop action. The response is a first-order dynamic fea-turing a 100-ms time constant adjusted by the power correctioncontroller parameters.

Finally, Fig. 14 shows the output overall voltage obtained bythe series interconnection of three cells. It contains three levelsandtheloadphasevoltagecontainssevenlevelswhichcorrespondto , with equal to the number of cells. It is possible tonote that in the load phase voltage, the commutation harmonics

are suppressed, and only the harmonics are present.Nevertheless, the low-order harmonics are still present due to thefact that the dc voltage ripple is additive in each cell because it isproduced by the same load current. Although, theoretically it ispossible to eliminate the output voltage second harmonic in thedc-link voltage, there is a practical limitation to obtain this result.The current controller must be tuned so that it follows accuratelythe reference given by the power equalization control loop, nev-ertheless its dynamic must be slower than the slowest switchingfrequency, in this case this is given by the inverter switching fre-quency. Thus, the input current does not follow fast enough thegenerated reference and the cancellation of the second harmonicis not as good as expected, however, even under this restrictionthe ripple of dc-link voltage is reduced to a half of the original.Naturally higher switching frequencies will allow faster dynamicresponses and better harmonic reduction.

V. CONCLUSION

This paper has shown that multicell converters can operatewith reduced energy storage requirements and can control

the supply reactive power. It was proposed to replace thediode-based front-end converter with an active voltage-sourcefront-end converter, and a novel control strategy. The topologyallows the regenerative operating mode and the control strategyforces the ac input current of each cell to follow a set of refer-ences such that a reduced second current harmonic circulatesthrough the dc-link electrolytic capacitor. Thus, the dc-linkcapacitor size in each cell is reduced while the overall inputdisplacement power factor can be maintained at unity. More-over, the active-front-end rectifier provides the capability ofcontrolling the quadrature component of the input current and,thus, the reactive input power. Experimental results prove thetheoretical considerations.

REFERENCES

[1] P. Hammond, “A new approach to enhance power quality for medium-voltage AC drives,” IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 202–208,Jan./Feb. 1997.

[2] J.-S. Lai and F. Z. Peng, “Multilevel converters—a new breed ofpower converters,” IEEE Trans. Ind. Appl., vol. 32, no. 3, pp. 509–517,May/Jun. 1996.

[3] L. M. Tolbert, F. Z. Peng, and T. G. Habetler, “Multilevel converters forlarge electric drives,” IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 36–44,Jan./Feb. 1999.

[4] Y. Liang and C. O. Nwankpa, “A new type of STATCOM based oncascading voltage-source inverters with phase-shifted unipolar SPWM,”IEEE Trans. Ind. Appl., vol. 35, no. 5, pp. 1118–1123, Sep./Oct. 1999.

[5] H. Akagi, Y. Kanzawa, and A. Nabae, “Instantaneous reactive powercompensators comprising switching devices without energy storagecomponents,” IEEE Trans. Ind. Appl., vol. IA-20, no. 3, pp. 625–630,May/Jun. 1984.

[6] J. Jinhwan, L. Sunkyoung, and N. Kwanghee, “A feedback lin-earizing control scheme for a PWM converter-inverter having a verysmall DC-link capacitor,” IEEE Trans. Ind. Appl., vol. 35, no. 5, pp.1124–1131, Sep./Oct. 1999.

[7] J. A. Du Toit and H. J. Beukes, “A distributed control strategy for multi-cell converters,” in Proc. IEEE APEC’01, vol. 1, Anaheim, CA, Mar.4–8, 2001, pp. 88–93.

[8] J. Espinoza and G. Joós, “State variable decoupling and power flow con-trol in PWM current source rectifiers,” IEEE Tran. Ind. Electron., vol.45, no. 1, pp. 78–87, Feb. 1998.


Marcelo A. Pérez was born in Concepción, Chile, in1976. He received the Engineer degree in electronicengineering and the M.Sc. degree in electrical engi-neering in 2000 and 2003, respectively, from the Uni-versity of Concepción, Concepción, Chile, where heis currently working toward the Ph.D. degree in thearea of control of power converters.

José R. Espinoza (S’92–M’97) was born in Con-cepción, Chile, in 1965. He received the Eng. degreein electronic engineering and the M.Sc. degreein electrical engineering from the University ofConcepción, Concepción, Chile, in 1989 and 1992,respectively, and the Ph.D. degree in electricalengineering from Concordia University, Montreal,QC, Canada, in 1997.

He is currently an Associate Professor in theDepartment of Electrical Engineering, University ofConcepción, where he is engaged in teaching and

research in the areas of automatic control and power electronics.

José R. Rodríguez (M’81–SM’94) received theEngineer degree from the Universidad Técnica Fed-erico Santa Maria, Valparaíso, Chile, in 1977, andthe Dr.-Ing. degree from the University of Erlangen,Erlangen, Germany, in 1985, both in electricalengineering.

Since 1977, he has been with the UniversidadTécnica Federico Santa Maria, where he is currentlya Professor and Academic Vice-Rector. During hissabbatical leave in 1996, he was responsible for themining division of Siemens Corporation in Chile.

He has several years consulting experience in the mining industry, especiallyin the application of large drives such as cycloconverter-fed synchronousmotors for SAG mills, high-power conveyors, controlled drives for shovels, andpower quality issues. His research interests are mainly in the areas of powerelectronics and electrical drives. In recent years, his main research interestsare in multilevel inverters and new converter topologies. He has authoredor coauthored more than 130 refereed journal and conference papers andcontributed to one chapter in the Power Electronics Handbook (New York:Academic, 2001).

Pablo Lezana was born in Temuco, Chile, in 1977.He is currently working toward the Ph.D. degree inpower electronics at the Universidad Técnica Fed-erico Santa María, Valparaíso, Chile.

His research interests include PWM rectifiers andmodern digital devices.

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