Department of electronics& Communication Engineering

GITAM UNIVERSITY,BENGALURU

Previous year Semester Questions DIGITAL LOGIC DESIGN

UNIT-1

1. Subtract 27810 from 49510 using the excess-3subtractor.2. Encode the decimal number using 6,3,1,-1 weighted code. Is it a self-complementing code?3.Draw the schematic of a 2 input CMOS NOR gate.4. The message below has been coded in Hamming code. Decode the message for single error detection code (message = 4 bits). 1001001 0111001 1110110 0011011. 5. Draw a convection table to convert BCD code to Gray code. 6.Convert (0011001.0101) 2 to decimal.7. Perform the following operations. a) 1100.010 – 1000.111 ii) 87-999 using 2’sarithmetic.

b) Encode the decimal number with the 8, 4,-2, -1 weighted code. c) Compare the characteristic features of TTL and CMOS logic.8. a)Consider the message bits m4 m3 m2 m1 = 1101. Encode it into

hamming code to detect single error. b) Convert a BCD code to excess -3 code. c) Convert (283.47)10 to binary code.9. Convert the decimal number 39.12 in to binary

b) Convert to octal i) 110012 ii) 1110101112 4c) If A = -24 and B = +16 4. i) Represent A andB in 8-bit 2’s complement ii) Find A+B iii) Find A-B10. Draw and explain TTL NAND gate with totemple output.11. Write a short descriptive notes on error detection code and error correction code.

12. In a new number system, X and Y are successive digits such that (XY)r = (25)10 and (YX)r = (31)10. Find X,Y,r

13. The 7’s complement of a certain octal number is 5264. Determine the binary and hexadecimal equivalents of the octal number

14. How many bits could be required to encode decimal number from 0 to 9999 in straight binary and BCD code? What would be the BCD equivalent of decimal 27 in 16 bit representation.

15. How many bits would be required to encode? i) 56 elements of information to Hamming code ii) 131 elements of information to Hamming code.

16. Define the terms (i) Cyclic codes (ii) Reflective code (iii) Unit distance codes. Also show that Gray code is both reflective andunit distance code.

UNIT-2

1. Minimize the given 5 variable function usingQM Tabular method f = (2, 4, 9, 10, 11, 12, 19,20, 21, 22, 23, 24, 25, 26, 29, 31).

2.Realize an 2 input EX-OR gate using minimum number of 2 input NAND gates.

3. Simplify the functions using K-map F = (0, 1, 2, 3, 4, 6, 7, 8, 9, 12, 13, 14, 15).

4.Check if f = is self dual. 4 c ac ab ac c ab

5.Obtain the canonical POS for f (A,B,C) = A . C B

6. Find the complement of . 4 f a b c d e

7.Obtain the switching function realized by thegiven gate method. 4

8.Simplify the given function . f A B C D

9. Find minimum sum of product form of the given function f=∑5,9,14,15+π 0,1,7,8,11,12,13 ∑

and realize the circuit.

10. Find the dual of f A C B D C

11. Express the following functions in sum of min terms and product of max terms i) F(A,B,C) = 1 ii) F(A,B,C) = (AB+C) (B+AC)

12. Implement the function Y = AB+A(B+C)+B(B+C)using Boolean theorems.

13. Simplify the function F(A,B,C,D) = (0,2,6,11,12,13,14) using k-maps and implementthe circuit using NAND gate only.

14.Simplify the function F(A,B,C,D) = (1,4,6,7,8,9,10,11,15) using Tabulation Method.

15. Determine the canonical SOP form for i) ii) 6 (, , ) Fxyzxy z xyz (, , ) ( ) Fxyzxy z b) Solve and find the value of A,B,C and D for the given expressions

6 0; ; AAB AB ACAB AC CD CD

16. Find the complement of 6 f ABCDEF

17. Simplify the following function using QM table method 0,1,3,4,7,13,15,19,20,22,23,29,31f

UNIT-3

1.Design a 5 to 32 line decoder using 3 to 8 line decode, active low outputs with 2 active low and one active high enable. 2. Draw the logic diagram of 8 to 3 line encoder using three input NAND gates.3. Develop a set of Boolean equations which canbe used for implementing a circuit that compares two 4 bit words A and B and gives an active high out put for each of the three possible conditions A>B, A=B and A<B. 4.Implement f (A,B,C,D) = (0,1,3,5,6,8,9,11,12,13) using 8:1 MUX.5. Design the gate circuit of 8:1 MUX.

6. Implement the following function using 8:1 MUX

7. Implement the following function using 8:1 MUX f(A,B,CD)= (3,4,5,6,8,9,10,13,14,15)∑8. Design a Full adder circuit using AND, OR, NOT gates. 9. Develop a 3 to 8 live decoder using NOR gates only.10. Design a Full adder using Half adders and carry look ahead adders.11. Design a BCD-to decimal decoder.

12. Design 8×1 multiplexer using 2×1 multiplexer. 13. Difference between encoder and priority encoder.14. Implement the logic shown below using NAND gates only.

15. Design a combinational circuit with three inputs x, y and z and three outputs A,B and C when the binary input is 0,1,2 or 3, the binary output is one greater than the input.

16. Design a 2 to 4 decoder using NOR gates only.

UNIT-41. With the aid of external logic, convert D type flip-flop to a JK flip-flop.

2. Design a synchronous modulo-12 counter usingNAND gates and JK flip flops.3. Design a 3 stage shift register which is an universal register.

4.Draw the timing diagram of a 4 stage twisted ring counter for a period of 8 clock pulses.

5. Design a modulo -12 counter using a shift rigister and feedback logic.

6. Design a serial in serial out right shift register of 4 bit. Draw the timing diagram of each flip flop output.

7. A 5 stage ripple counter uses flip flops having a delay time of 30 ns and a decode timeof 50 ns. Determine the maximum frequency of operation of the counter.

8.Explain how Master slave flip flop achieves the “race around condition”.

9. Draw and explain Master-Slave D-Flip-Flop.

10. Explain SR Flip-Flop with help of NAND gates also obtain its excitation table.

11.Discus about Race-around condition.

12. Design a Modulo-7 binary counter using J K Flip-Flop. Draw its

state diagram.

13.What are the applications of Flip-Flops?

14. A ripple counter uses Flip-Flop having tpd=12 ns. What can be the largest mode counter constructed from Flip-Flops and operated frequency at 10MHz?

15. Show how a JK flip flop can be constructed using a T flip flop and other logic gates

16.Given a 100 MHz clock signal, derive a circuit using D flip flops to generate 50 MHz and 25 MHz clock signal. Draw a timing diagramfor all three clock signals.

17. Design a 4 bit universal shift register using JK flip flops .

18. Design a counter circuit which counts 0,4,6,7,1,0. Design the circuit using JK flip flops.

UNIT-5

1. a Reduce the number of states in the following state table and tabulate the reduced state table.PS NS1Z x=0 x=1 A D, 0 H, 1 B F, 1 C, 1 C D

D, 0 C, 0

F, 1 E, 1

E C, 1 D, 1 F D, 1 D, 1 G D, 1 C, 1 H B, 1 A, 1

2. Write a brief note on Hazards and races.3. The output Z of a fundamental mode, two input sequential circuit is to change from 0 to 1 only when x2 changes from 0 to 1 while x1=1. The output changes from 1 to 0 only when x1 changes from 1 to 0 while x2=1. Find a minimum row reduced flow table.

4.Draw a state diagrams of a sequence detector which can detect 011.5. Design a sequence detector with overlapping,the sequence is 10101. Use SR flip flops in the design.

6. What are static and dynamic hazards? Explainwith an example each. 7.Draw the state table for a synchronous circuit, write one input x, and one output z, which operates according to the following sequences. at t = 0, the initial state is A and x (t) = 0for t < 0. i) z(t) = x(t)+x(t-1) ii) z(t) = x(t).x(t-1) Where the change from eq (i) to eq (ii) occurs at time such that x ( ) = x ( -1) = x ( -2) = 1 and the changefrom (ii) to (i) occurs at time T such that x (T) = x (T-1) =x (T-2) = 0. 6 8.Write a brief note on Merger graph. 9. Design a sequence detector with over lapping, the sequence is 10110. Use JK Flip-Flop.

10.What is merger graph? Explain.

11. Find a state assignment for the following synchronous sequential .

0 1 A B/0 E/0

B D/0 A/1C D/1 A/0D B/1 C/1E A/0 A/0

12. Give the procedure for analysing of Fundamental Mode Circuits.13. Derive a state diagram for an FSM that has an input x and an output z. The machine generates Z = 1 when 1001 or 1111 bit patternsare detected, else Z = 0 6 .

14. Design a three bit parity generates. For every three bits the parity bit P = 1 if and only if the number of 1’s in sequence is odd 6 .

15. a) Design a serial binary adder using only NAND gates and S-R flip flops.16.Derive a hazard free minimum cost SOP implementation for f(x1,x2x3,x4,x5)= m(2,3,14,17,19,25,26,30)+D(10,23,27,31)∑

ANALOG ELECTRONICS& CIRCUITSUNIT-1

1. Write a short note on IC desigN2. Compare MOSFET and BJT 3. Draw and explain about MOS current steering circuit

4.Explain about the general considerations of High Frequency responseUNIT -2

1. Explain the high frequency response of Common Source amplifier using Millers Theorem.2. Explain the small signal model of common-gate amplifier with active loads4.Derive the short-circuit transconductance GRmR of the MOS cascade Amplifier5.Draw and explain about BJT cascade.6. Discuss briefly the choice of transistor configuration in a cascade amplifier.7. Explain Current-Mirror Circuits with Improved Performance.8. Explain the working principle of cascade amplifier and also derive the expression for the voltage gain.9. What are the different types of distortions possible in amplifier outputs.

UNIT-3

1. Explain the small signal operation of MOS differential pair.2. Obtain the common mode gain and CMRR of BJT differential amplifier 3.Obtain the Frequency Response of the Differential Amplifier using i) Resistively Loaded MOS Amplifier ii) Active Loaded MOS Amplifier4. What are multistage amplifiers? Draw the equivalentcircuit of RC coupled amplifier in the mid frequency range, high frequency range and low frequency range

and derive the equations for current gain, voltage gain, upper 3 dB frequency and lower 3 dB frequency.5. What is the effect of voltage gain and Band width in cascaded amplifiers?

UNIT-4

1. Draw and explain about the four basic topologies 2. Derive ARifR, RRifR and RRofR for a Voltage Amplifier 3.Determine the loop gain of a Feedback Amplifier4. Drive ARifR, RRifR and RRofR for a TransconductanceAmplifier5. What are different types of feedback amplifier topologies? Explain with the help of block diagrams.6. A voltage-series negative feedback amplifier has a voltage gain without feedback of A=250 input resistance Ri=5K, output resistance R0=20K and feedback ratio =0.01. Calculate the voltage gain Af, input Resistance Rif and output resistance Rof of the amplifier with feedback.7. Determine Rif, Rof of voltage shunt feedback amplifier 8. A voltage series negative feedback amplifier has a voltage gain without feedback A=450, Ri=3kΩ and Ro=20kΩ and feedback ratio β=0.01. Calculate the Af, Rif, Rof with feedback9. Compare negative feed back and positive feedback.10. What are the advantages of negative feedback amplifier? Explain the basic concept of feedback amplifier.11.What are the different types of negative feedback? Explain how input and output impedances of any two feedback amplifiers are effected?12. Draw the block diagram of feedback amplifier and state its each function.

13.How can you say that feed back effects on bandwidthof an amplifier?14. What are the four possible topologies of feed backamplifier? Identify the output signal and feed back signal . o X f X Explain in detail.15. What is the concept of feed back. Explain characteristics of negative feed-back amplifier. 16. Draw the equivalent circuit for a voltage amplifier. What are the values of Ri and Ro.17. Determine the Voltage Gain, input and output impedence with feed back for voltage series Feed back having A=-100, Ri = 10K ohms Ro= 20 K ohms for a feed back of a) β = 0.1b) β = 0.5

UNIT-5

1. Draw and explain the operation of Class C Power amplifier 2. For the class B output stage VRccR=6V and RRLR=4Ω.If the output is a sinusoid with 4.5V peak amplitude, find i) the output power ii) the average power drawn from each supply 3. the power efficiency obtained at this output voltage 4. Explain how biasing can be done for Class AB Circuit 5. Write a short note on Power BJTs6. How power amplifiers are different from voltage amplifiers? Explain the operation of class A power amplifier obtain its conversion efficiency.7. What is crossover distortion? How do we eliminate this distortion? What are the advantages of class B over class A power amplifier?

8. Draw the schematic of Class A amplifier. Explain its working.9. With Neat Schematic explain the working of Class ABamplifier.10. What is the significance of heat sink in power amplifier?11. Determine the conversion efficiency of class B power amplifiers.12.How power amplifiers are different from voltage amplifiers

ANALOG COMMUNICATIONS

UNIT-1

1. Explain the operation of square law modulators. Usenecessary equations.2. A 400W carrier is modulated to a depth of 75%. Calculate the total power in the AM3. Explain the generation of double sideband suppressed carrier (DSB-SC) modulation. Write the necessary equations. 4. A 360W carrier is simultaneously modulated by two audio waves with modulation percentages of 55 and 65 respectively. What is the total sideband power radiated?5. Draw the block diagram of phase cancellation SSB generator and explain how the carrier and the unwanted sideband are suppressed.6.Draw the spectrum of single tone AM wave giving necessary mathematical equations 7. Compare SSB with DSB SC and conventional AM.

8. How AM is generated using square law modulator? Derive relevant expressions.9. Show the block diagram for phase shift method of SSB generation and explain its working 10.Distinguish between TDM and FDM.

UNIT-2

1. Write about FM generation using parameter variationmethod. 2. Why pre-emphasis and de-emphasis circuits are necessary in frequency modulation and demodulation?3. Compare the performances of FM with AM.4. Distinguish between NB FM and WB FM 5. Describe the generation of FM using Armstrong method with a neat block diagram5. Draw the circuit diagram of a Foster-Seeley discriminator for demodulating the FM signals and explain its operations with phasor diagrams 6. Discuss the advantages and disadvantages of FM overAM7. Define FM and PM modulation. Write their equations. Explain a mechanism to convert PM signal into FM signal.8.With the help of block diagram, explain FM demodulation using PLL.9. Give the procedure to determine the effective bandwidth of an FM signal.10. Describe the generation of FM signal using indirect method.11. Differentiate between narrow band FM and wide bandFM.12. Draw the frequency multiplier circuit and explain its operation.

13. Explain about indirect method of generating frequency modulation 14. The equation of an angle modulated voltage is v(t) – 10 sin (108t + 3 sin 104t). What form of angle modulation is this? Calculate the carrier and modulating frequencies, the modulation index and deviation and the power dissipated in a 100Ω resistor?

UNIT-3

1. Derive the equations for power spectral density ofnc (t) and ns (t). 2.Explain about noise bandwidth and spot noise figure.3. The noise present at the input to a two port is 1 W. The noise figure F is 0.5 dB. The receiver gain ga = 1010. Calculate : (i) the available noise power contributed by the 2 port (ii) the output available noise power.4. Write short notes on “Thermal Noise” 5. Derive the expression for the overall noise figure of a cascaded amplifier with two stages.6.Explain the following(i) Equivalent Noise bandwidth (ii) Effective noise temperature 7.Explain “Linear filtering” in brief.8. Explain about quadrature representation of noise 9. An antenna has a noise temperature Tant = 100K. Itis connected to a receiver which has an equivalent noise temperature Te = 1400K. The midband available gain of the receiver is gao = 1010 and with respect to its midband frequency, the noise bandwidth is BN = 1.5 x 105Hz. Find the available output noise power.10. Explain the effect of filtering on noise bandwidth 6

11.An antenna has a noise temperature Tant = 40K. It is connected to a receiver which has an equivalent noise temperature Te = 1000K., gao = 1010, and receiver is represented by a parallel RLC filter having the 3dB bandwidth of 10MHz. Find: (i) Noise bandwidth (ii) available output noise power.

UNIT-4

1. Calculate signal to noise ratio for SSB system. 2. Explain about FM threshold effect.3. Derive an expression for SNR at the output for coherent reception with SSB modulation 4.Discuss the S/N ratios at the input and output of Envelope detector and product demodulator used for Normal AM. Hence compare their performance.5. Draw the AM receiver model and determine the signal to noise ratio of AM system 6.Explain the capture effect and threshold effect in FM 7.Derive the output SNR of FM demodulator with small noise conditions .8. What is noise equivalent bandwidth? Explain.9. Derive the expression for signal to noise ratio inAM10. Draw the circuit for AGC and explain its operation.

UNIT-5

1. Draw the block diagram of superheterodyne receiver. Explain about each block. What are its advantages? 2. Write about the following: a) Image frequency rejection. b) Tracking in superhetrodyne receiver.

3. What is the necessity of Tracking in radio receiver? Explain the three point tracking employed in radio receiver 4. What is the necessity for an amplitude limiter in an FM receiver? Explain the operation of a typical limiter.5. Draw the block diagram of FM transmitter and explain its working.b) Explain the terms i) Sensitivity ii) Selectivity iii) Fidelity of receiver.6. What is the necessity of AGC? Explain about delayed AGC7.Explain about: i) Sensitivity ii) Selectivity iii)Fidelity iv) Image rejection ratio 8.What are the factors that influence the choice of intermediate frequency 9.Define image frequency and image rejection in superheterodyne receiver. In a receiver the loaded Qof the antenna coupling circuit is 100. If the I.F. is 455 KHz, calculate (i) Image frequency and its rejection ratio for tuning at 1100 KHz. (ii) Image frequency and rejection ratio for tuning at 25 MHz

FILTERS AND WAVESHAPING CIRCUITS

UNIT-1

1. Obtain the equation for Filter Transfer function 2. A second order filter has its poles at The ()()1/23/2.sj=−± transmission is zero at ω = 2 rad/sec and is unity at dc(ω=0). Find the transfer function .3. Obtain the transfer function of Butterworth Filter that meets the general transmission specifications

4.With a neat diagram explain how a second orderLCR Resonator can be excited without changing the natural structure.

UNIT-2

1. With a neat diagram explain the analysis of Antoniou-Inductance Simulation Circuit using Op-Amps 2.Draw an LCR Resonator by using Op-Amp and explain the operation.4. Explain the basic principle of tuned amplifier using a MOSFET.5.Investigate the effect of Finite Op-Amp bandwidth on the operation of the Two-Integrator-Loop Filter

UNIT-3

1. Explain the operation of logarithmic amplifier with neat diagram 2.Explain the operation of analog multiplier 3.Explain the operation of Peak Detector 4.Explain the operation of Precision Rectifierswith a neat diagram

UNIT-4

1.Discuss about Barkhaussen Criteria. How can sustained oscillations be produced? 2.Explain the operation of Wein Bridge Oscillator with a neat diagram.

3.With a neat circuit explain the Bistable Circuit with Non- inverting Transfer Characteristics .4.Obtain the Triangular waveform with the help of an Astable Multivibrator.5. Derive the frequency of oscillation of RC phase shift oscillator and explain the circuit6.The resonant circuit of a tuned collector transistor oscillator has a resonant frequencyof 5 MHz. If value of capacitance is increasedby 40%, calculate the new resonant frequency7. Why R.C phase shift oscillators are needed?8. Draw the Circuit Diagram of LC Oscillators. Give the expression for AB.b) What are the important factors in choosing acertain type of oscillator. 9.What are the advantages of Crystal Oscillator? What is piezo electric effect? 10.Give the expression for sustaining oscillations in Colpitts Oscillator.11. Explain the main difference between an amplifier and an oscillator 12. Draw and explain Wein Bridge Oscillator andderive the expression for frequency of oscillator 13. How oscillators are produced in RC phase shift oscillator without any input signal. Explain with the help of circuit.14. Explain the working principle of Weinbridge oscillator. Derive the expression for frequency of oscillations 15. Compare colpitts oscillator and Hartely oscillator. Derive the expression for frequency of oscillation for colpits oscillator

16.Draw and explain the RC phase shift oscillations.

UNIT-5

1. Derive the expression for Sweep Error, Displacement Error and Transmission Error for an Exponential Charging Circuit. Obtain the relation between the three errors .2. Derive the expressions for Sweep Speed Error for Miller and Bootstrap Circuits with necessary diagrams and equations.3.