KEK—93-7

JP9401063

KEK Report 93-7 August 1993 H/D

Lecture Note on Digital Circuit Design for High Energy Physics Experiment

Hirokazu KEDA

NATIONAL LABORATORY FOR HIGH ENERGY PHYSICS

National Laboratory for High Energy Physics, 1993

KEK Reports are available from:

Technical Information & Library National Laboratory for High Energy Physics MOho,Tsukuba-shi Ibaraki-ken, 305 JAPAN

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Lecture Note on Digital Circuit Design for High Energy Physics Experiment*

HIROKAZU IKEDA

National Laboratory for High Energy Physics 1-1 Oho, Tsukuba, Ibaraki-ken, 305 Japan

ABSTRACT

This lecture gives basic ideas and practice of the digital circuit design for high

energy physics experiment. The lecture has a special emphasis on a simulation

study with a hardware description language. The student could complete a design

of a simple RISC based computer after finishing this course.

* Prepared for the summer semester course in 1993 of the graduate University for advanced studies. V1.0 Apr 28, 1993 V2.0 May 30, 1993 V2.1 June 12, 1993 V3.0 July 30, 1993

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1. Introduction

1.1. GENERAL DESCRIPTION

The design concepts on the electronics system for high energy physics exper­

iment meet with a drastic innovation of methodology and/or technology. Tra­

ditional way was to put preamplifiers on the detector end, whose outputs are

transmitted via a large bundle of cables to an electronics hut to be processed by

data acquisition modules. The accelerator operation cycle was bfis to 20 its ,

which was enough to compensate for latency of the trigger decision circuit. This

approach does not work for the recent high luminosity collider experiment. In or­

der to meet with high trigger rate, large data size, radiation damage issues, and an

enormous number of readout channels, we try to apply VLSI technologies to the

de'ector instrumentation for the high energy physirs experiment. The front-end

VLSis have complicated digital control capabilities as well as analog processing

functions, which are directly mounted on a high density printed circuit board. The

back-end digital circuits are operated with high frequency clock signal where a

pipe-line operation takes an essential role. These electronic system are designed

with an aid of circuit simulators based on analog oriented (SPICE) method and/or

digital oriented (VHDL) method. In this text we would like to give access to a dig­

ital circuit design in terms of HDL from Cadence design systems Inc. The analog

circuit issues were described in:

H.Ikeda, "Lecture note on circuit technology for high energy physics experiment",

KEK Report 92-9, July 1992. Students were encouraged to learn analog circuit

technologies together with this lecture course. An analog circuit idea might give

novel ideas for digital circuit design as well as to provide basics about electronic

circuits.

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1.2. REFERENCES

1. Introduction to electronics: P.Holowitz and W.IIill,"The art of electronics", Cambridge University Press,

1980

K.Shimoda and K.Sakurai, "Fundamentals of electronics", Syokabo, 1983 K.Sakurai and K.Shimoda, "Fundamentals of electronic instrumentation",

Syokabo, 1984

2. Digital integrated circuits:

N. H. E. Wcste and K. Eshraghian, "Principles of CMOS VLSI Design, A Systems Perspective", Addison-Wesley

Shibata et al., "Basic course for VLSI technology", Heibonnsha, 19S6 D.F.Stout and M.Kaufmann, "Handbook of microcircuit design and applica­tion", McGraw-Hill Book Company, 1980

D.A.Hodges and H.G.Jackson,"Analysis and design of digital integrated cir­cuits", McGraw-Hill, Inc., 1983 C.Mead and L.Conway, "Introduction to VLSI Systems", Addison-Wesley, 1980

3. Back-plane Bus System:

U.S. NIM Committee, "Standard, NIM Instrumentation System", DOE/ER-

0457T, May 1990

U.S. NIM Committee, "Modular Instrumentation and Digital interface Sys­

tem ( CAMAC )", ANSI/IEEE Std 583-1975

U.S. NIM committee, "IEEE Standard FASTBUS Modular High-Speed Data

Acquisition and Control System", ANSI/IEEE Std 960-1986

4. Computers:

G. J. Myers, "Advances in Computer Architecture", John Wiley & Sons,

Inc., 1978

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1.3. ORGANIZATION OF THE LECTURE NOTE

The materials in this lecture note has been organized as follows. In the follow­

ing chapter we discuss briefly the Boolean algebra, and related topics. We go into

detailed HDL description of primitive gates. In Chapter 3, we consider the combi­

national logics. Chapter 4 treats the sequential logics. Chapter 5 is the description

about memory devices. Chapter 6 deals with a small scale RISC computer to

demonstrate a practical design work.

2. Boolean algebra and logic functions

2.1. BOOLEAN ALGEBRA

We do not intend to go into detail of the Boolean algebra. The identities of the Boolean algebra are listed in Table 1, which give basic ideas of a binary implementation of digital circuit architecture. NAND and NOR are quite common entities of digital circuit design; they are described in terms of the Boolean algebra:

NAND ^>x~*y = x + y (2.1)

NOR->~xTy = x*y (2.2)

These relations exhibit apparent duality of the Boolean algebra.

2.2. TRUTH TABLE AND KARNAUGH MAP

Table 2 gives truth tables for NAND, NOR and XOR. The truth table just

defines response of output to input. Karnaugh map has more subtle idea, from

which we can describe a response function. In Tabic 3 we can see presentations

of NAND, NOR, and XOR in terms of Karnaugh map. For NOR and XOR, the

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Karnaugh maps still looks trivial, however, we find something different for NAND:

x*y + x*y + x*y-*x + y (2.3)

The adjacent l's appeared in the Karnaugh map are subjects lor reduction; they

are marked in the Table. For those who do not believe in availability of Karnaugh

map yet, we try to describe an adder in Karnaugh map, which is shown in Table 4.

We can readily write down the Boolean expression as:

3 = a*l>*Ci+a*b*Ci + a*l)*cj + a*b*Cj (2.4)

co = a*6*Cj + <i*6*c; + a*6*Cj + a * 6 * c 7 - + a * 6 + 6 * C j + a*c ; (2.5)

In order to reach the "minimum sum of product form" , we apply the Boolean

algebra successively, or can use a reduction technique with the Karnaugh map.

The last result of Eq. (2.5) is directly obtained with the Karnaugh map. We

should note the order of (a,b). The distance between adjacent (a,b) is 1 in terms

of Hamming distance. The Hamming distance is defined as:

d(x,y) =\xl-yl\ + \xO-yO\ (2.6)

with x = (xl,iO) and y = (#1,2/0) for a two bit code. A direct proliferation for a

n-bit code is still justified.

2.3. PRIMITIVE GATE

An exact circuit configuration is described for TTL, ECL, and CMOS circuits.

RTL and DTL circuits are not discussed here because these circuits are overcome

with new technologies.

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TTL gates Figure 1 shows a TTL NAND gate. The TTL gate is characterized in terms of a multi-emitter input and a totem-pole output. The totem-pole output has an active pull-up and pull-down capability. A modified version of TTL output stage has an open collector output stage. Since the open collector output has only an active pull-down capability, we provide a pull-up resistor for each signal line. The open collector output is employed for the CAMAC back-plane and other bus driver application.

ECL gates Figure 2 shows an ECL NOR gate. The ECL gate is characterized in

terms of a current switch and an emitter follower output. While the transistors

for TTL are operated in a saturation region, the ECL transistors are operated in

a linear region to enhance the switching speed and propagation delay. The ECL

output stage allows 0.7V voltage swing for a 50 fi load. The FASTBUS employs

ECL gates to drive and/or receive backplane signals. The ECL signal has a wired-

or capability with positive .true, logic. The FASTBUS fully utilizes the ECL

wired-or capability.

NIM gates Figure 3 shows a NIM receiver and driver circuit together. The driver stage is essentially compatible with current mode logic. We can borrow many ideas from ECL circuit. The driver stage is to feed 16mA pulse to 50 ft coaxial cable. We assume that the coaxial cable is terminated at the far end.

CMOS gates Figure 4 shows a CMOS NAND gate. The drive capability of the

CMOS output stage depends on W/L ratio of the output transistor. W is under­

stood as gate width, and L is understood as gate length ( distance between source

and drain). A CMOS gate with large W/L can drive a large capacitance load.

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2.4. HDL DESCRIPTION OF PRIMITIVE GATES

INV The Boolean function of the INVerter is:

* = V (2.7)

where y and x are understood as input and output of the INVerter. The HDL

description of the CMOS inverter is as follows:

module inv ( x, y) ;

input y ;

output x ;

supplyl vdd ;

supplyO vss ;

pmos # 1 mOl (x, vdd, y) ;

nmos #1 m02 (x, vss, y) ;

cndmodule

where supplyl and supplyO are understood as 5.0 V ( Vdd rail ) and 0.0 V ( Vss

rail ). The arguments for pMOS and nMOS transistor are arranged in an order

of drain, source, and gate. The numbers prefixed with # designate time delay of

the components. In the first line of the HDL description we can find a module

statement, where we recommend to arrange the arguments so that outputs come

first and inputs come later. The CMOS inverter consists of a pair of p-channel and

n-channel MOS transistor, whose instance names are mOl and m02, respectively.

The equivalent SPICE description is:

.SUBCKT INV 2 1

.MODEL PMOSX PMOS VTO=-0.88,

.MODEL NMOSX NMOS VTO=0.89,. VDD 3 0 5.0V

MOI 2 1 3 3 PMOSX L=IA W=24 M02 2 1 0 0 NMOSX L=1.2 W=8

.ENDS

The SPICE simulation goes into detail of the transistor operation, while the tran­

sistors are just a switch element in the HDL simulation. In order to design a large

scale digital VLSI, the HDL simulation is superior than the SPICE simulation

because of its simulation speed and simplicity, however, the HDL simulation is

justified only when each small scale digital entity is verified with the SPICE simu­

lation. In order to put emphasis on the digital circuit nature we do not use SPICE

description any more throughout this lecture. We rely on Verilog HDL description

to present circuit configurations.

NAND2 The NAND2, i.e. 2-input NAND gate, consists of two pMOS transistors

and two nMOS transistors. The pMOS transistors are located in parallel, xv'hile

the nMOS transistors are in series. Students should describe NAND3, NAND4,

and NOR4 for later use.

module nand2 (x, yl, y2); input y l , y2; output x;

supplyl vdd;

supplyO vss;

pmos # 2 mOl (x, vdd, yl);

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pmos #2 m02 (x, vdd, y2); nmos #1 m03 (x, n04d, y2); nmos #1 m04 (n04d, vss, yl); endmodule

NOR2 NOR2 has a dual structure of NAND2. pMOS transistors are arranged as

series while the nMOS transistors are located in parallel.

module nor2 (x, yl, y2);

input yl,y2;

output x;

supplyl vdd;

suppJyO vss;

pmos # 1 mOl (mOld, vdd, yl);

pmos # 1 m02 (x, mOld, y2);

nmos # 2 rn03 (x, vss, y2);

nmos # 2 m04 (x, vss, yl);

endmodule

TRINV Tri-state gate is commonly used to share a bus line. When "enb" is

negated, the output of the tri-state gate is in a high impedance state, which gives

negligible influence on the bus line. When "enb" is asserted, TRINV works exactly

same as INV.

module trinv (x, y, enb); input y,enb;

output x;

supply 1 vdd;

supplyO vss;

pmos # 1 mOl (x, vdd, mOlg);

nmos # 1 m02 (x, vss, m02g);

inv iOl (m02g, iOly);

inv i02 (i02x, y);

nand2 naOl (iOly, enb, y);

nand2 na02 (mOlg, enb, i02x);

endmodule

XOR2, exclusive or The Boolean expression of the exclusive or function is:

X0R2 -*x*y + x*y (2.8)

A direct implementation of XOR2 function will be:

module xor2 (z, x, y);

input x,y;

output z;

inv iOl (ivOlx, x);

inv i02 (iv02x, y);

nand2 na03 (na03x, ivOlx, y);

nand2 na04 (na04x, iv02x, x);

nand2 na05 (z, na03x, na04x);

endmodule

- 1 0 -

A schematic from another implementation of X0R2 function is shown in Figure 5, where a transfer gate technique is employed to realize the logic function. In order to squeeze the layout geometry, the transfer gate technique is quite commonly used in the CMOS digital circuit.

2.5. LOGIC SYMBOLS

There is no unique way to describe logic symbols for schematic entry purpose.

In Figure 6 we show an example of symbols for basic logic functions. It was common

to use MIL Std logic symbols; however, IEEE Std presentation is common in these

days.

2.6. EXERCISE

1) 3-input NAND Describe a 3 input nand gate. NAND3 consists of three pMOS

transistors and three nMOS transistors. The I/O specifications are defined below:

module natid3 (x,y2,yl,y0); input y0,yl,y2; output x; cndmodule

2) 4-input NAND Describe a 4-input nand gate. NAND4 consists of four pMOS

transistors and four nMOS transistors. The I/O specifications are defined below:

module nand4 (x,y3,y2,yl,y0); input y0,yl,y2,y3; output x; cndmodule

3) 4-input NOR Describe a 4-input NOR gate. NOR4 consists of four pMOS

transistors and four nMOS transistors. It is interesting to note that N0R4 is quite

similar to NAND4 if V„ is understood as Va, V44 as V,a, pMOS as nMOS, and

nMOS as pMOS. The I/O specifications are defined below:

module nor4 (x,y3,y2,yl,y0);

input y0,yl,y2,y3;

output x;

endmodule

4) 8-bit AND arithmetic block Describe an 8-bit AND arithmetic block. This

block will be used as a part of an ALU block appearing in Chapter 6. AND8B

consists of eight NAND2 gates and eight INV gates. The I/O specifications are

defined below:

module and8b (c,a,b);

input [7:0] a,b;

output [7:0] c;

endmodule

where [7:0] is understood that signals "a" and "b" are organized as 8-bit wide data.

The individual signal element is designated as a[7], a[6], a[5], and etc.

5) 8-bit XOR arithmetic block Describe an 8-bit XOR arithmetic block. This

block is used as a part of an ALU block appearing in Chapter 6. XOR8B consists

of eight XOR2 gates. The I/O specifications are defined below:

- 1 2 -

module xor8b (c,a,b);

input [7:0] a,b;

output [7:0] a;

endmodule

6) 8-bit tri-state buffer block The HDL module is named as TRBUF8B. TR-

BUF8B is understood as a non-inverting 8-bit tri-state output buffer. TRBUF8B

consists of eight TRINV gates and eight INV gates. The I/O specifications are

defined below:

module trbuf8b(x,y,enb);

input [7:0] y;

input enb;

output [7:0] x;

endmodule

3. Combinational logic

3.1. ADDEII

A circuit block called full adder is described. The full adder block executes a

one bit arithmetic operation of add. Cascading nco" output to "ci", we can make

an adder with arbitrary bit width. We already learned about Boolean expressions

for the full adder. Make sure that the following HDL description is compatible

with the Boolean expressions (2.4) and (2.5).

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module fadder (s, co, a, b, ci);

input a,b,ci;

output s,co;

inv ilOl (ilOlx, co);

inv il02 (il02x, a);

inv il03 (il03x, b);

invil04 (il04x, ci);

nand2nl01 (nlOlx, a, b);

nand2 nl02 (nl02x, a, ci);

nand2 nl03 (nl03x, b, ci);

nand3 nl04 (co, nlOlx, nl02x, nl03x);

nand3 nl05 (nl05x, il02x, il03x, il04x);

nand3 nl06 (nl06x, a, b, ci);

nand2 nl07 (nl07x, ilOlx, nl05x);

nand2 nl08 (s, nl07x, nl06x);

endmodule

FADDER is an element of ADD8B, 8-bit binary adder.

3.2. ENCODER

Binary code encoder The binary encoder provides a one-to-one mapping from

{8'h80, 8'h40, 8'h20, 8'hlO, 8'h08, 8'h04, 8'h02, 8'hOl} to {3'blll , 3'bllO, 3'blOl,

3'blOO, 3'bOll, 3'b010, 3'b001, 3'bOOO}. 8'h** is understood as 8-bit binary num­

ber with hexadecimal presentation. 3'b*** is understood as 3-bit binary number

with binary presentation. The binary code encoder is described as:

module encbin (q,v,d); input [7:0] d;

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output [2:0] q;

output v;

nor4 nr02 (qx2,d[7],d[6],d[5],d[4]):

nor4 nrOl (qxl,d[7],d[6],d[3],d[2]):

nor4 nrOO (qx0,d[7l,d[5],d[3],d[l]);

inv i02 (q[2],qx2);

inv iOl (q[l],qxl);

inv iOO (q[0],qx0);

datchk daOl (v,d);

endmodule

The output of the encoder is valid when only one bit among the 8-bit inputs is

.true.. We describe a circuit to check the integrity of the input condition.

module datchk(v,d); input [7:0] d; output v;

nor2 nrOl (xl,d[0],d[l]); nor2 nr02 (x2,d[2],d[3]); nor2 nr03 (x3,d[4],d[5]); nor2 nr04 (x4,d[6],d[7]); xor2 exOl (cl,d[0],d[l]); xor2 ex02 (e2,d[2],d[3]); xor2 ex03 (e3,d[4],d[5]); xor2 ex04 (e4,d[6],d[7]); nand4 naOl (yl,el,x2,x3,x4); nand4 ;.;02 (y2,xl,e2,x3,x4); nand4 na03 (y3,xl,x2,e3,x4); nand4 na04 (y4,xl,x2,x3,e4);

- 1 5 -

nand4 na05 (v,yl,y2,y3,y4);

endmodule

Gray code encoder The Gray code encoder keeps the Hamming distance as 1

between the adjacent output codes. Table 5 shows the Gray code together with

the ordinary binary code. The Gray code is frequency used for a high speed Plash

A-to-D converter, where a miss code is a serious issue due to deviations of latch

timing. Make sure that the transient behavior of the Gray coding is less harmful

than the binary coding.

module encgray(q,v,d);

input [7:0] d;

output [2:0] q; output v;

nor4 nr02 (qx2,d[7],d[6],d[5],d[4]):

nor4 nrOl (qxl,d[5],d[4],d[3],d[2]); nor4 nrOO (qx0,d[6],d[5],d[2],d[l])i inv i02 (q[2],qx2);

inv iOl (q[l],qxl);

inv iOO (q[0],qx0); datchk daOl (v,d); endmodule

- 1 6 -

3.3. PRIORITY CHAIN

Encoder's output for ENCBIN and/or ENCGRAY is valid when at least and only one input bit ( and at least one bit ) is .true.. Priority encoder gives still a valid output for multiple .ture. bits. The output corresponds to the input .true, bit located at the nearest neighbour of the MSB ( most significant bit). The scheme of a priority encoder is frequently used for a sparse data scan of the front end data acquisition circuits. The priority encoder consists of a priority chain ( PRCHAIN ) and an encoder ( ENCBIN ). The circuit block PRCHAIN is described as:

module prchain (q,i); input [7:0] i; output [7:0] q; supplyl vdd; supplyO vss; inv iv07 (q[7],iv07y); inv iv06 (q[6],iv06y); inv iv05 (q[5],iv05y); inv iv04 (q[4l,iv04y); inv iv03 (q[3j,iv03y); inv iv02 (q[2],iv02y); inv ivOl (q[l],iv01y); inv ivOO (q[0],iv00y); nand2 na07 (iv07y,i[7],vdd): nand2 na06 (iv06y,i[6j,xh6); nand2 na05 (iv05y,i[5],xh5); nand2 na04 (iv04y,i(4],xh4); nand2 na03 (iv03y,i[3],xh3); nand2 na02 (iv02y,i[2],xh2); nand2 naOl (iv01y,i[l],xhl);

- 1 7 -

nand2 naOO (ivOOy,i[0],xhO); nor2 nr06 (xh6,i[7J,vss); nor2 nr05 (xh5,i[6],xh6b); nor2 nr04 (xh4,i[5],xh5b); nor2 nr03 (xh3,i[4],xh4b); nor2 nr02 (xh2,i[3],xh3b); nor2 nrOl (xhl,i[2],xh2b); nor2 nrOO (xhO,i[l],xhlb); inv ivl6 (xh6b,xh6); inv ivl5 (xh5b,xh5); inv ivl4 (xh4b,xh4); inv ivl3 (xh3b,xh3); inv ivl2 (xh2b,xh2); inv ivll (xlilb,xhl); inv ivlO (xhOb,xhO); cndmodule

Combining PRCHAIN with ENVBIN we get a description of ENCPRI, priority

encoder.

module encpri (q,v,d);

input [7:0] d;

output [2:0] q;

output v;

wire [7:0] i;

prchain prOl (i,d);

cncbin en02 (q,v,i);

endmodule

- 1 8 -

3.4. DECODER

Decoder provides a reverse function of the encoder. The Boolean expressions for a 3-to-8 decoder are:

c7 = z'O * il * i'2 c6 = ?0*il *i2

c5 = iO * tl * i2

c4 = 10 * iT * i2

c3 = z'O * i\ * z'2

c2 = zO * :'l * i2

cl = z'0*iT*i2

cO = z'0*il * i'2

The 3-to-8 decoder gives an one-to-one correspondence:

{0,1,2,3,4,5,6,7} -» {8'A1,8/A2,8'A4,8'A8,8'A10,8'A20,8'A40,8'A80} (3.1)

The HDL module name is DEn328, which is a part of the MEM8W appearing in Chapter 5. The HDL description is shown below.

module dec328 (c,i); input [2:0] i; output [7:0] c; inv iOl (iOx, i[0]); inv i02 (ilx, i[l]); inv i02 (i2x, i[2]);

- 1 9 -

iOx, ilx, i'2x);

i[0], ilx, i2x),

iOx, i[l]. i2x);

HO], Kl]. i2x);

iOx, ilx, W); i(01, ilx, i[2]); iOx, i[l]> i[2]);

i[0], i[l], my,

and3 aO (c[0], ; and3 al (c[l], and3 a2 (c[2], i and3 a3 (c[3], and3 a4 (c[4], and3 a5 (c[5], and3 a6 (c[6], i and3 a7 (c[7], endmodule

/ / module and3 (x,yl,y2,y3);

input yl,y2,y.3;

output x;

nand3 naOl (z,yI,y2,y3);

inv ivOl (x,z);

endmodule

3.5. DEMULTIPLEXOR

Demultiplexer is employed to route signals into two ways or more. In the following example, "in" signal is led to "outl" when "sel" is .true., when "sel" is .false., "outO" is the output port for "in".

module demux (outl, outO, in, sel);

input in, sel;

output outl, outO;

inv ivOl (iv01x,sel);

and2 aOl (outl,sel,in);

- 2 0 -

and2 a02 (outO,iv01x,in);

endmoudle

/ / module and2 (x,yl,y2); input yl,y2; output x; nand2 naOl (na01x,yl,y2);

invOl iv02 (x,na01x); cndmodulc

3.6. MULTIPLEXOR

Multiplexor is conceptually a counterpart of the demultiplexer. The two input

multiplexor chooses one of two inputs for output. When "scl" is .true., "inl" is

selected; when "sel" is .false., "inO" is selected.

module mux (x,inl,inO,sel); input inl,inO,sel;

output x;

inv iOl (iOlx, sel); nand2 na02 (na02x, inl, sel);

nand2 na03 (na03x, inO, iOlx);

nand2 na04 (x, na02x, na03x); cndmodule

- 2 1 -

3.7. EXEIICISE

1) 8-bit adder The HDL module name is ADD8B. ADD8B is a part of the arith­

metic logical unit appearing in Chapter 6. ADD8B consists of eight FADDER

blocks. The I/O specifications are described below:

module add8b (c, ov, a, b); input [7:0] a,b; output [7:0] c;

output ov;//overflow bit endmodule

where "ov" indicates that the output is not contained in the 8-bit code. As an

advanced exercise I would like to ask you to describe SUB8B, an 8-bit subtraction

arithmetic block. An additional logic entity is XOR2. The "ci" input for the

FADDER block should be asserted as .true..

2) 5-bit multiplexor

The HDL module name is MUX5B. MUX5B is a part of the RISC computer ap­

pearing in Chapter 6. MUX5B consists of five MUX blocks. The I/O specifications

are described below:

module mux5b (x,inl,inO,sel); input [4:0] inl.inO;

input sel;

output [4:0] x; endmodule

- 2 2 -

3) Generation of 8-bit negative number

The module name is NEG8B. You can use ADD8B and INV ( or XOR ) to imple­ment NEG8B. The I/O specifications are described below:

module ncg8b (x,y);

input [7:0] y;

output [7:0] x;

endmodule

4) Zero detect circuit

The module name is ZEltODET. ZERODET responds with 1 v/hen all the input

bits are zero, which is essentially an 8-input NOR gate. ZERODET is a part of

the arithmetic logical unit appearing in Chapter 6. The I/O specifications are

described below:

module zerodet (zero, d);

input [7:0] d;

output zero;

cndmoudle

5) 2-to-4 decoder

DEC224 is a part of the random access memory appearing in Chapter 5. The I/O

specifications are described below:

- 2 3 -

module dec224 (c,i);

input [1:0] i;

output [3:0] c;

cndmodulc

4. Sequential logic

4.1. FLIP-FLOP

RS flip-flop The RS flip-flop is understood as a reset/set flip-flop. When "set" is

asserted, "q" output turns .true.. When "reset" is asserted, "q" output is negated

and "qbar" output turns .true.. It may be not clear what happens when the RS

flip flop receives set and reset simultaneously. We put an explicit priority on the

"reset" function. The HDL description for RSFF is shown below:

module rsff (q,qbar,set,reset);

input set,reset;

output q,qbar;

inv iOl (iOlx, reset);

inv i02 (i02x, naOlx);

nand2 naOl (naOlx, set, iOlx);

nor2 nrOl (qbar, i02x, q);

nor2 nr02 (q, reset, qbar);

endmodule

- 2 4 -

D flip-flop D flip-flop stands for data flip-flop. The D flip-flop is to synchronize

the data's leading edge to the the clock signal. Another application of D flip-flop

is to strobe data from a bus line and save it.

1) Primitive D flip-flop o:: latch:

The HDL module LATCH is described below:

module latch (q,qbar,d,ck); input d,ck; output q,qbar; nand2 naOl (na01x,d,ck); nand2 na02 (na02x,na0lx,ck); nand2 na03 (q,na01x,qbar); nand2 nafM (qbar,na02x,q); endmodule

There is a trouble about the primitive D flip-flop. When "ck" is .true., a state change of "d" input appears directly on the "q" output; the "q" output is not

necessarily synchronous to the "ck" toggle edge.

2) Master slave D flip-flop:

The master-slave D flip-flop overcomes the inadequate nature of the primitive D

flip-flop. The master-slave flip-flop uses both edges of "ck": "ck(u)", rising edge, and "ck(d) n, falling edge.

module dff (q,qbar,d,ck)

input d,ck;

output q,qbar;

inv ivll (ivllx.d);

inv iv09 (iv09x,ck);

- 2 5 -

invivLO (ivl0x,iv09x); nand2 naOl (na01x,d,iv09x); nand2 na02 (na02x,ivllx,iv09x); nand2 na03 (na03x,na01x,na04x); nand2 na04 (na04x,na02x,na03x); nand2 na05 (na05x,na03x,ivl0x); nand2 na06 (na06x,na04x,ivl0x); nand2 na07 (q,na05x,qbar); nand2 na08 (qbar,na06x,q); cndmodule

Another implementation of the master-slave flip-flop ( DFFX ) with a gated in­

verter ( GTINV ) is shown below:

module dffx (q,qb,d,ck);

output q,qb;

input d,ckb;

trireg gtllout,gtlOout;

inv iv02 (gtOckb,ck);

inv ivOl (gt03ck,gt0ckb);

inv iv08 (gt03in,gtllout);

inv iv05 (qb,q);

inv iv09 (q,gtlOout);

gtinv gt l l (gtllout.d, gt0ckb,gt03ck);

gtinv gt03 (gtllout,gt03in,gt03ck,gt0ckb);

gtinv gtlO (gtlOout.q, gt0ckb,gt03ck);

gtinv gt07 (gtl0out,gt03in,gt03ck,gt0ckb);

endmodule

/ /

- 2 6 -

module gtinv (qb,d,ck,ckb);

output qb;

input d,ck,ckb;

supplyO vss;

supply 1 vdd; nmos # ! nmOl (niii01d,vss,ck); nmos #1 nm08 (qb,nm01d,d); pmos # 1 pm09 (qb,pm04d,d); pmos # 1 pm04 (pm04d,vdd,ckb);

endmodule

The "trircg" property shows that the designated node is a capacitive storage node.

The gated logic shows low power nature and occupies small silicon area. The

operation of GTINV looks same as TRINV. TRINV is applied for I/O pads and/or

bus driver, while GTINV is used as a building block of a function cell.

3) Edge triggered D flip-Hop:

The edge triggered D flip-flop uses only "ck(u)", however, it works almost same as

the master slave flip-flop.

module dffr ( q, qb, d, elk, rstbar); input elk,rstbar,d; output q,qb;

nand2 naOl (cf, dl, cbf);

nand3 na02 (cbf, elk, cf, rstbar); nand3 na03 (dl, d, dbl, rstbar);

nand3 na04 (dbl, dl, clk.cbf);

nand2 na05 (q, cbf, qb);

nand3 na06 (qb, dbl, q, rstbar); cndmodulc

- 2 7 -

JK flip-flop Table 6 shows operation modes of the master-slave JK flip-flop. You

can find that JK flip-flop is a versatile entity of flip-flop function.

module jkff(q,qbarj,k,clock,setbar,clearbar);

output q,qbar;

input j,k,clock,setbar,clearbar;

inv ivOl (kbar.k);

nand4 naOl (a,qbar,j,clearbar,f);

nand4 na02 (b,f,clearbar,kbar,q);

and2 an04 (c,a,b);

nand3 na03 (d,e,sctbar,c);

nand3 na05 (e,d,clock,dearbar);

nand3 naOC (f,e,clock,c);

nand3 na07 (q,setbar,e,qbar);

nand3 na08 (qbar,q,f,clearbar);

endmodule

JKFF is applied for SCNT5B, a 5-bit synchronous counter, DNCNT5B, a 5-bit

down counter, and UDCNT5B, a 5-bit up/down counter, in this Chapter, and PC,

a 5-bit program counter, appearing in Chapter 6.

Setup time and hold time The constraints associated with the operation of D flip-flop and/or JK flip-flop are setup time, hold time and minimum pulse width for "ck" and/or "rstbar", which depend on the detail of the circuit. The setup time is defined as an interval from establishment of "d" to "ck(u)". The hold time is define as an interval from , 1ck(u) n to the state change of "d".

- 2 8 -

4.2. SHIFT REGISTER

4-bit shift register The 4-bit shift register SHIFT4B consists of four DFFR blocks.

"si" is fed in to the DFFR chain at the timing of "ck(u)". The output appears on

"q[3:0]\

module shift4b (q,si,ck,r); output [3:0] q; input si,ck,r; dffr dfOl (q[0]„si,ck,rb); dfTr df02 (q[l]„q[0],ck,rb); dffr df03 (q[2]„q[l],ck,rb); dffr df04 (q[3]„q[2],ck,rb); inv ivOl (rb,r); cndmodule

In the circuit description of SHIFT4B, ",," is to ignore an argument which should be otherwise located there.

Frequency divider The frequency divider FDIV8 consists of SHIFT4B and INV

gates. FDIV8 gives 1/8 frequency of "ckin".

module fdiv8 (ckout,ckin,r);

input ckin,r;

output ckout; wire [3:0] q;

shift4b shOl (q,si,ckin,r);

inv ivOI (si,q[3]);

inv iv02 (ckout,si); endmodule

- 2 9 -

Sequencer The sequencer is a shift register chain which is clocked conditionally

and/or unconditionally. CAMAC and/or FASTBUS operation sequence can be

implemented with this sequencer. When "ena" becomes .true., the sequencer gets

up at the timing of "ck(u)" to assert "q[0]". Unless "d[0]n is .true., the sequencer

cannot move to the next stage. In this way, the sequencer takes a handshake

operation between "q[7:0]" and "d[7:0]". It is nice to implement the FASTBUS

master sequence: AS-AK ( primary address cycle), DS-DK ( secondary address

cycle ), and DS-DK ( data cycle ) with this sequencer.

module seqctrl (q,d,ena,ck,rst);

input ena,ck,rst;

input [7:0] d;

output [7:0] q;

wire [7:0] qx,andx;

dffr dfOl (qx[0]„si,ckx,rb);

dffr df02 (qx[l]„qx[0],ckx,rb);

dffr df03 (qx[2]„qx[l],ckx,rb);

dffr df04 (qx[3]„qx[2],ckx,rb);

dffr df05 (qx[4]„qx[3],ckx,rb);

dffr df06 (qx[5]„qx[4],ckx,rb);

dffr df07 (qx[6]„qx[5],ckx,rb);

dffr df08 (qx[7],si,qx[6j,ckx,rb);

dffr df09 (qx8,qx8b,qx[7],ckx,rb);

xor2 XoOl (q[0],qx[0],qx[l]);

xor2 xo02 (q[l],qx[l],qx[2]);

xor2 xo03 (q[2],qx[2],qx[3));

xor2 xo04 (q[3],qx[3],qx[4]);

- 3 0 -

xor2 xo05 (q[4],qx[4],qx[5]); xor2 xoOC (q[5],qx[5],qx[6]); xor2 xo07 (q[6],qx[6],qx[7]);

xor2 xo08 (q[7],qx[7],qx[0]);

and8b anOl (andx,q,d); zerodet zeOl (zerox,qx); and2 an02 (zero,zerox,qx8b);

nor4 nrOl (nr01x,andx[0],andx[l],andx[2],andx[3]); nor4 nr02 (nr02x,andx[4],andx[5],andx[6],andx[7]); nand2 naOl (na01x,nr01x,nr02x);

or2 orOl (or01x,zero,na01x);

and2 an03 (an02x,or01x,ena); dflr dflO (cnax„an02x,ckb,rb);

and2 an04 (ckx,ck,cnax);

inv ivOl (ckb,ck); inv iv02 (rb.rst);

cndmoudle

/ / module or2 (x,yl,y2);

input yl,y2;

output x;

nor2 nrOl (nr01x,yl,y2);

inv ivOl (x,nr01x);

cndmodulc

In order to compare "q[*]n and "dl*]", we employ XOR2 gates.

- 3 1 -

4.3. COUNTER

Ripple counter The 5-bit ripple counter consists of five D flip-flops. The output of the D flip-flop is fed into "elk" input of the higher-bit D flip-flop. RCNT5B is a five bit ripple counter, which consists of five DFFR's.

module rcnt5b (q,ck,rbar);

input ck,rbar;

output [4:0] q;

dffr dfOO ( q[0], dO, dO, ck, rbar);

dffr dfOl ( q[l], dl , dO, dO, rbar);

dffr df02 ( q[2], d2, dO, dl, rbar);

dffr df03 ( q[3], d3, dO, d2, rbar);

dffr df04 ( q[4], d4, dO, d3, rbar);

endmodule

The ripple counter has a trouble associated with gate delay. The gate delay effect

is prominent when the output changes from 5'hOf to 5'hlO.

Synchronous counter The synchronous counter overcomes the gate delay problem.

Unless yo do have a special reason or justification for a particular application, it is

recommended to use a synchronous counter instead of a ripple counter. SCNT5B

is a five bit synchronous counter, which consists of five JKFF's and and gates.

module scnt5b (q,ck,sbar,rbar,te);

input ck,sbar,rbar;

input te;//toggle enable

output [4:0] q;

- 3 2 -

jkff jkOO (q[0]„te,te,ck,sbar,rbar); and2 anOO (tel,te,q[0]); jkfF jkOl (q[l]„tel,teL,ck,sbar,rbar);

and3 anOl (te?.te,q[0],q[l]);

jkff jk02 (q[2]„te2,tc2,ck,sbar,rbar);

and4 an02 (tc3,te,q[0],q[l],q[2]); jkffjk03 (q[3]„tc3,tc3,ck,sbar,rbar);

and5 an03 (te4,te,q[0),q[l],q[2],q[3]);

jkff jk04 (q[4]„te4,te4,ck,sbar,rbar);

endmodule

While SCNT5B counts "up wards", the DNCNT5B counts "down wards". Exam­ining toggle conditions for JKFF's, you can find exact differences between SCNT5B and DNCNT5B.

module dncnt5b (q,cb,ck,sbar,rbar,te);

input ck,sbar,rbar;

input te;//toggle enable

output [4:0] q;

output cb;//borrow

wire [4:0] qb;

wire te5;

assign cb=te5;

jkffjkOO(q[0],qb[0],te,te,ck,sbar,rbar);

and2 anOO (te00,te,qb[0]);

jkffjk01(q[l],qb[l],te00,te00,ck,sbar,rbar);

and3 auOl (te01,te,qb[0],qb[l]);

jkff jk02 (q[2],qb[2],te01,te01,ck,sbar,rbar);

and4 an02 (te02,te,qb[0],qb[l],qb[2]);

- 3 3 -

jkff jk03 (q[3],qb[3],te02,te02,ck,sbar,rbar);

and5 an03 (te03,te,qb[0],qb[l],qb[2],qb[3]);

jkff jk04 (q[4],qb[4],te03,te03,ck,sbar,rbar);

and6 an04 (te5,te,qb[0],qb[l],qb[2],qb[3],qb[4]);

endmodule

4.4. EXERCISE

1) 4-inp»t AND Apply NAND2 and NOR2 to implement AND4. The I/O speci­fications are shown below:

module and4 (x,yl,y2,y3,y4); input yl,y2,y3,y4; output x; endmodule

2) 5-input AND Apply NAND2, NAND3, and NOR2 to implement AND5. The

I/O specifications are shown below:

module and5 (x,yl,y2,y3,y4,y5);

input yl,y2,y3,y4,y5;

output x;

endmoule

- 3 4 -

.')) Up/down counter Merging SCNT5B and DNCNT5B together, you can build an up/down counter, UDCNT5B. UDCNT5B is a part of the LIFOADDIt, and LIF032W appearing in Chapter 5. UDCNT5B consists of JKFF, MUX, and subsidiary AND gates. When "up" is .true., the counter gets increment by one with "ck(u)"; when "up" is -false., the counter goes down by one. The I/O specifications are shown below:

module udcnt5b (q,cb,ck,up,sbar,rbar,te);

input ck,sbar,rbar;

input te;//toggle enable

input up;//count-up when .true.

output [4:0] q;

output cb;//carry or borrow

cndmodulc

4) DS-DK handshake sequence

Implement a DS-DK handshake circuit block with a pair of SEQCTRLs. The

sequencers operate with independent clock frequencies, "ds", "dk", and "rst" are

global signals for this circuit block. You can count the number of DS-DK handshake

with SCNT5B. It is a nice idea to include a function to set the number of DS-DK

handshakes. The signal's specifications are described below:

module dsdk_sync;

reg ckl;//c!ock for master sequencer

reg ck2;//clock for slave sequencer

reg rst;//system reset

reg start;//start signal for master sequencer

- 3 5 -

reg [4:0] qp;//preset counter wire ds;//data sync from master sequencer wire dk;//data acknowledge from slave sequencer wire [7:0] ql;//output of master sequencer wire [7:0] q2;//output of slave sequencer supplyO vss;//0 V power rail

supplyl vdd;//5 V power rail

wire [4:0] qc;//word counter endmodule

5. Storage elements

5.1. REGISTER LATCH

An eight-bit register latch is described in terms of DFFR. LATCH8B is applied for an accumulator and an instruction register of the RISC computer appearing in Chapter 6. The HDL module LATCH8B is described below:

module Iatch8b (q,d,ck,ena,rst);

input [7:0] d;

input ck,rst;

input ena;//latch enable

output [7:0] q;

dffr dfOl (q[0]„d[0],eck,rb);

dffr df02 (q[l]„d[l],eck,rb);

dffr df03 (q[2]„d[2],eck,rb);

dffr df04 (q[3]„d[3],eck,rb);

dffr df05 (q[4]„d[4],eck,rb);

- 3 6 -

dffr df06 (q[5]„d[5],eck,rb); dffr df07 (q[6]„d[6],eck,rb):

dffr df08 (q[7]„d[7],eck,rb)i

inv ivOl (rb,rst);

and2 anOl (eck,ck,ena);

ctidmodulc

5.2. RANDOM ACCESS MEMORY, RAM

An eight-word block of a random access memory is shown below. The HDL

module name is MEM8W. WORD8B is the one-word block of the random access

memory. Figure 7 shows a basic memory cell schematic. The node CO is a capaci-

tive storage. The input stage consists of two switches; one is to select this memory

cell and another is to write to the memory cell. The output stage consists of three

transistors. The transistor NOOD is to regenerate the stored signal. NOOF and

NOOE arc to led the signal on the data bus.

module memSw (do,di,mr,mw,addr,sel);

input [7:0] di;

input mr,mw,sel;

input (2:0] addr;

output [7:0] do;

wire [7:0] selx;

and2 anOl (mrx,mr,sel);

and2 an02 (mwx,mw,sel);

dcc328 deOl (selx,addr);

word8b woO (do,di,mrx,mwx,selx[0]);

word8b wol (do,di,mrx,mwx,selx[l]);

- 3 7 -

word8b wo2 (do,di,mrx,mwx,selx[2])

word8b wo3 (do,di,mrx,mwx,selx[3])

word8b wo4 (do,di,mrx,mwx,selx[4j)

word8b wo5 (do,di,mrx,mwx,selx[5])

word8b wo6 (do,dt,mrx,mwx,se]x[6])

word8b wo7 (do,di,mrx,mwx,se]x[7])

endmodule

/ / module wordSb (do^i^nrjinw^el);

input [7:0] di;

input mr,mw,sel;

output [7:0] do;

supplyO vss;

trireg c0,cl,c'2,c3,c4,c5,c6,c7; nmos # 1 m

nmos | 1 n

nmos # 1 n

nmos # l n

nmos # l n ,

nmos # 1 n

nmos # 1 n

nmos # 1 n

nmos # 1 n;

nmos # 1 ni

nmos # 1 ni

nmos # 1 n

nmos # 1 n

nmos # 1 n

nmos # 1 n

nmos # 1 ni

Ob (bO,di[0],sel);

0c (c0,b0,mw);

lb (bl,di[l],sel);

lc (cl,bl,mw);

2b (b2,di[2],sel);

2c (c2,b2,mw);

3b (b3,di[3l,sel);

3c (c3,b3,mw);

4b (b4,di[4],sel);

4c (c4,b4,mw);

5b (b5,di[5],sel);

:5c (c5,b5,mw);

6b (b6,di(6],sel);

6c (c6,b6,mw);

7b (b7,di[7],sel);

7c (c7,b7,nvw);

nmos # 1 noOd (do[0],dO,sel);

nmos # 1 noOe (dO,cO,mr);

nmos # 1 noOf (eO,vss,cO);

nmos # 1 nold (do[l],dl,sel);

nmos # 1 nole (dl,cl,mr);

nmos # 1 nolf (el,vss,cl);

nmos # 1 no2d (do[2],d2,sel);

nmos # 1 no2e (d2,e2,mr);

nmos #1 no2f (e2,vss,c2);

nmos # 1 no3d (do[3],d3,sel);

nmos # 1 no3e (d3,e3,mr);

nmos # 1 no3f (e3,vss,c3);

nmos # 1 no4d (do[4],d4,sel);

nmos # 1 no4e (d4,c4,mr);

nmos # 1 no4f (e4,vss,c4);

nmos # 1 no5d (do[5],d5,sel);

nmos #1 no5e (d5,e5,mr);

nmos # 1 no5f (e5,vss,c5);

nmos # 1 no6d (do[6],d6,seJ);

nmos # 1 no6e (dG,e6,mr);

nmos # 1 no6f (e6,vss,c6);

nmos #1 no7d (do[7],d7,sel);

nmos # 1 no7e (d7,e7,mr);

nmos # 1 no7f (e7,vss,c7);

endmodule

5.3. FlRST-IN FIRST-OUT MEMORY, FIFO

FIFO stands for First-in First-out memory. Data are read out in exactly same order which are written into. FIFO is used as an elastic buffer to rectify data transfer rate. The address control circuit, FIFOADDR, will be described as:

module fifoaddr(addr, mr,mw,empty,full, write,read,syncs,reset,cs);

output [4:0] addr;

output mr,mw,empty,full;

input write,read,syncs,reset,cs;

supplyl vdd;

wire [4:0] qr,qw,qwx;

wire ter,tew;

wire eqb,zcroi>;

assign ter=cqb;

assign tuw=zerob;

and2 anOl (sync,syncs,cs);

and2 an02 (full,write,zero);

and2 an03 (empty,read,eq);

nand2 naOl (ckr,sync,read);

nand2 na02 (ckw,sync,write);

scnt5b scOl (qr,ckr,vdd,rb,ter);//for read pointer

scnt5b sc02 (qw,ckw,vdd,rb,tew);//for write pointer

inv5b ivOl (qwx,qw);

add5b adOl (zero,qr,qwx);

dffr dfOl (df01q,df01qb,zero,syncb,rbw);

inv iv02 (zerob,zero);

comp5b coOI (eq,qr,qw);

dffr df02 (df02q,df02qb,eq,sync,rbr);

inv iv03 (eqb,eq);

- 4 0 -

inv iv04 (rb,resct);

inv iv05 (syncb.sync);

nor2 nrOl (rbw,read,reset);

nor2 nr02 (rbr,write,reset);

nor2 nr03 (mr,ckr,df02q);

nor2 nrQ4 (mw,ckw,df01q);

mux5b rauOl (addr,qw,qr,write);

endmodule

mux5b muOI (addr,qw,qr,WTite);

/ / module inv5b (x,y);

input [4:0] y;

output [4:0] x;

inv ivOO (x[0],y[0]);

inv ivOl (x[l],y[l]);

inv iv02 (x[2],y[2]);

inv iv03 (x[3],y[3]);

inv iv04 (x[4],y[4]);

endmodule

/ / module add5b (zero,a,b);

input [4:0] a,b;

output zero;

wire [4:0] co,s;

supplyO vss;

fadder faOO (s[0],co[0],a[0],b[0],vss);

fadder faOl (s[l],co[l],a[l],b[l],co[0])

fadder fa02 (s[2],co[2],a[2],b[2],co[l]);

fadder fa03 (s[3],co[3],a[3],b[3],co[2J);

fadder fa04 (s[4],co[4],a[4],b[4],co[3j);

nor5 nrOl (zero,s[0],s[lj,s[2],s[3],s[4]);

endmodule

/ / module nor5 (x,yl,y2,y3,y4,y5); input yl,y2,y3,y4,y5; output x; nor2 nrOl (nr01x,yl,y2); nor3 nr02 (nr02x,y3,y4,y5); and2 anOl (x,nr01x,nr02x); endmodule

5.4. LAST-IN FIRST-OUT MEMORY, STACK

We are familiar with Stack because HP's hand-carried calculator adopts a Stack oriented arithmetic algorithm, where PUSH and POP are relevant instruc­tions. The stack is commonly used as a part of a mini- ( micro -) computer. The contents of the register hie are temporarily written into the stack at the timing of "interrupt". When the computer goes back to the condition before the interrupt, the contents of the stack are read back to the register file. The address generation circuit block for Stack is shown below:

module lifoaddr (addr,mr,mw,empty,full,push,pop,syncs,reset,cs); input push,pop; input syncs,reset,cs;

output full,empty;

output [4:0] addr; output mr,nw; supply 1 vdd;

and2 anOO (sync,syncs,cs);

- 4 2 -

udcnt5b udOl (addr,cb,ckx,push,vdd,rb,iv08x);

and2 anOl (empy,cb,pop);

and2 an02 (fuly,cb,push);

dffr dfOl (empty,,cmpy,syncx,rb);

dffr df02 (full„fuly,syncx,rb);

dffr df03 (teb,te,or01x,syncbx,rbx);

inv iv02 (syncb,sync);

inv iv03 (rb,rcset);

and2 an03 (mw,push,syncx);

and2 an04 (mr,pop,syncx);

and2 an05 (an05x,empty,push);

and2 an06 (an06x,full,pop);

and2 an07 (syncx,sync,te);

and2 an08 (popx,pop,te);

and2 an09 (pushx,push,tc);

dffr df04 (pushxx„pushx,syncb,pushx);

nor3 nr03 (rbx,an05x,an06x,reset);

or2 orOl (or01x,empty,full);

or2 or02 (ckx,popx,pushxx);

inv iv08 (iv08x,or01x);

inv iv09 (syncbx,syncx);

endmodule

5.5. PROGRAMMABLE LOGIC ARRAY

PLA stands for programmable logic array. A theoretical basis of PLA is that

any combinational logic can be described in terms of sum of products. The PLA

module listed below contains a program code for a full adder. The Boolean expres­

sion of the full adder was discussed in Chapter 2. The basic implementation of the

- 4 3 -

full adder was described in Chapter 3. This time we try to make the full adder

function in terms of PLA. Figure 8 shows a complete schematic of LADDERS cir­

cuit block. The entire PLA block consists of eight circuit blocks of LADDERS.

The input signals, IN [3:0], are doubled in width together with their negated sig­

nals. These signals, INX[7:0] are fed into LADDRE8, which is actually an nMOS

vertical chain to implement "and" function for INX[7:0]. At the output node of

LADDERS there located a pull-up transistor. The pull-up transistor is actually a pMOS transistor with small drivability, i.e. with small W/L ratio. The outputs

from LADDER8s, OUT[7:0], are fed into NAND4 to implement, "or" function for

OUT[7:0]. The 8-bit vectors PGO, PG1, PG2, PG3, PG4, PG5, PG6 and PG7

determine function of the PLA as a whole. Unless P C s asserts to be .true., the

nMOS transistors designated by the PCs are always on; they have nothing to do

with INX[7:0]. A lengthy description for the PLA circuit block is shown below:

module pla (q,in);

input [3:0] in;

output [1:0] q;

reg [7:0] Pg0,pgl,pg2,pg3,pg4,pg5,pg6,pg7;

wire [7:0] inx,out;

assign inx[0]=in[0];

assign inx[l]=in[lj;

assign inx[2]=in[2];

assign inx[3]=in[3j;

inv ivOO (inx[4),in[0]);

inv ivOl (inx[5],in[l]);

inv iv02 (inx[6],in[2j);

inv iv03 (inx[7],in[3]);

ladder8 laOO (out[0],inx,pg0);

ladder8 laOl (out[l],inx,pgl);

- 4 4 -

laddcrS la02 (out[2],inx,pg2);

ladders la03 (out[3],inx,pg3);

ladder8 la04 (out[4],inx,pg4);

Iaddcr8 la05 (out[5],inx,pg5);

ladderS la06 (out[6],inx,pg6);

laddcrS la07 (out[7],inx,pg7);

nand4 naOO (q[0],out[0],out[l],out[2],out[3]);

nand4 naOl (q[l],out[4],out[5],out[6],out[7]);

initial//program for full adder

begin

pg0=8'60H0-0001;

pgL=8'60011-0100;

pg2=8'60101.0010;

pg3=8'60000.0111;

pg4=S'50000-OUO;

pg5=8' 40000.0101;

pg6=8'60000.0011;

pg7=8 '6Hl l . l l l l ;

end

//assign ci=in[0];

//assign a=in[l];

//assign b=in[2];

//assign co=q[l];

//assign s=q[0];

endmodule

/ / module ladder8 (out,in,prg);

input [7:0] in,prg;

output out;

supplyO vss;

- 4 5 -

puilup ouOl (out);

pullup puOO (nmOg);

puilup puOl (nmlg);

pullup pu02 (nm2g);

puilup pu03 (nm3g);

pullup pu04 (nm4g);

pullup pu05 (nm5g);

pullup pu06 (nm6g);

pullup pu07 (nm7g);

nmos # 1 nmO (out,nmOs,nmOg);

nmos # 1 nml (nmOs,nmls,nmlg);

nmos #1 nm2 (nmls,nm2s,nm2g);

nmos # 1 nm3 (nm2s,nm3s,nm3g);

nmos # 1 nm4 (nm3s,nm4s,nm4g);

nmos # 1 nm5 (nm4s,nm5s,nm5g);

nmos # 1 nm6 (nm5s,nm6s,nmbg);

ntnos #1 nm7 (nm6s,vss,nm7g);

nmos # 1 nmOO (nmOg,in[0],prg[0]);

ntnos # 1 nmOl (nmlg,in[l],prg[l]);

nmos #1 nm02 (nm'2g,in[2],prg[2]);

nmos # 1 nm03 (nrn3g,in[3],prg[3]);

nmos # 1 nm04 (nm4g,in[4],prg[4j);

nmos # 1 nm05 (nm5g,in[5],prg[5]);

nmos # 1 nm06 (nm6g,in[6],prg[6j);

nmos # 1 nm07 (nm7g,in[7],prg[7]);

endmodule

5.6. EXERCISE

1) MEM32W, 32-word random access memory block MEM32W is a 32-word ran­

dom access memory. MEM32W consists of MEM8W, DEC224, TRINV and sub­

sidiary gates. The I/O specifications are described below:

module mem32w (do,di,mr,mw,addr,cs);

input [7:0] di;

input mr,mw;

input cs;

input [4:0] addr;

output [7:0] do;

endmodule

2) FIFQ32W, 32-word fifo memory block Describe a 32-word fifo memory. FIF032W|

consists of FIFOADDR, and MEM32W. The I/O specifications are defined below.

module fifo32w(do, di, empty, full, write, read, sync, reset, cs);

input write, read, sync, reset, cs;

input [7:0] di;

output empty, full;

output [7:0] do;

endmoudle

- 4 7 -

3) LIF032W, 32-word stack block Describe a 32-word lifo memory. LIF032W consists of LIFOADDR and MEM32W. The I/O specifications are defined below.

module lifo32w (do, di, empty, full, push, pop, sync, reset, cs); input push, pop, sync, reset, cs; input [7:0] di; output [7:0] do; output empty, full; endmoudle

6. Design of RISC computer

6.1. SPECIFICATION OF THE MODEL COMPUTER

Address space The data word of the machine is 8-bit wide. The available address space is from 0 to 31.

Data presentation Numerical value is presented as a binary code. There is no a priori definition of a negative value.

Instruction code The instruction code is subdivided into 3 bits of operation code and 5 bits of address field ( operand ). \

Accumulator The accumulator is an 8-bit register;

Instructions The operation codes are listed in Table 7. There are three flow control signals; HALT, SKIPJF JERO, and JUMP. ADD, AND, and XOR are implemented as functions of ALU. LOAD and STORE are for data transfer between the random access mememory and the accumulator.

- 4 8 -

Operation sequence An operation sequence for a single instruction is subdivided into 8 steps;

1. For a half clock period from fetch(u): address setup

Address source is the program counter.

2. For a half clock period from clk2 * fetch * clk(u): Instruction fetch

3. For a half clock period from fetch * clkJ2(d): Instruction load

4. For a half clock period from fetch * elk3. * clk(u): Idle

5. For a half clock period from fetch(d): Address setup Address source is the instruction register.

6. For a half clock period from fetch * clkJl * clk(u): Operand fetch

7. For a half clock period from fetch * clkJl(d): ALU operation

8. For a half clock period from fetch * clkJ2 * clk(u): Store result

Figure 9 shows the timing diagram for the clock signals.

6.2. DESIGN OF RISC COMPUTER

Instruction register The instruction register is an 8-bit latch; LATCH8B is applied

for the instruction register.

Instruction decoder The instruction decoder acquires operational code form the

instruction register to interpret it and to issues load.accum ( load accumulator

), menu-tad ( memory read ), memjor ( memory write ), incite ( increment

- 4 9 -

program counter ), loadjpc (load program counter ), and loadJr (load instruction register ). The conditions to set or reset these signals are tabulated in Table 8.

module decoder (loadjaccum,memj,ead,memju7r,inc-pc,load-pc,

/oadJrjhaltjOpcode.fetchjZero.cll^c/fc^rst);

input fetch,zero,clk,c/fc-2;

input rst;

input [7:0] opcode;//decoded opcode

output loadjaccum,memjread,memjwr,inc-pc,load4)c,loadjr; output halt;

supply 1 vdd;

wire [7:0] d,q;

inv ivOl (fetchbar/etdi);

inv iv02 (rstbar ;.);

inv iv03 (clk2 ,ctk2); inv iv04 (clkb,clk);

nor2 nr30 (rst3,rst,fetch);

and2 an20 (rstl,rstbar,fetch);

/ / l ) load accumulator

dffr dflO (/oa<Laccum„df21y,clk2b,rst3);

/ /2) memory read

dffr d(20 (df20x„fetch,clk,rstl);

nor4 nr20 (nr20x,opcode[2],opcode[3],opcode[4],opcode[5]);

inv iv20 (iv20x,nr20x);

and2 an21 (df21y,iv20x,fetchbar);

dffr df21 (df21x„df21y,clk,rst3);

or2 or2l (memj-eoJ,df20x,df21x);

/ /3) memory write

and3 an30 (d(30y,fetchbar,clk2b,opcode[6]);

- 5 0 -

dffr df30 (mem _u>r „df30y,clk,rst3); / /4) increment program counter

and3 an40 (an40x,clkb,c/fc.2)fctchbar);

and3 an42 (df40y,fetchbar,clk2b,opcode[7));

dffr df40 (df40x„df40y,clk,rst3);

and3 an43 (an43x,fetchbar,zero,opcode[l]);

dffr df41 (df41x„an43x,clk2b,rst3);

nor3 nr40 (nr40x,an40x,df40x,df41x);

inv iv40 (jncj>c,nr40x); / /5) load program counter

and2 an50 (df50y,fetchbar,opcode[7J); dffr df50(/oa<<4)c„df50y,clk2b,rst3);

/ /6) load instruction register dffr df60 (/oarfjr„fetch,clk2b,rstl); / /7) halt

and2 an70 (df70y,fetchbar,opcode[0]); dffr dfTO (halt„df70y,clk,rstbar); endmoduie

Program counter The program counter looks a little bit complicated compared with SCNT5B and or RCNT5B. An extra feature of the program counter is "le". When "le" is .true., nd[4:0]" is written into the program counter at the timing of "ck(u) n. The clock signal fed into the program counter is "incpc".

module pc (q,ck,d,rb,le);

output [4:0] q;

input ck,rb;

input le;//load enable

- 5 1 -

input [4:0] d;

wire [4:0] db;

supplyl sb;//vdd

inv ivOO (db[0],d[0]);

inv ivOl (db[l],d[l]) ;

inv iv02 (db[2],d[2]);

inv iv03 (db[3],d[3]);

inv iv04 (db[4],d[4]);

inv iv05 (te,le);

mux2b muOO ({te01,teOO},{d[0],db[0]},{te,te},le);

jkfFjkOO(q[0]„te01,teOO,ck,sb,rb);

and2 anOO (tcl,te,q[0]);

mux2b muOl ({tell,telO},{d[l],db[l]},{tel,tel},le);

jkffjk01(q[l]„tell,telO,ck,sb,rb);

and3 anOl (te2,te,q[0],q[l]);

mux2b mu02 ({te21,te20},{d[2],db[2]},{te2,te2},le);

jkff jk02 (q[2]„te2L,te20,ck,sb,rb);

and4 an02 (te3,te,q[0],q[l],q[2]);

mux2b mu03 ({te31,te30},{d[3],db[3]},{te3,te3},le);

jkff jk03 (q[3]„te3l,te30,ck,sb,rb);

and5 an03 (te4,te,q[0],q[l],q[2],q[3]);

mux2b mu04 ({te41,te40},{d[4],db[4]},{te4,te4},Ie);

jkff jk04 (q[4]„te4L,te40,ck,sb,rb);

endmodule

/ / module mux2b (x,inl,inO,se]);

input [1:0] inl,in0;

input sel;

output [1:0] x;

mux muOO (x[0],inl[0],inO[0],sel);

- 5 2 -

mux muOl (x[l],inl[l],inO[0],sel); endmodule

Arithmetic logical unit, ALU The arithmetic logical unit consists of ZERODET,

ADD8B, AND8B, XOR8B, and subsidiary circuit blocks. These circuit blocks are

defined in the previous Chapters. The output of the ALU block is equipped with

TRBUF8B blocks.

module alu ( alu-out, zero, opcode, data, accum, clock);

input [7:0] data, accum;

input [7:0] opcode;//decoded opcode

input clock;

output [7:0] alujmt; output zero;

wire [7:0] addx,andx,xorx;

supplyl vdd;

zerodet zeOl (zero,accum);

add8b adOl (addx„accum,data);

and8b anOl (andx,accum,data);

xor8b xoOl (xorx,accum,data);

nor4 nrOl (nr01x,opcode[0],opcode[l],opcode[6],opcode[7]);

inv ivOl (iv01x,nr01x);

trbuf8b trOl (aluj>ttt,a.ccum,\v01x);

trbufSb tr02 (a/u.x>ur,addx,opcode[2]);

trbufSb tr03 (<z/u-oai,andx,opcode[3]);

trbuf8b tr04 (a/u-0ut,xorx,opcode[4]);

trbufSb tr05 (a/«.0ut,data,opcode[5]);

endmodule

- 5 3 -

Accumulator The accumulator is a register which stores output data of the ALU.

The HDL description of the accumulator is exactly same as LATCH8B.

Clock generator The clock generator is terminated with HALT instruction. AD

external RESET activate the clock generator again. The HDL description of the

clock generator ( CLOCKS ) is shown below.

module clocks (fetch,c/A_2,clk,ck,halt,rbar);

input ck,ha)t,rbar;

output fetcb,c/A-_2,clk;

supply 1 sbar;

inv ivOl (te.halt);

jkff jkOO(clk„te,te,ck,rbar,sbar);

and2 anOO (tel,te,clk);

jkff jk01(c//;_2,qlb,tel,tel,ck,sbar,rbar);

and3 anOl (te2,te,clk,qlb);

jkff jk02 (fetch,,te2,te2,ck,sbar,rbar);

cndmodulc

6.3. ASSEMBLING THE RISC PROCESSOR

module cpu (data,mem_rea<f,meTnju>r,addr,ck,reset); input ck,reset; inout [7:0] data; output [4:0] addr;

- 5 4 -

output menuead,tncmju!r; wire [7:0] qacc,alujntt,qins,apcodc;

wire [2:0J xop;

wire [4:0] yop,qpc;

assign yop[0]=qins[0];

assign yop[l]=qins[l];

assign yop[2]=qins[2j;

assign yop[3]=qins[3j;

assign yop[4]=qins[4];

assign xop[0]=qins[5];

assign xop[l]=qins[6];

assign xop[2]=qins[7];

//clock generator

inv ivOl (rbar,reset);

clocks clOl (fetch,cM_2,clock,ck,halt,rbar);

//accumulator

latch8b laOl (qacc,a/ujoui,clock,/oaiLaccum,reset);

//Tristate buffer

nor3 nrOl (eiibbuf,77iem_read,fetch,c/ifc-2);

trbufSb trOl (data,a/u^our,enbbuf);

//instruction register

latch8b la02 (qins,data,clock,/oacfJr,reset);

//instruction decoder

dec328 decOl (opcode,xop);

decoder dec02 [loadjiccujn,memsead,mtmju>r,incjpc,load^c , loa <fjr,halt,opcode,fetch,zero,clock,c/fc_2,reset);

//arithmetic logical unit

nor3 nr02 (nr02x,clock,fetch,cU--2);

inv iv02 (ckalu,nr02x);

alu alOl (a/u-our,zero,opcode,data,qacc,ckalu);

- 5 5 -

//program counter pc pcOl (qpc,«'ncjJC,yop,rbar,/oad_pc); mux5b muOl (addr,qpc,yop,fetch); endmodule

We should remember that the primitive circuit entities we have applied to imple­ment circuit blocks for the RISC computer are pMOS, and nMOS primitives. We are very close to the actual VLSI RISC computer design.

6.4. OPERATION OF RISC COMPUTER

The test fixture in Verilog-XL is shown below. At first we load a program code with assertion of "boot". Negating "boot" and resetting the computer, we can execute the program.

module testj;puO; reg ck,reset,boot;

reg [7:0] rom; wire [4:0] addr; wire [7:0] data,do,di; supplyl vdd;

cpu cOl (data,mem-rea<f,memjwr,addr,ck,reset); mem32w mOl (do,data,men)_rea</,me77jj£?r,addr,vdd); trbufSb trOl (data,do,booty);

trbufSb tr02 (data,rom,bootx); and2 anOl (bootx,boot,memj-ea</); and2 an02 (booty,bootb,mem _read); inv ivOl (bootb.boot); initial

- 5 6 -

begin

ck=0;

reset=1;

boot=l;

rom=8'b000J)000;//halt

#25 reset=0;

//program load

©(posedge memjread) #10 rom=8'bl01.00000;//load

©(posedge memjread) #10 rom=8'bl01-10000;//data[0] load

©(posedge memjread) #10 rom=8'bll0.0000;//store

©(posedge memjread) #10 rom=8'bl01-00000;//load

©(posedge memjread) #10 rom=8'b010-10001;//data[l] add

©(posedge memjread) #10 rom=8'bll0_0001;//store

©(posedge memjread) #10 rom=8'bl01.00000;//load

©(posedge memjread) #10 rom=8'bll0-10010;//data[2] store

©(posedge memjread) #10 rom=8'bll0.0010;//store

©(posedge memjread) #10 rom=8'bl01-00000;//load

©(posedge memjread) #10 rom=8'b000.0000;//data[3] halt

©(posedge memjread) #10 rom=8'bll0.0011,7/store

©(posedge memjread) #10 rom=8'bl01-00000;//load

©(posedge memjread) #10 rom=8'b0(XLlllll;//data[16]....a=31

©(posedge memj-ead) #10 rom=8'bll0.10000;//store

©(posedge memjread) #10 rom=8'bl01.00000;//load

©(posedge memjread) #10 rom=8'b000-0001;//daU[16]....b=l

©(posedge memjread) #10 rom=8'bll0_10001;//store

©(posedge memjread) #10 rom=8'b000.0000;//halt

#1000 reset=l;

#100 reset=0;boot=0;

//execution

#1000 reset=l;

- 5 7 -

#100 Sstop;

end

always #20 ck=~ck;

endmodule

where "<§(posedge memj-ead)" is to specify the timing of mem_rea<f(u). "always #20" is understood as to execute a specified operation for each 20 ns. "ck=~ck" is to toggle the signal "ck". Figure 10 shows the timing diagram for the execution phase.

6.5. EXERCISE

1) Subtraction

Code a subtraction program, where included are LOAD, XOR, ADD, STORE and

HALT instructions. You should note that:

{a.xor.8'hff).add.8'h0l -» - a (6.1)

where a is an arbitrary 8-bit number. Figure 11 shows the timing diagram for the

execution phase.

2) Loop operation

Code a loop operation program, where included are LOAD, ADD, SKIP IF ZERO,

JMP, and HALT instructions. Figure 12 shows the timing diagram for the execu­

tion phase.

3) OR operation

Code a OR operation program, where included are LOAD, XOR, STORE, AND,

- 5 8 -

and HALT instructions. You should note that

(a.xor.S'hff) ->5 (6.2)

and

a.and.b —* a.or.b (6.3)

Figure 13 shows the timing diagram for the execution phase.

- 5 9 -

7. Summary A practice of a digital circuit design was presented with special emphasis on

the HDL description. A complicated digital circuit such as a computer block can be well described in a hierarchy fashion. We put little emphasis on the schematic oriented design. Students should comprehend themselves about complementary nature between design methodologies based on HDL and schematic entry. In order to complete the VLSI design of the logic circuit, we must go through a layout design and a post-layout simulation where included are examination and optimiza­tion of wiring delays and/or fan-out capabilities related with the wiring and/or gate capacitance. The digital circuit issues related with a communication and/or information theory were totally skipped to postpone them for an advance course of the lecture series. The test fixtures to examine HDL modules appeared in this text are available on request.

ACKNOWLEDGEMENTS

We would like to appreciate encouragement of Prof's Ii. Sugawara, Y. Kimuara, S. Iwata, and Y.Watase for their providing us a chance to complete the lecture note. Mr. Tairadate from the Graduate University of Advanced Study, Mr. Matsushita from Tokyo Metropolitan University, Mr. Abe from Tsukuba University, and Mr. Natori from Chuoh University are appreciated for their patience during the lecture course and careful reading of this lecture note.

- 6 0 -

APPENDIX :Possible implementation for exercises 2.6.1) 3-input NAND

module nand3 (x,y2,yl,y0); input y0,yl,y2; output x; supplyl vdd; supplyO vss; pinos # 3 mOl (x,vdd,yO); pmos # 3 m02 (x,vdd,yl); pmos # 3 m03 (x,vdd,y2); nmos # 1 m04 (x,m05d,y0); nmos # 1 m05 (m05d,m06d,yl); nmos # 1 m06 (m06d,vss,y2); cndmodule

2.6.2) 4 input NAND

module nand4 (x,y3,y2,yl,y0); input y0,yl,y2,y3; output x; supplyl vdd; supplyO vss; pmos #4 mOl (x,vdd,yO); pmos #4 m02 (x,vdd,yl); pmos #4 m03 (x,vdd,y2); pmos #4 m04 (x,vdd,y3); nmos # 1 m05 (x,m05d,y0); nmos # 1 m06 (m05d,m06d,yl); nmos # 1 m07 (m06d,m07d,y2); nmos # 1 m08 (m07d,vss,y3); endmodule

2.6.3) 4-input NOR

- 6 1 -

module nor4 (x,y3,y2,yl,y0); input y0,yl,y2,y3; output x; supplyl vdd; supplyO vss; pmos # 1 mOl (m01d,vdd,y0); pmos # 1 m02 (m02d,m01d,yl); pmos # 1 m03 (m03d,m02d,y2); pmos # 1 m04 (x,m03d,y3); nmos #4 m05 (x,vss,yO); nmos #4 m06 (x,vss,yl); mnos #4 m07 (x,vss,y2); nmos #4 m08 (x,vss,y3); endmodule

2.6.4) 8-bit AND arithmetic block

module and8b (c,a,b); input [7:0] a,b; output [7:0] c; wire [7:0] na; nand2 naOO (na[0],a[0],b[0]); nand2 naOl (na[l],a[l],b[l]); nand2 na02 (na[2],a[2],b[2]); nand2 na03 (na[3],a[3],b[3]); nand2 na04 (na[4],a[4],b[4]); nand2 na05 (na[5],a[5],b[5]); nand2 na06 (na[6],a[6],b[6]); nand2 na07 (na[7],a[7],b[7]); inv ivOO (c[0],na[0]); inv ivOl (c[l],na[lj); inv iv02 (c[2],na[2]); inv iv03 (c[3],na[3]); inv iv04 (c[4],na[4]); inv iv05 (c[5],na[5]); inv iv06 (c[6],na[6]); inv iv07 (c[7],na[7]); endmodule

- 6 2 -

2.6.5) 8-bit XOR arithmetic block

module xor8b (c,a,b); input [7:0] a,b; output [7:0] c; xor2 xOO (c[0],a[0],b[0j) xor2 xOl (c[l],a[l],b[lj) xor2 x02 (c[2j,a[2],b[2]); xor2 x03 (c[3],a[3],b[3j)i xor2 x04 (c[4],a[4],b[4]); xor2 x05 (c[5],a[5],b[5]); xor2 x06 (c[6],a[6],b[6])i xor2 x07 (c[7],a[7],b[7]); cndmodulc

2.6.6) 8-bit tri-state buffer block

module trbuf8b(x,y,enb); input [7:0] y; input enb; output [7:0] x; wire [7:0] z; trinv trOO (x[0],z[0],enb); trinv trOl (x[l],z[lj,enb); trinv tr02 (x[2],z[2],enb); trinv tr03 (x[3],z[3],enb); trinv tr04 (x[4],z[4],enb); trinv tr05 (x[5],z[5],enb); trinv tr06 (x[6],z[6j,enb); trinv tr07 (x[7],z[7],enb); inv ivOO (z[0],y[0]); inv ivOl (z[l],y[l]); inv iv02 (z[2],y[2]); inv iv03 (z[3],y[3]); inv iv04 (z[4],y[4]);

- 6 3 -

inv iv05 (z[5],y[5]): inv iv06 (z[6],y[6]); inv iv07 (z[7],y[7]);

endmodule

3.7.1) 8-bit adder

module add8b (c, ov, a, b);//c=a+b input [7:0] a,b; output [7:0] c; output ov;//overflow bit supplyO vss; wire ov,co8; assign ov=c08; fadder faOO (c[0], col, a[0], b[0], vss); fadder faOl (c[lj, co2, a[l], b[l], col); fadder fa02 (c[2), co3, a[2], b[2], co2); fadder fa03 (c[3], co4, a[3], b[3], co3); fadder fa04 (c[4], co5, a[4], b[4], co4); fadder fa05 (c[5], co6, a[5], b[5], co5); fadder fa06 (c[6], co7, a[6], b[6], co6); fadder fa07 (c[7], co8, a[7], b[7], co7); endmodule

3.7.1X) 8-bit subtracter

module sub8b (c, a, b);//c=a-b input [7:0] a,b; output [7:0] c; supply 1 vdd; wire [7:0] bx; xorSb xoOl (bx,b,{vdd,vdd,vdd,vdd,vdd,vdd,vdd,vdd}); fadder faOO (c[0], col, a[0], bx[0], vdd); fadder faOl (c[l), co2, a[l], bx[l], col); fadder fa02 (c[2], co3, a[2], bx[2], co2); fadder fa03 (c[3], co4, a[3], bx[3], co3);

- 6 4 -

fadder fa04 (c[4|, co5, a[4], bx[4], co4); fadder fa05 (c(5j, co6, a[5], bx[5], co5); fadder fa06 (c[6], co7, a[6], bx[6], co6); fadder fa07 (c[7], co8, a[7], bx[7], o>7); cndmodulc

3.7.2) 5-bit multiplexor

module mux5b (x,inl,in0,sel); input [4:0] inl,in0; input sel; output [4:0] x; mux muOO (x[0],ini[0],inO[0],sel); mux muOl (x[l],inl[l],inO[l],scl); mux mu02 (x[2],inl[2],in0[2],sel); mux mu03 (x[3j,inl[3],in0|3],sel); mux mu04 (x[4],inl[4],in0[4],sel); endmodule

3.7.3) Generation of 8-bit negative number

module neg8b (x,y); input [7:0] y; output [7:0] x; wire [7:0] xOlx; supplyl vdd; suppIyO vss; inv8b ivOl (xOlx.y); add8b aOl (XjOV^OlxJvsSjVsSjVss.vss^ss^ss.vsSjVdd}); endmodule / / module inv8b(x,y); input [7:0] y; output [7:0] x; inv ivOO (x[0],y[0]); i. v ivOl (x[l),y[l]);

- 6 5 -

inv iv02 (x[2],y[2]); inv iv03 (x[3],y[3J); inv iv04 (x[4J,y[4J); inv iv05 (x[5],y[5]); inv iv06 (x[6j,y[6]); inv iv07 (x[7],y[7]); endmodule

3.7.4) Zero detector circuit

module zcrodct (zcro,d); input [7:0] d; output zero; nor2 nrOl (nr0lx,d[0],d[l]); nor2 nr02 (nr02x,d[2],d[3]); nor2 nr03 (nr03x,d[4],d[5]); nor2 nr04 (nr04x,d[6],d[7]); and4 anOl (zero.nr01x,nr02x,nr03x,nr04x); cndmodule

3.7.5) 2-to-4 decoder

module dec224 (x,y); input [1:0] y; output [3:0] x; wire [1:0] yb; inv ivOO (yb[0],y[0]); inv ivOl (yb[l],y[l]) ;

and2 p.nOO (x[0],yb[0],yb[l]); and2 a n d (x[l],y[0],yb[l]); and2 an02 (x[2],yb[0],y[l]); and2 an03 (x[3],y[0],y[l]); endmodule

4.4.1) 4-input AND

- 6 6 -

module and4 (x,yl,y2,y3,y4); input yl,y2,y3,y4; output x; nand2 naOl (na01x,yl,y2); nand2 na02 (na02x,y3,y4); nor2 niOl (x,na0lx,na02x); endmoudle

4.4.2) 5-input AND

module and5 (x,yl,y2,y3,y4,y5); input yl,y2,y3,y4,y5; output x; nand2 naOl (na01x,yl,y2); nand3 na02 (na02x,y3,y4,y5); nor2 nrOl (x,na0lx,na02x); cndmoudlc

4.4.3) Up/down counter

module udcntSb (q,cb,ck,up,sbar,rbar,te); input ck,sbar,rbar; input te;//toggle enable input np;//count-up when .true. output [4:0] q; output cb;//carry or borrow wire [4:0] qb; wire te5; assign cb=te5; j kff jk00( q [0] ,qb(0] ,te,te,ck,sbar,rbar); and2 anOO (te00,te,qb[0]); and2 an 10 (tel0,te,q[0]); mux muOO (tel,tel0,te00,up); jkffik01(q[l],qb[l],tel,tel,ck,sbar,rbar); and3 a n d (tc01,te,qb[0],qb[l]);

- 6 7 -

and3aiill (tell,te,q[0],q[l]); mux muOl (te2,tell,te01,up); jkff jk02 (q[2],qb[2j,te2,te2,ck,sbar,rbar); and4 an02 (te02,te,qb(0],qb[l],qb[2]); and4 anl2 (tel2,te,q[0],q[l],q[2]); mux mu02 (te3,tcl2,te02,up); jkff jk03 (q[3],qb(3],te3,te3,ck,sbar,rbar); and5 an03 (te03,te,qb[0],qb[l],qb[2],qb[3]); and5 anl3 (tel3,te,q[0],q[l],q[2],q[3]); mux mu03 (te4,tel3,te03,up); jkff jk04 (q[4],qb[4],te4,te4,ck,sbar,rbar); and6 an04 (te04,te,qb[0],qb[l],qb[2],qb[3],qb[4]); and6 anl4 (tel4,te,q[0],q[l],q[2],q[3],q[4]); mux mu04 (te5,tel4,te04,up); endmodule / / module and6 (x,yl,y2,y3,y4,y5,y6); input yl,y2,y3,y4,y5,y6; output x; nand2 naOl (na01x,yl,y2); nand2 na02 (na02x,y3,y4); nand2 na03 (na03x,y5,y6); nor3 nrOl (x,na01x,na02x,na03x); endmodule

4.4.4) DS-DK handshake circuit block

module dsdkjync; reg rst,ckl,ck2,start; reg [4:0] qp;//preset counter wire ds,dk; wire [7:0] ql,q2; supplyO vss; supplyl vdd; wire [4:0] qc;//word counter / / master sequencer seqctrl seOl (ql, {dkb,dk,dkb,dk,dkb,dk,dkb,dk}, startx,ckl,rsteq);

- 6 8 -

inv ivOl (dkb.dk); inv iv02 (rstb,rst); inv iv03 (rsteqb,rsteq); or2 orOL (or01x,ql[0],ql[2]); or2 or02 (or02x,ql[4],ql[6]); or2 or03 (dsx,or01x,or02x); dffr dfOl (ds,dsckb,dsx,ckl,rstb); dffr df02 (startx„starty,ckl,rsteqb); scnt5b scOl (qc,dsckb,vdd,rsteqb,startx); compSb coOl (cqx,qc,qp); dffr df03 (eq„eqx,ckl,rstb); or2 or07 (rsteq,cq,rst); or2 or08 (starty,stastx,start);

/ / slave sequencer seqctrl se02 (q2, {dsb,ds,dsb,ds,dsb,ds,dsb,ds}, startx,ck2,rst); inv iv04 (dsb,ds); or2 or04 (or04x,q2[l],q2[3]); or2 or05 (or05x,q2[5],q2[7]); or2 or06 (dk,or04x,or05x); / / test vectors initial begin rst=l; ckl=0; ck2=0; start=0; qp=8'b 10001 ;//set word count #25 rst=0;//release reset #100 start=l;//start data transfer #200 start=0; #10000 rst=l; #100 $stop; end always #40 ckl=~ckl;//clock for master sequencer always #70 ck2=~ck2;//clock for slave sequencer cndmodule / / 5-bit comparator

- 6 9 -

module comp5b (eq,a,b); input [4:0] a,b; output eq; wire [4:0] c; xor2 xOO (c[0],a[0],b[0]); xor2 xOl (c[l],a[l],b[lj); xor2 x02 (c[2],a[2],b[2]); xor2 x03 (c[3],a[3],b[3]); xor2 x04 (c[4],a[4],b[4]); nor5 nrOl (eq,c[0],c[l],c[2],c[3],c[4]); endmodule

5.6.1) 32-word random access memory

module mem32w (do,di,mr,mw,addr,cs); input [7:0] di; input mr.mw; input cs; input [4:0] addr; output [7:0] do; wire [3:0] selx,scl; wire [7:0] dx; wire [2:0] addrx; wire [1:0] addry; assign addrx[2]=addr[2]; assign addrx[l]=addr[l]; assign addrx[0]=addr[0]; assign addry[l]=addr[4]; assign addry[0]=addr[3]; dec224 deOl (selx,addry); and2 anOO (sel[0],selx[0],cs); and2 anOl (sel[lj,selx[l],cs); and2 an02 (sel[2],selx[2],cs); and2 an03 (sel[3],selx[3],cs); mem8w mOO (dx,di,mr,mw,addrx,sel[0]); mem8w mOl (dx,di,mr,mw,addrx,sel[l]); mem8w m02 (dx,di,mr,mw,addrx,sel[2]); mem8w m03 (dx,di,mr,mw,addrx,se][3]);

- 7 0 -

trinv trOO (do[0],dx[0],mr) trinv trOl (do[l],dx[lj,mr): trinv tr02 (do[2],dx[2],mr): trinv tr03 (do[3],dx[3],mr); trinv tr04 (do[4],dx[4],mr); trinv tr05 (do(5],dx[5],mr); trinv tr06 (do[6],dx[6j,mr); trinv tr07 (do[7],dx[7],mr); pullup puOO (dx[0]); pullup puOl (dx[lj); pullup pu02 (dx[2]); pullup pu03 (dx[3j); pullup pu04 (dx[4]); pullup pu05 (dx[5j); pullup pu06 (dx[6]); pullup pu07 (dx[7]); cndmodule

5.6.2) FIF032W, 32-word fifo memory block

module fifo32w(do,di,empty,full,write,read, sync,reset,c3); input writc,read,sync,reset,cs; input [7:0] di; output cnipty,full; output [7:0] do; wire [4:0] addr; fifoaddr fiO?. (addr, mr,mw,empty,full, write,read,sync,reset,cs); mem32w meOl (dojd^mrjmw^ddrjCs); endmoudle

5.6.3) LIF032W, 32-word stack block

module lifo32w(do,di,empty,full,push,pop,sync,reset,ca); input push,pop,sync,reset,cs; input [7:0] di; output [7:0] do;

- 7 1 -

output cmpty,full; wire [4:0] addr; lifoaddr HOI (addr,mr,mw,empty,fu]l,push,pop,sync,reset,cs); mem32w meOl (do,di,iiir,mw,addr,cs); endmoudle

6.5.1) Program for subtraction

©00000 8'M01-10011;// load d ©00001 8'MOOJOOOl;// xor b ©00010 8'6010.10010;// add c ©00011 8'A010.10000;// add a ©00100 8'6110.10100;// store e ©00101 8'MOOJOOOOO;// halt ©10000 8'fiOOO.lllll;// a=31 ©10001 8'6000J00101;/ / b=5 ©10010 8'AOOO.OOOOl;// c=l ©10011 8' t l l l . l l lLl; / / d=-l 910100 8'WOO.OOOOO;// e

6.5.2) Program for loop operation

©00000 8'6101_ 10000;// load a ©00001 8'6010-10011;// add d ©00010 8'AOOlJOOOOO;// skip if zero ©00011 8'6111.00001;// jmp ©00100 8'6000J)0000;// halt ©10000 8'4000J00011;// a=3 ©10011 8'fcll l . l l l l l; / / d=-l

6.5.3) Program for OR operation

- 7 2 -

©00000 8'6101.10000;// load a 900001 8'6100.10011;// xor d ©00010 8'M10-10010;// store w ©00011 8'M01-10001;// load b ©00100 8'6100-100ll;// xor d ©00101 8'6011-10010;// and w ©00110 8'MOO-100U;// xor d ©00111 8'6110.10010;// store w ©01000 8'6000-00000;// halt ©10000 8'6101-01010;// a=8'h*a ©10001 8'A010-10101,// b=8'h55 ©10010 S'WOO.OOOOO;// w ©10011 8'6111-1H11;// d=-l

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TABLE CAPTIONS

1: Boolean identities 2: Truth tables for primitive logic functions 3: Karnaugh map 4: Karnaugh map of a full adder 5: List of Gray code 6: Truth table for the master-slave JK flip-flop 7: Instruction codes 8: Set or reset condition of control signals

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Table 1. Boolean identities

def. 1 x,y g B =*•* + y,x*y,x,y 6 B

dcf. 2 o,iefi,i^o dcf. 3 i 6 f l * i + 0 = i , i * l =x

def. 4 x,y e B => x + y = y + x,x*y = y *x

def. 5 x,y,z£B=>x*(y + z) = (x*y) + (x*z),x + (y*z) = (x + y)*(x + «> def. 6 J 6 f l ^ i - f i = l , i * i = 0

Th. 1 i * 0 = 0,1 + 2: = x,x *x = x,x + {y * z) = (x * y)*z = x*y*z

Th. 2 1 + 1 = 1

Th. 3 X = X

Th. 4 x*y = 0,x + y = l=>x = y

Th. 5 x + y = y for arbitrary y =*• x = 0

Th. 6 Th. 6 x + y = x*y

Th. 7 x + y * x = x

Th. 8 (x + 3f) + z = x + (2/ + z) = x + y + 2

Th. 9 i * J/ = y for arbitrary y => x = 1

Th. 10 xj? = x + y

Th. 11 x*(y + x) = x

Tb. 12 (x + y)*(x + z) = x*z + x*y

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Table 2 Truth table for NAND and NOR

(a) NAND function

x (input) y (input)

0

z(output)

(b) NOR function x (input) y (input) z (output)

0 0 1

1 0 0

0 1 0

1 1 0

(c) XOR function

x (input) y (input) z (output)

0 0 0

1 0 1

0 1 1

1 1 0

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Table 3. Karnaugh map

(a) NAND function

x=0 x=l

y=0 1 1

y= l 1 0

(b) NOR function

x=0 x=l

y=0 1 0

y= l 0 0

(c) XOR function

x=0 x=l

y=0 0 1

y=i 1 0

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Table 4. Karnaugh map of a full adder

(a) output for s

(a,b)=(0,0) (a,b)=(0,l) (a,b)=(l,l) (a,b)=(l,0)

ci=0 0 1 0 1

ci=l 1 0 1 0

(b) output for co

(a,b)=(0,0) (a,b)=(0,l) (a,b)=(l,l) (a,b)=(l,0)

ci=0 0 0 1 0

ci=l 0 1 1 1

I

Table 5. List of 3-bit Gray code

Decimal Gray code Binary code

0 3'bOOO 3'bOOO (d(7,0)=3)

1 3'b001 3'b001 (d(0,l)=l)

2 3'b011 3'b010 (d(l,2)=2)

3 3'b010 3'b011 (d(2,3)=l)

4 3'bllO 3'blOO (d(3,4)=3)

5 3 ' b l l l 3'blOl (d(4,5)=l)

6 3'blOl 3*bU0 (d(5,6)=2)

7 3'blOO 3'blll (d(6,7)=l)

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Table 6. Truth table for the master-slave JK flip-flop

J K clock setbar clearbar output ( qn+i )

X X X 0 0 undetermined

X X X 0 1 1

X X X 1 0 0

X X 0 1 <?»

0 0 u 1 In

0 1 u 1 0

1 0 u 1 1

1 1 u 1 5̂ X X d 1 <7n

Table 7. Programming for PLA

inx[0] inxfl] inx[2] inx[3] inx[4] inx[5) inx[6] inx[7]

ci a 6 - ci a 6 -

PgO 1 0 0 0 0 1 1 Q a* 4* ci

pgl 0 0 1 0 1 1 0 0 a* b * ci

Pg2 0 1 0 0 1 0 1 0 a*b*ci

Pg3 1 1 1 0 0 0 0 0 a*b* ci

Pg4 0 1 1 0 0 0 0 0 a* b

Pg5 1 0 1 0 0 0 0 0 b*ci

Pg6 1 1 0 0 0 0 0 0 a*ci

Pg7 1 1 1 1 1 1 1 1 -

- 8 1 -

Table 8. Instruction code

Instruction code action of ALU

3'hO halt pass accumulator

3'hl skip if zero pass accumulator

3'h2 add data .add. accumulator

3'h3 and data .and. accumulator

3'h4 xor data .xor. accumulator

3'h5 load pass data

3'h6 store pass accumulator

3'h7 jump pass accumulator

- 8 2 -

Table 9. Set or reset conditions for control signals

Signals reset conditions set conditions

memjread reset

/etcA(u), fctch(d)

fetch * clk(u)

fetch * clk(u) * (opcode = 2,3,4,5)

j'ncpc reset, fetch[u) fetch(d)

fetch * clk(u) * clkJl * (opcode = 7)

fetch * c/i_2(u) * zero * (opcode — 1)

loadJr reset, fetch[d) fetch * clkJ2(d)

loadjaccum reset, fetch(u) fetch * clkJZ(d) * (opcode = 2,3,4,5)

loadjpc reset, fetch(v) fetch * dkJ2(d) * (opcode = 7)

mem-WT reset, felch{u) fetch * clk(u) * clkJi * (opcode = 6)

halt reset fetch * clk(u) * (opcode = 0)

- 8 3 -

FIGURE CAPTIONS 1) TTL NAND gate 2) ECL NOR gate 3) NIM receiver and diver gate 4) CMOS NAND gate 5) Schematic of XOR2 with a transfer gate technique 6) Logic symbols for schematic entry 7) Basic memory cell 8) LADDER8 circuit block 9) Timing diagram for the clock signals

10) Timing diagram for testjcpuO 11) Timing diagram for teatu:pul 12) Timing diagram for test jcpu2 13) Timing diagram for testjcpuS

- 8 4 -

©a 0

1) TTL NAND gate

- 8 5 -

2) ECL NOR gate

- 8 6 -

I

J^-6 .0

0' <

(i e e o ^ 5 . 2

\

3 ?-

3) NIM receiver and diver gate

- 8 7 -

-Q&-

6'

- « — *

ik> s

r

4) CMOS NAND gate

- 8 8 -

DD; I \ I

AilAj j ^

IV18

B : I \ I

SW\C

IVI7

§W"

' • - 1 •> <> \~+i-

PM09

07*1 6 j N

MH07S,

urn 6^ |«-J44

e-&

\* !:! 1

MU4D NMUJN

— [<-&<)

_X;0\I

5) Schematic of X0R2 with a transfer gate technique

- 8 9 -

- D & •

- C O 0 O 3 I>

S ' ^Aun J H I W M _ . . „ . . t> o° o

- s s - O- 3>

O- 5>

6) Logic symbols for schematic entry

- 9 0 -

DO

SEL NOOF N

—t S

DO

MR H« (>

EO

DI , y NOOD

"HF" ~UF>~ H « — O

-75S<>

7) Basic memory cell

- 9 1 -

INVOl PHO

Hs

-»e oe ee sa ee ©a sa & 1 I PM2 I PH3 PH4 PMS PM6 PM7 PM8 41 £1 ,,Sj ..Sl .̂ 1 M .SI *

NM0(

fiTq

WOI

NM2G

•o e 4 e ' (i

PG*[1 | &M2,

mu

J-*

PG-

NM4G

" | 1 1 J ! HH56

W

[31 • M l

PG* [51

NMJ_

NM3

NH3:

HHO

"4J-,

—Irr"

NM6G

1-Ti G*[«]

PG*I7

T G* 17 ]

NM5!

NHS

•3HJ

3) LADDER8 circuit block

- 9 2 -

9) Timing diagram for the clock signals

- 9 3 -

I IO | o i In | « In |oj

JL

JO) Timing diagram for test_cpuO

- 9 4 -

[W 113 |pr ]ll ]02 112 ]M | l> ]04 f 1.1 [»S [oo ~

1' h IE n, i i .

11) Timing diagram for test-cpul

- 9 5 -

J"

| M 110 |ai I n |oi | M \<a | I I |»i [n [oi [w [03 [ti [ei J» | M jw | j

00-001

»» n I' n I ' I- I' i» |w [M |o;

|oe [»i |oi ] M ] ]m I oi ]u [ |m [« ] ]n }~

12) Timing diagram for teat-cpu2

- 9 6 -

13) Timing diagram for tcstxpu'l

i - 9 7 -