Nuclear Instruments and Methods in Physics Research A 626–627 (2011) 82–89

Contents lists available at ScienceDirect

Nuclear Instruments and Methods inPhysics Research A

0168-90

doi:10.1

$This

DACEL2n Corr

E-m

journal homepage: www.elsevier.com/locate/nima

Latest results of SEE measurements obtained by the STRUREDdemonstrator ASIC$

A. Candelori c, G. De Robertis a, A. Gabrielli b, S. Mattiazzo c, D. Pantano c, A. Ranieri a,n, M. Tessaro c

a INFN Section of Bari, Via Orabona 4, c.a.p. 70126, Bari, Italyb Physics Department, University of Bologna, Viale Berti Pichat 6/2, c.a.p. 40127, Bologna, Italyc INFN, Section of Padova, Via Marzolo 8, c.a.p. 35131, Padova, Italy

a r t i c l e i n f o

Article history:

Received 22 July 2010

Received in revised form

20 September 2010

Accepted 4 October 2010Available online 13 October 2010

Keywords:

CMOS integrated circuits

Radiation hardening

Single Event Effects

Soft Errors

02/$ - see front matter & 2010 Elsevier B.V. A

016/j.nima.2010.10.018

study has been financed by the INFN V Commi

Experiment.

esponding author.

ail address: antonio.ranieri@ba.infn.it (A. Rani

a b s t r a c t

With the perspective to develop a radiation-tolerant circuit for High Energy Physics (HEP) applications, a

test digital ASIC VLSI chip, called STRURED, has been designed and fabricated using a standard-cell library

of commercial 130 nm CMOS technology by implementing three different radiation-tolerant architec-

tures (Hamming, Triple Modular Redundancy and Triple Time Redundancy) in order to correct circuit

malfunctions induced by the occurrence of Soft Errors (SEs). SEs are one of the main reasons of failures

affecting electronic digital circuits operating in harsh radiation environments, such as in experiments

performed at HEP colliders or in apparatus to be operated in space. In this paper we present and discuss

the latest results of SE cross-section measurements performed using the STRURED digital device, exposed

to high energy heavy ions at the SIRAD irradiation facility of the INFN National Laboratories of Legnaro

(Padova, Italy). In particular the different behaviors of the input part and the core of the three radiation-

tolerant architectures are analyzed in detail.

& 2010 Elsevier B.V. All rights reserved.

1. Introduction

One of the main objectives of the DACEL2 Collaboration is to findthe best mitigation architecture to be adopted as a guideline for thenext digital ASIC generations to be designed and fabricated in thenewest commercial deep submicron CMOS technologies for HighEnergy Physics (HEP) applications. As a matter of fact, especially inthe case of digital circuits, one of the main concerns, whenoperating in high radiation environments, is the occurrence ofthe so called Single Event Effects (SEEs).

SEEs are due to the collection, at a sensitive node of an electronicdevice beyond a threshold value, of the charge generated in thesilicon substrate by a strongly ionizing particle, such as heavy ions(Z41), or fragments induced by nuclear interactions of protonsand neutrons with the atom nuclei. Both protons and neutrons, andheavy ions can cause SEEs in electronic devices operating inradiation harsh environments (i.e., nuclear reactors, High EnergyPhysics collider experiments, spacecraft missions, and so on).Protons and neutrons cause SEE’s mainly indirectly, i.e. by ioniza-tion induced by nuclear fragments produced by nuclear reactionwith the atoms in the electronic devices. On the contrary, heavyions, which have a higher Linear Energy Transfer (LET) thanprotons, can induce SEEs directly by ionization. Nevertheless a

ll rights reserved.

ssion, in the framework of the

eri).

correlation between SEEs induced by protons and heavy ions hasbeen found [1,2].

The charge collected at a sensitive node of a digital circuit mayinduce a momentary voltage perturbation, which nevertheless caninfluence the voltage value of more than one circuit node. Forinstance, when a voltage spike is produced near a combinatorialnode of a circuit, it can propagate within the circuit to next node,and so on; in this case a Single Event Transient (SET) is induced andthis effect is more relevant in digital circuits operating at high clockfrequencies. On the other hand, if the momentary voltage pertur-bation is latched by a memory element, a Single Event Upset (SEU)can be induced. The magnitude of the voltage perturbation dependson the charge collected at the sensitive node, which depends on theparticle LET and is consequently strictly related to the particle massand energy and to the material in which the particle travels. SETsand SEUs are SEEs relevant for digital electronics [3,4] also calledSoft Errors (SEs) because they are recoverable. In order to preventthe SE occurrence, it is a good practice to introduce some sort ofredundancy inside the circuit architecture [5,6].

A SET can be considered as a SEU in combinatorial logic, such asin inverters or NAND gates: in fact, the SET lasts only for a shortperiod of time, propagating along the circuit tree and, whenlatched, can produce a ‘‘permanent’’ Soft Error until the cell isrewritten and set to its original state.

In fact the temporal width of a SET voltage waveform in anaffected node can determine if a SET will be eventually latched(fault) or not (no fault), depending on how long (in time) is theperturbation and how high is the operating frequency of the circuit.

A. Candelori et al. / Nuclear Instruments and Methods in Physics Research A 626–627 (2011) 82–89 83

For deep submicron CMOS technologies, a large fraction of observedSEs is estimated to be related to latched SETs. Moreover, while errorcorrection codes and latch-hardening designs [7] can be used toprotect memory elements, a complete protection against combina-torial logic SETs is quite difficult and involves considerable perfor-mance penalties: a more manageable approach is to design a limitedprotection against SETs by targeted performance tradeoffs, where thecircuits can be more vulnerable, i.e. the clock and reset lines.

In this study we have evaluated the vulnerability to SEs inducedby heavy ions of three different radiation-tolerant architectures forthe same digital circuit implementation. A digital ASIC VLSI testchip called STRURED (STRUctures for REDundancy) has beenspecifically designed and produced in a commercial 130 nmCMOS technology, implementing a pipelined sequential and com-binatorial logic composed by nearly 200,000 gates. The circuit hasbeen designed using three different radiation-tolerant architec-tures, which are compared in terms of robustness, power con-sumption, dimensions, circuit implementation complexity andradiation hardness. The first radiation-tolerant architecture con-tains just a coding scheme to verify the output data integrity(Hamming code [8]) capable to correct a single bit error in aregister, while the other two implement two different redundancyschemes for SE correction: Triple Modular Redundancy (TMR) [5]and Triple Time Redundancy (TTR) [6].

Fig. 1. Block diagram of the STRURED test digital chip.

Fig. 2. Block diagram of the complex digital circuit implemented in the STRURED test dig

TTR). The complex circuit is composed of ‘‘Input Register’’, ‘‘XOR-matrix’’ and ‘‘Key’’.

Finally, the best architecture will be recommended in the designfor the implementation of the future radiation hard digital ASICs inthe same commercial 130 nm CMOS technology to be operated inHigh Energy Physics experiments, such as in the future LHCupgrade (Super-LHC), where the irradiation conditions in operationare expected to be very harsh and effective countermeasures mustbe introduced in the VLSI chip design [9].

2. STRURED test digital chip

The technology considered to design the STRURED test digitalchip is a commercial 130 nm CMOS technology, which employs sixaluminum layers insulated by silicon oxide (SiO2) for a total of 6 mmthickness. Moreover all unused areas are aluminum filled obtaininga compact structure, which does not allow SE laser testing [10], andit obliges us to perform irradiation tests by using heavy ion beamsfor measuring the SE cross-section as a function of the impingingparticle LET.

The STRURED device is composed of four digital circuits asshown in Fig. 1.

The first block, called ‘‘Unprotected Shift Register’’, is a Flip-Flop256 bit long shift-register chain, which is completely unprotectedagainst Soft Errors. This block is used only as a standard referencefor a possible comparison among the considered commercial130 nm CMOS technology and other technologies by implementingthe same simple digital circuit.

The other three blocks called ‘‘Hamming test’’, ‘‘TMR test’’ and‘‘TTR Test’’ implement, as shown in Fig. 2, the same complex digitalcircuit, which consists of

�

ital

a 64 bit ‘‘Input Register’’ reading a byte at a time from the inputdata bus;

� a 64 bit ‘‘Key Register’’ written as a header inside the input data

packet;

� one processing matrix called ‘‘XOR-matrix’’ composed of 26

registers, each with 128 bits and a XOR-logic inserted betweenthe true data and the ‘‘Key Register’’;

� a Finite State Machine (FSM) controlling the data flux, writing in

the registers, etc.

The first redundancy architecture, called ‘‘Hamming test’’ inFig. 1, is shown in Fig. 3; it contains just a coding scheme accordingto the linear Hamming algorithm, which allows the verification ofthe data output integrity, only a full protection on single bit errors

chip by the three different radiation-tolerant architectures (Hamming, TMR and

> x

y

z

xA

xB

xC

xAxBxCyAyByCzAzBzC

F (x,y,z)F fA

>

>

clk

clk

> x

y

z

xAxBxCyAyByCzAzBzC

F (x,y,z)F fB

>

>clk

> x

y

z

xAxBxCyAyByCzAzBzC

F (x,y,z)F fC

>

>clk

clk

clk

yA

yB

yC

clk

clk

clkzA

zB

zC

clk

clk

clk

Fig. 4. Block scheme of the TMR architecture implemented in the STRURED test digital chip.

x

y

zF (x,y,z)

F f

clk

Input registerHamming coded

Combinatorial logicOutput register

Hamming coded

Err

or c

orre

ctio

n

clkE

ncod

ing

Err

or c

orre

ctio

n

clk

Enc

odin

g

Fig. 3. Block scheme of the Hamming architecture implemented in the STRURED test digital chip.

x

y

z

FclkA

clkB

clkC

> f

clkA

clkB

clkC

>

clkA

clkB

clkC

>

clkA

clkB

clkC

>

x

y

z

clkAclkBclkC

F (x,y,z)

Fig. 5. Block scheme of the TTR architecture implemented in the STRURED test

digital chip.

A. Candelori et al. / Nuclear Instruments and Methods in Physics Research A 626–627 (2011) 82–8984

has been introduced in each register, i.e. no Soft Error protection isat all foreseen.

The last two architectures implement other two differentredundancy schemes in order to correct the Soft Error eventsand are used to obtain a specific logic redundancy, althoughconceptually different in terms of functionality.

The circuit implemented by using a Triple Modular Redundancy(TMR) scheme, called ‘‘TMR test’’ in Fig. 1, is shown in Fig. 4; itcontains a replica three times of the combinatorial and sequentiallogic of the circuit, plus a ‘‘Voter Logic’’ at the input paths, whichdecides the correction to be adopted on the basis of the resultsobtained by the three blocks of the circuit.

Finally, the circuit implemented using a Triple Time Redun-dancy (TTR) scheme, called ‘‘TTR test’’ in Fig. 1, is shown in Fig. 5; itadopts only one time the combinatorial part of the circuit withoutany replica, but it uses a three times replica of the system clock,obtained from the main clock circuit, delayed three times by a fixedquantity, for strobing the input data into the sequential part of thecircuit. The delay among the three clocks has been chosen greaterthan few nanoseconds, i.e. greater than the sum of the setup andhold time of the Flip-Flops in the circuit plus the expectedmaximum transient time. This allows the glitch to be latchedinside the only one memory element. Its output, as shown in Fig. 5,is finally voted before sending the results to the input of thecombinatorial logic of the circuit.

A SET in the Reset line of a digital circuit can corrupt more thanone bit of a register, consequently we used a large buffer (notshown in the previous Fig. 3–5) to minimize SET effects in the Resetline of the three protected architectures, even if this is not 100%

A. Candelori et al. / Nuclear Instruments and Methods in Physics Research A 626–627 (2011) 82–89 85

safe. Moreover in TTR and TMR architectures we also triplicate theReset line; in this case a SET in one Reset net will corrupt only one ofthe three Flip-Flop shift-register chains.

The same considerations must be taken into account for theother sensitive lines, for instance the clock net. A single clock linedriving all the Flip-Flops is a critical net; a SET in this line cancorrupt more than one bit of a register. Also in this case we usedlarge clock drivers to minimize SET effects but, as for the Reset line,this does not guarantee a full protection. In the TMR architecturewe triplicate the clock tree (as shown in Fig. 4): a SET in a clock netwill corrupt only one of the three Flip-Flop shift-register chains,while in TTR scheme we need in any case three independent clocktrees (as shown in Fig. 5).

In redundant circuits a single permanent fault is not detectablebecause it is masked by the redundancy. Consequently in order toevidence the presence of permanent faults, it is mandatory to use‘‘Scan Path chains’’ [11] (not shown in Figs. 4 and 5). A permanentfault in the circuit does not make it utilizable; thanks to the use ofthese Scan Path chains, we were able to evidence the absence ofpermanent faults in the circuits:

�

TabRes

Shif

C

U

H

T

T

before irradiation and

� after each irradiation run for all the tests.

In the case of ‘‘Scan Path’’ use, the ‘‘Scan Enable Line’’ can also bea critical net for SETs because a SET in the ‘‘Scan Enable Line’’ cancorrupt many Flip-Flops. In the TTR and TMR implementations weused three independent ‘‘Scan Enable Lines’’ in order to prevent thisproblem.

The layout of the STRURED test digital chip, having anarea of 7�7 mm2, is shown in Fig. 6, where the three differentarchitectures (Hamming, TTR and TMR) are clearly distinguishableas three horizontal regions, while the two pairs of vertical bars are

Fig. 6. Layout of the STRURED test digital chip.

le 1ources comparison among the three radiation-tolerant architectures (Hamming, TTR a

t Register are reported as a reference for the considered CMOS technology.

ircuit Area (mm2) Gates

nprotected Shift Register 217030 5023

amming test 390928 9049

TR test 522783 12101

MR test 849683 19668

power stripes. The ‘‘Unprotected Shift Register’’ is embedded insidethe circuit and is not clearly visible in the layout.

Before the irradiation campaign, in order to evaluate theperformances of the three different radiation-tolerant architec-tures, we focused the attention on the comparison for occupiedarea, number of gates, number of cells and simulated powerconsumption, as summarized in Table 1. Data for theUnprotected Shift Register cannot be compared directly with thethree complex radiation-tolerant digital circuits, and are reportedfor completeness as a reference for the considered commercial130 nm CMOS technology.

As shown in Table 1 the areas and the number of gates requiredfor implementing the TTR and TMR architectures are a factor 1.3and 2.2 higher, respectively, than the value required for theHamming code. Similarly the power consumptions for the TTRand TMR architectures are a factor 1.5 and 2.1 higher, respectively,than that for the Hamming scheme. As expected the TMR structureoccupies more circuit resources (area, number of gates, number ofstandard cells and power consumption) than the other tworadiation-tolerant architectures.

3. Experimental setup

Irradiation experiments have been performed at the SIRADirradiation facility of the Tandem-XTU accelerator at the INFNNational Laboratories of Legnaro (Padova, Italy) [12]. We usedvarious ion species from 12C to 79Br, featuring LET values rangingfrom 2.1 up to 41.8 MeV cm2/mg, as reported in Table 2 for theincidence angle of 01, where the energy and LET values are referredto the silicon surface of the device under test (DUT), and have beencorrected for the ion energy loss in the 3 mm Al and 3 mm SiO2 thicksurface layers, using the simulation program SRIM 2010 [13]. Ionspecies required for the experiment were selected by consideringdifferent possible charge states obtained with one or two strippersand the Tandem-XTU accelerator operating between 10.5 and15 MV, accordingly to the possible operating conditions [12].The requested beam current was nearly E1 nA.

The ion species considered for irradiation were chosen duringthe experiment according to the SE cross-section data measuredexperimentally. In order to save the time required to change the ion

nd TMR) implemented in the STRURED test digital chip. the data for the Unprotected

Standard cells Simulated power (mW)

8 19651 8.16

2 35734 14.13

4 37939 21.0

6 81892 30.1

Table 2Main features of the ion beams considered in the test.

Ion Energy (MeV) LETincident at 01 (LET at the silicon

surface for an incidence angle of 01)

(MeV cm2/mg)

12C 67 2.112C 90 1.616O 85 3.619F 96 4.719F 119 4.135Cl 172 13.379Br 242 41.8

A. Candelori et al. / Nuclear Instruments and Methods in Physics Research A 626–627 (2011) 82–8986

beam energy, we increased the effective LET (LETeffective) of theimpinging ions by a factor of 1.15, 1.30, 1.41 and 1.55 by tilting theDUT at an angle of 301, 401, 451 and 501 with respect to the ionbeam; this allows an increase in the charge collected within thesensitive region of the DUT without changing the ion energy.

We know from experimental evidences [14] that the LETthreshold and the saturation cross-section values scale down byscaling down the CMOS technology node. Accordingly to theseconsiderations, we estimated the expected maximum SE rate forthe Unprotected Shift Register as a function of ion flux. In fact, byconsidering that the Unprotected Shift Register contains 256 bitsand assuming an ‘‘a priori’’ SE saturation cross-section ofE10�9 cm2/bit for the considered commercial 130–nm CMOStechnology, we expected a SE rate of E0.026 Hz with a flux of105 ions/cm2 s, typically available at the SIRAD irradiation facility.

A special Test Bench board has been developed for mounting theDUT (see Fig. 7); this board contains the necessary logic to controland to set the test patterns, which must circulate inside theregisters of the STRURED test digital circuits. An Ethernetinterface has been implemented in the board to control itsfunctionality by a PC connected to it.

Two test modes have been foreseen. In the first one, namedAutomatic Test Equipment (ATE) mode, the PC sends ‘‘Test Vectors’’to the FPGA, which, through the ‘‘Scan Path’’ chains, stimulates theSTRURED ASIC and verifies the output. ‘‘Test Vectors’’’’ have beengenerated by using the Synopsys TetraMAX ATPG software with a99% coverage. This test has a duration of few seconds; it has beenconsidered to check the chip functionality before irradiation andafter each irradiation run.

The second mode of operation, called Soft Error (SE), is used tocompare the data at the output of each of the four digital circuits inthe STRURED chip (see Fig. 1) with the reference ones for SEdeterminations. The system clock frequency directly affects the SEdetection; the higher the running frequency, the higher theprobability of SET occurrence; however, SETs and SEUs are notdistinguishable at the output of the ASIC. In our case all the testshave been performed by considering the maximum operatingfrequency, which is 80 MHz, i.e. the worst case for Soft Errors.Our goal is to analyze the global effect on our device provoked fromSE induced by heavy ions, disregarding the different behaviorbetween SETs and SEUs, and collecting data in the worst case withthe system clock running at the maximum allowed frequency of

Fig. 7. Test beam setup: the Test Bench Board, with the STRURED chip covered by a

protecting cap, is at the center of the photograph. The protecting cap was removed

during irradiation. On the left side there is a quartz for beam diagnostic.

80 MHz. The STRURED test digital chip was consequentlystimulated using a sequence of formatted data packed at the80 MHz clock frequency and its outputs are checked againstradiation induced Soft Errors. The detected errors are thenstored into three FIFOs with time stamp and other relevant data.All the data were then sent to the PC for registration through theEthernet interface.

4. Experimental results

Before each irradiation run we used the ATE mode of operationin order to verify the circuit functionality and we never observedany permanent error or destructive event during the test.

The SE cross-section of a digital integrated circuit depends onthe impinging particle LET with a typical Weibull dependence:

sðLETÞ ¼ sSat 1�eðLET�LET0=WÞS� �

ð1Þ

where LET is the effective ion Linear Energy Transfer at the siliconsurface, s the SE cross-section, LET0 the LET threshold value, sSat

the saturation cross-section value and W and S are the fit para-meters. Parameter W, also called ‘‘width’’, and parameter S, which isa dimensionless exponent, depend on the shape of the Weibull fit.The LET threshold value is an onset parameter, which correspondsto the LET value at which the cross-section value in Eq. (1) is zero.

According to the commonly accepted models, four regions canbe distinguished:

1.

a sub-threshold region, where the ion LET does not produce anysignificant SE;

2.

a threshold region, where the ion LET produces a measurable SEcross-section (in our case higher than 10�12 cm2/bits);

3.

a transition region, over the LET threshold, where the SE cross-section rapidly grows by orders of magnitude on linearlyincreasing the ion LET;

4.

a saturation region, where the SE cross-section slightly dependsonly on the particle LET.

A Weibull fit analysis was performed for the SE cross-sectionvalues as a function of the effective ion LET at the silicon surface forthe four digital circuits implemented in the STRURED chip by fittingthe experimental data with Eq. (1).

As previously stated, in our test the ion LET values referred to theDUT silicon surface (LETincident) have been corrected for the ionenergy loss in the 3 mm thick Al and 3 mm thick SiO2 surface layers,while the effective LET increase, due to the DUT tilting angle withrespect to the ion beam direction, has been taken into account byintroducing the 1/cos(W) dependence [15,16] as reported in Eq. (2):

LETðWÞ ¼LET

cosyð2Þ

The cross-section values were calculated as the ratio betweenthe number of Soft Errors (# errors) and the ion fluence (ions/cm2)multiplied by the number of bits constituting each block of thecircuit as reported in Eq. (3), where the cos(W) term takes intoaccount the correction on the fluence when DUT is tilted by anangle W with respect to the ion beam direction:

s¼ #errors

ion fluence� number of bits� cosðWÞ ð3Þ

The sSat and LET0 values are the parameters of interest, whichwe want to evaluate, because they give an estimation of thevulnerability of the circuit (high sSat and low LET0 values) or, in

A. Candelori et al. / Nuclear Instruments and Methods in Physics Research A 626–627 (2011) 82–89 87

other terms, the degree of radiation hardening (low sSat and highLET0 values) with respect to SEs.

A deep data analysis has been performed for the three redun-dancy circuits (Hamming, TTR and TMR) in order to identify thedifferent sources of faults and to estimate, for each one, thecorresponding cross-section values.

While doing this evaluation it has been possible to distinguishthe fault events according to the following classification:

�

‘‘Input Register’’—faults in the 64 bits input register propagat-ing thereafter toward the XOR-matrix up to the circuit output; � ‘‘XOR-matrix’’—faults in a single bit of the XOR-matrix of 3328

bits propagating up to the circuit output;

� ‘‘Key Register’’—one or more corrupted bits in the Key Register

that produces errors in the output data;

� ‘‘FSM’’—one error in the Finite State Machine or in the data counter

that produces a loss in the synchronism of the circuit, which doesnot come back to the initial conditions in a new data packet;

�

Fig. 8. SE cross-section data, with black error bars, as a function of the effective ion

‘‘Reset’’—a spurious signal that overcomes the protectionszeroing the output data;

LET at the silicon surface in the case of the ‘‘XOR-matrix’’ block for the three

� redundancy (Hamming—green triangles, TMR—red crosses and TTR—cyan circles)

‘‘Clock’’: a spurious clock signal that produces a momentarymisalignment of the output data;

circuits operating at the maximum 80 MHz frequency. The data for the Unprotected

� Shift Register (blue circles) are reported for completeness and must be considered as

a reference for the considered commercial 130 nm CMOS technology. The solid lines

are the Weibull fits of the SE cross-section curves. (For interpretation of the

‘‘Counter’’—due to an error in the data counter, the circuitproduces a different number of outcoming data with respect tothe incoming ones and

references to colour in this figure legend, the reader is referred to the web version of

� this article.)

Fig. 9. SE cross-section data, with black error bars, as a function of the effective ion

LET at the silicon surface in the case of the ‘‘Input Register’’ block for the three

redundancy (Hamming—green triangles, TMR—red crosses and TTR—cyan circles)

circuits operating at the maximum 80 MHz frequency. The data for the Unprotected

Shift Register (blue circles) are reported for completeness and must be considered as

a reference for the considered commercial 130 nm CMOS technology. The solid lines

are the Weibull fits of the SE cross-section curves. (For interpretation of the

references to colour in this figure legend, the reader is referred to the web version of

this article.)

‘‘Unknowns’’—any other unknown error source.

The more relevant and meaningful data results, useful for ourdiscussion concerning the three redundancy circuits, come fromthe first two classes (‘‘Input Register’’ and ‘‘XOR-matrix’’), whichcontribute for 95% of all the SEs detected at the circuit output, andfor this reason we will discuss in detail only these ones. The otherfault classes contribute only 5% to the total SE cross-section of thethree redundancy circuits and appear only for high LET values in thesaturation region of the s(LET) curve.

The SE cross-sections of the three redundancy architecturesimplemented in the STRURED chip, as a function of the effective ionLET at the silicon surface, are shown in Fig. 8 for the ‘‘XOR-matrix’’block and in Fig. 9 for the ‘‘Input Register’’ case. The correspondingparameters obtained by the Weibull fits of the experimental dataare reported in Tables 3 and 4 .

The Unprotected Shift Register SE cross-section data have beenreported in both Figs. 8 and 9 for completeness and must beconsidered as a reference for the considered commercial 130 nmCMOS technology. The measured SE cross-section values are in therange 2.99�10�9–65.5�10�9 cm2/bit by varying the ion LET inthe range 2.1–56.7 MeV cm2/mg.

The XOR-matrix SE cross-section data at the output of theHamming architecture, normalized to the number of bits, as a functionof ion LET are also shown in Fig. 8; the values range from3.88�10�12 cm2/bit for an ion LET of 2.1 MeV cm2/mg up to187�10�12 cm2/bit for an ion LET of 56.7 MeVcm2/mg in satura-tion. The corresponding SE cross-section data for the TMR and TTRarchitectures are significantly lower being 1.82�10�12 and10.9�10�12 cm2/bit at the maximum ion LET of 56.7 MeV cm2/mgin saturation, respectively. No Soft Error has been detected with across-section 42.14�10�12 and 41.43�10�12 cm2/bit at theoutput of the TMR and TTR architectures, respectively, due to ionimpacts in the XOR-matrix for LET values lower than 19.7 MeV cm2/mg. This evidences that the TMR and TTR architectures significantlyimprove the radiation hardness not only by decreasing the cross-section values in the saturation region with respect to the Hammingscheme but also by appearing insensitive to SE for higher LET valuesthan the Hamming architecture. As previously stated the radiationhardness of the TMR and TTR structures is better than the Hamming

scheme due to the triple redundancy introduced in the clock andreset lines.

This is confirmed by the Weibull fits of SE cross-section data,which are reported in Table 3. The LET threshold is 0.93 MeV cm2/mgfor the Hamming architecture and increases to 18.5 MeV cm2/mg forthe TMR and TTR implementations. Finally, the sSat values from theWeibull fits are very close to the experimental cross-section data atthe highest ion LET, apart for the TTR circuit. The growing trend of the

Table 3Parameter values obtained by the Weibull fits of the SE cross-section data in Fig. 8 for the ‘‘XOR-matrix’’ block of the three redundancy circuits (Hamming, TMR and TTR). The

parameters values for the Unprotected Shift Register are reported for completeness.

Unprotected Shift Register Hamming TMR TTR

sSat (cm2/bit) 65.5�10�9 1.85�10�10 1.75�10�12 9.18�10�12

LET0 (MeV cm2/mg) 1.82 0.93 18.5 18.5

W (MeV cm2/mg) 19.6 41.3 0.38 43.7

s 0.78 1.19 0.59 0.53

Table 4Parameter values obtained by the Weibull fits of the SE cross-section data in Fig. 9, for the ‘‘Input Register’’ block of the three redundancy circuits (Hamming, TMR and TTR). The

parameters values for the Unprotected Shift Register are reported for completeness.

Unprotected Shift Register Hamming TMR TTR

sSat (cm2/bit) 65.5�10�9 69.7�10�10 16.9�10�10 8.99�10�10

LET0 (MeV cm2/mg) 1.82 1.97 1.09 17.6

W (MeV cm2/mg) 19.6 26.8 23.3 16.6

s 0.78 0.81 1.21 0.97

A. Candelori et al. / Nuclear Instruments and Methods in Physics Research A 626–627 (2011) 82–8988

TTR curve in Fig. 8 may depend on the temporal relationship betweenthe clock phase delay and the transient pulse width induced by theparticle hit. Heavy ions can generate transients larger than themaximum value tolerable by the circuit with the considereddesigned delay, reducing the correction capability.

The ‘‘Input Register’’ SE cross-section data, at the output of threeredundancy circuits as a function of ion LET are shown in Fig. 9. Thevalues for the Hamming architecture range from 1.24�10�10 cm2/bitat an ion LET of 2.1 MeV cm2/mg up to 64.8�10�10 cm2/bit at an ionLET of 56.7 MeV cm2/mg. The corresponding SE cross-sectiondata for the TMR and TTR architectures in the saturation regionare again significantly lower than those for the Hamming schemebeing, for instance, 16.6�10�10 and 8.99�10�10 cm2/bit at themaximum ion LET of 56.7 MeV cm2/mg, respectively. The sSat

values of the Weibull fits reported in Table 4 are very close to theexperimental cross-section data at the highest ion LET value. The SEcross-section data and the Weibull fits confirm that the TMR and TTRarchitectures significantly improve the radiation hardness bydecreasing the cross-section values in the saturation region, withrespect to the Hamming scheme. On the contrary, the LET thresholdvalues, reported in Table 4, are very low for the Hamming and TMRarchitectures being 1.97 and 1.09 MeV cm2/mg, respectively. The LET0

parameter remains high at 17.6 MeV cm2/mg only for the TTRscheme. This is due to the fact that the ‘‘Input Register’’ of the TTRarchitecture is intrinsically hardened in this specific case due to thetriple sampling of the primary inputs. As a matter of fact in this case theLET threshold value is quite similar to the value of 18.5 MeV cm2/mgshown in Fig. 8.

As a general trend the SE cross-section data, reported in Fig. 9 foreach of the three redundancy architectures, are significantly higherthan the corresponding values reported in Fig.8, highlighting thatthe sensitivity to SEs normalized to the number of bits is higher forthe ‘‘Input Register’’ block than for the ‘‘XOR-matrix’’ part of thecomplex digital circuit. This is mainly due to the fact that the ‘‘InputRegister’’ is less protected than the ‘‘XOR-matrix’’ due to the SEsoriginating in the buffers connected to the input pads.

5. Conclusion

This article analyzes

1.

The Soft Error (SE) sensitivity of a simple test digital device, i.e. along Flip-Flop shift-register chain (256 bits), designed using astandard-cell library in a commercial 130 nm CMOS technology.

This circuit can be considered as a reference for the consideredtechnology. The measured cross-section values are in the range2.99�10–65.2�10�9 cm2/bit, by varying the ion LET in therange 2.1–56.7 MeV cm2/mg.

2.

The Soft Error sensitivity of a complex digital circuit, whoseblock diagram is shown in Fig. 2, and implemented in the samecommercial 130 nm CMOS technology by three differentredundancy architectures (Hamming, TTR and TMR), whichare described in Section 3.

Concerning the circuit design, the areas and the number of gatesrequired for implementing the TTR and TMR architectures are afactor 1.3 and 2.2 higher, respectively, than the correspondingvalues required for the Hamming scheme. Similarly the powerconsumption for the TTR and TMR architectures is a factor 1.5 and2.1 higher, respectively, than those for the Hamming circuit.

The irradiation results have shown that the ‘‘Input Register’’ and‘‘XOR-matrix’’ blocks contribute for 95% of all the SEs detected atthe circuit output. In particular, the SE cross-section data shown inFig. 8 and the corresponding Weibull fits reported in Table 3 for the‘‘XOR-matrix’’ have evidence that the TMR and TTR architecturessignificantly improve the radiation hardness not only by decreasingthe cross-section values in the saturation region, with respect to theHamming scheme, but also by appearing insensitive to SEs forhigher LET values than the Hamming architecture. The radiationhardness of the TMR and TTR structures is consequently better thanthe Hamming circuit, due to the triple redundancy introduced inthe clock and reset lines.

The SE cross-section data shown in Fig. 9 and the correspondingWeibull fits reported in Table 4 for the ‘‘Input Register’’ have againevidenced that the TMR and TTR architectures significantlyimprove the radiation hardness by decreasing the cross-sectionvalues in the saturation region, with respect to the Hammingscheme. Nevertheless the LET threshold remains high at17.6 MeV cm2/mg only for the TTR architecture. This is due tothe fact that the ‘‘Input Register’’ of the TTR scheme is intrinsicallyhardened in this specific case, due to the triple sampling of theprimary inputs.

Finally as a general trend, the SE data for the ‘‘Input Register’’ ofeach of the three redundancy architectures are significantly higherthan the corresponding values for the ‘‘XOR-matrix’’, highlightingthe higher sensitivity to SEs, when normalized to the number of bitsfor the ‘‘Input Register’’; this is mainly due to the fact that the‘‘Input Register’’ block is less protected than the ‘‘XOR-matrix’’ dueto the SEs originating in the buffers connected to the input pads.

A. Candelori et al. / Nuclear Instruments and Methods in Physics Research A 626–627 (2011) 82–89 89

The TMR architecture offers a better radiation hardness than theother two radiation-tolerant schemes, if we limit our analysis to SoftError events in the core of the circuit, i.e. the ‘‘XOR-matrix’’, thanks tothe three times replica of the circuit, which give a more robustprotection. On the contrary, if we consider the Soft Errors in the inputpads of the circuit, i.e. in the ‘‘Input Register’’ block, the TTR architecturepresents better radiation hardness than the other two radiation-tolerant schemes, due to the triple sampling of the primary inputs.

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