Fast $V_{\rm TH}$ Transients After the Program/Erase of Flash Memory Stacks With High$k$ Dielectrics

$: Fast $V_{\rm TH}$ Transients After the Program/Erase of Flash Memory Stacks With High$k$ Dielectrics$
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 3, MARCH 2011 631

Fast VTH Transients After the Program/Erase ofFlash Memory Stacks With High-k Dielectrics

María Toledano-Luque, Robin Degraeve, Mohammed B. Zahid, Ben Kaczer, Pieter Blomme, Jorge A. Kittl,M. Jurczak, Jan Van Houdt, Senior Member, IEEE, and Guido Groeseneken, Fellow, IEEE

Abstract—A fast response technique is developed to investigatethe short-term postprogram and post-erase discharge in Flashmemory devices. The procedure is based on fast VTH-evaluationmethods developed for bias temperature instability and providesthe transient characteristics after 20 ms under the program orerase conditions. The following different structures are investi-gated: 1) SiO2/high-k stacks; 2) charge trap memories; 3) andfloating gate memories. Dielectrics targeted for Flash memoryapplications are used as charge trap layers and interpoly di-electrics. In this paper, we show results on Al2O3, DyScO, GdScO,and hexagonal and perovskite LuAlO. The postprogram andpost-erase curves hold useful information about the dielectricproperties and are used as a fast screening technique for alterna-tive materials.

Index Terms—Charge trap memory, high-k dielectrics,TaN–AlO–SiN–oxide–Si (TANOS), trap characterization.

I. INTRODUCTION

A GREAT effort has been devoted in the last years towardthe reduction of the feature size of the NAND Flash

memories while trying to avoid the loss of gate couplingcapacitance. The introduction of high-k materials in the 40-nmnode may mitigate this problem, but below this featuresize, the crosstalk among neighbors may require the intro-duction of charge trapping devices. From this perspective,new innovations have been introduced in the form of thesilicon–oxide–nitride–oxide–silicon (SONOS) architecture toenlarge the program/erase (P/E) window and improve retention.SONOS devices rely on the hole tunneling for erasing, whichrequires a reduction of the thickness of the SiO2 tunneling layerto 2 nm or less in order to speed the erase operation, but withsuch thin SiO2 layers, poor data retention is unavoidable. Oneof the alternatives to circumvent this concern while keeping

Manuscript received October 1, 2010; accepted November 30, 2010. Date ofpublication January 24, 2011; date of current version February 24, 2011. Thework of M. Toledano-Luque’s was supported in part by the Spanish Ministryof Education and Science under Contract TEC2010-18051 and in part by theGrant Program “José Castillejo” (ref. JC2009/00052). The review of this paperwas arranged by Editor S. Deleonibus.

M. Toledano-Luque is with the Interuniversity Microelectronics Center,3001 Leuven, Belgium, on leave from the Departamento Física AplicadaIII, Universidad Complutense de Madrid, 28040 Madrid, Spain (e-mail:[email protected]).

R. Degraeve, M. B. Zahid, B. Kaczer, P. Blomme, J. A. Kittl, M. Jurczak, andJ. Van Houdt are with Interuniversity Microelectronics Center, 3001 Leuven,Belgium.

G. Groeseneken is with Interuniversity Microelectronics Center, 3001Leuven, Belgium, and also with the Department of Electrical Engineering(ESAT), Katholieke Universiteit Leuven, 3000 Leuven, Belgium.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2010.2100821

a thick (4-nm) SiO2 tunneling layer is the introduction ofhigh-k/metal gate. This increases the electric field through thetunneling oxide during the erase operation. However, the lossof charge to the gate turns up as a significant issue when thesealternative dielectrics are used [1]–[3].

Conventional retention tests are long-term/high-temperatureexperiments showing the charge loss by leakage mechanismsthrough tunnel or top oxide layers [4]. However, immediatelyafter the program and the erase, there is also a fast transientVTH shift, which is related to discharging phenomena in thedielectrics. In order to observe this transient, fast time-resolvedVTH-shift measurements are required.

In a previous paper [5], we introduced the methodology tomeasure these fast postprogram and fast post-erase transientsand the involved discharging mechanisms. We also showed howto extract information about the dielectric defect density profilein SiO2/high-k and charge trap memories based on Al2O3. Itwas also highlighted that this technique cannot provide quanti-tative information about the energy position nor the density ofthe traps; it presents several advantages. First, it does not needdedicated structures unlike trap spectroscopy by charge andinjection and sensing (TSCIS) that is applied to SiO2/high-kstacks with thin (1-nm) SiO2 interface layer [6] and photo-depopulation spectroscopy (PDS) that needs transparent elec-trodes [7]. Second, it is a time-efficient technique useful forperforming a fast evaluation of new materials. Third, it allowsthe scanning of electron traps below the Si conduction band.

In this paper, a detailed explanation of the technique ispresented in Section II, and the structures under study aredescribed in Section III. Afterward, the fast discharge techniqueis applied to different structures: SiO2/high-k stacks in orderto understand the discharging mechanisms in Al2O3, GdScO,DyScO, and LuAlO high-k materials (see Section IV); floatinggate memories with Al2O3, GdScO, and DyScO as interpolydielectrics (see Section V); and charge trap memories withAl2O3 and LuAlO as blocking layers (see Section VI). Finally,we summarize the conclusions of this work in Section VII.

II. MEASUREMENT METHODOLOGY

The methodology for measuring fast postprogram and post-erase transients is based on the previously bias temperatureinstability experimental procedure [8]. The main difference liesin using the gate capacitance CG to follow the threshold voltageVTH shift instead of the drain current ID. The advantage of thisapproach is that simple capacitors can be used in the experimentin place of complete transistors.

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632 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 3, MARCH 2011

Fig. 1. Measurement procedure of the PPD technique. (a) A program voltageVPROG is applied to the gate for 1 s. Afterward, the VG is switched to 0 Vto study the PPD transient. During the entire process, the VG is interrupted tomonitor the gate capacitance CG at VSENSE. The change of CG is convertedto VTH shift by means of the initial CG–VG curve, as shown in (b) and (c).

Fig. 1 shows the measurement sequence of the techniquein the case of postprogram discharge (PPD). The stack understudy is incorporated as the gate dielectric of an n-channelmetal–oxide–semiconductor capacitor with p-junction. A se-quence of positive voltage pulses VPROG with exponentiallyincreasing length from tPROG = 20 ms to 1 s is applied to thegate. In between the pulses, the gate voltage VG is switchedfor a short time of 20 ms to the sense voltage VSENSE, whichis chosen so that CG strongly varies around VSENSE, i.e., aboutthe flatband voltage of the devices after programming. This pro-cedure assures that the sense voltage is lower than the thresholdvoltage of the devices, minimizing the effect of these pulses.

Afterward, VG is fixed to 0 V and switched to VSENSE formonitoring the fast transients immediately after the program.

The CG measured at VSENSE is converted to VTH shift usingthe reference CG–VG curve obtained on the fresh device.

Since the transient shown in Fig. 1 is caused by the dischargeof dielectric traps, we named our technique PPD. Similarly,post-erase discharge (PED) is defined using a sequence ofnegative voltage pulses at VERASE in the first second.

A single instrument Agilent E4980A Precision inductance–capacitance–resistance meter is used to apply the gate voltageVG and measure the gate capacitance CG. Due to this simplesetup, the charging and discharging phases can be registeredby interrupting the gate voltage only for 20 ms. This is a shortperiod of time compared with the conventional setups that needat least 1 s to track the VTH.

III. SAMPLE DESCRIPTION

SiO2/high-k, floating gate, and charge trap capacitors witha gate area of 50 × 50 µm2 and p-junction were fabricatedon 300-mm wafers. The description of the evaluated stacks isshown in Table I. For the stacks with Al2O3, different SiO2

thicknesses were used to get insight into the main mechanismsof VTH shift after the program and the erase. For comparison,other alternative high-k dielectrics with potential use in thefloating gate (DyScO and GdScO) and charge trap (LuAlO)memories were also evaluated [9], [10].

SiO2 tunnel oxide was thermally grown by in situ steamgeneration procedure. Low-pressure chemical vapor depositionSiN of 6 nm was used as a trapping layer in the charge trapmemory stacks. Interuniversity Microelectronics Center clean[11] was used as a pretreatment before the interpoly dielectricdeposition in the floating gate memory stacks. High-k layerswere grown by either atomic layer deposition (Al2O3 andhexagonal and perovskite LuAlO) or metal–organic chemicalvapor deposition (GdScO and DyScO). Further details of thedeposition conditions can be found elsewhere [12]–[14]. For thestacks with Al2O3, different post-deposition annealing treat-ments were evaluated: 1100 ◦C O2 or 1000 ◦C N2. Physicalvapor deposition (PVD)-TaN was used as a metal gate for theSiO2/high-k stacks and the charge trap memories, and PVD-TiN was used for the floating gate memories.

Note that the thickness of the high-k layers was adjusted toobtain similar equivalent oxide thickness (EOT) for the high-kdielectrics. Therefore, when stacks with the same total EOT areprogrammed at fixed VPROG, the same voltages drop throughtunnel oxide, trapping layer, and high-k layers, independentlyof the high-k material.

IV. UNDERSTANDING THE DISCHARGE MECHANISMS

ON SiO2/HIGH-k STACKS

In order to understand the trapping and detrapping mecha-nisms in high-k dielectrics, we first apply the technique to two-layer stacks formed by SiO2 and Al2O3. Fig. 2(a) shows VTH

shift as a function of tPROG and tPPD measured on a 2/10-nmSiO2/Al2O3 stack. The band diagrams of the stack during theprogram and postprogram conditions are given in Fig. 2(c) and(d), respectively.

During the program, the positive VTH shift is due to theelectron trapping at the SiO2/Al2O3 interface and in the Al2O3

TOLEDANO-LUQUE et al.: FAST VTH TRANSIENTS AFTER P/E OF FLASH MEMORY STACKS 633

TABLE IDEVICE SPLIT TABLE. SiO2/HIGH-k, FLOATING GATE, AND CHARGE TRAP MEMORY STACKS ARE EXAMINED IN THIS PAPER

Fig. 2. Program transients and PPD curves for the SiO2/Al2O3 stacks with (a) 2-nm and (b) 3-nm SiO2 layers. Note that VPROG was chosen to keep the sameelectric field in both stacks. The band diagrams during (c) the program and (d) postprogram conditions shown in (a) for the 2-nm SiO2/Al2O3 stack, togetherwith the mechanisms of trapping/detrapping of charge. At these program conditions, the electron injection level is above the high-k conduction band.

bulk, i.e., mechanism (1). At a fixed program field, the programlevel depends on the trap density. Note that a VTH shift of about4 V is reached after 1 s under the program conditions, pointingto a significant trap density. In parallel to this process, electrondetrapping from deep levels of the Al2O3 to the metal gate ishappening due to the high electric field [15], i.e., mechanism(2). Since this discharge is close to the gate, it has only a smalleffect on VTH.

In the discharge phase at VG = 0 V, we already observe, after20 ms, a clear VTH drop [see drop (3) in Fig. 2(a)]. This fasteffect is due to either the tunneling back of electrons from theSiO2/Al2O3 interface traps to the substrate, i.e., mechanism(3a) in Fig. 2(c), and/or the electron detrapping from Al2O3

shallow traps to the gate, i.e., mechanism (3b) in Fig. 2(c). Todiscriminate between the two mechanisms, a stack with theSiO2 thickness increased to 3 nm was measured in order to


Fig. 3. Program transients and PPD curves for the (a) SiO2/Al2O3 and (b) SiO2/DyScO (65% Dy) stacks with 1-nm SiO2. At this program condition, theelectron injection level is below the high-k conduction band, explaining the lower ΔVTH during the program with respect to Fig. 2. Since the EOT of theSiO2/Al2O3 and SiO2/DyScO stacks is identical, the voltage drops through SiO2, and the high-k are the same for the both stacks at fixed VPROG. In line withthe interpretation presented in Fig. 2, the lower VTH drop for DyScO indicates a lower DT at the interface SiO2/high-k; however, the steeper slope at longerdischarging times points to a higher bulk trap density and/or shallower energy level.

Fig. 4. TSCIS maps for (a) Al2O3 and (b) DyScO (65% Dy) confirm the following interpretation given in Fig. 3: 1) the DyScO traps are placed in the bulk andnot close to the interface; and 2) the DyScO bulk traps have both a higher density and shallower energy level.

suppress the electron backtunneling. The corresponding pro-gram transient and PPD curve for this stack (3/10-nmSiO2/Al2O3) are shown in Fig. 2(b). Note that the VPROG

was adjusted to keep the same electric field in both structures.Since the thicker SiO2 layer eliminates the VTH drop [seeFig. 2(b)], we conclude that the tunneling-back mechanism (3a)is dominant in the SiO2/Al2O3 stacks with SiO2 equal to orthinner than 2 nm. Thus, a significant amount of charge isaccumulated close to the interface between both dielectrics.

Remarkably, a slight positive shift after the program in the3/10-nm SiO2/Al2O3 stack is observed in Fig. 2(b). Thispositive VTH shift indicates either the drift of electrons towardthe substrate or electron trapping in a deep Al2O3 energy levelclose to the gate, i.e., mechanism (6), which was previously dis-charged during the program conditions, i.e., mechanism (2). Bymeans of a new developed technique named gate-sense TSCIS(GS-TSCIS), the traps placed in the Al2O3 close to the gatewere scanned. From this technique, we found that a high densityof traps is aligned with the work function of the metal gate, andproduces an increase in the VTH after programming [15].

After the initial drop at VG = 0 V, the discharge of traps fromthe bulk of the high-k continues, i.e., mechanisms (4) and (5) inFig. 2(d). The PPD rate is determined by both the trap densityand the trap energy level. This is clearly evidenced by compar-ing a 1/10-nm SiO2/Al2O3 stack with a 1/22-nm SiO2/DyScO(65% Dy) stack (see Fig. 3) at fixed VPROG. The larger PPD

rate for DyScO suggests either a higher bulk trap volumedensity DT or shallower defects. Since PPD is an accumulativetechnique, we cannot distinguish between both effects. In orderto gain insight, the TSCIS maps [7] were registered for bothstacks, as shown in Fig. 4. In the TSCIS maps, the trap densityis plotted as a function of both the distance from the interfaceand the energy position measured from the Si conduction bandin a flatband condition. The TSCIS measurements show that incomparison with Al2O3 [see Fig. 4(a)], DyScO [see Fig. 4(b)]has both higher bulk trap density and shallower energy position,thus explaining the steeper discharge transient in Fig. 3(b).

Moreover, the TSCIS maps (see Fig. 4) corroborate ourinterpretation of the PPD curves (see Fig. 3) so far. First, notethat the VTH drop at the start of the PPD is lower for DyScOcompared with Al2O3, indicating a reduced SiO2/high-kinterface trap density, which is in agreement with the TSCISresults.

Fig. 5(a) shows the program transients and the PPD curvesfor DyScO with three different compositions. From Fig. 5(a),two observations are made: 1) there is no significant VTH dropafter the 1-s program, indicating a low SiO2/DyScO interfacetrap density; and 2) the PPD rate is lower for 35% Dy, indicatinga reduced electron trap density compared with higher Dy con-centrations. The TSCIS confirms these conclusions (not shownhere). However, the PPD rate in all the DyScO samples is stillhigher than in Al2O3 [see Fig. 3(a)].


Fig. 5. Program transients and PPD curves for the (a) SiO2/DyScO stacks and the (b) SiO2/GdScO stacks with different compositions. Thicknesses of the high-klayers were chosen to keep the same EOT in all the stacks, so the voltage drops through SiO2, and high-k are the same for the six stacks.

Fig. 6. Erase transient and PED curves for the SiO2/Al2O3 and SiO2/LuAlOstacks with 1-nm SiO2. Conversely to LuAlO, negative VTH shift is observedfor Al2O3.

The program transients and the PPD curves for GdScO [seeFig. 5(b)] are similar to those of DyScO. However, the VTH shiftreached during the program conditions is higher, suggesting ahigher total trap density in the stack. Since we do not observe aclear VTH drop after program state, we conclude that the trapsare in the bulk of the high-k material.

In both the DyScO and GdScO cases, the bulk traps have ahigher density of shallow traps than Al2O3. Since the shallow-trapped electrons move out faster than the deep ones, theretention will be an issue to overcome if these materials areused as interpoly dielectrics in the floating gate memories or asblocking dielectrics in the charge trap memories [16]. Indeed,the higher discharge rate for GdScO results in worse dataretention with respect to DyScO (not shown here).

Similar to PPD, Fig. 6 shows the erase transients and PEDcurves for the SiO2/Al2O3 and the SiO2/LuAlO stacks. Unex-pectedly, the behavior of the curves is opposite. Conversely toAl2O3, the LuAlO erase transient presents a positive VTH shiftdue to electron gate injection.

However, for Al2O3, the negative VTH shift can only beexplained, assuming electron detrapping from a defect band inAl2O3 to the substrate. In order to strengthen this interpretation,the erase transients and PED curves were registered for thestacks with 10-nm Al2O3 and different SiO2 thicknesses (seeFig. 7). Observe that VERASE was adjusted to obtain the sameelectric field (in uncharged state). Remarkably, for identicalinjection field, a larger negative VTH shift after the 1-s eraseis observed for a thicker SiO2 layer. This can be explained byelectron detrapping from Al2O3 deep traps to the Si conductionband, as shown in Fig. 8. The larger voltage drop over a thicker

Fig. 7. Erase transients and PED curves for the SiO2/Al2O3 stacks with 1-,2-, and 3-nm SiO2 layers. Note that VERASE was varied to keep the sameelectric field for the three stacks. The thicker the SiO2 layer, the larger thenegative VTH shift.

Fig. 8. Band diagrams during the erase for the SiO2/Al2O3 stacks with1- and 3-nm SiO2 thicknesses under the erase conditions presented in Fig. 7.

SiO2 layer enables the emission of the electrons trapped in deepAl2O3 energy levels to the silicon conduction band, as shownin Fig. 8. Conversely, for the thinner SiO2 layer, the energylevel of the trapped electrons is below the Si conduction bandexplaining the lower erase level reached. However, we cannotdiscard an analogous explanation assuming a defect band forthe holes in the Al2O3 above the silicon valance band. However,since the tunneling probability for the holes is quite reduced,compared to the electrons, we inclined toward the formerexplanation. Additionally, this interpretation has recently beenconfirmed by PDS and two-pulse capacitance–voltage spec-troscopy on samples with similar processing conditions [17].


Fig. 9. Erase transients and PED curves for the (a) SiO2/DyScO and (b) SiO2/GdScO stacks with different compositions. (a) Strong suppression of electrondetrapping/hole injection is observed for DyScO with 35% Dy composition. (b) A significant electron detrapping from high-k is observed for the threecompositions.

Fig. 10. (a) Program transient and PPD curve and (b) erase transient and PEDcurve for a floating gate stack with Al2O3 as an interpoly dielectric. Note theimportant overshoot after both the program and erase conditions.

Fig. 9 shows the PED measurements for DyScO and GdScOwith different compositions. As is the case for Al2O3, bothmaterials present a negative VTH shift when a negative voltageis applied to the gate. The PED measurements for DyScO[see Fig. 9(a)] show, surprisingly, no significant VTH shift in35% Dy, indicating no electron traps with deep energy level.All observations suggest a structural difference between the35% Dy and higher Dy concentrations. This is confirmed byphysical analysis demonstrating that only for 35% Dy that nosilicate was formed [18]. The PED curves for GdScO [seeFig. 9(b)] show an important electron detrapping for all threecompositions. Note that the VTH shift reaches 1.2 V for thelower concentration of Gd (35%). Conversely to DyScO, thePED curves do not show the total annihilation of deep electrontraps for 35% Gd, suggesting the silicate formation is strongerfor GdScO than for DyScO.

Fig. 11. (a) Program transients and PPD curves and (b) erase transients andPED curves for floating gate stacks with DyScO and GdScO as interpolydielectrics.

V. APPLICATION TO THE FLOATING GATE MEMORIES

PPD and PED can also be successfully applied to the floatinggate stacks, i.e., stacks with poly-Si floating gate incorporatedbetween the SiO2 tunneling oxide and the top dielectric. Fig. 10presents the transient characteristics during the program and theerase and the PPD and PED curves for a floating gate memorystack with 10-nm Al2O3 as an interpoly dielectric. In both theprogram and erase cases, the curves show a clear overshootwhen VG is switched to 0 V. Note that this behavior was alsoobserved in the previous section [see Fig. 2(b)] in the two-layer stacks when the SiO2 layer was 3 nm. This overshoot isdue to the charge and discharge of deep traps in Al2O3 locatedclose to the gate that produce an inherent instability of the VTH

shift during the first seconds after the P/E of the stack. It isworth noting that this instability can be a cause of concern if


Fig. 12. Program transients and PPD curves for the SiO2/SiN/Al2O3 stacks annealed in O2 and N2 atmospheres with (a) 4- and (b) 7-nm SiO2 layers. LargerVTH shift is observed for an O2-annealed sample due to the higher trap density in Al2O3. Therefore, the bulk traps in Al2O3 help to enlarge the P/E window.

alternative dielectrics are introduced in multilevel applications.For comparison, the technique was applied to floating gatedevices with DyScO and GdScO as interpoly dielectrics. Fig. 11shows the PPD and PED curves. Note that the program level[see Fig. 11(a)] reached after 1 s under the program conditionsis larger for the scandates than it is for Al2O3. The largerdielectric constant of these scandates, compared with Al2O3,produces a larger drop of electric field through SiO2, thus boost-ing the program speed. In addition, the overshoot at the start ofthe discharge phase is reduced with respect to Al2O3, pointingto a reduced trap density in deep levels close to the gate for thesematerials. However, the high density of shallow traps displayedby these materials (see Section IV) causes an unacceptable lossof charge from the floating gate, i.e., poor retention. Comparingthe PPD curves for both scandates, we observe an earlier lossof charge for the stack with GdScO, in agreement with theconclusion obtained in the previous section (see Fig. 5).

Finally, note that the erase level [see Fig. 11(b)] reached inthe scandate stacks is lower than in the stack with Al2O3. This isrelated to the lower band gap in these materials [19] comparedwith Al2O3, resulting in a lower barrier for electron injectionfrom the gate.

VI. APPLICATION TO SIO2/SIN/HIGH-kCHARGE TRAP MEMORIES

PPD was also applied to a 4/6/10-nm SiO2/SiN/Al2O3

memory stack. In Fig. 12(a), the data for the stacks annealedin O2 and N2 atmospheres are shown. After 1 s in the programconditions, the VTH shift for O2 PDA is about 1 V larger thanfor N2 PDA. It is worth stressing that the program transientand the PPD transient for the samples annealed in nitrogenatmosphere at 1000 ◦C and 1100 ◦C overlap, indicating thatthe differences observed in Fig. 12(a) are due to the atmosphereand not to different annealing temperature. Therefore, the keyfactor among these samples is the annealing atmosphere. Theband diagram of the structure during the program conditions inFig. 13(a) shows that during the program, electrons are injectedin SiN and Al2O3, i.e., mechanism (1), causing a positive VTH

shift. Additionally, electron emission from deep Al2O3 trapsclose to gate is taking place, i.e., mechanism (2).

The difference in the VTH shift for the two annealingprocesses during the program conditions is also observed whennitride is left out of the stack (see Fig. 14). This indicates that

Fig. 13. Band diagrams for the SiO2/SiN/Al2O3 stack with 4-nm SiO2

during the (a) program and (b) PPD conditions shown in Fig. 12(a).

Fig. 14. Program transients and PPD curves for the SiO2/Al2O3 stacksannealed in N2 and O2 atmospheres. A larger VTH shift after the 1-s programis observed for an O2-annealed sample and a larger PPD rate. These indicate ahigher bulk trap density for the O2 annealing conditions.

the nitride layer is not the cause of the difference. Furthermore,in Fig. 14 the PPD rate for O2-annealed Al2O3 is larger.These observations indicate a higher bulk trap density in theO2-annealed Al2O3 (as confirmed by the TSCIS). We concludethat the Al2O3 traps help to open the P/E window on TaN–AlO–SiN–oxide–Si (TANOS) devices. In other words, Al2O3

is not only a blocking layer but partly also a trapping layer.In Fig. 12(a), after VG is switched to 0 V, VTH positively con-

tinues shifting during ∼10 s. This effect is attributed to electrontrapping near the gate of the Al2O3 deep traps, i.e., mecha-nism (3) in Fig. 13(b). To reinforce this explanation, we per-formed a new experiment in a stack composed of 4/6/5/12-nmSiO2/SiN/Al2O3/LuAlO in order to avoid the direct contactof Al2O3 with the metal gate. As shown in Fig. 15, the fastVTH shift and the overshoot of the curve is reduced, indicatinga reduction of deep traps aligned with the work function of the


Fig. 15. Program transients and PPD curves for the SiO2/SiN/Al2O3 andSiO2/SiN/Al2O3/LuAlO stacks. Faster positive VTH shift after 20 ms atVG = 0 V and larger overshoot for Al2O3 are observed. These indicate ahigher trap density at deep energy levels aligned with the metal gate for Al2O3.

gate for LuAlO. These fast processes produce an inherent VTH

instability just after program that has to be taken into accountin the use of these TANOS stacks in multilevel applications,where a precise control of the program level is mandatory [20].Further treatments to cure the traps between alumina and themetal gate may mitigate this instability.

After 10 s, a negative VTH shift, indicating electron detrap-ping, becomes predominant. As shown in Fig. 13(b), electrondetrapping to both the substrate and the gate (mechanisms(5) and (6), respectively) can produce this negative VTH shift.To prevent electron backtunneling, i.e., mechanism (5), weincreased the SiO2 thickness to 7 nm. The corresponding PPDresults [see Fig. 12(b)] still show a negative VTH shift after10 s for N2 PDA, whereas for O2 PDA, the programmedlevel remains approximately stable for 10 000 s. The physicalcharacterization performed on similar processing conditionsdemonstrated that there are no striking morphological differ-ences between the two annealing processing [14]. We concludethat a significant electron detrapping to the gate is occurringfor N2 PDA Al2O3, which is likely due to electron dischargingfrom shallow traps [see Fig. 4(a)], compared with the O2 PDAsample where electrons are stored at deeper energy levels.

For comparison, Fig. 16 shows the program transients andthe PPD curves for the charge trap memories with LuAlO inhexagonal and perovskite phases. Remarkably, an anomalouserase is produced for hexagonal LuAlO, i.e., a positive shiftwith respect to the initial VTH is observed. This positive shiftis due to the reduced band gap of hexagonal LuAlO, which isinsufficient to avoid electron injection from the gate. On theother hand, a reasonable P/E window is reached in the case ofperovskite phase LuAlO.

VII. CONCLUSION

We have measured and have explained the fast VTH transientsafter charging the dielectrics by electrons (program) and holes(erase) in a wide variety of nonvolatile memory gate stacks.These transients provide qualitative information about the di-electric properties and can be used as a fast screening techniquefor alternative materials. When applied to Flash memory stacks,the role of high-k traps is revealed. Proper modeling of opera-tion and retention of Flash memories can only be achieved byconsidering the charge traps in both nitride and high-k layers.

Fig. 16. (a) Program transients and PPD curves and (b) erase transients andPED curves for the charge trap memory stacks with LuAlO in hexagonal andperovskite phases. Anomalous erase is observed for hexagonal LuAlO due toelectron injection from the gate because of its reduced band gap.

ACKNOWLEDGMENT

The authors would like to thank the Interuniversity Mi-croelectronics Center (IMEC) Device Reliability and Electri-cal Characterization (DRE) and Nonvolatile Memory Groupsand AMSIMEC for helpful discussions and input throughoutthis paper. This work was performed under IMEC nonvolatilememory program that is part of IMEC core partner affiliationprogram.

REFERENCES

[1] S.-C. Lai, H.-T. Luea, J.-Y. Hsieh, M.-J. Yang, Y.-K. Chiou, C.-W. Wu,T.-B. Wu, G.-L. Luo, C.-H. Chien, E.-K. Lai, K.-Y. Hsieh, R. Liu, andC.-Y. Lu, “A study on the erase and retention mechanisms for MONOS,MANOS, and BE-SONOS non-volatile memory devices,” in Proc. VLSITechnol., Syst. Appl., 2007, pp. 23–25.

[2] K. Kim, “Technology for sub-50 nm DRAM and NAND flash manufac-turing,” in IEDM Tech. Dig., 2005, pp. 323–326.

[3] E. Vianello, F. Driussi, A. Arreghini, P. Palestri, D. Esseni, L. Selmi,N. Akil, M. J. Van Duuren, and D. S. Golubovic, “Experimental andsimulation analysis of program/retention transients in silicon nitride-basedNVM cells,” IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 1980–1990,Sep. 2009.

[4] R. Liu, H.-T. Lue, K. C. Chen, and C.-Y. Lu, “Reliability of barrierengineered charge trapping devices for sub-30 nm NAND flash,” in IEDMTech. Dig., 2009, pp. 745–748.

[5] M. Toledano-Luque, R. Degraeve, M. B. Zahid, B. Kaczer, J. Kittl,M. Jurczak, G. Groeseneken, and J. Van Houdt, “Resolving fast VTH

transients after program/erase of flash memory stacks and their relationto electron and hole defects,” in IEDM Tech. Dig., 2009, pp. 749–752.

[6] R. Degraeve, M. Cho, B. Govoreanu, B. Kaczer, M. B. Zahid,J. Van Houdt, M. Jurczak, and G. Groeseneken, “Trap Spectroscopy byCharge Injection and Sensing (TSCIS): A quantitative electrical techniquefor studying defects in dielectric stacks,” in IEDM Tech. Dig., 2008,pp. 775–778.

[7] V. V. Afanas’ev and A. Stesmans, “Photoionization of silicon particlesin SiO2,” Phys. Rev. B, Condens. Matter, vol. 59, no. 3, pp. 2025–2034,Jan. 1999.


[8] B. Kaczer, T. Grasser, P. J. Roussel, J. Martin-Martinez, R. O’Connor,B. J. O’Sullivan, and G. Groeseneken, “Ubiquitous relaxation in BTIstressing—New evaluation and insights,” in Proc. IEEE IRPS, 2008,pp. 20–27.

[9] B. Govoreanu, J. A. Kittl, J. De Vos, A. Rothschild, P. Blomme,D. Wellekens, D. Ruiz Aguado, M. Jurczak, and J. Van Houdt, “The flashmemory cell for the nodes to come: Material requirements from a deviceperspective,” ECS Trans., vol. 19, no. 2, pp. 649–668, May 2009.

[10] J. A. Kittl, K. Opsomer, M. Popovici, N. Menou, B. Kaczer, X. P. Wang,C. Adelmann, M. A. Pawlak, K. Tomida, A. Rothschild, B. Govoreanu,R. Degraeve, M. Schaekers, M. Zahid, A. Delabie, J. Meersschaut,W. Polspoel, S. Clima, G. Pourtois, W. Knaepen, C. Detavernier, V. V.Afanas’ev, T. Blomberg, D. Pierreux, J. Swerts, P. Fischer, J. W. Maes,D. Manger, W. Vandervorst, T. Conard, A. Franquet, P. Favia, H. Bender,B. Brijs, S. Van Elshocht, M. Jurczak, J. Van Houdt, and D. J. Wouters,“High-k dielectrics for future generation memory devices,” Microelec-tron. Eng., vol. 86, no. 7–9, pp. 1789–1795, Jul.–Sep. 2009.

[11] F. De Smedt, C. Vinckier, I. Cornelissen, S. De Gendt, and M. Heyns, “Adetailed study on the growth of thin oxide layers on silicon ozonoted sol-utions,” J. Electrochem. Soc., vol. 147, no. 3, pp. 1124–1129, Mar. 2000.

[12] A. Rothschild, L. Breuil, G. Van Den Bosch, O. Richard, T. Conard,A. Franquet, A. Cacciato, I. Debusschere, M. Jurczak, J. Van Houdt,J. A. Kittl, U. Ganguly, L. Date, P. Boelen, and R. Schreutelkamp, “Postdeposition anneal of Al2O3 blocking dielectric for higher performanceand reliability of TANOS flash memory,” in Proc. ESSDERC, Athens,Greece, 2009, pp. 272–275.

[13] R. Thomas, P. Ehrhart, M. Roeckerath, S. Van Elshocht, E. Rije,M. Luysberg, M. Boese, J. Schubert, M. Caymax, and R. Waser, “Liquidinjection MOCVD of dysprosium scandate films: Deposition character-istics and high-k applications,” J. Electrochem. Soc., vol. 154, no. 7,pp. G147–G154, May 2007.

[14] L. Breuil, C. Adelmann, G. Van Den Bosch, A. Cacciato, M. B. Zahid,M. Toledano-Luque, A. Suhane, A. Arreghini, R. Degraeve, S. VanElshocht, I. Debusschere, J. Kittl, M. Jurczak, and J. Van Houdt, “Opti-mization of the crystallization phase of rare-earth aluminates for blockingdielectric application in TANOS type flash memories ,” in Proc. 40th Eur.Solid-State Device Res. Conf., Seville, Spain, 2010, pp. 440–443.

[15] R. Degraeve, M. Zahid, G. Van Den Bosch, P. Blomme, L. Breuil,B. Kaczer, M. Mercuri, A. Rothschild, A. Cacciato, M. Jurczak,G. Groeseneken, and J. Van Houdt, “Explanation of anomalous erasebehavior and the associated device instability in TANOS flash using newtrap characterization technique,” in Proc. SSDM, 2009, pp. 428–429.

[16] H.-T. Lue, S.-C. Lai, T.-H. Hsu, Y.-H. Hsiao, P.-Y. Du, S.-Y. Wang,K.-Y. Hsieh, R. Liu, and C.-Y. Lu, “A critical review of charge-trappingNAND flash devices,” in Proc. 9th ICSICT , 2008, pp. 807–810.

[17] M. B. Zahid, D. Ruiz Aguado, R. Degraeve, W. C. Wang, B. Govoreanu,M. Toledano-Luque, V. V. Afanas’ev, and J. Van Houdt, “Applying com-plementary trap characterization technique to crystalline γ-phase- Al2O3

for improved understanding of non-volatile memory operation and reli-ability,” IEEE Trans. Electron Devices, vol. 57, no. 11, pp. 2907–2916,Nov. 2010.

[18] S. Van Elshocht, C. Adelmann, T. Conard, A. Delabie, A. Franquet,L. Nyns, O. Richard, P. Lehnen, J. Swerts, and S. De Gendt, “Silicateformation and thermal stability of ternary rare earth oxides as high-kdielectrics,” J. Vac. Sci. Technol. A, Vac. Surf. Films, vol. 26, no. 4,pp. 724–730, Jul. 2008.

[19] M. Raekers, K. Kuepper, S. Bartkowski, M. Prinz, A. V. Postnikov,K. Potzger, S. Zhou, A. Arulraj, N. Stusser, R. Uecker, W. L. Yang,and M. Neumann, “Electronic and magnetic structure of RScO3 (R =Sm,Gd,Dy) from X-ray spectroscopies and first-principles calculations,”Phys. Rev. B, Condens. Matter, vol. 79, no. 12, p. 125 114, Mar. 2009.

[20] B. Kim, S.-J. Baik, S. Kim, J.-G. Lee, B. Koo, S. Choi, and J.-T. Moon,“Characterization of threshold voltage instability after program in chargetrap flash memory,” in Proc. IEEE IRPS, 2009, pp. 284–287.

María Toledano-Luque was born in Madrid, Spain,in 1980. She received the M.Sc. degree in electricalengineering, the M.Sc. degree in physics, and thePh.D. degree from the Universidad Complutense deMadrid (UCM), Madrid, Spain, in 2003, 2009, and2008, respectively.

In 2003, she became a member of the ThinFilms and Microelectronics Research Group, UCM.In 2007, she was with the Department of AppliedPhysics (Electronics), UCM, as an Assistant Profes-sor. She is currently a Postdoctoral Researcher with

the Interuniversity Microelectronics Center, Leuven, Belgium, working in thefield of advance electrical characterization.

Robin Degraeve received the M.Sc. degree in elec-trical engineering from the University of Gent, Gent,Belgium, in 1992 and the Ph.D. degree from theCatholic University of Leuven, Leuven, Belgium,in 1998.

In 1992, he joined the Complementary Metal–Oxide–Semiconductor (CMOS) Reliability andCharacterization Group, Interuniversity Micro-electronics Center (IMEC), Leuven, where he iscurrently working as a Senior Researcher. His workhas focused on the reliability aspects of thin

insulating layers under electrical stress. His current interests and activitiesinclude hot-carrier-related reliability issues in MOS field-effect transistors, thestudy of the physics of degradation and breakdown phenomena in gate oxidefilms, the reliability of Flash memory devices, the reliability of ultrathin oxideand oxynitride layers for very large scale integration technologies, and thecharacterization and reliability of high-k materials as gate insulators for futureCMOS generations and memory applications.

Mohammed B. Zahid received the UniversityDiploma in electrical and computer science from theUniversity of Technologies (IUT), Cachan, France,in 2001 and the B.S. degree in electrical engineering,the M.S. degree in microelectronics, and the Ph.D.degree in “Characterization of high-k layers as thegate dielectric for MOSFETs” from Liverpool JohnMoores University, Liverpool, U.K., in 2002, 2003,and 2007, respectively.

He was a Postdoctoral Researcher with the Groupof Device Reliability and Electrical Characterization

(DRE), Interuniversity Microelectronics Center, Leuven, Belgium, where heis currently working on high-power-based GaN devices and characterizationof nonvolatile memory (NVM) with alternative high-k dielectrics. His researchinterests include the technology and novel electrical characterization techniquesand reliability for NVM, Flash memory, and GaN high-power devices.

Ben Kaczer received the M.S. degree in physicalelectronics from Charles University, Prague, CzechRepublic, in 1992 and the M.S. and Ph.D. degreesin physics from The Ohio State University (OSU),Columbus, in 1996 and 1998, respectively. For hisPh.D. research on the ballistic-electron emission mi-croscopy of SiO2 and SiC films, he received theOSU Presidential Fellowship and support from TexasInstruments, Inc., Dallas.

In 1998, he was with the Reliability Group,Interuniversity Microelectronics Center (IMEC),

Leuven, Belgium, where his activities have included the research of thedegradation phenomena and reliability assessment of SiO2, SiON, high-k, andferroelectric films, planar and multiple-gate field-effect transistors, circuits, andcharacterization of Ge/III–V and metal–insulator–metal devices. He is currentlya Senior Reliability Scientist with IMEC. He has authored or coauthored morethan 250 journal and conference papers and presented invited papers andtutorials at several international conferences.

Dr. Kaczer received three Best and Outstanding Paper Awards at Interna-tional Reliability Physics Symposium (IRPS) and the Best Paper Award atthe International Symposium on the Physical and Failure Analysis of Inte-grated Circuits (IPFA). He has served or is serving at various functions atthe International Electron Devices Meeting, IRPS, Semiconductor InterfaceSpecialists Conference, International Conference on Informatics and Systems,and Workshop on Dielectric Materials.

Pieter Blomme, biography not available at the timeof publication.


Jorge A. Kittl received the M.Sc. and Ph.D. degreesin applied physics from California Institute of Tech-nology, Pasadena, in 1987 and 1991, respectively.

Between 1991 and 1993, he was a Post-Doc withHarvard University. From 1993 to 2007, he was withTexas Instruments, where he held several positions inresearch and development, manufacturing, and prod-uct businesses. He was a Distinguished Member ofthe Technical Staff leading the research and develop-ment of silicides for several complementary metal–oxide–semiconductor technology nodes and later the

Director of the WW internet audio business unit. He is currently a ChiefScientist with Interuniversity Microelectronics Centre, Leuven, Belgium, withresearch areas in high-k dielectrics, metal gates, and contacting technologiesfor memory and logic applications. He has authored or coauthored about200 technical publications and has presented over 20 invited talks at interna-tional conferences.

M. Jurczak, biography not available at the time ofpublication.

Jan Van Houdt (SM’02) was born in Leuven,Belgium, on June 20, 1963. He received the M.Sc.degree in electrical and mechanical engineeringand the Ph.D. degree in applied sciences fromthe Katholieke Universiteit Leuven, Leuven, in1987 and 1994, respectively. His M.S. thesis dealtwith the degradation of short-channel metal–oxide–semiconductor (MOS) transistors under hot-carrierinjection conditions. His Ph.D. work concentrated onthe physics and characteristics of high injection MOS(HIMOS) Flash memory devices.

After his M.S. thesis, he joined the Interuniversity Microelectronics Center(IMEC), Leuven. In 1990, he invented the HIMOS transistor, which is anovel fast-programmable Flash electrically erasable programmable read-onlymemory cell that has led to a high-performance cost-effective nonvolatilememory technology, on which he holds numerous international patents. In1996, he became responsible for the development and dissemination of Flashmemory technology based on IMEC’s proprietary concepts, including thelicensing and the transfer of these technologies toward four industrial productlines. Since 1999, he has been managing the Memory Group, IMEC. Since2000, he has been also managing IMEC’s Industrial Affiliation Program onAdvanced Memory Technology and expanded it to become one of IMEC’slargest research programs today. He has published more than 160 papers ininternational journals, wrote 2 book chapters, and accumulated more than 140conference contributions (including more than 25 invitations and 5 best paperawards). He has filed more than 50 patent applications worldwide in the areaof nonvolatile memories, out of which 27 patents have been granted so far.His research interests include the physics of semiconductor devices, hot-carrierinjection and degradation phenomena in MOS structures, thin dielectrics,modeling and optimization of the floating gate and nitride nonvolatile memorydevices, physics, and reliability and design aspects of memories in general.

Dr. Van Houdt received the Best Student Paper Award at the 22nd EuropeanSolid-State Device Research Conference in 1992 and the Scientific Award ofthe Royal Academy for Science, Literature and Fine Arts of Belgium in 1995.He serves (or served) on the program and/or organizational committees ofthe IEEE Nonvolatile Semiconductor Memory Workshop; the IEEE ReliabilityPhysics Symposium; the European Solid-State Device Research Conference;the International Conference on Memory Technology and Design (ICMTD);the IEEE International Workshop on Memory Technology, Design and Testing(Taiwan); the Solid-State Devices and Materials Conference; the MaterialsResearch Society Symposium On Nonvolatile Memory Technologies; the IEEEInternational Memory Workshop; the IEEE International Electron DevicesMeeting; and the IEEE Semiconductor Interface Specialists Conference. In2007, he was the General Chairman of the ICMTD.

Guido Groeseneken (F’05) received the M.Sc. de-gree in electrical and mechanical engineering and thePh.D. degree in applied sciences from the KatholiekeUniversiteit (KU) Leuven, Leuven, Belgium, in 1980and 1986, respectively.

In 1987, he joined the Research and Develop-ment Laboratory of Interuniversity MicroelectronicsCenter (IMEC), Leuven, where he is currently re-sponsible for the research in reliability physics fordeep submicrometer complementary metal–oxide–semiconductor (CMOS) technologies. From October

2005 to April 2007, he was responsible for the IMEC Post-CMOS Nanotech-nology Program within IMEC’s core partner research program. Since 2001, hehas been a Professor with the Department of Electrical Engineering (ESAT),KU Leuven, where he is currently the Program Director of the Master inNanoscience and Nanotechnology and is coordinating a European ErasmusMundus Master Program in nanoscience and nanotechnology. He has madecontributions to the fields of nonvolatile semiconductor memory devices andtechnology, reliability physics of very large scale integration technology, hotcarrier effects in MOS field-effect transistors (FETs), time-dependent dielectricbreakdown of oxides, negative-bias-temperature instability effects, electrostaticdischarge protection and testing, plasma-processing-induced damage, electricalcharacterization of semiconductors, and characterization and reliability ofhigh-k dielectrics. He has authored or coauthored more than 500 publicationsin international scientific journals and in international conference proceedingsand has authored six book chapters. He is the holder of ten patents in his fieldsof expertise. Recently, he has been also interested in nanotechnology for post-CMOS applications, such as carbon nanotubes for interconnect applications andtunnel FETs for alternative nanowire devices.

Dr. Groeseneken became an IMEC Fellow in 2007. He has served as atechnical program committee member of several international scientific confer-ences, including the IEEE International Electron Device Meeting (IEDM), theEuropean Solid State Device Research Conference, the International ReliabilityPhysics Symposium, the IEEE Semiconductor Interface Specialists Confer-ence, and the Electrical Overstress/Electrical Static Discharge Symposium.From 2000 to 2002, he acted as the European Arrangements Chair of IEDM.In 2005, he was the General Chair of the Insulating Films on SemiconductorConference, which was organized in Leuven.

Fast $V_{\rm TH}$ Transients After the Program/Erase of Flash Memory Stacks With High$k$ Dielectrics

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