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Transcript of E&TC FY.pdf - Rajarshi Shahu College of Engineering
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
Department of Electronics and
Telecommunication Engineering Structure and Syllabi
F.Y. M. Tech. (2019 Pattern) w.e.f. Academic Year 2020-2021
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 1
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
Department of Electronics and Telecommunication
Engineering
Vision
“
Mission
To entrust the students with fundamentals of Electronics and Telecommunication Engineering for successful carrier
To enable students to pursue higher education, research and promote Entrepreneurship
To serve the nation through techno-social development.
Vision “To create an educational environment to meet the challenges of modern Electronics and Telecommunication engineering industry through state of art technical knowledge and innovative approach”.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 2
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune
University, Pune)
Department of Electronics and TelecommunicationEngineering Program Outcomes (POs)
Engineering Graduates will be able to: 1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering specialization to the solution of complex engineering problems. 2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering sciences. 3. Design/development of solutions: Design solutions for complex engineering problems and design system components or processes that meet the specified needs with appropriate consideration for the public health and safety, and the cultural, societal, and environmental considerations. 4. Conduct investigations of complex problems: Use research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions. 5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools including prediction and modeling to complex engineering activities with an understanding of the limitations. 6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering practice. JSPM’s Rajarshi Shahu College of Engineering Department of IT Engineering 7. Environment and sustainability: Understand the impact of the professional engineering solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development. 8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice. 9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary settings. 10. Communication: Communicate effectively on complex engineering activities with the engineering community and with society at large, such as, being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions. 11.Project management and finance: Demonstrate knowledge and understanding of the engineering and management principles and apply these to one’s own work, as a member and leader in a team, to manage projects and in multidisciplinary environments. 12.Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent and life-long learning in the broadest context of technological change. Department of Electronics and Telecommunication Engineering
Program Specific Outcomes (PSOs) Upon successful completion of UG course in Information Technology, the students will attain following Program Specific Outcomes:
1. Graduate will demonstrate the ability to apply knowledge of Electronics and Telecommunication to identify, formulate and solve Engineering problems useful to society.
2. Graduate will demonstrate an ability to design, implement and analyze various functional elements of Electronics and Telecommunication domain, interpret data and work with multidisciplinary approach.
3. Graduate will demonstrate the analytical and managerial skills with a virtue of continued learning; carry out the professional and entrepreneurial responsibilities in Electronics and Telecommunication Engineering field considering environmental issues.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 3
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to SavitribaiPhule Pune
University,Pune)
Highlights of the Syllabus
Curriculum of Electronics and Telecommunication Engineeringcourse is designed in consultation with
The salient features of curriculum designed in associationwith KPIT, Nayan Electronics and Matrix automations.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 4
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to SavitribaiPhule Pune
University,Pune)
Unique features of the curriculum
1. Curriculum centered at Outcome Based Education: The new Curriculum is based on student-centered instruction models that focus on measuring student performance through outcomes. The outcomes include subject knowledge, industry required skills and attitudes.
2. Emphasize on Advanced courses: The nature of the new curriculum is rigorous and well prescribed so that the students can spend more time on preparation and self-study. This will benefit them to grasp and get expertise in the most effective way.
3. Promote Creativity and Innovation: Along with experiential learning, the curriculum also motivates the students to inculcate creativity and innovation. Apart from conventional lab, the curriculum provides a freedom for students to perform industry assignments, pilot projects, innovative development, etc.
4. Three Tracks in M-Tech: The curriculum provides three tracks in the curriculum as
I. VLSI II. Embedded System II. Signal Processing
5. Industry Induced Internship Program
To support ever demanding industry requirements, the curriculum has included an industry internship with an objective to learn technologies pertaining to their discipline and enhance their technical knowledge with a support of the live platform of Industry.
6. Motivation for Self Learning:
The curriculum also offers a freedom to students to take the initiatives in their learning needs and set the goals with the help of online learning platforms like MOOCs, NPTEL, Swayam, etc.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 5
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune
University,Pune)
F. Y. M. Tech. (VLSI and Embedded Systems)
Semester-I
Course Code
Course
Teaching Scheme Semester Examination Scheme of Marks Credits
TH TU PR ISE (15)
MSE (25)
ESE (60)
TW PR OR TOTAL
TOTAL
EC5101 Digital CMOS Design 4 -- -- 15 25 60 -- -- -- 100 4
EC5102
Embedded System Design
3 -- -- 15 25 60 -- -- -- 100 3
EC5105
Research Methodology and Intellectual Property Rights
3 -- -- 15 25 60 -- -- -- 100 3
EC5103 Elective-I 3 -- -- 15 25 60 -- -- -- 100 3
EC5104 Elective-II 3 -- -- 15 25 60 -- -- -- 100 3
EC5106 Lab Practice I -- -- 4 -- -- -- 50 - 50 100 2
EC5107 Online course/
certification -- -- 4 -- -- -- 50 - 50 100 2
EC5108 Audit Course -- -- -- -- -- -- -- -- -- -- --
Total 16 -- 8 75 125 300 100 - 100 700 20
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 6
F. Y. B. Tech. (Electronics &Telecommunication Engineering) Semester-I
Elective-I Elective-II
Code No. Title Code No. Title
EC5103A IC Design with HDL EC5104A Nan electronics
EC5103B Embedded Automotive System EC5104B Embedded Product Design
EC5103C Image and Video Processing
EC5104C Speech and Audio Processing
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
Name of Audit Courses
EC5108 Technical Paper writing ME5107 Value Education In Engineering
CE5107
Disaster Management CS5108 Constitution of India
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 7
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
S. Y. B. Tech. (Electronics &Telecommunication Engineering)
Semester-II
Course Code
Course
Teaching Scheme
Semester Examination Scheme of Marks Credits
TH TU PR ISE (15)
MSE (25)
ESE (60)
TW PR OR TOTAL TOTAL
EC5109 Analog IC Design 3 -- -- 15 25 60 -- -- -- 100 3
EC5110 Embedded Signal Processor Architecture
3 -- -- 15 25 60 -- -- -- 100 3
ES5104 Advance Engg. Mathematics 4 -- -- 15 25 60 -- -- -- 100 4
EC5111 Elective-III 3 -- -- 15 25 60 -- -- -- 100 3
EC5112 Elective-IV 3 -- -- 15 25 60 -- -- -- 100 3
EC5113 Lab Practice II
-- -- 4 -- -- -- 50 -- 50 100 2
Total 16 -- 4 75 125 300 50 -- 50 600 18
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 8
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
Select Any One
Elective-III Elective-IV
Code No. Title Code No. Title
EC5111A Advanced Signal Processing Technology
EC5112A MEMS and NEMS
EC5111B Artificial Intelligence and
Machine Learning EC5112B Multirate signal Processing
EC5111C Design for Testability EC5112C Industrial IOT
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 9
Subject Code Title Page No Semester -I
EC5101 Digital CMOS Design 11
EC5102 Embedded System Design 14
EC5105 Research Methodology and Intellectual Property Rights 17
EC5103A IC Design with HDL 20
EC5103B Embedded Automotive System 23
EC5103C Image and Video Processing 26
EC5104A Nan electronics 29
EC5104B Embedded Product Design 32
EC5104C Speech and Audio Processing 35
Semester-II
EC5109 Analog IC Design 40
EC5110 Embedded Signal Processor Architecture 43
ES5104 Advance Engineering Mathematics 46
EC5111A Advanced Signal Processing Technology 49
EC5111B Artificial Intelligence and Machine Learning 51
EC5111C Design for Testability 54
EC5112A MEMS and NEMS 57
EC5112B Multirate signal Processing 60
EC5112C Industrial IOT 63
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 10
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
SEMESTER I Syllabus
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 11
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -I [EC5101]: Digital CMOS Design
Teaching Scheme: TH: 04 Hours/Week
Credit 04
Examination Scheme: In Sem. Evaluation: 15 Marks
Mid Sem. Exam. : 25 Marks
End Sem. Exam : 60 Marks
Course Prerequisites: Physical and Fundamental properties of semiconductor devices, Band diagram
concept, Fermi Energy level, p type and n type properties of semiconductor and their junctions.
Course Objective:
1. To learn MOSFET models and layout fundamentals
2. To nurture students understanding in performance parameters of digital CMOS design
3. To understand the delay model
4. To study the advanced trends in MOSFET
Course Outcome:
After successful completion of the course, students will able to:
CO1: Express basic fundamentals of MOSFET to prepare basic gates design using CMOS technology.
CO2: Ability to design different CMOS circuits using various logic families along with circuit layout.
CO3: Ability to use tools for VLSI IC design.
CO4: Express the different types delay of MOSFETs
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 12
Course Contents
UNIT-I MOSFET Models 06 Hours
MOS Capacitance models, MOS Gate Capacitance Model, MOS Diffusion Capacitance Model. Non ideal
I-V Effects, MOSFET equivalent circuits and analysis, Parasitic; Technology scaling; Lambda parameter;
wiring parasitic; SPICE Models
UNIT-II MOSFET Layout 06 Hours
CMOS layout techniques; Transient response. CMOS Technologies: Layout Design Rules CMOS Process
Enhancements: Transistors, Interconnect, Circuit Elements, Beyond Conventional CMOS. CMOS
Fabrication and Layout: Inverter Cross-section, Fabrication Process, Stick Diagrams.
UNIT-III Performance Parameters 08 Hours
Transistor as a switch, Inverter characteristics, Integrated circuit layout: design rules, parasitic, static
CMOS logic: Inverter, NAND and NOR gate, Multiplexers and flip flop, calculate active area on chip.
UNIT-IV RC Delay 08 Hours
Static, dynamic and short circuit power dissipation, Propagation delay, power delay product, Delay
estimation: RC Delay model, linear delay model, logical efforts, parasitic delay, Interconnect:
Resistance, capacitance, delay, cross talk. Design margin.
UNIT-V Circuit Families 08 Hours
Circuit families: static CMOS, Ratioed circuit, Dynamic circuits, Domino logic, NORA logic, Low
power logic design, Techniques for low power, High speed design.
UNIT-VI Advanced Trends 06 Hours
Different types of MOSFETs, Material for performance improvement, Fin FET, Junction less Transistor,
Gate-all-around MOSFET and characteristics.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 13
BOOKS:
Text:
T1: Neil Waste and Kamara, “Principles of CMOS VLSI Design”, 4TH Edition, Education Asia.
T2: S-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, Third Edition,
McGraw-Hill.
References:
R1: M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits: A Design Perspective,
Pearson (Low Price Edition).
R2: S-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, Third Edition,
McGraw-Hill.
R3: Samir Palnitkar, “Verilog HDL – A Guide to Digital Design and Synthesis”, PHI.
R4: Introduction to Nanotechnology, Sulabha Kulkarni.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 14
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech Semester- I (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -I [EC5102]: Embedded System Design
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Prerequisites Course :Fundamentals of Microcontrollers, Basic concepts of operating system with the
concepts of embedded C programming knowledge.
Course Objective:
1. To understand various design issues in embedded systems
2. To apply programming concepts of ARM 9
3. To learn embedded LINUX operating system
4. To make aware of the significance of embedded network processors
Course Outcome:
After successful completion of the course, students will able to:
CO1. Design ARM Processor based Embedded Systems
CO2. Write Programme in Embedded in C
CO3. Design device drivers using Linux operating system
CO4. Understand attributes of Network Protocol.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 15
Course Contents
UNIT-I Introduction to Embedded Systems 07 Hours
Introduction to Embedded Systems: Introduction to Embedded Systems, Architecture of Embedded
System, Design Methodology, Design Metrics, General Purpose Processor, System On chip.
Embedded system design and development:Embedded system design, Life-Cycle Models,
Development tools, Introduction to Development Platform Trends (only introduce IDE, board
Details and Application) Arduino, Beaglebone, Rasberry PI, Intel Galileo Gen 2.
UNIT-II ARM CORTEX series 06 Hours
ARM CORTEX series features, Improvement over classical series, CORTEX ARM processors series,
Features and applications, Survey of CORTEX based controllers from various manufacturers.
UNIT-III ARM-M3 Based Microcontroller LPC1768 08 Hours
ARM-M3 Based Microcontroller LPC1768 Features, Architecture block diagram & its description,
System Control, Clock & Power Control, Pin Connect Block. CMSIS Standard, Bus Protocols Ethernet,
CAN, USB, Bluetooth.
UNIT-IV Embedded Linux 08 Hours
System architecture, BIOS versus bootloader, Booting the kernel, Kernel initialization, Space
initialization, Boot loaders and Storage considerations.
UNIT-V Linux kernel construction 08 Hours
Interrupt and exception, Object interface, Multi-Processor Architecture, Kernel build system,
Obtaining a custom Linux kernel, File systems, Device drivers, Kernel configuration.
UNIT-VI Embedded System Design Case Studies 06 Hours
Design Case Studies like Automated Meter Reading Systems (AMR), Digital Camera, Certification and
documentation: Mechanical Packaging, Testing, reliability and failure analysis, Certification (EMI / RFI)
and Documentation. Study of any two real life embedded products in detail.
BOOKS:
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 16
Text:
T1:Noergaard Tammy, “Embedded Systems Architecture”, Elsevier Publication.
T2:Hallinan Christopher, “Embedded Linux Primer: A Practical Real-World Approach”, Second
Edition, Pearson Education.
References:
R1: Shibu, “Introduction to Embedded Systems”, second edition TMH.
R2: Comer D E, “ Network System Design using Network Process”, PHI. First edition
R3: .Croeley Patrick, Franklin M. A ,Hadimioglu H &Onufryk P Z, ”Network Processor Design,
Issues and Practices”, vol-1-2, Elsevier.
R4:Uyless Black,” Computer Networks-Protocols,StandardsInterfaces”,Second Edition PHI.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 17
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -I [EC5105]: Research Methodology and IPR
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites: This is a mandatory course for PhD students at the Faculty of Engineering. The
basic knowledge of various domains in Electronic.
Course Objective:
1. The Objective of this course is to make students learn and understand basic Concepts of research
methodology.
2. The process of literature review, writing of research report. and forming of practical engineering
problems.
3. designing of its solutions effectively and meaningfully. To understand various aspects of
intellectual property.
Course Outcome:
After successful completion of the course, students will able to:
CO1 : Give an overview of the research methodology and explain the technique of defining a research
problem.
CO2 : Explain carrying out a literature search, its review, developing theoretical and conceptual
frameworks and writing a review.
CO3 : Explain various research designs and their characteristics
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 18
CO4: Explain the art of interpretation and the art of writing research reports.
CO5 : Explain various forms of the intellectual property, its relevance and business impact in
thechanging global business environment
CO6: Discuss leading International Instruments concerning Intellectual Property Rights.
Course Contents
UNIT-I Research Methodology 07 Hours
Introduction, Meaning of Research, Objectives of Research, Motivation in Research, Types of Research,
Research Approaches, Significance of Research, Research Methods versus Methodology, Research and
Scientific Method, Importance of Knowing How Research is Done, Research Process, Criteria of Good
Research, and Problems Encountered by Researchers in India. Defining the Research Problem: Research
Problem, Selecting the Problem, Necessity of Defining the Problem, Technique involved in Defining a
Problem.
UNIT-II Reviewing the literature 07Hours
Place of the literature review in research, Bringing clarity and focus to your research problem, Improving
research methodology, Broadening knowledge base in research area, Enabling contextual findings, How
to review the literature, searching the existing literature, reviewing the selected literature, Developing a
theoretical framework, Developing a conceptual framework, Writing about the literature reviewed.
Research Design: Meaning of Research Design, Need for Research Design, Features of a Good Design,
Important Concepts Relating to Research Design, Different Research Designs, Basic Principles of
Experimental Designs, Important Experimental Designs.
UNIT-III Design of Sampling 06 Hours
Introduction, Sample Design, Sampling and Non-sampling Errors, Sample Survey versus Census
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 19
Survey, Types of Sampling Designs. Measurement and Scaling: Qualitative and Quantitative Data,
Classifications of Measurement Scales, Goodness of Measurement Scales, Sources of Error in
Measurement Tools, Scaling, Scale Classification Bases, Scaling Technics, Multidimensional Scaling,
Deciding the Scale. Data Collection: Experimental and Surveys, Collection of Primary Data, Collection of
Secondary Data, Selection of Appropriate Method for Data Collection, Case Study Method.
UNIT-IV Testing of Hypotheses 06 Hours
Hypothesis, Basic Concepts Concerning Testing of Hypotheses, Testing of Hypothesis, Test Statistics and
Critical Region, Critical Value and Decision Rule, Procedure for Hypothesis Testing, Hypothesis Testing
for Mean, Proportion, Variance, for Difference of Two Mean, for Difference of Two Proportions, for
Difference of Two Variances, P-Value approach, Power of Test, Limitations of the Tests of Hypothesis.
Chi-square Test: Test of Difference of more than Two Proportions, Test of Independence of Attributes,
Test of Goodness of Fit, Cautions in Using Chi Square Tests.
UNIT-V Interpretation and Report Writing 08 Hours
Meaning of Interpretation, Technique of Interpretation, Precaution in Interpretation, Significance of
Report Writing, Different Steps in Writing Report, Layout of the Research Report, Types of Reports, Oral
Presentation, Mechanics of Writing a Research Report, Precautions for Writing Research Reports.
UNIT-VI Intellectual Property 06 Hours
Introduction to IPR, Types of IPRs, Types of Patents, WIPO, WTO, TRIPs, Protection of Undisclosed
Information, Enforcement of Intellectual Property, Office procedures of filing and prosecution
BOOKS:
Text:
T1: An introduction to Research Methodology, Garg B.L et al ,RBSA Publishers 20022.An Introduction
to Multivariate Statistical Analysis Anderson T.W,Wiley 3rdEdition, 2003.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 20
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -I [EC5103A]: IC Design with HDL
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation: 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites:Basic programming concepts, Logic gates combinational design. Knowledge of
algorithms and flowchart, use of variable and signals, FPGA blocks.
Course Objective:
1. To study Basics of analog IC designing and small signal models.
2. To understand the design principles of different types of amplifier.
3. To learn different types of op-amps
4. To understand the implementation of linear and non – linear analog block implementation and their
testing
Course Outcome:
After successful completion of the course, students will able to:
CO1: Developed ability to design analog building blocks of VLSI circuit.
CO2: student will able to design different types of amplifiers.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 21
CO4: Express basic fundamentals of current mirrors.
CO3: Developed ability to build SPICE deck of MOS integrated circuits.
Course Contents
UNIT-I Introduction to VHDL 06 Hours
Basic concepts of hardware description languages. Hierarchy, Concurrency, Logic and Delay
modeling. Data objects, Data types, Architecture selection, configuration statements, power of
configuration.
UNIT-II Behavioral Modeling 08 Hours
Behavioral styles of hardware description. Inertial delay, transport delay, Architecture of event driven
simulators. Generics, Block statements, Test bench types.
UNIT-III Sequential Processing 06 Hours
Process statement, sensitivity list, Signal assignment v/s Signal variable, Sequential statement, Wait
statement, Exit and Assert statement.
UNIT-IV Syntax of HDL 06 Hours
Syntax and Semantics of HDL: Variable and signal types, arrays and attributes. Operators, expressions
and signal assignments. Entities, architecture specification and configurations. Component
instantiation.
UNIT-V Subprograms and packages 07 Hours
Subprogram: function, conversion function, resolution function, packages: package declaration, package
body, Sub program overloading, parameters overloading, synthesis, constraints and attributes, Technology
library.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 22
UNIT-VI Procedure and Functions 07 Hours
Concurrent and sequential constructs. Use of Procedures and functions, Examples of design using
VHDL or Verilog. Synthesis of logic from hardware description.
BOOKS:
Text:
T1.Allen P E and Holberg D R, “CMOS Analog Circuit Design”, 2ndEdition, Oxford University
Press.
T2. B. Razavi, “Design of Analog CMOS Integrated Circuits”, 2nd Edition, Prentice-Hall, 1998.
References:
R1. R. Jacob Baker, “CMOS Circuit Design, Layout and Simulation”, 4th edition Wiley, 2005.
R2. M. Ismail, “Analog VLSI: Signal and Information Process”, 3rd edition, McGraw-Hill, 1994.
R3. P.R. Gray and R.G. Meyer, Analysis and design of Analog Integrated circuits, 3rdEdition, John Wiley
and Sons, 1993.
R4. Behzad Razavi, “RF Microelectronics”, 2nd Edition, Prentice-Hall PTR,1998",
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 23
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -I [EC5103B]: Embedded Automotive Systems
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites:Fundamentals of Sensor technology, Basic concepts of communication protocols,
Concepts of Vehicular system.
Course Objective:
1. To introduce the potential of automotive systems in industries
2. To understand Automotive Sensory Systems
3. To explain the importance of automotive control in system design
4. To make student aware of different Automotive protocolsfor internal communication
Course Outcome:
After successful completion of the course, students will able to: On completion of the course,
student will be able to -
CO1:Realize the fundamentals of different Automotive Systems
CO2: Learn utility of sensors and instrumentation in vehicle systems
CO3: Design control system for various vehicular Units
CO4: Acquire knowledge of various automotive protocols
Course Contents
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 24
UNIT-I Automotive Systems 08 Hours
Automotive systems overview :automotive vehicle technology, overview of vehicle categories,
various vehicle sub systems like chassis, body, driveline, engine technology, fuelling technology,
vehicle emission, brakes, suspension, emission, doors, dashboard instruments, wiring harness,
safety & security , comfort & infotainment, communication & lighting, future trends in automotive
embedded systems : hybrid vehicles, electric vehicles.
UNIT-II Automotive Sensory System 08 Hours
Automotive sensory system: automotive sensors and transducers: temperature, manifold and
barometric pressures, humidity, carbon dioxide (co2), carbon monoxide (co), oxygen (o2) sensor,
proximity distance sensors, engine speed sensor, throttle position sensor, pressure sensors, knock
sensor & mass flow sensor. typical sensors specifications & microcontroller interface
considerations, sensor calibration, curve fitting.
UNIT-III Automotive Control System 06 Hours
Automotive control system design: digital engine control, features, control modes for fuel control,
discrete time idle speed control, egr control, variable valve timing control.
UNIT-IV Engine Control System 06 Hours
Electronic ignition control, integrated engine control system, summary of control modes, cruise
control system, cruise control electronics, anti-locking braking system, electronic suspension
system, electronic steering control, four-wheel steering.
UNIT-V Automotive Protocols 06 Hours
Automotive Protocols: the need for protocol, automotive protocols: lin, can, kwp2000 & j1939,
flex ray.
UNIT-VI Software Tools for Automotive System 06 Hours
Calibration and diagnostics tools for networking of electronic systems like ecu software and testing
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 25
tools, ecu calibration tools, vehicle network simulation. advanced trends in automotive electronics:
autosar architecture.
BOOKS:
Text:
T1: William B. Ribbens, “Understanding Automotive Electronics- An Engineering Perspective”,
T2: Ronald K. Jurgen, “Automotive Electronics Handbook”, Mc-Graw Hill.
Reference:
R1: Kiencke, Uwe, Nielsen &Lars, “Automotive Control Systems for Engine, Driveline and
Vehicle”, Second edition, Springer Publication.
R2: Tao Zhang, Luca Delgrossi, “Vehicle Safety Communications: Protocols, Security and
Privacy”, Wiley Publication.
R3: Robert Bosch,” Automotive Handbook”, Fifth edition, SAE Publications.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 26
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System) Academic Year – 2020-2021 Semester -I
[EC5103C]: Image and Video Processing
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites: Fundamentals of digital signal processing.
Course Objective:
1. To learn basic concepts of image processing, fundamentals and mathematical models in digital
image and video processing.
2. To study different types of image transforms for image processing
3. To develop time and frequency domain techniques for image enhancement
4. To understand Image segmentation, restoration, and morphological signal Processing with
applications.
5. To expose the students to current applications, techniques and issues in image and video
processing.
6. To develop image and video processing applications in practice
Course Outcome:
After successful completion of the course, students will able to:
CO1. To learn basic concepts of image processing, fundamentals and mathematical models in
Digital image and video processing.
CO2. To study different types of image transforms for image processing
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 27
CO3. To develop time and frequency domain techniques for image enhancement
CO4. To understand Image segmentation, restoration, and morphological signal Processing
With applications.
CO5. To expose the students to current applications, techniques and issues in image and video
Processing.
CO6. To develop image and video processing applications in practice.
Course Contents
UNIT-I Fundamentals of Image processing and Image Transforms 06 Hours
Basic steps of Image processing system sampling and quantization of an Image – Basic relationship
between pixels Image, Basic operations on images-image addition, subtraction, logical operations,
scaling, translation, rotation. Image Histogram. Transforms: 2 – D Discrete Fourier Transform, Discrete
Cosine Transform (DCT), Discrete Wavelet ransforms, Haar, Hadamard, PCA
UNIT-II Image Processing Techniques 06 Hours
Image Enhancement: Spatial Domain methods: Histogram Processing & Specification, Fundamentals of
Spatial Filtering, Smoothing Spatial filters, Sharpening Spatial filters Frequency Domain methods: Basics
of filtering in frequency domain, image smoothing, image sharpening, selective filtering Image,
Segmentation: segmentation– average, weighted average, first order and second order, Hough transform,
Thresholding.
UNIT-IIIImage registration06 Hours
Operational goal of registration, Classification of registration methods - Geometrical transformations,
Rigid transformations, Nonrigid transformations, Rectification, Point-based methods, Points in rigid
transformations, Points in scaling transformations, Points in perspective projections, Points in curved
transformations, Surface-based methods, Disparity functions, Head and hat algorithm, Distance
definitions, Distance transform approach, Iterative closest point algorithm, Weighted geometrical feature
algorithm, Intensity-based methods, Similarity measures.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 28
UNIT-IVColour Image processing06 Hours
Color Models, Pseudocolor Image Processing, Basics of Full-Color Image Processing, Color
Transformations , Formulation ,Color Complements , Color Slicing , Tone and Color Corrections,
Histogram Processing , Smoothing and Sharpening , Color Image Smoothing , Color Image
Sharpening , Image Segmentation Based on Color , Segmentation in HSI Color Space ,
Segmentation in RGB Vector Space , Color Edge Detection , Noise in Color Images , Color Image
Compression.
UNIT-V Image Morphology 06 Hours
Basics, SE, Erosion, Dilation, Opening, Closing, Hit-or-Miss Transform, Boundary Detection, Hole
filling, connected components, convex hull, thinning, thickening, skeletons, pruning, Geodesic Dilation,
Erosion, Reconstruction by dilation and erosion.
UNIT-VI Basic Steps of Video Processing 06 Hours
Analog video, Digital Video, Time varying Image Formation models : 3D motion models, Geometric
Image formation , Photometric Image formation, sampling of video signals, filtering operations,2-D
Motion Estimation: Optical flow, general methodologies, pixel based motion estimation, Block matching
algorithm, Mesh based motion Estimation, global Motion Estimation, Region based motion estimation,
multi resolution motion estimation. Application of motion estimation in video coding.
BOOKS:
Text:
T1:Gonzaleze and Woods,” Digital Image Processing “, 3rd edition, Pearson
T2:Yao Wang, JoemOstarmann and Ya – quin Zhang, ”Video processing and communication“, 1st
edition , PHI
References:
R1:. M. Tekalp ,”Digital video Processing”, Prentice Hall International
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 29
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -I [EC5104A]: Nanoelectronics
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites :Hybridization in semiconductor material, nano properties and physics of
semiconductor, semiconductor devices and its band theory.
Course Objective:
1. To get introduced to Nanoelectronics and nanotechnology.
2. To understand working of Nano scale transistor.
3. To understand modelling aspects of Nanoscale devices from perspective of circuit Course
4. To study the fabrication technology of nanoscale devices
Course Outcome:
After successful completion of the course, students will able to:
CO1: Building molecular level devices and systems.
CO2: Design of Carbon-based Nano-electronic devices.
CO3: Express basic fundamentals of nanoscale devices.
CO4: Student will able to analyze fabrication techniques of nanoscale device.
Course Contents
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 30
UNIT-I Introduction to Nanoelectronics 06 Hours
Band structures in Silicon, Historical development and basic concepts of crystal structure, defects,
Crystal growth and wafer fabrication, crystal planes and orientation. Modern CMOS technology.
UNIT-II Material in Nanotechnology 08 Hours
The fundamental science behind nanotechnology, bio systems, molecular recognition, quantum mechanics
& quantum ideas, optics. Smart materials & Sensors, self-healing structures, heterogeneous
nanostructures& composites, encapsulations, natural nano-scale sensors, electromagnetic sensors,
biosensors, electronic noses.
UNIT-III Band Theory of Solids 08 Hours
Band Theory of Solids. Kronig-Penny Model. Brillouin Zones. Shrink-down approaches: Introduction,
CMOS Scaling, The nanoscale MOSFET, Finfets, Vertical MOSFETs, limits to scaling, system
integration limits (interconnect issues etc).
UNIT-IV Nanoelectronics devices 06 Hours
Resonant Tunneling Diode, Single electron transistors, Carbon nanotube electronics, Band structure
and transport, devices, applications 2D semiconductors, Graphene, transition metal dichalcogenides,
atomistic simulations.
UNIT-V Fabrication Techniques 06 Hours
Low Temperature Scanning Probe Microscopy, Dynamic ForceMicroscopy.-. Nanolithography,
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 31
Lithography using photons, electron beams soft lithography. Bio-medical applications.
UNIT-VI Measurement methods and Tools 08 Hours
Electron microscopy, Atomic Force Microscope, X-Ray photoelectron Spectroscopy, Profilometers,
Reflectometers.
BOOKS:
Text:
T1. Springer Handbook of Nanotechnology
T2. Rattner Mark, Rattner Daniel, “Nanotechnology: A Gentle Introduction to the Next Big Idea”
References:
R1. KulkarniSulbha K, “Nanotechnology: Principals& Practices”, Capital Publications
R2. VlaimirMitin, “Introduction to nanoelectronics science, Nanotechnology, Engineering and
Applications”, Cambridge. University Press
R3. G.W. Hanson, Fundamentals of Nanoelectronics, Pearson, 2009.
R4. K.E. Drexler, Nanosystems, Wiley, 1992.
R5. J.H. Davies, The Physics of Low-Dimensional Semiconductors, Cambridge University Press,1998.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 32
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -I [EC5104B]: Embedded Product Design
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation: 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites:Fundamentals of Design, Basic concepts of modeling
1. To outline the major components that constitute an embedded system
2. To Implement small programs to solve well-defined problems on an embedded platform
3. To Develop familiarity with tools used to develop in an embedded environment.
4. To understand real world interfacing with different embedded processor.
Course Outcome:
After successful completion of the course, students will able to:
CO1: Describe and Analyze the hardware, software, components of embedded product design
CO2: Understand different components of anembedded processor and their interactions.
CO3: Become familiar with programming environment used to develop embedded systems.
CO4: Understand key concepts of embedded systems like IO, timers, interrupts, interaction with
peripheral devices.
CO5: Specify and Identify debugging techniques for an embedded system.
Course Contents
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 33
UNIT-I Introduction to Electronic Product Design 06 Hours
Man machine dialog and Industrial design, user-centered design, five element of successful design,
cognition, ergonomics. Packaging and factors, design for manufacture, assembly and disassembly, wiring,
temperature, vibration and shock. Safety, noise, energy coupling, grounding, filtering and shielding.
UNIT-II Hardware Design & testing methods 06 Hours
Design process. Identifying the requirements, formulating specifications, design specifications,
Specifications verses requirements, System partitioning, Functional design, architectural design,
Functional model verses architectural model. Prototyping. Performance and Efficiency measures.
Formulating a test plan, writing specifications, Test procedure and test cases, Egoless design, design
reviews. Unit debug and test: black box test, white box test, grey box test.
UNIT-III Software Design and Testing methods 06 Hours
Types of Software. Waterfall model of software development. Models, metrics and software limitations.
Risk abatement and failure preventions. Software bugs and testing. Good programming practice. User
interface. Embedded, Real time software.
UNIT-IV ARM CORTEX based design I 08 Hours
Need of operating system in developing applications in embedded system, desired features of operating
system & hardware support from processor, Firmware development using CMSIS standard for ARM
Cortex. ARM-CM3 Based interfacing with RGB LED, LCD, Keyboard, Seven Segment, TFT Display,
Sensors (Temperature & Weight measurement), MOTOR control using PWM.
UNIT-V ARM CORTEX based design II 07 Hours
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 34
Design of a Sensor-Based Adaptive Smart Home System Using ARM Cortex-M3, Design of a robotic
arm Using ARM Cortex-M3, ARM Based Embedded System for Industrial Application Using TCP/IP
Network, RFID based product design, GSM based product design.
UNIT-VI Real World Interfacing with ARM-CM3 Based Microcontroller 07 Hours
Concept of USB, CAN, and Ethernet based communication using microcontrollers. CAN, USB,
ETHERNET applications in embedded c.
BOOKS:
Text:
T1:Kim Fowler, Electronic Instrument Design, Oxford university press. ISBN 9780195083712,1996
T2:Robert J. Herrick, “Printed Circuit board design Techniques for EMC Compliance”, Second edition,
IEEE press.
T3:JosephYiu, “The Definitive Guide to the ARM Cortex-M”, Newness, ELSEVIER
References:
R1. James K. Peckol, “Embedded Systems – A Contemporary Design Tool”, John Wiley & Sons
publication, 2008
R2. J C Whitakar,” The Electronics Handbook”, CRC press.
R3. LPC 17xx User manual (UM10360) :- www.nxp.com
R4. ARM architecture reference manual: - www.arm.com 4. Trevor Martin,”AnEngineer‟s
Introduction to the LPC2100 series”, Hitex (UK) Ltd.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 35
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -I [EC5104C]: Speech and Audio Processing
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites:Basics of sound, Acoustics, Signal processing.
Course Objective:
To characterize the speech signal as generated by a speech production model To understand the motivation of short-term analysis of speech and audio To extract the information of the speech or audio signals in terms of cepstral features To provide a foundation for developing applications in this field
Course Outcome:
After successful completion of the course, students will able to:
CO1: Analyze speech signal to extract the characteristic of vocal tract (formants) and vocal cords (pitch). CO2: Solve practical problems with some basic audio and speech signal processing
Techniques.
CO3: Design simple systems for realizing some multimedia applications with some basic audio and
speech signal processing techniques.
CO4: Implement algorithms for processing speech and audio signals considering the
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 36
properties of acoustic signals and human hearing
Course Contents
UNIT-I Speech signal digital model 07 Hours
Speech production, acoustic theory , lossless tube models ,digital models, linear prediction of speech,
auto correlation, formulation of LPC equation, solution of LPC equations, Levinson Durbin algorithm,
Levinson recursion, Schur algorithm, lattice formulations and solutions, PARCOR coefficients,
Spectral analysis of speech, Short Time Fourier analysis, filter bank design. Auditory Perception:
Psychoacoustics, Frequency Analysis and Critical Bands, Masking properties of human ear.
UNIT-II Speech coding 07 Hours
Sub-band coding of speech, transform coding, channel vocoder,formant vocoder, cepstralvocoder, vector
quantizer coder, Linear predictive Coder. Speech synthesis, pitch extraction algorithms, gold Rabiner
pitch trackers, autocorrelation pitch trackers.
UNIT-III Speech Processing 06 Hours
Voice/unvoiceddetection, homomorphic speech processing, homomorphic systems for convolution,
complex cestrum’s, pitch extraction using homomorphic speech processing. Sound Mixtures and
Separation, CASA, ICA & Model based separation.
UNIT-IV Speech Transformations 06 Hours
Time Scale Modification, Voice Morphing. Automatic speech recognition systems , isolated word
recognition, connected word recognition- large vocabulary word recognition systems, pattern
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 37
classification, DTW, HMM, speaker recognition systems, speaker verification systems – speaker
identification Systems.
UNIT-V Audio Processing 06 Hours
Audio signal, Non speech and Music Signals, Modeling , Differential transform and sub-band coding of
audio signals & standards, High Quality Audio coding using Psychoacoustic models, MPEG Audio
coding standard.
UNIT-VI Magnetism and Superconductivity 06 Hours
Music Production, sequence of steps in a bowed string instrument , Frequency response measurement of
violin, guitar, Audio Data bases and applications , Content based retrieval, raga identification, musical
instrument classification.
BOOKS:
Text Books:
T1:Rabiner L.R. & Schafer R.W., “Digital Processing of Speech Signals”, Prentice Hall Inc.
T2: Dr. S. D. Apte, Speech and audio Processing,John Wiley &Sons, Inc.
References:
R1. Rabiner L.R. & Gold, “Theory and Applications of Digital Signal Processing”, Prentice Hall of India
R2. O'Shaughnessy, D. “Speech Communication, Human and Machine”. Addison, Wesley.
R3. Deller, J., J. Proakis, and J. Hansen. “Discrete, Time Processing of Speech Signals. “Macmillan.
R4. Ben Gold & Nelson Morgan,“Speech and Audio Signal Processing”, John Wiley &Sons, Inc.
R5. Papamichalis P.E., “Practical Approaches to Speech Coding”, Texas Instruments, Prentice Hall
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 38
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -I [EC5106]: Lab Practice -I
Laboratory Assignments/Experiments:
1. Write a program for 4*4 Matrix Keypad Interface.
2. To develop character device driver for GPIO
3. One experiment based on any one of development Platform: Arduino, Beaglebon,
Rasberry Pi, Intel Galileo Gen 2.
4. Interfacing USB & CAN of LPC 1768.
5. Write a program for External Interrupt
6. Write a program for Sensing Engine Speed, Load and Temperature.
7. Develop a transistorized Ignition Driver.
8. Design a single cylinder engine Management System.
9. Perform a case study for any two automotive protocols.
10. Study the functional design aspects of Hybrid Automotive Systems.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 39
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
SEMESTER II Syllabus
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 40
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -II [EC5109]: Analog IC Design
Teaching Scheme:
TH: 03 Hours/Week
Credit
03
Examination Scheme:
In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks
Course Prerequisites:Basic analog circuit knowledge, properties of each linear and non linear devices in
semiconductor, technology scaling for devices.
Course Objective:
1. To study Basics of analog IC designing and small signal models.
2. To understand the design principles of different types of amplifier.
3. To learn different types of op-amps
4. To understand the implementation of linear and non – linear analog block implementation and
their testing
Course Outcome:
After successful completion of the course, students will able to:
CO1: Developed ability to design analog building blocks of VLSI circuit.
CO2: student will able to design different types of amplifiers.
CO3: Express basic fundamentals of current mirrors.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 41
CO4: Developed ability to build SPICE deck of MOS integrated circuits.
Course Contents
UNIT-I MOSFET Overview 07 Hours
MOSFET as a switch, Diode and active resister, MOS small signal model. Overview of noise in analog
circuit. Current sink and sources. Short channel regime; Current sinks and sources.
UNIT-II Current Mirrors 08 Hours
Current mirrors: Current matching, temperature behavior, cascade current mirror, wide swing current
mirror, voltage references.
UNIT-III CMOS Amplifiers 06 Hours
CMOS Amplifiers: Design of CMOS amplifiers, Inverting amplifiers, Common source amplifier, Common
Gate amplifier, Common drain amplifier.
UNIT-IV Cascade Amplifier 07 Hours
Single stage amplifier: common source amplifier, source follower, current source loads, cascade
amplifier, folded cascade, output stage. Class AB and push-full amplifier.
UNIT-V Op-Amps 08 Hours
Differential amplifier: source coupled pair, source cross coupled pair, cascade loads. Wide swing
differential amplifier and operational amplifier: high speed Op-Amps..
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 42
UNIT-VI High Frequency Amplifier 08 Hours
HF Amplifiers &Low Noise Amplifier: Open and Short circuit methods to estimate bandwidth, multistage
amplifier for high bandwidth, Low Noise Amplifier (LNA) design, noise and power trade off.
BOOKS:
Text:
T1.Allen P E and Holberg D R, “CMOS Analog Circuit Design”, 2ndEdition, Oxford University
Press.
T2. B. Razavi, “Design of Analog CMOS Integrated Circuits”, 2nd Edition, Prentice-Hall, 1998.
References:
R1. R. Jacob Baker, “CMOS Circuit Design, Layout and Simulation”, 4th edition Wiley, 2005.
R2. M. Ismail, “Analog VLSI: Signal and Information Process”, 3rd edition, McGraw-Hill, 1994.
R3. P.R. Gray and R.G. Meyer, Analysis and design of Analog Integrated circuits, 3rdEdition, John Wiley
and Sons, 1993.
R4. Behzad Razavi, “RF Microelectronics”, 2nd Edition, Prentice-Hall PTR,1998",
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 43
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -II [EC5110]: Embedded Signal Processor Architectures
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites:Fundamentals of signals and system, Basic concepts of transforms
Course Objective:
1. To impart knowledge on the theoretical aspects of signal analysis and processing
2. To explore DSP Processor architectures
3. To understand DSP algorithms
4. To elaborate real world DSP applications
Course Outcome:
After successful completion of the course, students will able to:
CO1: Designing system with linear filters using DFT
CO2: Develop technical abilities of designing any applications with FIR and IIR filters
CO3: Port algorithms on DSP Processor Platforms
CO4: Design Adaptive filters
CO5: Analyze filter structures
Course Contents
UNIT-I Signal Analysis and Processing 08 Hours
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 44
Signal Analysis and Processing: Discrete Fourier Transform, Fast Fourier Transform, Design of FIR
Filters using windowing technique, Design of IIR Filters through Impulse invariance and bilinear
transformation technique, Algorithms of Adaptive Filters, Design and Applications of Adaptive Filters
UNIT-II Introduction to Digital signal processing systems 06 Hours
Introduction to Digital signal processing systems, MAC, Barrel shifter, ALU, Multipliers, Dividers, DSP
processor architecture, Software developments, Selections of DSP processors, Hardware interfacing, DSP
processor architectures: TMS 320C54XX, TMS 320C67XX.
UNIT-III Blackfin processor 06 Hours
Blackfin processor: Architecture overview, memory management, I/O management, Real time
implementation Considerations, Memory System and Data Transfer, Code Optimization.
UNIT-IV DSP algorithms 08 Hours
Representations of the DSP algorithms, Block diagrams, Signal flow graph, Data-flow graph, Dependence
graph. Iteration bounds: Critical Path, Loop Bound, Algorithm to compute iteration bound, Longest Path
Matrix (LPM).
UNIT-V 06 Hours
Practical DSP Applications: Audio Coding and Audio Effects, Digital Image Processing, Two-
Dimensional Filtering, Image Enhancement, DTMF generation and detection
UNIT-VI 06 Hours
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 45
FFT algorithms, Wavelet algorithms, Adaptive algorithms: system identification, inverse modeling,
noise cancellation, prediction
BOOKS:
Text:
T1:Woon-SengGan, Sen M. Kuo, “Embedded Signal Processing With the Micro Signal Architecture”,
Wiley-IEEE Press.
T2: KuoSen M, Woon-SengGan,“ Digital Signal Processors: Architectures, Implementations and
Applications”, Prentice-Hall.
References:
R1: Proakis J G, Manolakis D G, “Digital Signal Processing ,Principles, Algorithms and Applications”,
Prentice-Hall.
R2: Lawrence R. R, Bernard Gold, “Theory and Application of Digital signal Processing”, Prentice-
Hall.
R3: ParhiKeshab , “VLSI Digital Signal Processing System”, Wiley Publication.
.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 46
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -II [ES5104]: Advanced Engineering Mathematics
Teaching Scheme: TH: 04 Hours/Week
Credit 04
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites:Elementary notions of Matrices, Statistics and Probability
Course Objective:
1.To understand mathematical fundamentals for various courses like Communication Engineering,
Computer security, Software engineering, Computer architecture, Machine learning.
Course Outcome:
After successful completion of the course, students will able to:After successful
CO1: Apply concepts in Linear algebra in engineering field.
CO2: Apply concepts of graph theory to solve problems of connectivity.
CO3 : Apply statistical methods like correlation, regression analysis of a given data as applied to machine
Intelligence.
CO4 : Understand the basic notions of discrete and continuous probability and apply probability theory
For prediction of a given data.
CO5: Solve problems related to Fourier transform and applications to Signal and Image processing.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 47
Course Contents
UNIT-I Linear Algebra-Vector Space 08 Hours
Vector Space, Subspaces, Span of a set, Linear Dependence and Independence, Basis and Dimensions,
Rank-nullity theorem. Inner Product Space, Orthogonality, Gram–Schmidt Method.
UNIT-II Linear Algebra-Linear Transformation 08 Hours
Linear Transformation, Matrix for Linear transformation, Nonsingular Linear Transformation, inverse of
Linear Transformation, Eigen values and Eigen vectors, Diagonalization, Principal component analysis
(PCA), Singular Value Decomposition (SVD)
UNIT-III Graph Theory 08 Hours
Basic terminologies, Simple graphs, Multi graphs and Weighted graphs, Paths and circuits, Euler and
Hamiltonian paths and circuits, Shortest path problems, Shortest path algorithm, Planer graphs, directed
graphs, trees, rooted trees, binary search trees, spanning trees, application to minimum spanning tree
problem, Kruskar’s and Prim’s algorithms for minimum spanning tree.
UNIT-IV Statistics 08 Hours
Measures of central tendency, Measures of dispersion, Moments , Simple Correlation and Regression
,Testing of Hypothesis, Chi-Square Test, P –value of a test , Analysis of Variance (ANOVA)-one way
and two way classification.
UNIT-V Probability Theory 08 Hours
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 48
Probability, Conditional probability, Bay’s Theorem, Random variables, Probability mass function,
Probability density function, Mathematical Expectation, Probability distribution: Binomial, Possion,
Normal and Hypergometric Distribution.
UNIT-VI Fourier Transform 08 Hours
Fourier Transform, Fourier Sine and Cosine Transform and their inverses, Discrete Fourier Transform,
Inverse Discrete Fourier Transform, Fast Fourier Transform, Convolution.
BOOKS:
Text:
T1. David C. Lay, “Linear Algebra and its Applications,” 12th impression 2011, Pearson Education Inc,.
T2.Gilbert Strang , “ Linear Algebra and its Applications,” 10th Indian reprint 2011, Cengage Learning
(Indian Edition).
References:
R1. B.A. Ogunnaike, “Random Phenomena:Fundamentals of probability and Statistics for Engineers”,
CRC Press, 2010.
R2. K.H. Rosen, “Discrete Mathematics and its Application”, Tata McGraw Hill publication.
R3. Henry Stark, John W. Woods,” Probability and Random processes with Applications to Signal
Processing”, Pearson Education, 3rd edition.
R4. G.C. Beri “Business Statistics”, second Edition, Tata McGraw Hill publication.
R5.I.R. Millar, J.E. Freund and R. Johnson, “Probability and Statistics for Engineers”, 4th edition, PHI
R6 E. Kreyszig, “Advance Engineering Mathematics”, 10th edition,Wiley,2015
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 49
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -II [EC5111A]: Advanced Signal Processing Technology
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites:Advanced calculus and familiarity with introductory complex variable theory.
Previous exposure to linear system theory for continuous-time signals, including Laplace and Fourier
transforms is required.
Course Objective:
1. Design and testing of systems for advanced signal processing.
2. Understanding of Digital Signal Processor architecture
3. Analysis of Signal using different parameter.
Course Outcome:
After successful completion of the course, students will able to:
CO1: Understanding of advanced methods of signal processing and analysis,
CO2: Utilize advanced methods of signal processing
CO3: Design and verify a realization aimed at a particular practical task
CO4: Apply the concept for real time application.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 50
Course Contents
UNIT-I Architecture and instruction set of DSP processor 07 Hours
Introduction to TMS320C6x processor, architecture, pipelining, linear and circular addressing modes,
TMS320C6x instruction set, assembler directives, timers, interrupts, serial I/O, DMA,fixed and floating
point data format.
UNIT-II Digital signal processing and DSP systems 07 Hours
Advantages of DSP, characteristics of DSP systems, DSP applications. DSP processors, architecture
and instruction set.
UNIT-III Numeric representations and arithmetic 06 Hours
Floating point numbers, IEEE 754 standard for floating point numbers
UNIT-IV Memory Architectures 06 Hours
Memory structures wait states, extended memory interfaces, addressing mechanisms.
UNIT-V Execution control 06Hours
Hardware looping, interrupts, stack, relative branch support Pipelining: pipelining and performance,
pipelining depth, interlocking, branching effects, interrupt effects,
UNIT-VI Peripherals 06Hours
Serial / parallel ports, timers, communication ports, on-chip A/D and D/A converters,
external interrupts, on-chip debugging facilities, power consumption, clocking.
BOOKS:
Text:
T1: Advanced Digital Signal Processing Principles, Algorithms andApplications, Pearson, Fourth Edition, Proakis, Manolakis, T2. Advanced Digital Signal Processing-Shaila Apte-Wiley India publication
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 51
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -II [EC5111B]: Artificial Intelligence and Machine Learning
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites: Background in basic programming and Data Structures or equivalent knowledge
will be required for this course.
Course Objective:
The Objective of this course is to provide a strong foundation of fundamental concepts in Artificial
Intelligence along with a basic exposition to the goals and methods of Artificial Intelligence.To enable
the student to apply these techniques in applications which involve perception, reasoning and learning.
Course Outcome:
After successful completion of the course, students will able to:
CO1: Understand the various searching techniques, constraint satisfaction problem and example
problems- game playing techniques.
CO2: Apply these techniques in applications which involve perception, reasoning and learning.
CO3: Explain the role of agents and how it is related to environment and the way of evaluating it and
how agents can act by establishing goals.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 52
CO4: Acquire the knowledge of real world Knowledge representation.
CO5: Analyze and design a real world problem for implementation and understand the dynamic
behavior of a system.
CO6:Use different machine learning techniques to design AI machine and enveloping applications for
real world problems.
Course Contents
UNIT-I Foundations for ML 06Hours
MLTechniques overview, Validation Techniques (Cross-Validations), Feature, Reduction/Dimensionality
reduction, Principal components analysis (Eigen values, Eigen vectors, Orthogonality.
UNIT-II Clustering 06Hours
Distance measures, Different clustering methods (Distance, Density, Hierarchical), Iterative
distance-based clustering, Dealing with continuous, categorical values in K-Means, Constructing a
hierarchical cluster, K-Medoids, k-Mode and density-based clustering, Measures of quality of
clustering.
UNIT-III Classification 06Hours
Naïve Bayes Classifier, Model Assumptions, Probability estimation, Required data processing, M-
estimates, Feature selection: Mutual information, Classifier, K-Nearest Neighbors: Computational
geometry; Voronoi Diagrams; Delaunay Triangulations, K-Nearest Neighbor algorithm; Wilson
editing and triangulations, Aspects to consider while designing K-Nearest Neighbor Support Vector
Machines: Linear learning machines and Kernel space, Making Kernels and working in feature
space SVM for classification and regression problems, Decision Trees, Random forest .
UNIT-IV Foundations for AI 06Hours
AI: Application areas, AI Basics (Divide and Conquer, Greedy, Branch and Bound, Gradient
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 53
Descent), NN basics (Perceptron and MLP, FFN, Backpropagation).
UNIT-V Knowledge Representation of AI 06Hours
Knowledge Representation: Procedural Vs Declarative Knowledge, Representations & Approaches
to Knowledge Representation, Forward Vs Backward Reasoning, Matching Techniques, Partial
Matching, Fuzzy Matching Algorithms and RETE Matching Algorithms; Logic Based
Programming- AI Programming languages: Overview of LISP, Search Strategies in LISP, Pattern
matching in
LISP , An Expert system Shell in LISP, Over view of Prolog, Production System using Prolog
UNIT-VI Neural Networks 06Hours
Image classification, Text classification, Image classification and hyper-parameter tuning, Emerging
NN architectures, Building recurrent NN, Long Short-Term Memory, Time Series Forecasting
BOOKS:
Text:
T1: Machine Learning, Tom Mitchell , McGraw Hill, 1997
References:
R1: The Elements of Statistical Learning, Trevor Hastie, Robert Tibshirani& Jerome Friedman,
Springer Verlag, 2001
R2: Pattern Classification, Richard,Duda, Peter E. Hart and David G. Stork, John Wiley & Sons
Inc., 2001
R3: Neural Networks for Pattern Recognition, Chris Bishop, Oxford University Press, 1995
R4: Artificial Intelligence, George F Luger, Pearson Education Publications
R5: Artificial Intelligence : A modern Approach, Russell and Norvig, Printice Hall
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 54
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -II [EC5111C]: Design for Testability
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites:Combinational logics, test vectors, net list through VHDL, synthesis and verification
of devices, look up tables, digital logic families.
Course Objective:
1. To study techniques in testing of VLSI chips.
2. To understand fault models and their use in testing of VLSI Circuits.
Course Outcome: After successful completion of the course, students will able to:
The student will be able to
CO1: Understand theory of combinational circuits for writing VHDL program.
CO2: Apply concept registers and counters with CAD tools.
CO3: Exhibit the knowledge of static and dynamic Hazards for design of vending machine controller.
CO4: Use Fault models for testing various VLSI circuits.
CO5:Design Circuits for Testability.
Course Contents
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 55
UNIT-I Need of Testability 07 Hours
Controllability and observability, Types of faults, Need of design for testability, Fault models and CMOS
test methods.
UNIT-II Scope of Testing 06 Hours
Scope of testing and verification in VLSI design process. Issues in test and verification of complex
chips, embedded cores and SOCs. Fundamentals of VLSI testing. Fault models. Automatic test
pattern generation.
UNIT-III Design for Testability 08 Hours
Design for testability. Scan design. Test interface and boundary scan. System testing and test for SOCs.
Iddq testing. Delay fault testing. BIST for testing of logic and memories. Test automation.
UNIT-IV Design Verification Technique 08 Hours
Design verification techniques based on simulation, analytical and formal approaches. Functional
verification. Timing verification. Formal verification. Basics of equivalence checking and model
checking.
UNIT-V System Test design 06Hours
System test and core-based design, ATPG, Embedded core test fundamentals. Design verification
techniques based on simulation, analytical and formal approaches. Functional verification.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 56
UNIT-VI Hardware Emulation 06Hours
Hardware emulation. Parametric testing, Reliability modeling, Yield models.
BOOKS:
Text:
T1: Charles H. Roth, ―Digital system design using VHDL‖, Thomson Publication
T2: M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design,
second edition, IEEE Press, 1990.
References:
R1: Brown, Vranesic ―Fundamentals of digital logic design with VHDL‖, McGraw Hill
R2: John F. Wakerly,‖Digital Design principles and practices‖, 3rd edition, PHI publications
R3: T. Krop, Introduction to Formal Hardware Verification, Springer Verlag, 2000.
R4: P. Rashinkar, L. Singh, System-on-a-Chip Verification-Methodology and Techniques, Kluwer second
edition, Academic Publishers, 2001.
R5:M. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-
Signal VLSI Circuits, Kluwer Academic Publishers,2000. Second edition.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 57
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -II [EC5112A]: MEMs and NEMs
Teaching Scheme: TH: 03 Hours/Week
Credit 03
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites: Basic electronic devices, application of each semiconductor materials with respect
to their properties, fabrication ideology and different process.
Course Objective:
1. To understand the multidisciplinary aspects of MEMS.
2. To study various applications of MEMs
3. To understand their fabrication and modelling methods of MEMs and NEMS devices.
4. To gain the concepts of MEMS sensors and measurement methods.
Course Outcome:
After successful completion of the course, students will able to:
CO1: Appreciate the underlying working principles of MEMS and NEMS devices.
CO2: Analyse different sensing and actuation methods and their applications.
CO3 : Ability to design and model these devices.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 58
CO4: Apply different measurement methods and tools for electrical applications.
Course Contents
UNIT-I Introduction to MEMs 06 Hours
Intrinsic characteristics of MEMS, miniaturization, Sensors and actuators, sensor noise and design
Complexity, packaging and integration, stress and strain, intrinsic stress, torsion deflections, types
of beams and deflection of beams.
UNIT-II MEMS based sensors and actuators 08 Hours
Electrostatic sensors and Actuators, Thermal sensing and actuation, piezoresistive sensing and
Actuation, Magnetic actuation. Comparison of major sensing and actuation methods. Case studies of
Selected MEMS: Acceleration sensors, gyros etc.
UNIT-III Fabrication Modules 06 Hours
Review of Basic MEMS/NEMS fabrication modules: Oxidation, Deposition Techniques, Lithography
(LIGA), and Etching.
UNIT-IV Micromachining 06 Hours
Micromachining: Surface Micromachining, sacrificial layer processes, Stiction; Bulk Micromachining,
Isotropic Etching and Anisotropic Etching, Wafer Bonding.
UNIT-V Mechanics of solids in MEMS/NEMS 08 Hours
Mechanics of solids in MEMS/NEMS: Stresses, Strain, Hooke’s law, Poisson effect, Linear Thermal
Expansion, Bending; Energy methods. Brief Overview of Finite Element Method. Modeling of Coupled
Electromechanical Systems.
UNIT-VI Measurements methods and tools 07 Hours
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 59
Electrical methods: Hot probe method, Sheet resistance, Hall Effect measurements. Physical
Measurements: Fourier Transform Infrared Spectroscopy, Electron microscopy, Atomic Force
Microscope, X-Ray photoelectron Spectroscopy, Profilometers, Reflectometers
BOOKS:
Text:
T1: Chang Liu, Foundations of MEMS, Pearson Education.
T2: Minhang Bao, Analysis and Design Principles of MEMS Devices, Elsevier.
References:
R1. S. D. Senturia, Microsystem Design, Kluwer Academic Publishers, 2001.
R2. M. Madou, Fundamentals of Micro fabrication, CRC Press, 1997.
R3. G. Kovacs, Micromachined Transducers Sourcebook, McGraw-Hill, Boston, 1998.
R4. M.H. Bao, Micromechanical Transducers: Pressure sensors, accelerometers, andgyroscopes,
Elsevier, New York, 2000..
R5. Journals: 1. Journal of Microelectromechanical Systems, IEEE/ASME.IEEE Transactions on
Nanotechnology.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 60
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -II [EC5112B]: Multirate Signal Processing
Teaching Scheme: TH: 04 Hours/Week
Credit 04
Examination Scheme: In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Total :100 Marks Course Prerequisites: Basic knowledge of signal system and signal processing is mandatory to understand .
Course Objective:
1. To understand state-of-the –art in multirate systems
2. To familiarize with wavelet theory, its implementation and representation
3. To understand the fundamentals of multirate signal processing and its applications
4. To study the theory and construction of wavelets and its practical implementations
Course Outcome:
After successful completion of the course, students will able to:
CO1 :Design and implement perfect reconstruction filter bank systems
CO2 : Specify and identify various implementation multiphase and polyphase representation
CO3:Design and implement wavelet-based systems.
CO4:Describe and analyze a compression or denoising system using wavelets
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 61
Course Contents
UNIT-I Fundamentals of Multirate systems 07 Hours
Basic multirate operations and their spectral representation. Fractional Sampling rate alteration,
Interconnection of building blocks, Noble identities, polyphase representations, Efficient structures
for decimation and interpolation filters.
UNIT-II Filter banks 07Hours
Uniform DFT filter banks, efficient structures for fractional decimation, Multistage
implementations, Applications of multirate systems, 2-channel QMF filter banks, Errors in the QMF
bank, conditions for perfect reconstruction, polyphase implementation, M-channel filter banks.
UNIT-III Wavelet Transforms 06 Hours
Continuous wavelet transform and short time Fourier transform, uncertainty principle and time -frequency
tiling
UNIT-IV Discrete wavelet transform 06 Hours
Haar scaling and wavelet functions, Daubechies wavelets. Designing orthogonal wavelet systems,
Discrete wavelet transform and relation to filter banks, computing and plotting scaling and wavelet
functions.
UNIT-V Biorthogonal wavelets 08 Hours
Biorthogonality in vector space, biorthogonal wavelet systems, construction of biorthogonal wavelet
systems. Frequency domain approach for designing wavelets: derivation of Daubechies wavelets.
Parametric design of orthogonal and biorthogonal wavelets.
UNIT-VI Wavelet packet analysis 06 Hours
Wavelet packet analysis, lifting schemes, Applications of wavelets in compression and denoising.
BOOKS:
Text:
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 62
T1:P. P. Vaidyanathan, Multirate Systems & Filter banks ,Prentice Hall
T2: K. P. Soman, K. I. Ramachandran, N. G. Resmi, PHI, Insight into wavelets from theory to practice.
References:
T2:.K.P. Soman, K. I. Ramachandran, N. G. Resmi, PHI, Insight into wavelets from theory to practice
T3:G. Strang& T. Nguyen , Wavelets and Filter bank, Wellesly-Cambridge.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 63
JSPM’s RAJARSHI SHAHU COLLEGE OF ENGINEERING
TATHAWADE, PUNE-33 (An Autonomous Institute Affiliated to Savitribai Phule Pune University,Pune)
F.Y.M. Tech (VLSI and Embedded System)
Academic Year – 2020-2021 Semester -II [EC5112C]: Industrial Internet of Things
Teaching Scheme:
TH: 03 Hours/Week
Credit
03
Examination Scheme:
In Sem. Evaluation : 15 Marks
Mid Sem. Exam : 25 Marks
End Sem. Exam : 60 Marks
Course Prerequisites: Knowledge of networking
Course Objective:
The Objective of this course is to make students learn and understand basic Concepts and principles of
IOT to design practical engineering problems and apply its solutions effectively and meaningfully. To
understand IIOT to building up of models, design issues, practical oriented skills and problem-solving
challenges in industry are the great task of the course.
Bring the IoT perspective in thinking and building solutions
Introduce the tools and techniques that enable IoT solution and Security aspects
Course Outcome:
After successful completion of the course, students will able to:
CO1:Bring the IoT perspective in thinking and building solutions.
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 64
CO2: Introduce the tools and techniques that enable IoT solution and Security aspects.
Course Contents
UNIT-I Introduction to IoT 07 Hours
Sensing, Actuation, Basics of Networking, Communication Protocols, Sensor Networks, Machine-
to-Machine Communications, Interoperability.
UNIT-II Introduction to IoT 07 Hours
Introduction, IoT Vs. IIoT, Why IIOT and why now? Introduction to Industry 4.0, Innovation and
IOT, Key benefits and opportunities, Architecture of IIOT, Market Segments and Verticals,
Economics of IoT
UNIT-III Enabling Technologies 06 Hours
Software defined Network for IoT, The role of Blockchain and Crypto Platforms in IIOT.
CloudComputing, Fog Computing.
UNIT-IV Security and Case studies 06 Hours
Importance of Security and Architecture, IoT Use-Cases and Case Studies: Healthcare, Power Plants,
Inventory Management & Quality Control, Plant Safety and Security, Connected Vehicles and Smart
Grid, Applications of UAVs in Industries.
UNIT-V Security in IIOT 07 Hours
Importance of Security and Architecture, Cyber-physical systems, IIoT security -vulnerabilities,
attacks, and countermeasures, security lifecycle.
UNIT-VI Case Studies in IIOT 07 Hours
Dr.B.D.Jadhav Dr. Mrs. S.V. Kedar Dr. R. K. Jain
B.O.S. Chairman Dean Academics Director RSCOE, Pune 65
IIoT Use-Cases and Case Studies: Healthcare, Power Plants, Inventory Management and Quality
Control, Plant Safety and Security, Connected Vehicles and Smart Grid, Applications of UAVs in
Industries.
BOOKS:
Text:
T1:Alasdair Gilchrist, “Industry 4.0,the Industrial Internet of Things”, Apress , 2018.
T2: Pethuru Raj and Anupama C. Raman , “The Internet of Things: Enabling Technologies, Platforms,
and Use Cases", CRC Press, 2017
T3: Internet of Things: A Hands-on Approach", by Arshdeep Bahga and Vijay Madisetti Universities
Press, 2017
T4: Rusell and D. Van Duren, “Practical Internet of Things Security,” Packt Publishing, 2016
References:
R1:Sabina Jeschke, Christian Brecher, Houbing Song, Danda B. Rawat, “ Industrial Internet of Things,
Cyber-manufacturing Systems,”Springer Series in Wireless Technology, Springer,2016
R2: NPTEL Course: INTRODUCTION TO INTERNET OF THINGS
R3. Research papers