Enhanced Acquisition and Tracking in All Digital Phase-Locked Loops

Circuits Syst Signal Process (2008) 27: 537–552DOI 10.1007/s00034-008-9042-y

Enhanced Acquisition and Tracking in All DigitalPhase-Locked Loops

Reza Danesfahani · Mohammad Moghaddasi ·Mahmood Mahlouji

Received: 23 April 2007 / Revised: 22 October 2007 / Published online: 3 June 2008© Birkhäuser Boston 2008

Abstract This paper presents a technique to substantially mitigate the tracking jit-ter of all digital phase-locked loops and, hence, enhance the overall performance ofthe loop. This has been achieved by a structure utilizing a notch filter in a cascadearrangement with the loop filter to suppress the undesired frequency components andpreserve the DC value at the output of the loop filter, which represents the trial valueof the carrier phase error. A rapid acquisition of the error and a bit error rate (BER)performance close to theoretical results have been achieved.

Keywords All digital phase-locked loop · Carrier phase synchronization · BER ·Acquisition · Tracking · Jitter

1 Introduction

A vital function of the receiver in synchronous communication systems is the carrierand symbol timing synchronization, which consists of the detection and correctionof the carrier and symbol timing errors. Any reduction in the tracking jitter of thesynchronizer can improve the overall performance of the system. All digital phase-locked loops are key components of modern communication systems. They have beenwidely applied to lock onto the carrier phase component in the received signal and,hence, attempt to rotate back the signal space diagram of the received signal to its

R. Danesfahani (�) · M. Moghaddasi · M. MahloujiTelecommunications Group, Faculty of Engineering, Science and Research Branch, Islamic AzadUniversity, Tehran, Irane-mail: [email protected]

M. Moghaddasie-mail: [email protected]

M. Mahloujie-mail: [email protected]

mailto:[email protected]



538 Circuits Syst Signal Process (2008) 27: 537–552

original location. The analysis, design, and performance of DPLLs have been inves-tigated extensively in the literature [1, 3, 4, 12, 15, 18, 22, 27, 28, 30]. One of theproblems in using any digital phase-locked loop (DPLL) is the presence of undesiredtracking jitter, which can deteriorate the overall performance of the system to an unac-ceptable level. In phase synchronization, tracking jitter is an unwelcome companion;indeed, its very name implies a nuisance effect. Generally, a low tracking jitter is adesirable feature to achieve a better bit error rate (BER) performance. One approachto reduce the excessive tracking jitter is to lessen the loop gain. The impact of sucha strategy is to prolong the acquisition time, which is not desirable in applicationssuch as those in low-Earth orbit satellites [9, 10] in which speed of acquisition is ofprime importance. However, any increase in the gain will aggravate the jitter. There-fore, in practice, a compromise between the gain and jitter establishes a reasonableperformance; the loop gain factor is tweaked to a level which results in an acceptablesynchronization performance.

In [29] a DPLL architecture has been presented to adaptively optimize the track-ing jitter using a jitter estimation block to achieve minimum jitter operation. In [21]a low-noise DPLL design technique to achieve minimum jitter from a given DPLLhas been described which not only estimates the timing jitter of a DPLL, but alsofinds the optimal bandwidth minimizing the overall DPLL jitter. The effects of vary-ing DPLL design parameters on timing jitter have been investigated in [23] to obtainminimum output jitter. In [5] a technique for achieving fast settling and good stabilityin all digital phase-locked loops has been proposed which utilizes self-monitoring toobtain the parameters necessary for feedforward compensation. The jitter reductionapproach taken in [20] and [7] is based on making a modification to symbol timingerror detection algorithms of [11] and [25], respectively, to reduce the level of jit-ter for M-PSK signals. In [2] a new dynamic gain modification algorithm has beenproposed to enhance the speed of transient response and tracking behavior of DPLLswithout changing the order of the loop. In this algorithm, the gain of the loop digitalfilter is made a function of the sampled value of the signal at every sampling instance.Automatic frequency control (AFC) loops may be utilized to synchronize the carrierfrequency error. In [6] a smart filter was introduced to improve the tracking perfor-mance of the Gardner AFC loop [13]. This smart filter was further employed in aphase synchronization loop to make the tracking performance almost jitter free [8].

The above literature survey of different jitter reduction techniques can be dividedinto five groups working on the following principles:

(1) Estimation of the jitter [21, 29](2) Selection of the loop design parameters [5, 23](3) Modification of the detector [7, 20](4) Dynamic modification of the loop gain [2](5) Modification of the loop filter [6, 8].

A technique to mitigate the tracking jitter in carrier phase synchronizers employingDPLLs, without sacrificing the acquisition speed, is proposed in the sequel. Thistechnique belongs to the last group and employs a structure incorporating a notchfilter in a cascade arrangement with the loop filter to modify the overall filteringperformance of the DPLL.

Circuits Syst Signal Process (2008) 27: 537–552 539

The organization of this paper is as follows. An overview of a system incorporatinga typical DPLL is presented in Sect. 2. The enhancement technique will be presentedin Sect. 3, which will be followed by simulation results in Sect. 4. Computationalcomplexity is addressed in Sect. 5. Further investigations into the applicability of theproposed approach with other error detection algorithms and modulation schemeswill be presented in Sect. 6. Our conclusions will be drawn in Sect. 7.

2 System Model

Figure 1 depicts a typical DPLL, which is used to synchronize the carrier phase error.The phase rotated complex sampled matched filter output after downsampling to onlyone sample per symbol is fed to a phase error detector (PED) which attempts todetermine the best estimate of the carrier phase error. The trial value of the error isdetermined by smoothing the error estimates using a loop filter. The resulting signal atthe output of the filter has information on the actual error estimated, acquisition time,and the tracking jitter. This signal is fed to a voltage-controlled oscillator (VCO) or adigital-controlled oscillator (DCO), which, in turn, together with a complex multiplierare used to rotate back the phase of the received signal to where it should be. TheVCO and DCO are controlled by input voltage and digital code, respectively. Theloop gain factor, β , controls the speed of acquisition of the error, and the amountof the tracking jitter. The specifications of the baseband model of a system are asfollows:

• Modulation: Binary phase-shift keying (BPSK)• PED: Digitized version of the Costas algorithm [17]• Excess bandwidth of root raised cosine filters at the transmitter and receiver: 50%• Loop filter: A digital integrator• Channel: Additive white Gaussian noise (AWGN).

It has been assumed that prior to phase synchronization the Doppler shift and symboltiming errors have been fully synchronized. In the next section, the enhancementtechnique is described.

Fig. 1 Carrier phase synchronization loop


3 Enhancement

During tracking, the trial value of the phase error, appearing at the output of the loopfilter, consists of a desired DC component representing the actual phase error and anunwanted high frequency component known as jitter. The latter must ideally vanish.Jitter-induced errors can substantially deteriorate the BER performance. To improvethe performance of DPLLs, the loop of Fig. 1 was enhanced as shown in Fig. 2 witha jitter reduction block whose main function is to single out the DC component. Thisblock consists of

• a first- or second-order notch filter• a summing junction.

Ideally, all input frequency components except DC pass through the notch filter. Bysubtracting the output of the filter from its input, only DC will be present at the outputof the jitter reduction block. However, in practice, some frequency components aboutDC also appear at the output of the jitter reduction block. Therefore, we expect to seean approximately jitter-free performance of the loop.

For a first-order notch filter, the transfer function is [19]

H1N(z) = K1 − z−1

1 − rz−1(1)

where r is the pole radius of the filter (0 � r < 1), z = ejωTs , ω is the angular fre-quency, Ts is the sampling period, and K is a scaling factor such that the maximumgain of the filter equals unity. Substituting the normalized frequencies ωTs = 0 andωTs = π in (1) results in H1N(z) = 0 and H1N(z) = 2K

1+r, respectively. By choosing

K = 1+r2 , H1N(z) is normalized. To eliminate the frequency components higher than

DC, the first-order jitter reduction block of Fig. 2 must have the following transferfunction:

H1R(z) = 1 − H1N(z)

= 1 − 1 + r

2

1 − z−1

1 − rz−1

Fig. 2 Enhanced carrier phase synchronization loop


= 1 − r

2

1 + z−1

1 − rz−1(2)

By substituting z = ejωTs in (2), it can be shown that the magnitude response ofH1R(z) is as follows:

∣∣H1R

(

ejωTs)∣∣ = 1 − r

2

√

2(1 + cos(ωTs))

1 + r2 − 2r cos(ωTs)(3)

which, as will be shown shortly, attenuates the unwanted jitter while the DC compo-nent is allowed to pass unattenuated.

The transfer function of a second-order notch filter is [19]

H2N(z) = K1 − 2 cosω0Tsz

−1 + z−2

1 − 2r cosω0Tsz−1 + r2z−2(4)

where ω0 is the notch frequency, r is the radius of the complex-conjugate pole pairlocated at the (normalized) frequency ω0Ts , and K is again a scaling factor. For theblock to mitigate the tracking jitter, the notch frequency must be set to zero. There-fore,

H2N(z) = K1 − 2z−1 + z−2

1 − 2rz−1 + r2z−2(5)

which reduces to zero and 4K/(1 + r)2 at ωTs = 0 and ωTs = π , respectively. Multi-plication of (5) by (1 + r)2/4K and subsequent subtraction from unity results in thefollowing transfer function of the second-order jitter reduction block:

H2R(z) = 1 − (1 + r)2

4

1 − 2z−1 + z−2

1 − 2rz−1 + r2z−2(6)

which can be written as

H2R(z) =(1−r)(r+3)

4 [1 + 2 1−rr+3z−1 − 3r+1

r+3 z−2]1 − 2rz−1 + r2z−2

(7)

which has two zeros at (3r + 1)/(r + 3) and −1, and a second-order repeated poleat r . Equation (7) can be written as

H2R(z) =(1−r)(r+3)

4 [(1 + z−1)(1 − 3r+1r+3 z−1)]

(1 − rz−1)2(8)

or

H2R(z) =[ 1−r

2 (1 + z−1)

1 − rz−1

][ r+32 (1 − 3r+1

r+3 z−1)

1 − rz−1

]

= H1R(z)

[ r+32 (1 − 3r+1

r+3 z−1)

1 − rz−1

]

(9)


Fig. 3 Magnitude response of jitter reduction blocks

whose magnitude response can be shown to be

∣∣H2R

(

ejωTs)∣∣ = (1 − r)(r + 3)

4

√

2(1 + cos(ωTs))(1 + ( 3r+1r+3 )2 − 2 3r+1

r+3 cos(ωTs))

1 + r2 − 2r cos(ωTs)(10)

The responses given by (3) and (10) have been plotted in Fig. 3. It is clearly seenthat the input DC component is allowed to pass unattenuated while high frequencycomponents are attenuated. The simulations in Sect. 4 confirm that blocks with suchresponses substantially mitigate the tracking jitter.

4 Simulation Results

To test the performance of the system of Fig. 2, the varying carrier phase error il-lustrated in Fig. 4 was used. For presentation purposes, only the first 1,000 symbolshave been shown. The simulated error was set to change stepwise at random every100 symbols in steps of ±5◦ and ±15◦. In synchronous demodulation, it is presumedthat the phase error remains unaltered for a long enough time for the DPLL to acquirethe error signal before the error is changed to a different value. The loop gain factorwas purposely set to a high value to achieve a fast acquisition. Under such conditions,the results shown in Fig. 5 were obtained, about which the following comments canbe made.

• The loop is trying to acquire the error. However, it is not clear when the error hasbeen acquired.

• The loop is trying to track the error about the stable point. However, the trackingjitter present in the loop is noticeable.


Fig. 4 Actual phase error

Fig. 5 Tracking performance before enhancement

As will be shown shortly, such a performance manifests itself as a poor BER. Froma practical perspective, this makes the simulated receiver, as it stands, useless for anyapplication.

Simulation of the enhanced loop using a first-order jitter reduction block withr = 0.9 at ω0Ts = 0 and β = 2.1 was carried out using the same conditions un-der which the modem with the original loop was simulated. An expression for β

in DPLLs with a first-order jitter reduction block has been derived in Appendix 1.


Fig. 6 Tracking performance after enhancement

The result shown in Fig. 6 was obtained, about which the following observations arereadily made.

• Unlike the original loop, the enhanced DPLL has clearly acquired the error.• The acquisition time of the phase error is only about 40 symbols, which is a clear

indication of the fast response of the enhanced DPLL.• After the acquisition time, the tracking jitter has been substantively mitigated.

Fast acquisition of the carrier phase error is a highly desirable feature in real-timeapplications. A fast acquisition time and a much mitigated tracking jitter are two ofthe salient features of the proposed enhancement.

The Monte Carlo BER counting simulation performances of the original and en-hanced DPLLs when the received signal was plagued with AWGN are shown inFig. 7. The theoretical BER results were plotted using p = 0.5 erfc(

√Eb/N0), where

erfc(x) is the complementary error function of x, and Eb/N0 is the ratio of energy perbit to noise spectral density [14]. For the typical BER confidence band (1.25p̂,0.8p̂),where p̂ is the estimated p, the total number of bits simulated was M = 10N+2 forthe theoretical BER of p = 10−N at any Eb/N0 [16]. The BER performance of theoriginal DPLL is not acceptable at all. Excessive tracking jitter is the sole contributorto this poor performance. The simulation results of the original DPLL enhanced withthe jitter reduction block are also shown in Fig. 7 with signal-to-noise ratios (SNRs)ranging from 0 to 10 dB. The BER results of the enhanced DPLL closely follow thetheoretical performance, which is of great importance. A low tracking jitter has amajor role in the resulting superior BER performance, which is close to theoreticalresults.

To investigate whether any further improvement can be achieved by a higher-orderDPLL, simulations were carried out using a second-order jitter reduction block withr = 0.9 at ω0Ts = 0 and β = 2.1. An expression for β in DPLLs with a second-order


Fig. 7 BER performance before and after enhancement

Table 1 BER results of DPLLs with first- and second-order jitter reduction blocks

SNR (dB) BERII BERI |BERII − BERI|

0 0.4012841092 0.4012841092 ≈0

1 0.0636456219 0.0653680220 0.0017224001

2 0.0414937759 0.0417188152 0.0002250393

3 0.0261355915 0.0261178437 0.0000177478

4 0.0137744842 0.0132170235 0.0005574607

5 0.0066010959 0.0066833304 0.0000822345

6 0.0027509711 0.0027399963 0.0000109748

7 0.0009534888 0.0009596119 0.0000061231

8 0.0002250231 0.0002301741 0.0000051510

9 0.0000409900 0.0000412016 0.0000002116

10 0.0000044600 0.0000044140 0.0000000460

jitter reduction block has been derived in Appendix 2. The simulation results havebeen tabulated in Table 1, in which BERI, BERII, and |BERI − BERII| represent theBER performance obtained with first- and second-order jitter reduction blocks, andthe magnitude of the difference between BERI and BERII, respectively. As is ob-served from the results, the difference between the BER performance obtained by us-ing a second-order jitter reduction block is marginal compared to that obtained usinga first-order jitter reduction block. With this in mind, and to keep the loop computa-tional complexity to a minimum, it suffices to use only a first-order jitter reductionblock, and, hence, the second-order jitter reduction block has been dispensed with.


Fig. 8 Smart filter [6]. Reproduced by written permission of the IET

Table 2 BER results of DPLLs with smart filter and first-order jitter reduction block

SNR (dB) BERSF |BERSF − BERI|

0 0.0817929003 0.3194912089

1 0.0590876861 0.0062803359

2 0.0419111484 0.0001923332

3 0.0254712175 0.0006466262

4 0.0132978723 0.0000808488

5 0.0067980965 0.0001147661

6 0.0028686173 0.0001286210

7 0.0011064395 0.0001468276

8 0.0002200700 0.0000101041

9 0.0000380807 0.0000031209

10 0.0000042088 0.0000002052

The first-order jitter reduction block was then replaced with the smart filter ofFig. 8, and the BER counting simulations were repeated. The modem specificationsremained the same as before. The numerical results shown by BERSF in the secondcolumn of Table 2 were obtained. As is seen from the third column, except at SNR =0 dB, the technique presented in this paper has a very close performance to that ofthe smart filter.

5 Complexity

The implementation of jitter reduction blocks given in (2) and (7) are based on adirect-form II transposed structure [26]. The resulting number of delay elements,scaling factors, and adders has been shown in the first and second columns of Table 3.

As is seen from Fig. 8, the smart filter consists of two scaling factors, oneadder, one multiplier, one integrator, two moving averagers, one comparator, and onedifference-in-time block. The integrator and difference-in-time block each requireone delay and one adder. The discrete-time input, x[n], and output, y[n], signals of


Table 3 Comparison of computational complexity of first-order jitter reduction (COMPI), second-orderjitter reduction Block (COMPII), and smart filter (COMPSF)

COMPI COMPII COMPSF

Delay elements 1 2 104

Scaling factors 2 5 4

Adders 2 4 7

Multipliers 0 0 1

Comparators 0 0 1

the moving averagers are related by [26]

y[n] = 1

M2 + 1

M2∑

k=0

x[n − k] (11)

where n is an integer and M2 is a positive constant, which was taken as 49 in [6].From (11), one can write

y[n] − y[n − 1] = 1

M2 + 1

(

x[n] − x[n − M2 − 1]) (12)

which has been used to determine the computational complexity of a moving aver-ager. As is seen from (12), a scaling factor, two adders, and M2 +2 delay elements arerequired to implement a moving averager. In the third column of Table 3, the overallcomputational complexity of the smart filter has been shown. It is clearly seen thatthe computational complexity of jitter reduction blocks is less than that of the smartfilter. This implies that it takes jitter reduction blocks less time to determine the out-put signal, which is of importance in fast applications. Furthermore, the proposedtechnique is simpler to implement than the smart filter, which requires a switch; it isnot always straightforward to set the switching criterion.

6 Further Investigations

The enhancement technique described herein is general and can be applied to DPLLsincorporating other PEDs. The aforementioned simulations were repeated with othercarrier phase error detection algorithms, such as the decision-directed maximum like-lihood algorithm and the decision-directed arctangent algorithm [24]. Furthermore,the BPSK modulation scheme was changed to quadrature phase-shift keying (QPSK),offset quadrature phase-shift keying (OQPSK), and π/4-shifted differentially en-coded quadrature phase-shift keying (π/4-DQPSK) modulation schemes, and thesimulations were repeated. The tracking and BER results obtained were consistentlybetter when the proposed enhancement was used.


7 Conclusions

In this paper, a simple yet powerful unified technique was presented to make thetracking performance of all digital phase-locked loops approximately jitter free. Inlight of the research carried out, a substantial improvement was made to the BERperformance. A fast acquisition time, a low computational complexity, and an opera-tion independent of the modulation and error detection schemes are other features ofthe proposed technique.

Acknowledgements The authors would like to gratefully thank the anonymous reviewers for their nu-merous invaluable suggestions and comments on improving the paper.

Appendix 1: Design of DPLLs with a First-Order Jitter Reduction Block

Frequency domain models of analog and all digital PLLs are shown in Figs. 9 and 10,in which θ and θ̂ are the carrier phase error and the trial value of the error, respec-tively.

In Fig. 9 the transfer function of the lowpass filter, assuming a first-order one, isgiven by

F(s) = 1

1 + τ1s

= G

G + s, G = 1/τ1 (13)

Fig. 9 Frequency domainmodel of analog PLL

Fig. 10 Frequency domainmodel of all digital PLL


where τ1 is the filter time constant. The loop transfer function is

H(s) = θ̂ (s)

θ(s)

= K0Kp

s2τ1 + s + K0Kp

(14)

which can be written as

H(s) = ω2n

s2 + 2ζωns + ω2n

(15)

where ζ = 12τ1ωn

and ωn =√

K0Kp

τ1are the damping factor and natural frequency of

the loop, respectively. Using a bilinear transformation [26],

F(z) = F(s)∣∣

s=C 1−z−1

1+z−1(16)

or

F(z) = K1(1 + z−1)

1 − z−1 + K2(17)

where K1 = GC−G

and K2 = 2GC−G

. The transfer function of the loop in Fig. 10 isgiven by

H(z) = θ̂ (z)

θ(z)

=KpK0K1(1+z−1)z−1

(1−z−1)(1−z−1+K2)

1 + KpK0K1(1+z−1)z−1

(1−z−1)(1−z−1+K2)

(18)

or

H(z) =KpK0K1K2+1 (z−1 + z−2)

1 + KpK0K1−K2−2K2+1 z−1 + KpK0K1+1

K2+1 z−2(19)

On the other hand, the loop transfer function in the z-domain can be found usinga bilinear transformation as

H(z) = H(s)∣∣

s= 2Ts

1−z−1

1+z−1

= ω2n

T 2s

4(1−z−1)2

(1+z−1)2 + 2ζωnTs

21−z−1

1+z−1 + ω2n

T 2s

4

(20)


The above equation can be written as

H(z) =θ2n

1+2ζ θn+θ2n(1 + z−1)2

1 + 2(θ2n−1)

1+2ζ θn+θ2nz−1 + 1−2ζ θn+θ2

n

1+2ζ θn+θ2nz−2

(21)

where θn = ωnTs

2 is half the normalized natural frequency. By equating the denomi-nators of the results obtained in (19) and (21),

KpK0K1 − K2 − 2

K2 + 1= 2(θ2

n − 1)

1 + 2ζθn + θ2n

(22)

and

KpK0K1 + 1

K2 + 1= 1 − 2ζθn + θ2

n

1 + 2ζθn + θ2n

(23)

By subtracting (22) from (23) and performing some simplifications, K2 is foundas

K2 = 4ζθn + 2θ2n

1 − 2ζθn − θ2n

(24)

By substituting K2 in (23),

KpK0K1 = 2θ2n

1 − 2ζθn − θ2n

(25)

With the transfer function of the first-order jitter reduction block in (2), the loopfilter transfer function can be written as

F(z) = β1 − r

2

1 + z−1

1 − rz−1(26)

By comparison of F(z) above with that in (17),

β1 − r

2

1 + z−1

1 − rz−1= K1(1 + z−1)

1 − z−1 + K2

= K1

1 + K2

(1 + z−1)

1 − 1K2+1z−1

(27)

With r = 11+K2

, and equating β 1−r2 with K1

1+K2, the loop gain factor is found as

β = 2rK1

1 − r(28)

By substituting K2 in the expression for r and performing some simplificationsthe normalized natural frequency is determined as

θn = −ζ +√

ζ 2 + 1 − r

1 + r(29)


Since 0 � r < 1 and θn must be positive, only the positive root has been acceptedin (29). With θn specified, K1 can be found from (25). Furthermore, β is found from(28).

Appendix 2: Design of DPLLs with a Second-Order Jitter Reduction Block

With the transfer function of the second-order jitter reduction block given in (7), theopen loop transfer function can be written as

G2(z) = K0Kpβz−1

1 − z−1H2R(z)

= K0Kpβ1 − r

4

(r + 3)z−1 − 2(r − 1)z−2 − (3r + 1)z−3

1 − (1 + 2r)z−1 + r(r + 2)z−2 − r2z−3(30)

To design the third-order DPLL of (30), the unity gain crossover frequency, f0,and phase margin, φ, are required. To this end,

∣∣G2

(

ej0)∣∣ = 1 (31)

and

π + arg[

G2(

ej0)] = φ (32)

where 0 = 2πf0Ts is the normalized unity gain crossover radian frequency. Bysubstituting z = ej0 in (30),

G2(

ej0) = K0Kpβ

1 − r

4

(r + 3)e−j0 − 2(r − 1)e−j20 − (3r + 1)e−j30

1 − (1 + 2r)e−j0 + r(r + 2)e−j20 − r2e−j30(33)

Since 0 � r < 1, it is deduced that K0Kpβ 1−r4 > 0. By substituting (33) in (31),

the loop gain factor, β , is found as

β = 4

K0Kp(1 − r)

√

1 − (1 + 2r)e−j0 + r(r + 2)e−j20 − r2e−j30

(r + 3)e−j0 − 2(r − 1)e−j20 − (3r + 1)e−j30(34)

Similarly,

arg

((r + 3)e−j0 − 2(r − 1)e−j20 − (3r + 1)e−j30

1 − (1 + 2r)e−j0 + r(r + 2)e−j20 − r2e−j30

)

= φ − π (35)

With r and φ known, 0 is found from (35) by numerical methods. With 0known, from (34) the loop gain factor is also found.

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Enhanced Acquisition and Tracking in All Digital Phase-Locked Loops

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