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Applied Soft Computing 12 (2012) 1440–1450

Contents lists available at SciVerse ScienceDirect

Applied Soft Computing

j ourna l ho me p age: www.elsev ier .com/ l ocate /asoc

nabling fuzzy technologies in high performance networking via an openPGA-based development platform

ederico Montesino Pouzolsa,d,∗, Angel Barriga Barrosb, Diego R. Lopezc, Santiago Sánchez-Solanod

Department of Biosciences, Center of Excellence in Metapopulation Biology, University of Helsinki, Viikinkaari 1, P.O. Box 65, FI-00014, FinlandDepartment of Electronics and Electromagnetism, University of Seville, Avda. Reina Mercedes s/n. Edif. CICA, E-41012 Seville, SpainTelefónica I+D, Don Ramón de la Cruz, 82-84, E-28006 Madrid, SpainMicroelectronics Institute of Seville (IMSE-CNM), CSIC, C. Americo Vespucio s/n, E-41092 Seville, Spain

r t i c l e i n f o

rticle history:eceived 3 April 2009eceived in revised form 29 July 2011ccepted 23 October 2011vailable online 12 November 2011

eywords:uzzy inferenceield programmable gate arraysomputer networksetwork traffic control

a b s t r a c t

Soft computing techniques and particularly fuzzy inference systems are gaining momentum as tools fornetwork traffic modeling, analysis and control. Efficient hardware implementations of these techniquesthat can achieve real-time operation in high-speed networking equipment as well as other highly time-constrained application fields is however an open problem. We introduce a development platform forfuzzy inference systems with applications to network traffic analysis and control. The platform addressesthe current requirements and constraints of high performance networking equipment. For the develop-ment process, we set up a methodology and a CAD tool chain that span the entire design process frominitial specification in a high-level language to implementation on FPGA devices. An FPGA developmentboard with PCI/PCIe interface is employed to support an open platform that comprises CAD tools aswell as IP cores. PCI compatible fuzzy inference modules are implemented as System-on-Programmable-

ongestion controlueuing controletwork performance

Chip (SoPC). We present satisfactory experimental results from the implementation of fuzzy systems for anumber of applications in analysis and control of Internet traffic. These systems are shown to satisfy oper-ational and architectural requirements of current and future high performance routing equipment. Theplatform proposed allows for the development of prototypes while avoiding large investments and com-plicated management procedures which constrain the testing and adoption of soft computing techniquesin high performance networking.

. Introduction

Soft computing techniques and particularly fuzzy inference sys-ems have been gaining momentum during the last decade as toolsor modeling, analysis and control of network traffic. Fuzzy infer-nce systems have been shown to be effective in areas such as trafficontrol in routers [16,28,76,68,31,13], support for differentiatedervices within the DiffServ architecture [58,77,74,18], real-timeraffic measurement, analysis and monitoring [61,63,62,64], powernd quality of service optimization for wireless networks [55,72], as

ell as end-to-end traffic control [65,27] and buffer control [49,64].

fficient hardware implementations of these techniques that canchieve real-time operation in high-speed communications

∗ Corresponding author at: Microelectronics Institute of Seville (IMSE-CNM), CSIC,. Americo Vespucio s/n, E-41092 Seville, Spain. Tel.: +34 954 466 666;ax: +34 954 466 600.

E-mail addresses: federico.montesinopouzols@helsinki.fi (F.M. Pouzols),arriga@us.es (A.B. Barros), diego@tid.es (D.R. Lopez), santiago@imse-cnm.csic.esS. Sánchez-Solano).

568-4946/$ – see front matter © 2011 Elsevier B.V. All rights reserved.oi:10.1016/j.asoc.2011.10.018

© 2011 Elsevier B.V. All rights reserved.

equipment as well as many other demanding application fields ishowever an open problem.

Current routing architectures pose two major challenges inthe design of new mechanisms: scalability and flexibility of imple-mentations. Here we introduce a platform and a companiondevelopment methodology for developing fuzzy systems that doesnot only fulfill operational requirements but also addresses thechallenges posed by current routing architectures.

A major research problem in Internet transport and networklayers is the development of traffic regulation mechanisms that cancope with the requirements of a growing diversity of technologies,applications and services. More generally, Internet traffic dynamicsis an increasingly complex topic of research [66].

As stated above, diverse research results show that fuzzy infer-ence systems can help solve current problems in Internet trafficcontrol. However, while many industrial applications of fuzzy sys-tems in a variety of fields have been reported, fuzzy systems for

traffic control have not yet found their way into real-world applica-tions. Despite the good performance of the aforementioned fuzzylogic based mechanisms for traffic analysis and control, there isa lack of architectures and design procedures for implementing

F.M. Pouzols et al. / Applied Soft Com

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Fig. 1. High-end routers technological trends (log scale) [38,39,47,19,46,15,56].

hem in a systematic manner yet addressing current challenges inigh performance networking systems. As a consequence, althoughignificant results in diverse applications of fuzzy systems in com-unications and networking have been reported since more than

decade [35], the deployment of these systems in the real world istill a challenge.

Both academia and major vendors are currently pushing foristributed and modular router designs, specially for high-endackbone routers. In these designs routers are composed of mod-les that can be mapped onto different processing elements whichommunicate over an internal network [38]. Hardware for high-nd networking systems has been traditionally developed in austom and unstructured manner. Nevertheless, reconfigurablerchitectures are employed in practice by most vendors and designethodologies for easing the development process are sought.Technological trends in Internet core routers and high-end

ommunications hardware in general (see Fig. 1) lead to hard con-traints specially regarding packet processing rates. During the lastears total Internet traffic has grown at over 80 percent per year,hich directly translates into a similar or even higher increase of

raffic volume in backbone routers. Overall, network traffic vol-me increases at a rate that outpaces advances in VLSI technology.ithin this context, two main constraints arise: scalability (pro-

essing units must be able to process up to millions of packetser second (Mpps or Mp/s)), and flexibility and reconfigurabilityf implementations (a requirement imposed by the fast increasingiversity of protocols and technologies involved) [38,70].

As further discussed in the next section, a number of techno-ogical and architectural factors impose strict constraints on trafficnalysis and control mechanisms in high performance networkingquipment. Hence, efficient yet flexible hardware implementationsf soft computing methods and specially fuzzy inference systemshat can achieve real-time operation in high-speed networkingquipment are needed. The motivation for this work is to overcomehese practical difficulties. The major contributions of this paperre as follows. The implementation of fuzzy inference systems isade possible within the practical constraints of contemporary

igh performance networking equipment. To this end, we provide development platform which includes a complete methodologynd automated design flow, as well as CAD tools. In addition, theseystems are evaluated in simulated, emulated and test scenarios.inally, this paper reports prototypes that provide evidence for theeasibility of these soft computing systems in contemporary higherformance networking equipment.

The next section outlines current implementation issues inetworking equipment which motivate this work. Then, Sec-ion 3 describes the development platform architecture defined for

mplementing fuzzy systems. Section 4 deals with the development

ethodology and design flow applied. Simulation and experi-ental implementation results are then presented in Section 5.

puting 12 (2012) 1440–1450 1441

Hardware (FPGA-based) implementation results are described anddiscussed in Section 6. Finally, we conclude in Section 7.

2. Implementation constraints in networking equipment

Routers can be classified into three classes depending on thelevel of deployment within the Internet. These classes correspondto access routers, campus or enterprise routers and core routers.The focus of this paper is particularly on core or high-end routers,those designed for network backbones. By tying together networksof the global Internet, routers made up a unified whole. While themain function of a router is to forward packets from a set of inputlinks to a set of output links, they must also implement complex dis-tributed routing algorithms, deal with diverse link technologies andprovide support for traffic engineering tasks, differentiated servicesas well as quickly evolving quality of service schemes.

The architecture of Internet routers has evolved at a fastrate since the first implementations appeared [36,67,19,46].Drastic changes have taken place during the past twodecades [14,22,24,48,6,70,15]. This evolution has been drivenby a number of technological trends and functional requirements.On the one hand, the divergence in performance increase seen bythe diverse components of a router (such as memory elements,interconnection links, programmable devices and processors,see Fig. 1) challenges router design. On the other hand, newfunctional requirements have arised as new applications, servicesand technologies are being deployed. As a consequence, a greatdeal of research efforts is ongoing to address these challenges inrouter design.

In this context, high throughput IP routers require that criti-cal tasks be identified and isolated, using tailored special purposemodules to perform them [6]. The basic principle in routinghardware design and Network Processing Unit (NPU) based sys-tems [23,26,25,45,24] is to exploit parallelism against the mainlimiting factor imposed on overall performance: the memory accessspeed. There are two main alternatives for the hardware imple-mentation of an NPU: architectures based on general purposeprocessors, such as the NPUs from a number of vendors [39], andspecific architectures, with better performance but lower flexibil-ity. In the latter case, the development time is excessively longas compared to the fast evolution of applications, protocols andservices.

Presently, a hybrid approach is followed to satisfy flexibilityrequirements. This leads to designs where high-end routers usegeneral purpose units together with co-processing and accelerationelements (processing engines) implemented as ASIC or on specificFPGA devices. FPGA devices are thus used not only for develop-ing prototypes but also for final products. In the current Internet,link speeds and packet processing rates are quickly increasing. Thepace at which the speed of memory elements as well as other com-ponents of the router processing units increases is significantlyslower. That is, the rates at which two key technological factorsevolve have been increasingly diverging, and it is expected thatthis trend will continue. As a consequence, many data storage andprocessing elements (or processing engines) in current routers areimplemented by means of specialized processing engines usingspecific hardware architectures [24–26,38,23].

Regarding traffic measurement, analysis and control, specifichardware architectures are sought in order to cope with theincreasing packet processing rates. Specific hardware architectureshave been proposed for measurement [30], analysis of network

engines [24–26]. In particular, when implementing active queuemanagement schemes, the packet queue control rate must be veryclose to the maximum packet processing speed attainable by a

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outer. This is a strong requirement that is further augmented bywo coincidental factors:

Traffic in packet switched networks is inherently bursty. Longbursts of packets at the highest link speed are fairly common ina broad spectrum of network scenarios [57].Queue lengths are commonly small, around a few tens of pack-ets [3].

hus, controlers must have a fine packet processing granularity inrder to cope with packet bursts and properly control small packetueues.

Let us now consider the implementation of fuzzy inference sys-ems applied to traffic analysis and control in routers. Though aully software solution would be obviously more flexible than aardware solution, it is very straightforward to show that soft-are implementations cannot currently attain inference rates of

he order of MFLIPS, tens of MFLIPS and higher even running onigh performance general purpose CPUs. In fact, the inference speedttainable by software implementations running on current generalurpose CPUs is in the best cases one order of magnitude below thatf the hardware implementations described in this paper (see chap-er 6 of [64] for detailed results). Furthermore, these high but stillnsufficient rates are only possible in general purpose architecturest the expense of a fully dedicated core of current high performanceeneral purpose processors, which would require unfeasible costnd power consumption, as tens or hundreds of these units areeeded in current routers. In addition, inference speed require-ents are expected to grow at a faster pace than that of software

ased processing units.Rather than using software implementations running on general

urpose hardware (that would imply higher cost and insufficienterformance in most cases), in current routing architectures com-utationally intensive and critical processes are run on hardwarerocessing engines that use specialized architectures. This is thease for instance of TCAM memories [56], often used for stor-ng and querying routing information bases. Even though in theast pure-ASIC implementations have been employed, currentlyhese engines are commonly implemented on one or several FPGAevices per interface card for better programmability and designexibility. Specific tasks are implemented by specialized subsys-ems whereas general purpose processing units realize high level

anagement tasks and coordination functions.Thus, efficient hardware implementations are required to fulfill

ommon operational requirements in traffic analysis and controlechanisms to be implemented in routers. Although implemen-

ations of fuzzy inference systems are usually computationallyntensive, their performance can be boosted by means of hardwaremplementations based on architectures tailored to fuzzy inference,hat exploit the inherent parallelism of fuzzy inference or otherwiseimplify the inference process.

Specific hardware architectures and design methodologies haveeen developed for fuzzy inference systems [8], thus making themn a priori feasible solution for processing massive traffic volumesn real-time. Enabling fuzzy technologies in this area of applicationy overcoming the issues discussed in this section is the main moti-ation of this work. A development platform to tackle this problems presented in the next section.

. Development platform for fuzzy inference systems withpplications to networking

We introduce an open FPGA-based platform for the develop-ent of modular fuzzy components of complex systems [60,59].

he platform is integrated with a comprehensive set of software

Fig. 2. Prototype development platform scheme.

tools and an environment for easing the development and val-idation of fuzzy systems. It has been successfully employed inorder to develop intelligent traffic analysis and control systems thatcan achieve real-time operation within current high performanceInternet routers. The platform has been developed with a twofoldobjective in mind:

• Enabling the automated and efficient (in terms of performanceand development effort) implementation of a number of fuzzysystems proposed throughout the last years.

• Fostering the research on fuzzy logic based solutions to Internettraffic analysis and control. This is a consequence of the avail-ability of a platform for validating hardware prototypes usinginexpensive equipment, which eases testing in experimental net-work environments.

Throughout more than a decade, strategies and methodologiesfor developing fuzzy logic based controlers have been proposedand applied. To date, most work on this topic has been focusedon industrial applications [10] and, more recently, on areas such assignal processing, image processing and switching power control.

Let us consider the task of evaluating a traffic analysis and con-trol system whose performance depends on the nature of traffic.Ideally, one should be able to deploy the system and study its per-formance in the real world. However this is most often impossible,specially in the case of active queue management schemes. There-fore, the availability of flexible means for evaluating such systemswith different traffic patterns (be it through simulation, emulationor implementation) is a key aspect of design. The platform is definedso that fuzzy systems are integrated as independent modules intocomplex systems.

Additional requirements are: seamless integration into currentrouter architectures [47], flexibility, and performance scalability upto higher requirements in current and foreseeable network tech-nologies. The platform provides a complete set of tools and anenvironment for easing the development of fuzzy systems for net-working prototypes as well as performing its validation.

Fig. 2 depicts the architecture of the platform. It is based ona commodity PC equipped with an FPGA development board withPeripheral Component Interconnect (PCI/PCIe) interface, thus mak-ing a flexible and inexpensive solution with no specific hardwarerequirements yet able to emulate the behavior of complex andexpensive routing equipment. This makes it possible to performexperimental validation by means of prototypes using inexpensivehardware.

Two main function blocks can be distinguished when imple-menting systems based on fuzzy technologies: those directly

related to fuzzy inference and those that can be classified asauxiliary functions, such as initialization, timing, pre- and post-processing [10]. The following model is used:

F.M. Pouzols et al. / Applied Soft Computing 12 (2012) 1440–1450 1443

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Fig. 3. Fuzzy SoPC as a PCI device.

Fuzzy inference modules (FIM), the potential system bottlenecks,are implemented on FPGA devices and described by means ofVHDL according to an specific processing architecture [8] tailoredfor efficient and fast fuzzy inference. This is described in the nextsection.In the basic configuration of the platform, all auxiliary functionsare implemented as software. Software can run on the PC oper-ating system as well as on optional components implemented onthe FPGA.

A flexible and open architecture for implementing fuzzy systemsn the FPGA has been defined. Within this architecture, depictedn Fig. 3, FIM modules are integrated as subsystems of a potentiallyomplex and reconfigurable fuzzy logic based digital systems.

Interconnection between the host PC and the fuzzy inferenceodule (FIM) is done through a standard PCI/PCIe bus. The inter-

al bus of the fuzzy digital system conforms to the WISHBONEogic bus [37] public domain standard. WISHBONE is a SoC intercon-ection architecture for portable IP cores, that connects a variableumber of components.

All top level interfaces are designed to be WISHBONE compat-ble. Both the WISHBONE bus controler and the PCI-WISHBONEridge [29] IP cores have been developed under free distribution

icenses by the OpenCores [54] organization as well as other enti-ies. An alternative option is a direct mapping between On-Chiperipheral Bus (OPB) [42] and WISHBONE signals, as most of themap one-to-one. While the WISHBONE-PCI bridge and WISHBONE

ontroler (Conbus [17]) are implemented in Verilog as provided bypenCores, the FIM modules are implemented in VHDL.

WISHBONE Systems can easily interface with other SoC bustandards, such as OPB [69] through the WISHBONE-OPB bridge. Anlternative option is a direct mapping between OPB and WISHBONEignals, as most of them map one-to-one. In its basic configuration,he system comprises three cores: the WISHBONE controler, theCI-WISHBONE bridge (as a master WISHBONE device), and a fuzzynference module implemented as a slave WISHBONE device. The

ISHBONE controler IP module employed supports up to 8 masternd 8 slave devices.

The PCI interface of the prototypes eases integration withouting architectures by major vendors [47,36]. Within routingrchitectures currently deployed in the Internet [39,47], fuzzy traf-c analyzers and controlers could be seamlessly integrated asrocessing engines whether at NPU and/or the output/input lineards depending on the quality of service scheme implemented. Ast will be described in Section 5, the configuration presented so farllows for the implementation of fuzzy processing units that cane generally applied to network traffic analysis and control. Addi-

ional IP cores (such as network interface card control, DMA devicesnd CPUs) can be incorporated in order to develop extended fuzzyrocessing units.

Fig. 4. Design flow of fuzzy systems for networking.

Within the prototyping platform presented, a fully automateddesign flow has been employed. The fuzzy systems design flow,described in the next section, covers from an initial high level fuzzysystem description to an FPGA implementation of FIMs.

4. Development methodology and design flow

A methodology and design flow tailored for the development offuzzy inference systems applied to Internet traffic analysis and con-trol have been defined. Fig. 4 shows a scheme of the design flow. Thewhole development process is covered, from initial specification tofinal implementation whether as software or digital hardware.

The design flow spans from initial specification in a high-levellanguage to an FPGA implementation of FIMs by means of the toolsincluded in the Xfuzzy development environment as well as tools inthe Xilinx ISE environment [73]. We leverage on the Xfuzzy [52,53]CAD suite of tools and a methodology [10] for the development offuzzy controlers to define a methodology and design flow tailoredfor the development of fuzzy systems applied to Internet trafficanalysis and control. The Xfuzzy environment eases the specifi-cation, verification and synthesis of fuzzy inference systems. Thewhole set of tools included in the environment is based on a com-mon high level specification language: XFL3 [51].

The first development stage (description) is performed using theXFL language (or alternatively, using visual interfaces that rely onthe XFL language), which can later be turned into C and VHDL codeamong other implementation options. An example of XFL specifi-cations is given in Section 5. The tool chain includes:

• The xfc and xfcpp tools (included in Xfuzzy), which turn an XFLspecification into C and C++code that can run in both user andkernel space.

ification into synthesizable VHDL code generated for a specificprocessing architecture for the efficient implementation of fuzzysystems with a good cost-performance ratio and an extremely

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short development cycle [53,7]. xfvhdl applies an active-ruledriven architecture for fuzzy inference, using simplified defuzzi-fication methods and parallelization in order to provide highinference rates. The output of xfvhdl can be feeded to a numberof synthesis tools, such as those from Xilinx and Synopsys.ns-2 [41], an open network simulator widely spread within theInternet research community.Operating system kernel (currently Linux and FreeBSD).

By following a well-established development methodology, weropose a much more efficient and formal approach that thoseurrently used for the development of processing units of Inter-et routers from major vendors [47,39]. The development stagesfter specification have been tailored for Internet traffic controlerevelopment as follows.

For network simulation, we have used ns-2, an object orienteddiscrete event driven simulator with support for a vast vari-ety of transport protocols, queueing systems, routing schemesand access media. This enables us to evaluate the performanceof traffic controlers under complex and realistic simulated sce-narios. Fuzzy controlers are integrated into ns-2 as componentsimplemented in C. This makes it easy to evaluate the influenceof various factors, such as the precision of fuzzy modules, in aconvenient manner.Verification is considered for both software and hardwareimplementations of fuzzy controlers. Software verification is per-formed over a controler implementation within the kernel of thegeneral purpose operating system running on the PC.

Three complementary approaches can be followed for verifyingardware prototypes of FIMs:

Verification by means of network simulators. To this end, codeand drivers to make it possible to access the FIM in the FPGAdevelopment card from ns-2 have been developed.Verification through emulated scenarios where a router is emu-lated by means of the prototyping platform. Validation inemulated scenarios is also possible with our prototyping archi-tecture by using the prototyping PC as a router within a networklaboratory or experimental network environment. This is doneby replacing standard queue control functionality in the operat-ing system network layer with that provided by the FIM in thedevelopment board. To this end, drivers have been for FreeBSD6.x and Linux 2.6.x kernels. Alternatively, emulated scenarios canbe constructed by means of software packages for network emu-lation.Verification in production environments in the Internet. This caseis hardly feasible in practice. In fact, disruptive experiments arecurrently not possible in real networks. Besides the lack of controlon the network conditions, most often there is no possibility toinject significant traffic loads or implement novel mechanisms.

As general hardware-software partition, the FIM module and itsnterfacing logic are implemented on hardware whereas all otherasks are implemented as software. This maximizes flexibility ofesigns while satisfying the operational constraints discussed inrevious sections.

The fact that disruptive experiments are not currently possi-le in real networks has hampered research on novel protocolsnd architectures during the last years. Recently, infrastructuresor network virtualization have raised considerable interest within

esearchers, institutions and agencies. There is a need for cleanlate designs in the Internet as well as realistic experiments inetwork science and engineering. Several initiatives for develop-

ng experimental facilities in support of disruptive experiments

puting 12 (2012) 1440–1450

through network virtualization are early stages of develop-ment, such as the Global Environment for Network Innovations(http://www.geni.net), and the Federated E-infrastructure Dedi-cated to European Researchers Innovating in Computing networkArchitectures (http://www.fp7-federica.eu). However, research isstill ongoing to address the complexity of such infrastructures.We entertain the hope that these initiatives will pave the way fortesting in real scenarios techniques such as the hardware imple-mentations of AQM schemes proposed here.

5. Application to Internet traffic analysis and control

Two approaches can be observed in currently deployed schemesfor traffic regulation in Internet, as well as proposed alterna-tives [71,40,64]:

• Distributed control, with functionality distributed among the endnodes in the network and implemented by means of end-to-endtransport protocols. Transmitter and receiver end nodes of packetflows cooperate so as to perform flow and congestion control aswell as fair distribution of network resources.

• Queue schedulers in intermediate nodes (routers). These mech-anisms can discriminate packet flows and enforce resourcedistribution and reservation on a per-hop basis.

Thus, regulation of packet flows from sender to receivers caninvolve all the network nodes in the end-to-end path and is per-formed on both an end-to-end and a per-hop basis. Such a schemeleads to a system that comprises multiple feedback loops with com-plex interactions. In what follows, we analyze fuzzy systems in twoareas of application: queuing control in routers, and end-to-endtraffic control. These systems have been designed and tested usingthe development platform described in previous sections.

5.1. Queuing control in routers

Current Internet routers at core networks process aggregatetraffic [44] which typically comprises millions of packets per sec-ond as well as millions of active end points and simultaneous flowsestablished by services and applications with an increasing diver-sity of traffic patterns.

The dominant queue control scheme in the current Internet isthe passive FIFO queue without classes of service (known as drop-tail), that discards packets when the storage space is full. Activeschemes (known as AQM – active queue management) are how-ever being developed and promoted [9,77] since AQM mechanismsare required to provide quality of service, differentiate services orpenalize misbehaving flows, among other demanded functionali-ties.

Although a number of AQM schemes have been proposed [40],properties of aggregate traffic [44] (such as self-similarity andburstiness at multiple time scales) make it difficult to stabilizepacket queues. There are major challenges in tuning AQM schemesin real environments and no generally accepted solution has beenfound.

A number of research results have been reported on theapplication of fuzzy systems to the general area of network traf-fic regulation [28,76,16] Additionally, recent results have beenobtained on the development of a fuzzy queuing theory as an exten-sion to classical queuing theory [76], which is the basis of manytraffic processing mechanisms in the current Internet. To cope with

the aforementioned problems, we focus on the notion of FAQM(fuzzy active queue management). By means of FAQM we aim atdefining aggregate traffic schedulers that can perform in a flexibleand adaptive manner. In this framework, a fuzzy inference system

F.M. Pouzols et al. / Applied Soft Computing 12 (2012) 1440–1450 1445

Table 1FAQMBestEffort rule base.

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egulates a variable number of packet queues. In the most basiccheme, inputs (linguistic variables of the rule base antecedents)re queue sizes as well as their variation whereas the output vari-ble is defined as a probability value or reference to determinehich packet should be sent next.

.1.1. Best-effort trafficThis section describes the design of the FAQMBestEffort fuzzy

ystem, which has been developed as a scheduler for best-effortraffic. FAQMBestEffort implements a traffic controler for conges-ion control in routers with no support for classes of service.

We propose a fuzzy scheduler that marks packets the same ways Random Early Detection (RED) [40] schedulers, i.e., discardinghem. Two inputs and one output are defined between the numberf currently queued packets and a desired value reference, whereasnput e(i − 1) is the deviation at the last time interval. The output ofhe system, pi, is defined as a probability value for marking the nextacket to be forwarded. In this case, as in AQM schemes currentlyost accepted within the Internet research community, marking

s defined as dropping the packet. The rule base is given in Table 1hereas the resulting control surface is depicted in Fig. 5. 7 linguis-

ic terms are defined for both inputs, ranging from NVB to PVB forncreasing differences. As for the output variable, 7 linguistic termsre defined for increasing levels of probability ranging from Z to H.his fuzzy system is defined using the XFL language as shown par-ially in Fig. 6. From this specification, C and VHDL implementationsre automatically generated by means of the CAD tools describedn previous sections.

A performance evaluation study was conducted on traditionalnd fuzzy traffic schedulers for routers. What follows is a summaryf results from the FAQMBestEffort scheduler as compared to the

esults from a RED system in a simulated network scenario whichesembles a typical network configuration where traffic schedulersan have a direct impact on overall network performance for endsers. We analyze the behavior of the traffic scheduler at a router

Fig. 5. FAQMBestEffort control surface.

Fig. 6. Fragment of the definition of the FAQMBestEffort fuzzy system using the XFLlanguage.

that resembles a campus access point (where current networkconfigurations commonly lead to a higher degree of performancedegradation as seen by end users [11,66]). A more detailed dis-cussion of realistic network scenarios can be found in [64] andreferences therein.

A performance comparison of both RED and FAQMBestEffortschedulers is outlined in terms of a number of metrics: queuesize, throughput (goodput) and packet delay distribution. Addi-tional properties and operational constraints (such as router loadand inference rate) is analyzed in Section 6.

Queue length oscillations are significantly lower for theFAQMBestEffort scheduler which also manages to keep a highermean queue length. Overall statistical properties of the oscillationsof both cases are summarized in Table 2, which shows mean queuelength, standard deviation, maximum peak value, minimum peakvalue, and 5% and 95% percentiles.

Application level throughput (goodput) resulting from bothschemes is compared in Fig. 7(a) and (b). As expected, the higherstability and mean queue length in the FAQMBestEffort case lead

Table 2Queue length statistics for the FAQMBestEffort evaluation experiment. Mean, stan-dard deviation, maximum peak value, minimum peak value, and 5th and 95thpercentiles are given.

Scheduler Mean Stdv Max. Min. 5 pc 95 pc

RED 24.6 9.6 50 0 9.1 41.1FAQM 33.8 4.6 46 20 26.1 41.1

1446 F.M. Pouzols et al. / Applied Soft Computing 12 (2012) 1440–1450

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Fig. 7. Application level throughput with RED and F

o higher goodput. As overall conclusion, results from FAQMBestEf-ort show a higher robustness in the presence of bursty traffic andutperforms results from RED for both bulk transfer and real-timeraffic, showing better performance in terms of queue length andtability, link utilization, as well as impact on end-to-end delay anditter.

These results imply that end users will experience a slightlyigher mean delay in the FAQMBestEffort. The delay increase is nev-rtheless negligible for current network technologies and indeedenerally lower than 5% of the overall end-to-end delay in our sim-lation scenario. On the other hand, FAQMBestEffort improves peakelay values as compared to those of RED controlers by approxi-ately 50%, which implies a significant improvement in end-to-end

itter. Thus, FAQMBestEffort performance is better for best effortraffic while the benefits it introduces for real-time traffic clearlyutperforms the hardly noticeable mean delay increase.

We note that, although developed for bulk transfer traffic witho time constraints, the higher degree of robustness and respon-iveness to packet bursts shown by FAQMBestEffort leads to anmprovement in end-to-end performance as experienced by timeonstrained services and applications. FAQMBestEffort is thus aractical compromise solution for currently deployed routers.

.2. End-to-end traffic control

A number of classes of rate control have been defined andpplied in packet switching networks, such as window based andquation based [33]. The prevalent transport protocol in the cur-ent Internet is Transmission Control Protocol (TCP), which usesindow based rate control mechanisms. Important limitations in

CP rate control are currently recognized. The research communitys developing protocols with alternative rate control schemes, suchs the TCP-Friendly Rate Control protocol (TFRC) and protocols withimilar yet extended schemes for rate control, such as the Streamontrol Transmission Protocol (SCTP) A number of extensions andodifications to TCP rate control are being developed as well, such

s HighSpeed TCP [32].We outline a fuzzy model for TCP-like window-based rate con-

rol and analyze its performance. The four standard algorithmsor controling the congestion window in standard TCP [65] arelow start, congestion avoidance, fast retransmit and fast recovery.hese algorithms apply different update policies to the congestionindow, which is defined as the maximum amount of bytes that

an be sent from sender to receiver without the sender havingeceived any acknowledgement from the receiver, i.e., the maxi-um amount of bytes in flight at any moment.The slow start and congestion avoidance algorithms define dif-

erent stages in the evolution of the congestion window. Fastetransmit and fast recovery are jointly applied for a third stage.

ach stage corresponds to a clearly identified network state andeads to the application of a specific window update policy. How-ver, the actual network state can be in between these 3 crisponditions. Additionally the knowledge about network state is

BestEffort control. (a) RED and (b) FAQMBestEffort.

uncertain and delayed. Rather than defining a set of exclusive states,we will consider the network to be in all states simultaneously, toa variable degree. A fuzzy rule based inference system infers thedegree to what the network is considered to be in a particular state.

In the extended fuzzy approach described here, three differentfuzzy stages are defined for slow start, congestion avoidance andfast retransmit/fast recovery [65]. Since the actual network stateis known with uncertainty, all network states are considered tooccur at the same time with a varying degree of certainty. Theextent to which the system is in one of these stages is evaluatedby three fuzzy inference systems whose outputs are regarded asa degree of certainty about current network state. This way, wemodel uncertainty about the actual network congestion state.

In the simplest case, the three sets of policies are combined asfollows. If we denote by �SS, �CA, and �FRFR the output of the threefuzzy inference systems, and by fSS, fCA and fFRFR the values givenby the standard update policies (which are generalized to �k andfk (1 ≤ k ≤ n) for a variable number n of network states, or stagesin the rate control algorithm, or sets of update policies), then thecertainty degree cj of a stage is defined as:

cj = �j∑nk=1�k

where the rule sets of the fuzzy inference systems should verify∑nk=1�k > 0. The final update policy for the congestion window,

cwnd, is computed as the weighted average of the update policiesassociated to all possible stages:

cwndi+1 = cwndi +n∑

j=1

cjfj(cwndi, ssthresh)

where sshthresh is the congestion window value defined as thresh-old between the slow start and congestion avoidance stages. Thisway, we have a rule based method that combines update policiesthat have been shown to be effective under certain conditions.The three systems defined have five inputs: a timeout concern-ing acknowledgement delays, the current congestion window value(cwndi), the sshthresh value, the current packet loss percentage andthe current round-trip time.

A comparative performance evaluation study was conducted ontraditional and fuzzy rate controlers. Results are shown here for acomparison of TCP Reno [2] (the most extended version of TCP in thecurrent Internet), HighSpeed TCP [32] and the fuzzy rate controlerdescribed here.

Fig. 8(a) compares the congestion window evolution for thethree alternatives analyzed, while Fig. 8(b) compares throughput.The network scenario considered is the same as the one describedin the previous subsection for analyzing queuing control systems.

As overall conclusions we can draw that the fuzzy extended ver-sion of TCP rate control shows higher robustness to loss events.This fact leads to higher final throughput (improved by approxi-mately 12% and 11% as compared to TCP Reno and HighSpeed TCP,

F.M. Pouzols et al. / Applied Soft Computing 12 (2012) 1440–1450 1447

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of service. It has two inputs, defined as the number of packets in twoseparated packet queues: a queue for expedited non-assured flowsand a queue for non-expedited assured flows, respectively. The

ig. 8. End-to-end connection in a simulated scenario: Fuzzy TCP (straight line), Hind (b) throughput evolution.

espectively). Additional simulations performed on network sce-arios under high congestion conditions confirm that the fuzzy rateontroler still provides proper and quick reactions to congestion.urther results for different simulated and emulated scenarios cane found in [64].

. Performance of hardware implementations

Using the development platform presented here, a numberf fuzzy systems for network traffic analysis and control weremplemented in hardware. This section discusses the results from

performance study of the hardware implementations of theystems listed in Table 3. A feasibility discussion addressing tech-ological and architectural constraints is also given.

Implementation results are reported for two different XilinxPGA devices. The first device is a Xilinx Spartan-3 FPGA, xc3s1500-g456-5 device (1.5 million equivalent gates) included in an AvNetDS-XLX-SP3-EVL1500 development board with standard PCI 2.0

nterface. It is a very low cost device for our target application. Thisevice has been selected with the aim of evaluating the feasibilityf the approach proposed here with constrained resources. The sec-nd device, with performance closer to that of the programmableogic devices used in current routing hardware, is a Xilinx Virtex-

FPGA, XC5VLX50T-1FF1136-1C-ES device, integrated in a XilinxXT FPGA ML505 board with PCIe interface.

The tool xfvhdl was used to generate VHDL descriptions fromFL specifications as explained in Section 4. xfvhdl provides sev-ral FIM implementation options. In particular, we set ROM basedtorage for the rule base and membership functions. An scheme ofhe design flow for generating hardware implementations of fuzzynference systems is shown in Fig. 9. In the synthesis stage, thefvhdl tool generates a VHDL description from an XFL specifica-ion. xfvhdl uses a cell library that contains parameterized VHDLescriptions for the basic building blocks of the specific architec-ure followed. Two kinds of blocks are included in this cell library:ata path blocks, which implement the fuzzy inference, and con-

rol blocks, which control memory read and write operations andhe operation scheduling control signals. These cells are defined in

way compatible with the VHDL restrictions of synthesis tools byajor vendors.

able 3uzzy inference systems implemented and their complexity in terms of inputs, lin-uistic terms and rules. The number of linguistic terms for each input as well as thesingle) output is indicated for each system.

System Inputs Linguistic terms Rules

FAQMBestEffort 2 7,7,7 37TCPSS 5 5,5,5,5,5,5,5 24RxBufferSize 2 5,5,5 25RTperf 4 5,5,5,5,5 27DSSelect 2 5,5,2 17AQMDSAF 2 3,3,4 7

ed TCP (dotted line) and TCP Reno (dashed line). (a) Congestion window evolution

A performance evaluation of the FIM architecture in terms ofinference speed, area and power consumption was conducted. Syn-thesis as well as place and routing were performed by means of thetools included in the Xilinx ISE environment [73].

The fuzzy systems listed in Table 3 implement intelligent Inter-net traffic analysis and regulation systems. RxBufferSize is a fuzzysystem for inferring dynamic buffer size depending on networkconditions (one-way delay and packet loss percentage). AQMDSAFis a regulator for the assured forwarding PHB within the differ-entiated services architecture. It has the same two inputs and oneoutput as FAQMBestEffort. However, the number of linguistic labelsis lower and the rule base is defined so that a higher guarantee ofdelivery is provided, i.e., higher forwarding probabilities are con-sidered.

DSSelect is a fuzzy classifier for class of service enabled net-works. DSSelect balances priorities between two different classes

Fig. 9. Design flow for hardware fuzzy inference systems.

1448 F.M. Pouzols et al. / Applied Soft Com

Fig. 10. FPGA implementation results summary for a Virtex-5 devices. Complexityopi

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f systems is given in terms of the number of inputs, linguistic terms and rules. Com-lexity of the implementations is given in terms of equivalent gates and maximum

nference rate.

ule base balances priorities depending on current queue lengthsollowing the approach proposed in [77].

RTperf is a fuzzy inference system for network performancevaluation [11,66]. RTperf is targeted at real-time network appli-ations and services, providing a quantitative measure of thedequacy of current network conditions for time constrained traf-c or real-time network applications. TCPSS implements a fuzzy

nference system for the slow start update policy in TCP-like end-o-end control, as described in Section 5.2. The other systems wereescribed in previous sections. For a more detailed description ofhese systems we refer the interested reader to [64] and referencesherein.

Fig. 10 shows a summary of implementation results for theirtex-5 device. A precision of 8 bits is considered for inputs, out-uts and membership functions. An 8 bits configuration was foundo satisfy overall precision requirements with no practical differ-nce as compared to a 16 bits configuration.

From the results shown in the figure we can draw the conclusionhat the speed variability with regards to the fuzzy system complex-ty (measured as number of inputs, rules, membership functionsnd accuracy) that characterizes the architecture and implementa-ion technology used are within the required bounds. This makes itossible to achieve high inference rates even for the most complexystems developed here.

In current router architectures, traffic analysis and regulationubsystems are integrated into input interface cards together withhe virtual output queue processing logic. In general, these subsys-ems can be thought of as queue schedulers that run, at most, atrequencies around the maximum per interface packet processingpeed.

Regarding inference rate, prototypes implemented on a lowerost, Xilinx Spartan-3 FPGA, could achieve above 60 MFLIPS. As dis-ussed in previous sections, packet queue controlers must have

fine packet processing granularity in order to cope with packetursts and properly control small packet queues. The finest process-

ng granularity is only possible if the maximum packet processingate is equal to or greater than the maximum number of packets perecond accepted by packet queues. Routers from the Cisco 12000,isco CRS series as well as Juniper M and T series process up to5 Mp/s, 40 Mp/s, 24 Mp/s and 60 Mp/s, respectively, per interfaceutput queue [20,21,34]. Thus, even a prototype implementationsing a low cost FPGA could provide in some cases the required

nference speed for the finest packet processing granularity in cur-ent high performance router families.

Power consumption was analyzed using so-called productionharacterization data for both the Spartan-3 and the Virtex-5

puting 12 (2012) 1440–1450

devices. That is, enough production silicon of these devices has beencharacterized to provide full power correlation over numerous pro-duction lots. Also, characterization data for all blocks in the devicefabric are included. Quiescent power consumptions are negligiblefor current high performance routers. Regarding dynamic power ofthe fuzzy inference modules, two cases were analyzed for frequen-cies ranging from 16 MHz through 150 MHz. In the first case, inputstimuli were generated using the standard test bench generatedby the xfvhdl tool. In the second, pessimistic case the toggle ratesfor inputs and outputs as well as flip-flops are set to 100% of theclock frequency. The dynamic consumption ranges approximatelybetween 2 mW and 23 mW for the first case. In the second case, therange is within 6 mW and 30 mW. Dynamic power consumptiondepends linearly on the system clock frequency and the number oftoggling nodes, as expected [1]. It can be observed that the powerconsumption of the fuzzy inference modules is negligible as com-pared to the overall power requirements of the systems they areaimed to be integrated in.

6.1. Discussion and previous work

Let us now discuss previous work on the implementation offuzzy systems for networking. Systems to perform tasks belongingto the physical and link layers of communications systems (such assignal filtering) have been reported in the literature. Some of themare based on FPGAs. However, we are not aware of proposals ofFPGA implementations of fuzzy systems applied to network trafficcontrol and network layer tasks in general.

The most closely related work we are aware of [4] reports aVLSI implementation that attains an inference rate of 3.3 MFLIPSfor a 60 MHz clock, which would not fulfill current requirements.However, this work dates back more than 10 years. Also, we notethough there are major differences between our proposal and theaforementioned work. Thus, a direct comparison cannot be done.In the latter case, the target application is traffic control for ATMnetworks. Additionally, it is based on a substantially different archi-tecture (using the concept of fuzzy processor) and the system isimplemented as an ASIC. The fuzzy processor employed requires18 cycles for a fuzzy inference. We note though that in a differentcontext, digital realizations achieving inference rates of the order ofthe MFLIPS were reported during the 1990s [43]. In particular, theauthors of [5] report an inference rate of the order of the MFLIPS foran architecture able to implement complex fuzzy systems. Morerecently, the potential to achieve inference rates of the order of50 MFLIPS with digital realizations and FPGA-based systems in par-ticular has been widely reported in the literature [50,12].

In addition, the solution proposed here provides a developmentmethodology and a tool chain that fulfill an important gap in currentcustom, unscalable and inefficient design schemes [39]. The com-plexity introduced into a routing system is negligible as comparedto the complexity increment that is taking place at present and isexpected to take place in the foreseeable future high performancerouters.

In fact, an FPGA approach to the implementation of router com-ponents is in line with the current trend towards FPGA-baseddevelopment router design of major vendors [47,36]. In particular,providing a PCI/PCIe compliant interface eases integration of fuzzyinference modules as processing units within current network pro-cessing architectures.

7. Conclusions

We have reported an open platform that eases the developmentof fuzzy systems and their implementation as SoPC on FPGAs. Asystematic development methodology and design flow is followed.

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F.M. Pouzols et al. / Applied So

he Xfuzzy environment automates development from initial high-evel fuzzy specifications to synthesizable VHDL.

The platform integrates both CAD tools and IP cores. Fuzzy infer-nce modules are integrated into a SoPC architecture made of openP cores that is suitable for developing fuzzy systems applied toetworking among many other possible areas. In addition, thoseoPC developed using the outlined architecture can be seamlesslyntegrated in current router architectures as processing units.

Successful results of the application of the platform to theevelopment of fuzzy systems for Internet traffic analysis and con-rol were also discussed. These fuzzy systems were validated andhown to provide a number of advantages over classic approaches.he FPGA hardware implementations of these fuzzy inferenceystems were also shown to satisfy operational requirements ofurrent and future high performance routing hardware in terms ofoth inference speed and resource consumption. Even prototype

mplementations using low cost FPGAs can provide the requirednference speed in current high performance routers.

The open development platform presented paves the way forurther development of efficient intelligent traffic controlers. Welso entertain the hope that the availability of such a platform willoster the development and deployment of fuzzy systems for aumber of areas where intelligent analysis systems are sought, suchs packet and flow identification, classification and filtering, amongther areas of active research. The platform proposed allows for theevelopment of prototypes while avoiding large investments andomplicated management procedures which constrain the testingnd adoption of soft computing techniques in high performanceetworking.

cknowledgements

This work was done while the first author was at IMSE-CNM. Thisork was supported in part by the European Community under theOBY-DIC Project FP7-IST-248858, by Spanish Ministerio de Cien-

ia y Tecnología under the Project TEC2008-04920, and by Junta dendalucía under the Project P08-TIC-03674, co-financed by FEDER.

eferences

[1] P. Abusaidi, M. Klein, B. Philofsky, Virtex-5 FPGA system power design consid-erations, Tech. Rep. WP285 (v1.0), Xilinx Inc., http://www.xilinx.com/support/documentation/white papers/wp285.pdf, February 2008.

[2] M. Allman, V. Paxson, W.R. Stevens, TCP Congestion Control, RFC 2581, InternetEngineering Task Force, Network Working Group, Status: Proposed Standard,1999.

[3] G. Appenzeller, I. Keslassy, N. McKeown, Sizing router buffers, in: ACM SpecialInterest Group on Data Communications (SIGCOMM) Conference, Portland, OR,USA, 2004.

[4] G. Ascia, V. Catania, G. Ficili, S. Palazzo, D. Panno, A VLSI fuzzy expert system forreal-time traffic control in ATM networks, IEEE Transactions in Fuzzy Systems5 (1) (1997) 20–31.

[5] G. Ascia, V. Catania, M. Russo, VLSI hardware architecture for complex fuzzysystems, IEEE Transactions in Fuzzy Systems 7 (5) (1999) 553–570.

[6] J. Aweya, IP router architectures: an overview, International Journal of Com-munication Systems 14 (5) (2001) 447–475.

[7] A. Barriga, S. Sánchez-Solano, P. Brox, A. Cabrera, I. Baturone, Modelling andimplementation of fuzzy systems based on VHDL, International Journal ofApproximate Reasoning 41 (2) (2006) 164–178.

[8] I. Baturone, A. Barriga, S. Sanchez-Solano, C.J. Jimenez, D.R. Lopez, Micro-electronic Design of Fuzzy Logic-based Systems, CRC Press, 2000, ISBN:0-8493-0091-6.

[9] S. Blake, D.L. Black, M.A. Carlson, E. Davies, Z. Wang, W. Weiss, An architec-ture for differentiated services, in: RFC 2475, Internet Engineering Task Force,Network Working Group, Category: Informational, December 1998, 1998.

10] A. Cabrera, S. Sánchez-Solano, P. Brox, A. Barriga, R. Senhadji, Hard-ware/software codesign of configurable fuzzy control systems, Applied SoftComputing 4 (3) (2004) 271–285.

11] P. Calyam, D. Krymskiy, M. Sridharan, P. Schopis, Active and passive measure-

ments on campus, regional and national network backbone paths, in: 14th IEEEInternational Conference on Computer Communications and Networks (ICCCN2005), San Diego, CA, USA, 2005.

12] Q. Cao, M.H. Lim, J.H. Li, Y.S. Ong, W.L. Ng, A context switchable fuzzy inferencechip, IEEE Transactions on Fuzzy Systems 14 (4) (2006) 552–567.

[

[

puting 12 (2012) 1440–1450 1449

13] S. Chandramathi, S. Shanmugavel, Fuzzy-based dynamic bandwidth allocationfor heterogeneous sources in ATM networks, Applied Soft Computing 3 (1)(2003) 53–70.

14] H.J. Chao, Next generation routers, Proceedings of the IEEE 90 (9) (2002)1518–1558.

15] H.J. Chao, B. Liu, High Performance Switches and Routers, Wiley/IEEE Press,2007, ISBN: 978-0470053676.

16] B.-S. Chen, Y.-S. Yang, B.-K. Lee, T.-H. lee, Fuzzy adaptive predictive flow con-trol of ATM network traffic, IEEE Transactions on Fuzzy Systems 11 (4) (2003)568–581.

17] J. Chi, et al., WISHBONE Conbus IP Core, May 2008, URL http://www.opencores.org/projects.cgi/web/wb conbus/.

18] C. Chrysostomou, A. Pitsillides, L. Rossides, A. Sekercioglu, Fuzzy logic con-trolled RED: congestion control in TCP/IP differentiated services networks, SoftComputing Journal 8 (20) (2003) 79–92.

19] Cisco Systems, Inc., The evolution of high-end router architectures, Tech.Rep., Basic Scalability and Performance Considerations for Evaluating Large-Scale Router Designs, 2001, URL http://www.cisco.com/en/US/products/hw/routers/ps167/.

20] Cisco Systems, Inc., Portable product sheet: router switching performancein packets per second (pps), Tech. Rep., Cisco Systems, December 2006, URLhttp://www.cisco.com/web/partners/downloads/765/tools/quickreference/routerperformance.pdf.

21] Cisco Systems, Inc., Cisco CRS-1 Distributed Route Processor Datasheet,July 2008, URL http://www.cisco.com/en/US/prod/collateral/routers/ps5763/product data sheet0900aecd80501c66.html.

22] D.E. Comer, Network processors: programmable technology for building net-work systems, The Internet Protocol Journal 7 (4) (2004) 3–12.

23] D.E. Comer, Network Systems Design Using Network Processors: Intel 2XXXVersion, Pearson Prentice Hall, Upper Saddle River, NJ, USA, 2005, ISBN:9780131872868.

24] P. Crowley, M.A. Franklin, H. Hadimioglu, P.Z. Onufryk (Eds.), Network Pro-cessor Design: Issues and Practices, vol. 1 of Computer Architecture andDesign, Morgan Kaufmann Publishers, San Francisco, CA, USA, 2002, ISBN:978-1558608757.

25] P. Crowley, M.A. Franklin, H. Hadimioglu, P.Z. Onufryk (Eds.), Network Pro-cessor Design: Issues and Practices, vol. 2 of Computer Architecture andDesign, Morgan Kaufmann Publishers, San Francisco, CA, USA, 2003, ISBN:978-0121981570.

26] P. Crowley, M. A. Franklin, H. Hadimioglu, P. Z. Onufryk (eds.), Network Pro-cessor Design: Issues and Practices, vol. 3 of Computer Architecture andDesign, Morgan Kaufmann Publishers, San Francisco, CA, USA, 2005, ISBN:978-0120884766.

27] R. de Oliveira, T. Braun, A delay-based approach using fuzzy logic to improveTCP error detection in ad hoc networks, in: IEEE Wireless Communications andNetworking Conference, Atlanta, USA, 2004.

28] G. Di Fatta, F. Hoffmann, G.L. Re, A. Urso, A genetic algorithm for the design of afuzzy controller for active queue management, IEEE Transactions on Systems,Man and Cybernetics, Part C: Applications and Reviews 33 (3) (2003) 313–334.

29] M. Dolenc, T. Markovic, PCI IP core specification, in: Tech. Rep. Rev. 1.2, Open-Cores.Org Free Open Source IP Cores and Chip Design, July, 2004.

30] Endace Limited, DAG Network Monitoring Cards, June 2008, URLhttp://www.endace.com/our-products/dag-network-monitoring-cards/.

31] R. Fengyuan, S. Xiunming, Design of a fuzzy controller for active queue man-agement, Computer Communications 25 (9) (2002) 874–883.

32] S. Floyd, HighSpeed TCP for large congestion windows, in: RFC 3649, Inter-net Engineering Task Force, Network Working Group, Category: Experimental,December 2003, 2003.

33] S. Floyd, E. Kohler, Internet research needs better models, ACM SIGCOMM Com-puter Communication Review 33 (1) (2003) 29–34.

34] E. Gardner, et al., T1600© Internet Routing Node Hardware Guide, JuniperNetworks, Inc., 2nd ed., November 2008, URL http://www.juniper.net/techpubs/hardware/t-series.html.

35] S. Ghosh, Q. Razouqi, H.J. Schumacher, A. Celmins, A survey of recent advancesin fuzzy logic in telecommunications networks and new challenges, IEEE Trans-actions on Fuzzy Systems 6 (39) (1998) 443–447.

36] W.J. Goralski, Juniper and Cisco Routing. Policy and Protocols for Multivendor IPNetworks, Wiley Publishing Inc., Indianapolis, IN, 2002, ISBN: 0-471-21592-9.

37] R. Herveille, et al., WISHBONE System-on-Chip (SoC) Interconnection Arhitec-ture for Portable IP Cores, Tech. Rep. Revision B.3, OpenCores Organization,September 2002.

38] M. Hidell, Decentralized Modular Router Architectures, Ph.D. Thesis, KTH-RoyalInstitute of Technology, September 2006.

39] M. Hidell, P. Sjödin, O. Hagsand, Control and Forwarding Plane Interaction inDistributed Routers, in: Tech. Re TRITA-S3-LCN-0501, Laboratory for Commu-nication Networks, Department of Signals, Sensors, and Systems. KTH RoyalInstitute of Technology, Stockholm, Sweden, March, 2005.

40] C. Hollot, V. Misra, D. Towsley, W. Gong, Analysis and design of controllers forRED routers supporting TCP flows, IEEE Transactions on Automatic Control 47(2002) 945–959.

41] Information Sciences Institute University of Southern California, ViterbiSchool of Engineering, The Network Simulator – ns-2, August 2008, URLhttp://www.isi.edu/nsnam/ns/.

42] International Business Machines Corporation, On-Chip Peripheral Bus: Archi-tecture Specifications. Version 2.1, April 2001.

1 ft Com

[

[

[

[

[[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

[

450 F.M. Pouzols et al. / Applied So

43] A. Kandel, G. Langholz, Fuzzy Hardware, Architectures and Applications, KluwerAcademic Publishers, Norwell, MA, USA, 1997.

44] T. Karagiannis, M. Molle, M. Faloutsos, A. Broido, A nonstationary Poisson viewof internet traffic, in: 23th Annual Joint Conference of the IEEE Computer andCommunications Societies (IEEE INFOCOM), vol. 3, Hong Kong, 2004.

45] L. Kencl, J.-Y.L. Boudec, Adaptive load sharing for network processors, IEEE/ACMTransactions on Networking 16 (2) (2008) 293–306.

46] S. Keshav, R. Sharma, Issues and trends in router design, IEEE CommunicationsMagazine 36 (5) (1998) 144–151.

47] A.K. Kloth, Advanced Router Architectures, CRC Press, 2005, ISBN: 0849335507.48] P.A. Lekkas, Network Processors: Architectures, Protocols and Platforms, 1st

ed., McGraw-Hill Professional, 2003, ISBN: 978-0071409865.49] W.W.K. Lin, A.K.Y. Wong, T.S. Dillon, Application of soft computing techniques

to adaptive user buffer overflow control on the Internet, IEEE Transactions onSystems, Man and Cybernetics Part C: Applications and Reviews 36 (3) (2006)397–410.

50] M.A. Manzoul, D. Jayabharathi, FPGA for fuzzy controllers, IEEE Transactions onSystems, Man and Cybernetics 15 (1) (1995) 213–216.

51] F. Moreno-Velo, S. Sánchez-Solano, A. Barriga, I. Baturone, D. López, XFL3: anew fuzzy system specification language, in: 5th WSEAS/IEEE Multiconferenceon Circuits, Systems, Communications and Computers (CSCC’01), Rethymon,2001.

52] F.J. Moreno-Velo, I. Baturone, A. Barriga, S. Sánchez-Solano, Automatic tuningof complex fuzzy systems with Xfuzzy, Fuzzy Sets and Systems 158 (18) (2007)2026–2038.

53] F.J. Moreno-Velo, I. Baturone, S. Sánchez-Solano, A. Barriga, Rapid design offuzzy systems with Xfuzzy, in: 12th IEEE International Conference on FuzzySystems (FUZZ-IEEE’03), St. Louis, MO, USA, 2003.

54] OpenCores Organization, OpenCores.Org: Free Open Source IP Cores and ChipDesign, September 2007, URL http://www.opencores.org.

55] B. Otal, L. Alonso, C. Verikoukis, Highly reliable energy-saving MAC for wirelessbody sensor networks in healthcare systems, IEEE Journal on Selected Areas inCommunications 27 (4) (2009) 553–565.

56] K. Pagiamtzis, A. Sheikholeslami, Content-addressable memory (CAM) circuitsand architectures: a tutorial and survey, IEEE Journal of Solid-State Circuits 41(3) (2006) 712–727.

57] K. Park, W. Willinger (Eds.), Self-Similar Network Traffic and Performance Eval-uation, Wiley Interscience, New York, USA, 2000, ISBN: 0-471-31974-0.

58] S. Patchararungruang, S.K. Halgamuge, N. Shenoy, Optimized rule-based delayproportion adjustment for proportional differentiated services, IEEE Journal onSelected Areas in Communications 23 (3) (2005) 261–276.

59] F.M. Pouzols, A. Barriga, D.R. Lopez, S. Sánchez-Solano, FPGA based implemen-tation of fuzzy controllers for internet traffic, in: XII IBERCHIP Workshop, SanJosé, Costa Rica, 2006.

60] F.M. Pouzols, A. Barriga, D.R. Lopez, S. Sánchez-Solano, Open FPGA-based devel-

opment platform for fuzzy systems with applications to communications, in:XXII Conference on Design of Circuits and Integrated Systems (DCIS’07), Seville,Spain, 2007.

61] F.M. Pouzols, A. Barriga, D.R. Lopez, S. Sánchez-Solano, Linguistic summa-rization of network traffic flows, in: 17th IEEE International Conference on

[

[

puting 12 (2012) 1440–1450

Fuzzy Systems (FUZZ-IEEE’2008), IEEE World Congress on Computational Intel-ligence, Hong Kong, China, 2008.

62] F.M. Pouzols, A.B. Barros, Automatic clustering-based identification of autore-gressive fuzzy inference models for time series, Neurocomputing 73 (10) (2010)1937–1949.

63] F.M. Pouzols, A. Lendasse, A.B. Barros, Autoregressive time series predictionby means of fuzzy inference systems using nonparametric residual varianceestimation, Fuzzy Sets and Systems 161 (4) (2010) 471–497.

64] F.M. Pouzols, D.R. Lopez, A. Barriga, Mining and Control of Network Traffic byComputational Intelligence, Studies in Computational Intelligence, Springer,2011, 310 pp.

65] F.M. Pouzols, D.R. Lopez, A. Barriga, S. Sánchez-Solano, Fuzzy end-to-end ratecontrol for internet transport protocols, in: 15th IEEE International Conferenceon Fuzzy Systems (FUZZ-IEEE’06), Vancouver, Canada, 2006.

66] D. Rolls, G. Michailidis, F. Hernández-Campos, Queueing analysis of networktraffic: methodology and visualization tools, Computer Networks 48 (3) (2005)447–473.

67] C. Semeria, T-series routing platforms: system and packet forwardingarchitecture, Tech. Rep. 200027-001, Juniper Networks, Inc. April 2002,URL http://www.arl.wustl.edu/ jst/cse/577/readings/juniperTseries.pdfhttp://www.arl.wustl.edu/http://www.arl.wustl.edu/ jst/cse/577/readings/juniperTseries.pdf.

68] P. Siripongwutikorn, S. Banerjee, D. Tipper, Fuzzy-based adaptive bandwidthcontrol for loss guarantees, IEEE Transactions on Neural Networks 16 (5) (2005)1147–1162.

69] R. Usselmann, et al., WISHBONE/OPB & OPB/WISHBONE InterfaceWrapper: Overview, September 2004, URL http://www.opencores.org/projects.cgi/web/opb wb wrapper.

70] G. Varghese, Network Algorithmics: An Interdisciplinary Approach to Design-ing Fast Networked Devices, Morgan Kaufmann, San Francisco, CA, USA, 2004,ISBN: 978-0120884773.

71] J. Wang, D.X. Wei, S.H. Low, Modelling and stability of FAST TCP, in: 24th AnnualJoint Conference of the IEEE Computer and Communications Societies (INFO-COM), Miami, FL, USA, 2005.

72] F. Xia, W. Zhao, Y. Sun, Y.-C. Tian, Fuzzy logic control based QOS manage-ment in wireless sensor/actuator networks, Sensors 7 (12) (2007) 3179–3191.

73] Xilinx©, Xilinx ISE 9.2i Software Manuals and Help – PDF Collection, 2007, URLhttp://www.xilinx.com/support/sw manuals/xilinx92/index.htm.

74] M.H. Yaghmaee, Design and performance evaluation of a fuzzy based traf-fic conditioner for differentiated services, Computer Networks 47 (6) (2005)847–869.

75] S. Yusuf, W. Luk, M. Sloman, N. Dulay, E.C. Lupu, G. Brown, Reconfigurablearchitecture for network flow analysis, IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems 16 (2) (2008) 57–65.

76] R. Zhang, Y.A. Phillis, V. Kouikoglou, Fuzzy Systems for Queuing Control,Springer-Verlag, London, UK, 2005, ISBN: 978-1-85233-824-4.

77] R. Zhang, Y.A. Phillis, J. Ma, A Fuzzy approach to the balance of drop and delaypriorities in differentiated services networks, IEEE Transactions on Fuzzy Sys-tems 11 (6) (2003) 840–846.