ELEC3720 Chapter 6 Program Organization in VHDL

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ELEC3720-2009-B6-PSB ACADEMY-LKH-Chapter 06 1

ELEC3720 Programmable Logic DesignELEC3720 Programmable Logic DesignChapter 06 Project Organization in VHDLChapter 06 Project Organization in VHDL


Review

• Synthesisable VHDL– Data Types, Operators, and Attributes– Code types:

– SIGNALS and VARIABLES» (and CONSTANTS and GENERICS)

– Finite State Machines

Concurrent Code:• Operators• WHEN• GENERATE• BLOCK

Sequential Code:• IF• WAIT• CASE• LOOP


VHDL Units


PACKAGE

PACKAGE package_name IS(declarations)

END package_name;

[ PACKAGE BODY package_name IS(FUNCTION and PROCEDURE descriptions)

END package_name; ]��

Example (Constants and Data Types):------------------------------------------------------------------------------LIBRARY ieee;USE ieee.std_logic_1164.all;------------------------------------------------------------------------------PACKAGE homebrew IS

TYPE state IS (st1, st2, st3, st4);TYPE colour IS (red, green, blue);CONSTANT vec : STD_LOGIC_VECTOR (3 downto 0) := “1111”;

END homebrew;------------------------------------------------------------------------------

The file that encapsulates the definition of STD_LOGIC is a package itself, known as std_logic_1164.�


PACKAGEExample (Constant, Data Types, and a Function):

------------------------------------------------------------------------------LIBRARY ieee;USE ieee.std_logic_1164.all;------------------------------------------------------------------------------PACKAGE homebrew IS

TYPE state IS (st1, st2, st3, st4);TYPE colour IS (red, green, blue);CONSTANT vec : STD_LOGIC_VECTOR (3 downto 0) := “1111”;FUNCTION positive_edge(SIGNAL s : STD_LOGIC)

RETURN BOOLEAN;END homebrew;------------------------------------------------------------------------------PACKAGE BODY homebrew IS

FUNCTION positive_edge(SIGNAL s : STD_LOGIC)RETURN BOOLEAN IS

BEGINRETURN (s’EVENT AND s=‘1’);

END positive_edge;END homebrew;


Using a PACKAGE

• Recall that the work library is included by default

• PACKAGE included with the library declaration:

LIBRARY ieee;USE ieee.std_logic_1164.all;USE work.homebrew.all;

Use all definitions in the

�package


COMPONENT

COMPONENT component_name ISPORT (

port_name : signal_mode signal_type;port_name : signal_mode signal_type... );

END COMPONENT;

---- COMPONENT declaration -------COMPONENT inverter IS

PORT ( a : IN STD_LOGIC;b: OUT STD_LOGIC);

END COMPONENT;

label: component_name PORT MAP (port_list);

---- COMPONENT instantiation -----U1: inverter PORT MAP (x, y);

Component declaration allows use of VHDL entities as subcircuit.

To call out the created component with a name.


Example - Combinational Logic

ENTITY inverter ISPORT (a : IN BIT;

b : OUT BIT);END inverter;-----------------------------------------------ARCHITECTURE inv OF inverter ISBEGIN

b <= NOT a;END inv;

ENTITY nand_2 ISPORT (a, b : IN BIT;

c : OUT BIT);END nand_2;-----------------------------------------------------ARCHITECTURE nand_2 OF nand_2 ISBEGIN

c <= NOT (a AND b);END nand_2;

ENTITY nand_3 ISPORT (a, b, c : IN BIT;

d : OUT BIT);END nand_3;-----------------------------------------------------ARCHITECTURE nand_3 OF nand_3 ISBEGIN

d <= NOT (a AND b AND c);END nand_3;

FILE: inverter.vhd FILE: nand_2.vhd

FILE: nand_3.vhd



ENTITY project ISPORT (a, b, c, d : IN BIT;

x, y : OUT BIT);END project;----------------------------ARCHITECTURE structural OF project IS

------------COMPONENT inverter IS

PORT (a : IN BIT; b : OUT BIT);END COMPONENT;------------COMPONENT nand_2 IS

PORT (a, b : IN BIT; c : OUT BIT);END COMPONENT;------------COMPONENT nand_3 IS

PORT (a, b, c : IN BIT; d : OUT BIT);END COMPONENT;------------SIGNAL w : BIT;

BEGINU1: inverter PORT MAP (b, w);U2: nand_2 PORT MAP (a, b, x);U3: nand_3 PORT MAP (w, c, d, y);

END structural;

FILE: project.vhd



PACKAGE homebrew IS----- inverter ------------COMPONENT inverter IS

PORT (a: IN BIT; b: OUT bit);END COMPONENT;----- 2-input nand -----COMPONENT nand_2 IS

PORT (a, b: IN BIT; c: OUT BIT);END COMPONENT;----- 3-input nand -----COMPONENT nand_3 IS

PORT (a, b, c: IN BIT; d: OUT BIT);END COMPONENT;----------------------------

END homebrew;

USE work.homebrew.all----------------ENTITY project IS

PORT (a, b, c, d: IN BIT;x, y: OUT BIT);

END project;-----------------ARCHITECTURE structural OF project IS

SIGNAL w: BIT;BEGIN

U1: inverter PORT MAP (b, w);U2: nand_2 PORT MAP (a, b, x);U3: nand_3 PORT MAP (w, c, d, y);

END structural;

FILE: homebrew.vhd FILE: project.vhd

To create a package with 3 components.


Component declarations


Component Port Notes

• Positional port mapping

• Nominal port mapping

• Open ports

COMPONENT inverter ISPORT (a: IN BIT; b: OUT BIT);

END COMPONENT;

U1: inverter PORT MAP (x, y);

U1: inverter PORT MAP ( y=>b, x=>a);

U2: my_circuit PORT MAP (x=>a, y=>b, w=>OPEN, z=>d);

Instance name must be unique.


Example - Two-Digit Counter

• Design a 2-digit decimal counter (0 to 99 to 0)– Asynchronous reset– Output on seven-segment display (SSD)


Example - Two-Digit CounterENTITY counter IS

PORT (clk, reset : IN STD_LOGIC;digit1, digit2 : OUT STD_LOGIC_VECTOR (6 downto 0));

END counter;-----------------------------------------------ARCHITECTURE counter OF counter ISBEGIN

PROCESS (clk, reset)VARIABLE temp1: INTEGER RANGE 0 TO 10;VARIABLE temp2: INTEGER RANGE 0 TO 10;

BEGINIF (reset=‘1’) THEN

temp1 := 0;temp2 := 0;

ELSIF (clk’EVENT AND clk=‘1’) THENtemp1 := temp1 + 1;IF (temp1 = 10) THEN

temp1 := 0;temp2 := temp2 + 1;IF (temp2=10) THEN

temp2 := 0;END IF;

END IF;END IF;



CASE temp1 ISWHEN 0 => digit1 <= “1111110”;WHEN 1 => digit1 <= “0110000”;WHEN 2 => digit1 <= “1101101”;WHEN 3 => digit1 <= “1111001”;WHEN 4 => digit1 <= “0110011”;WHEN 5 => digit1 <= “1011011”;WHEN 6 => digit1 <= “1011111”;WHEN 7 => digit1 <= “1110000”;WHEN 8 => digit1 <= “1111111”;WHEN 9 => digit1 <= “1111011”;WHEN OTHERS => NULL;

END CASE;CASE temp2 IS

WHEN 0 => digit2 <= “1111110”;...

END CASE;END PROCESS;

END counter;



ENTITY bcd_to_ssd ISPORT (digit : IN INTEGER RANGE 0 TO 9;

ssd_display : OUT BIT_VECTOR (6 downto 0));END bcd_to_ssd;--------------------------------------ARCHITECTURE ssd OF bcd_to_ssd ISBEGIN

PROCESS (digit)CASE digit IS

WHEN 0 => ssd_display <= “1111110”;WHEN 1 => ssd_display <= “0110000”;WHEN 2 => ssd_display <= “1101101”;WHEN 3 => ssd_display <= “1111001”;WHEN 4 => ssd_display <= “0110011”;WHEN 5 => ssd_display <= “1011011”;WHEN 6 => ssd_display <= “1011111”;WHEN 7 => ssd_display <= “1110000”;WHEN 8 => ssd_display <= “1111111”;WHEN 9 => ssd_display <= “1111011”;

END CASE;END PROCESS;

END ssd;

bcd_to_ssd.vhd


Example - Two-Digit CounterENTITY counter IS

PORT (clk, reset : IN STD_LOGIC;digit1, digit2 : OUT STD_LOGIC_VECTOR (6 downto 0));

END counter;-----------------------------------------------ARCHITECTURE counter OF counter IS

SIGNAL temp_digit1: INTEGER RANGE 0 TO 9;SIGNAL temp_digit2: INTEGER RANGE 0 TO 9;------------------COMPONENT bcd_to_ssd ISPORT ( digit : IN INTEGER RANGE 0 TO 9;

ssd_display : OUT BIT_VECTOR (6 downto 0));END COMPONENT;------------------

BEGINPROCESS (clk, reset)

VARIABLE temp1: INTEGER RANGE 0 TO 10;VARIABLE temp2: INTEGER RANGE 0 TO 10;

BEGIN...temp_digit1 <= temp1;temp_digit2 <= temp2;

END PROCESS;C1: bcd_to_ssd PORT MAP (temp_digit1, digit1);C2: bcd_to_ssd PORT MAP (temp_digit2, digit2);

END counter;

counter.vhd


Structural Descriptions in VHDL• Hierarchical design involves:

– creating and placing sub-circuits

– connecting sub-circuits to each other and to input/output terminals

• VHDL also supports these structural descriptions

– sub-circuits are called components

– placing components is called instantiation (creating instances)


Graphical Hierarchical Design

• Can create hierarchical graphical designs in Quartus II by:– Place all necessary files in a single project directory– Create Symbol Files– Instantiate components using the Block Tool– Connect components


GENERIC MAP• GENERIC parameters (and data attributes) enhance

reusability of code

label: compon_name GENERIC MAP (param. list) PORT MAP (port list);

Example: Parity GeneratorAdds a bit to a vector such that the number of onesin the new vector is even.

GENERIC MAP is similar to PORT MAP PORT MAP assigns signal names to the ports of a subcircuit GENERIC MAP assigns values to the parameters of the subcircuit.


Example - Parity Generator

ENTITY parity_gen ISGENERIC (n : INTEGER := 7);PORT ( input : IN BIT_VECTOR (n downto 0);

output : OUT BIT_VECTOR (n+1 downto 0));END parity_gen;---------------------------------------------------------------------------ARCHITECTURE parity OF parity_gen ISBEGIN

PROCESS (input)VARIABLE temp1: BIT;VARIABLE temp2: BIT_VECTOR (output’RANGE);

BEGINtemp1 := ‘0’;FOR i IN input’RANGE LOOP

temp1 := temp1 XOR input(i);temp2(i) := input(i);

END LOOP;temp2(output’HIGH) := temp1;output <= temp2;

END PROCESS;END parity;

FILE: parity_gen.vhd


Example - Parity Generator

ENTITY project ISGENERIC (n : INTEGER 2);PORT ( inp : IN BIT_VECTOR (n downto 0);

outp : OUT BIT_VECTOR (n+1 downto 0));END project;-------------------------------------------------------------------------ARCHITECTURE project OF project IS

----------------------COMPONENT parity_gen IS

GENERIC (n : INTEGER);PORT (input : IN BIT_VECTOR (n downto 0);

output : OUT BIT_VECTOR (n+1 downto 0));END COMPONENT;----------------------

BEGINC1: parity_gen GENERIC MAP(n) PORT MAP(inp, outp);

END project;

FILE: project.vhd

Overwrites n:=7in parity_gen.vhd


Example - Shift Register

LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY lpm; -- assume that this has been createdUSE lpm.lpm_components.all

ENTITY Shift ISPORT ( Clock,Reset,Shiftin,Load : IN STD_LOGIC;

R: IN STD_LOGIC_VECTOR(3 DOWNTO 0);Q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));

END shift;-------------------------------------------------------------------------ARCHITECTURE structure OF shift IS

----------------------instance: lpm_shiftreg -- instance of subcircuit lpm_shiftreg

GENERIC MAP (LPM_WIDTH => 4, LPM_DIRECTION => “RIGHT”)PORT MAP (data => R, clock => Clock, aclr => Reset, load => Load,

shiftin => Shiftin, q => Q);END structure;---------------------- GENERIC MAP sets the no.

of flip flops to 4 and direction of shifting to RIGHT.

PORT MAP assigns the names of entity to library component.


FUNCTION

FUNCTION function_name [<parameter_list>] RETURN data_type IS[ declarations ]

BEGIN(sequential statements)

END function_name;

• Parameters can be• Constants - [ CONSTANT ] constant_name: constant_type;• Signals - SIGNAL signal_name: signal_type;

• Variable parameters not allowed• Do not include RANGE (Integers, BIT_VECTOR, etc.)• Function only returns one value• Occurs as part of an expression

x <= maximum(a, b);IF x > maximum(a, b)...

Functions are subprograms in VHDL; they have a body and may have declarations.

Functions perform sequential computations and return a value as the value of the function.


Example - Positive Edge

------- Function body ---------------------FUNCTION positive_edge(SIGNAL s: STD_LOGIC)

RETURN BOOLEAN ISBEGIN

RETURN (s’EVENT AND s=‘1’);END positive_edge;------- Function call -----------------------...IF positive_edge(clk) THEN ......

This function inputs 1 signal from calling statement.

A Boolean is returned;TRUE or FALSE type of return.

It accepts a signal and tests of an event in the signal and the logic of the signal. The calling statement sends the

signal clk to the function to test for +ve edge. A TRUE/FALSE will be returned.



ENTITY dff ISPORT (d, clk, rst : IN BIT;

q : OUT BIT);END dff;----------------------------------------------ARCHITECTURE dff OF dff IS

----------------FUNCTION pos_edge(SIGNAL s: BIT)

RETURN BOOLEAN ISBEGIN

RETURN (s’EVENT AND s=‘1’);END pos_edge;----------------

BEGINPROCESS (clk, rst)BEGIN

IF (rst=‘1’) THEN q <= ‘0’;ELSIF pos_edge(clk) THEN q <= d;END IF;

END PROCESS;END dff;



PACKAGE homebrew ISFUNCTION pos_edge(SIGNAL s : BIT)

RETURN BOOLEAN;END homebrew;------------------------------------PACKAGE BODY homebrew IS

FUNCTION pos_edge(SIGNAL s : BIT)RETURN BOOLEAN IS

BEGINRETURN (s’EVENT AND s=‘1’);

END pos_edge;END homebrew;

USE work.homebrew.all;---------------------------------------------ENTITY dff IS

PORT (d, clk, rst : IN BIT;q : OUT BIT);

END dff;----------------------------------------------ARCHITECTURE dff OF dff ISBEGIN

PROCESS (clk, rst)BEGIN

IF (rst=‘1’) THEN q <= ‘0’;ELSIF pos_edge(clk) THEN q <= d;END IF;

END PROCESS;END dff;

homebrew.vhd dff.vhd

Use of the function now needs declaration. Any VHDL entity can use the test function by declaration.

The test of +ve edge isnow part of a package.


Example - Overloaded “+”

LIBRARY ieee;USE ieee.std_logic_vector.all;-----------------------------------------PACKAGE homebrew IS

FUNCTION “+” (a, b : STD_LOGIC_VECTOR)RETURN STD_LOGIC_VECTOR;

END homebrew;-----------------------------------------PACKAGE BODY homebrew IS

FUNCTION “+” (a, b : STD_LOGIC_VECTOR)RETURN STD_LOGIC_VECTOR IS

VARIABLE result: STD_LOGIC_VECTOR(a’RANGE);VARIABLE carry: STD_LOGIC;

BEGINcarry := ‘0’;FOR i IN a’REVERSE_RANGE LOOP

result(i) := a(i) XOR b(i) XOR carry;carry := (a(i) AND b(i)) OR (a(i) AND carry) OR

(b(i) AND carry);END LOOP;RETURN result;

END “+”;END homebrew;

homebrew.vhd

Overloading allows one operator to perform several different functions.

Overloaded ‘+’ adds 2 multibit numbers with a carry in.


Example - Overloaded “+”

LIBRARY ieee;USE ieee.std_logic_1164.all;USE work.homebrew.all;-----------------------------------------------------------------ENTITY add_bit IS

PORT (a: IN STD_LOGIC_VECTOR (3 downto 0);y: OUT STD_LOGIC_VECTOR (3 downto 0));

END add_bit;-----------------------------------------------------------------ARCHITECTURE add_bit OF add_bit IS

CONSTANT b: STD_LOGIC_VECTOR (3 downto 0) := “0011”;CONSTANT c: STD_LOGIC_VECTOR (3 downto 0) := “0110”;

BEGINy <= a + b + c; -- we can add numbers of different types now

END add_bit;

add_bit.vhd


PROCEDURE

PROCEDURE procedure_name [<parameter_list>] IS[ declarations ]

BEGIN(sequential statements)

END procedure_name;

• Parameters can be• Constants (default inputs)• Signals• Variables (default outputs)

• Can have any number of outputs• Edge detection not synthesisable

PROCEDURE my_procedure ( a: IN BIT; SIGNAL b, c: IN BIT;SIGNAL x: OUT BIT_VECTOR (7 downto 0);SIGNAL y: INOUT INTEGER RANGE 0 TO 99) IS

BEGIN...END my_procedure;

Procedures perform sequential computations and return values in global objects or by storing values into formal parameters.


Example - Sort

LIBRARY ieee;USE ieee.std_logic_1164.all;-------------------------------------------------------------------PACKAGE homebrew IS

CONSTANT limit: INTEGER := 255;PROCEDURE sort (SIGNAL in1, in2: IN INTEGER RANGE 0 TO limit;

SIGNAL min, max: OUT INTEGER RANGE 0 TO limit);END homebrew;-------------------------------------------------------------------PACKAGE BODY homebrew IS

PROCEDURE sort (SIGNAL in1, in2: IN INTEGER RANGE 0 TO limit;SIGNAL min, max: OUT INTEGER RANGE 0 TO limit) IS

BEGINIF (in1 > in2) THEN

max <= in1;min <= in2;

ELSEmax <= in2;min <= in1;

END IF;END sort;

END homebrew;

homebrew.vhd

There is no RETURN, the results are in the parameters.


Example - Sort

LIBRARY ieee;USE ieee.std_logic_1164.all;USE work.homebrew.all;-----------ENTITY min_max IS

GENERIC ( limit : INTEGER := 255);PORT ( ena : IN BIT;

inp1, inp2 : IN INTEGER RANGE 0 TO limit;min_out, max_out: OUT INTEGER RANGE 0 TO limit);

END min_max;--------------------ARCHITECTURE min_max OF min_max ISBEGIN

PROCESS (ena)BEGIN

IF (ena=‘1’) THEN sort (inp1, inp2, min_out, max_out);END IF;

END PROCESS;END min_max;

min_max.vhd


FUNCTIONS vs PROCEDURES

WAIT, COMPONENTS, Edge Detection

WAIT and COMPONENTS

Unsynthesisable elements

Called

Outputs

Inputs

Its own statementAs part of an expression

Returns any number of values

Returns a single value

Constants, Signals, or Variables

Constants or Signals

PROCEDUREFUNCTION


Summary

• Synthesisable VHDL– VHDL inherently concurrent– Data types– Attributes– Signals versus Variables

• Project Organisation– Libraries and Packages– Functions and Procedures– Hierarchical Design

» Schematics» Components

ELEC3720 Chapter 6 Program Organization in VHDL

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