EG21-G Reference Design - AURORA EVERNET

EG21-G

Reference Design

LTE Standard Module Series

Rev. EG21-G_Reference_Design_V1.0

Date: 2019-12-05

Status: Released

www.quectel.com

http://www.quectel.com/

LTE Standard Module Series EG21-G Reference Design

EG21-G_Reference_Design 1 / 8

Our aim is to provide customers with timely and comprehensive service. For any

assistance, please contact our company headquarters:

Quectel Wireless Solutions Co., Ltd.

Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai,

China 200233

Tel: +86 21 5108 6236

Email: [email protected]

Or our local office. For more information, please visit:

http://www.quectel.com/support/sales.htm

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http://www.quectel.com/support/technical.htm

Or email to: [email protected]

GENERAL NOTES

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PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT

TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT

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mailto:[email protected]

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http://www.quectel.com/support/technical.htm

mailto:[email protected]



About the Document

Revision History

Revision Date Author Description

1.0 2019-12-05 Lim PENG/

Woody WU Initial



Contents

About the Document ................................................................................................................................... 2

Contents ....................................................................................................................................................... 3

Figure Index ................................................................................................................................................. 4

1 Reference Design ................................................................................................................................. 5

1.1. Introduction ................................................................................................................................ 5

1.2. Power-on/off and Resetting Scenarios ...................................................................................... 6

1.2.1. Power-on Scenario ........................................................................................................... 6

1.2.2. Power-off Scenario ........................................................................................................... 7

1.2.3. Resetting Scenario ........................................................................................................... 8

1.3. Schematics ................................................................................................................................ 8



Figure Index

FIGURE 1: TIMING OF TURNING ON MODULE ............................................................................................... 6

FIGURE 2: TIMING OF TURNING OFF MODULE ............................................................................................. 7

FIGURE 3: TIMING OF RESETTING MODULE ................................................................................................. 8



1 Reference Design

1.1. Introduction

This document provides the reference design for Quectel EG21-G module. And the reference design

includes power-on/off/resetting scenarios, block diagrams of power supply and module design, UART

interfaces, (U)SIM interface, audio interfaces, etc.



1.2. Power-on/off and Resetting Scenarios

1.2.1. Power-on Scenario

VIL≤0.5V

VH=0.8V

VBAT

PWRKEY

≥500ms

RESET_N

STATUS(OD)

Inactive ActiveUART

NOTE 1

Inactive ActiveUSB

≥2.5s

≥12s

≥13s

VDD_EXT

About 100ms

BOOT_CONFIG & USB_BOOT Pins

≥100ms. After this time, the BOOT_CONFIG pins can be set to high level by external circuit.

Figure 1: Timing of Turning on Module

1. Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is

no less than 30ms.

2. When using MCU to control module to enter the emergency download mode, please follow the above

timing sequence. It is not recommended to pull up USB_BOOT to 1.8V before powering up VBAT.

Short the test points as shown in Figure 28 can manually force the module to enter download mode.

NOTES



1.2.2. Power-off Scenario

VBAT

PWRKEY

≥29.5s≥650ms

RUNNING Power-down procedure OFFModuleStatus

STATUS(OD)

Figure 2: Timing of Turning off Module

1. In order to avoid damaging internal flash, please do not switch off the power supply when the module

works normally. Only after the module is shut down by PWRKEY or AT command, the power supply

can be cut off.

2. When turning off module with the AT command, please keep PWRKEY at a high level after the

execution of the command. Otherwise, the module will turn itself back on after being shut down.

NOTES



1.2.3. Resetting Scenario

VIL≤0.5V

VIH≥1.3V

VBAT

≥150ms

ResettingModule

StatusRunning

RESET_N

Restart

≤460ms

Figure 3: Timing of Resetting Module

1. Please ensure that there is no large capacitance with the max value exceeding 10nF on PWRKEY

and RESET_N pins.

2. RESET_N only resets the internal baseband chip of the module and does not reset the power

management chip.

3. It is recommended to use RESET_N only when failing to turn off the module by AT+QPOWD

command or PWRKEY pin.

1.3. Schematics

The schematics illustrated in the following pages are provided for your reference only.

NOTES

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Power Supply Block Diagram

DC-DCDC 5V OUTe.g. DC 12V IN DC 3.8V @2.0A

EG21-GMIC29302WU

MOS ON/OFFUSB_VBUS

ENVBAT_EN

SGM2019-ADJYN5G/TRDC 3.3V

SGM2019-ADJYN5G/TRDC 1.8V

CODEC_EN

ENVDD_EXT

MIC29302WUEN

ALC5616

TLV320AIC3104or

Codec

VBUS_CTRLEN

POWER_EN

SD cardMOS ON/OFFEN

DC 3.3V @0.8ASD_PWR_EN

SGMIIDC 3.3V @0.8A

51K

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NOTE:A transistor translation circuit or a level translator TXS0108EPWR provided by Texas Instruments is recommended.

Reference Design Block Diagram

EG21-G

(U)SIM

VDD_EXT

FORCE_USB_BOOT

PCM

ANT_MAIN

ADC0

ADC1

MAIN UART

I2C

ANT_MAIN

WAKEUP_IN

STATUS

NET_MODE

NET_STATUS

MCU

PWRKEYGPIO_03

GPIO_04 RESET_N

GPIO_08

GPIO_05 W_DISABLE#

GPIO_06

USB USB

3.3V/1.8V

ALC5616

TLV320AIC3104or

(U)SIM Card

SDC2 SD Card

UART

DEBUG UART

Test Points

12-bit ADC0.3V～VBAT_BB

Status Indication

NOTE

VBAT3.8V, 2.0A

AP_READY

GPIO_01

GPIO_02

GPIO_07

GPIO_09

VDD

VBAT_EN

VBUS_CTRL

CODEC_POWER_EN

SD_PWR_EN

VDD_MCU

VBAT

Transistor Circuit

Main Antenna

Handset

or

Earphone

Level Translator

AR8033-AL1B-R FC3004SGMIIEPHY

RJ45

ANT_GNSS ANT_GNSS

GNSS Antenna

ANT_DIVANT_DIV

Rx-diversityAntenna

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Module Interface

1. Keep all RESERVED and unused pins unconnected, and ensure all GND pins are connected to the ground network.Notes:

2. Pins 73～84 are unused in the design, and can be ignored in schematic and PCB decal.

3. A common mode choke L0101 is recommended to be added in series between the module and customers' MCU in order to

Meanwhile, it is recommended to reserve the test points for upgrading the firmware over USB interface and minimize the

4. ADC pins cannot be directly connected to the module's power supply and the input voltage must not exceed VABT_BB.5. C0101 and C0102 should be placed close to the SGMII interface of the module.

Note 3

Note 6

Note 4

EG21-G

EG21-G

Note 5

extra stubs of the trace. The two resistors should be placed close to the module.

suppress EMI spurious transmission, and should be placed close to the module.

6. Do not pull up pin1,pin5, pin40,pin136,pin137and pin138 unless the module starts up sucessfully.

Meanwhile, these pins should be served as a keepout area.

R0111 NM_0R

R0109 NM_0R

R0113 100K

R0114 100K

R0116100K

R0115100K

R0118 0R

R0120 0R

R0122 0R

R0124 0R

R0108 0R

R0104 0R

R0106 0R

R0102 0R

1 WAKEUP_IN2 AP_READY3 RESERVED4 W_DISABLE#5 NET_MODE6 NET_STATUS7 VDD_EXT

8 GND9 GND

10 USIM_GND11 DBG_RXD12 DBG_TXD13 USIM_PRESENCE14 USIM_VDD15 USIM_DATA16 USIM_CLK17 USIM_RST18 RESERVED

19G

ND

20R

ES

ET_

N

21P

WR

KE

Y

22G

ND

23S

D2_

INS

_DE

T

24P

CM

_IN

25P

CM

_OU

T

26P

CM

_SY

NC

27P

CM

_CLK

28S

DC

2_D

ATA

3

29S

DC

2_D

ATA

2

30S

DC

2_D

ATA

1

31S

DC

2_D

ATA

0

32S

DC

2_C

LK

33S

DC

2_C

MD

34V

DD

_SD

IO

35A

NT_

DIV

36G

ND

37RESERVED

38RESERVED

39RESERVED

40RESERVED

41I2C_SCL

42I2C_SDA

43RESERVED

44ADC1

45ADC0

46GND

47ANT_GNSS

48GND

49ANT_MAIN

50GND

51GND

52GND

53GND

54GND

55R

ES

ER

VE

D56

GN

D57

VB

AT_

RF

58V

BA

T_R

F59

VB

AT_

BB

60V

BA

T_B

B61

STA

TUS

62R

I63

DC

D64

CTS

65R

TS66

DTR

67TX

D68

RX

D69

US

B_D

P70

US

B_D

M71

US

B_V

BU

S72

GN

D11

5U

SB

_BO

OT

116

RE

SE

RV

ED

113

RE

SE

RV

ED

114

RE

SE

RV

ED

141 RESERVED142 RESERVED 143RESERVED

144RESERVED

U0101-A

85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97 GND98 GND99 GND

100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND 111GND

112GND

117RESERVED

118RESERVED

119EPHY_RST_N

120EPHY_INT_N

121SGMII_MDATA

122SGMII_MCLK

123SGMII_TX_M

124SGMII_TX_P

125SGMII_RX_P

126SGMII_RX_M

127RESERVED

128USIM2_VDD

129RESERVED

130RESERVED

131RESERVED

132RESERVED

133RESERVED

134RESERVED

135RESERVED

136RESERVED

137RESERVED

138RESERVED

139RESERVED

140RESERVED

U0101-B

C0101 100nFC0102 100nF

1 2

34

L0101

DLM0NSN900HY2D

[6] USIM_GND[14] DBG_RXD[14] DBG_TXD

[6] USIM_VDD

[6] USIM_CLK[6] USIM_RST

[6] USIM_DATA

[4,5,6,11,13,14] VDD_EXT

[14] NET_STATUS

[14] NET_MODE[4] W_DISABLE_EG21-G

[4] AP_READY_EG21-G

[4] RESET_N[4,14] PWRKEY

[10]

AN

T_D

IV

[10]ANT_MAIN

[10]ANT_GNSS

[4,14] USB_VBUS

[6] RXD_EG21-G

[6] TXD_EG21-G

[6]

DTR

_EG

21-G

[6] RTS_EG21-G

[6] CTS_EG21-G

[6]

DC

D_E

G21

-G[6

]R

I_E

G21

-G[1

4]S

TATU

S[3

,5,1

4]V

BA

T

[3,5

,14]

VB

AT

[6] USIM_PRESENCE

[7,8] CODEC_PCM_IN

[7,8] CODEC_PCM_OUT

[7,8] CODEC_PCM_SYNC

[7,8] CODEC_PCM_CLK

[7,8]I2C_SDA

[14] USB_DM_TEST

[14] USB_DP_TEST

ADC0_INPUTADC1_INPUT

[7,8]I2C_SCL

[14] USB_BOOT

[4] WAKEUP_IN_EG21-G

[13] SD2_INS_DET

[13]

SD2_

DAT

A3

[13]

SD2_

DAT

A2

[13]

SD2_

DAT

A1[1

3]SD

2_D

ATA0

[13]

SD2_

CLK

[13]

SD2_

CM

D

[13]

VDD

_SD

IO

[11]USIM2_VDD

[11]SGMII_RX_M[11]SGMII_RX_P

[11]SGMII_TX_P[11]SGMII_TX_M[11]SGMII_MDIO_CLK[11]SGMII_MDIO_DATA

[11]EPHY_INT_N[11]EPHY_RST_N

[4] USB_DP

[4] USB_DM

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EG21-G

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Reference Design

5V power source from main board.

It is used to reset the module.It is used to turn on or off the module.

MCU Interface

The USB_VBUS pins of MCU and EG21-G should be powered by a 5V power system for USB detection, and USB_VBUS_CTRL is used to turn on/off USB_VBUS power supply.2. EG21-G can only work as a USB device and supports Full Speed and High Speed modes. To communicate with USB interface, MCU needs to support USB host or OTG function. 1. U0201 represents customers's MCU. The power domain of GPIO interfaces on EG21-G modules is 1.8V. If the domain on U0201's GPIO interfaces is the same, then the level translation circuit can be omitted.Notes:

3. AP_READY is used to detect the MCU's sleep state. For more details, please refer to

It is used to wake up the module. It is used to let the module enter airplane mode.

4. WAKEUP_IN_EG21-G should be kept at low level before the module starts up successfully.Quectel_EG21-G_Hardware_Design.

G

S D

Q0205

SI2333CDS-T1

Q0207

DTC043ZEBTL

R0204

10K

Q0202

DTC043ZEBTLQ0201

DTC043ZEBTL

Q0206

2SC4617TLQ

R02014.7K

R02024.7K

Q0204

DTC043ZEBTL

Q0203

DTC043ZEBTL

VDDGNDTXDRXDCTSRTS

USB_VBUSUSB_D+USB_D-

GPIO_01GPIO_02GPIO_03

USB_ID

GPIO_04GPIO_05GPIO_06GPIO_07GPIO_08GPIO_09GPIO_10GPIO_11GPIO_12GPIO_13

RIDCDDTR

U0201C0201

10nF

C0202

10nF

C0203

10nF

C0204

1nF

VDD_MCU

[6]RXD[6]TXD

[3]USB_DP[3]USB_DM

[3,4,14]USB_VBUS

[4]ON/OFF_MCU[4]RESET_MCU

[4]VBUS_CTRL

[5,14] DC_5V [3,4,14]USB_VBUS

[4] VBUS_CTRL

[4]W_DISABLE_MCU[4]SLEEP_STATUS

[3]RESET_N

[4] RESET_MCU

[3,14]PWRKEY

[4] ON/OFF_MCU

[6]CTS[6]RTS

[5]VBAT_EN

[3] AP_READY_EG21-G [4]SLEEP_STATUS

VDD_EXT VDD_EXT

[3]W_DISABLE_EG21-G

[4] W_DISABLE_MCU

[5]CODEC_POWER_EN

[3]WAKEUP_IN_EG21-G

[4] WAKEUP_IN_MCU

[4]WAKEUP_IN_MCU[13]SD_PWR_EN

[6]DTR

[6]RI[6]DCD

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DC-DC Application

Notes:

2. VBAT should be routed in star mode to VBAT_BB and VBAT_RF pins.

Power Supply Design

VBAT DesignClosed to VBAT_BB pins.

Closed to VBAT_RF pins.

1. The power supply must be able to provide sufficient current up to 2A or more.

VDD_1V8 = (R0310/R0312+1)*1.207 = 1.8V

Power Supply for PCM CodecVDD_3.3V = (R0305/R0308+1)*1.207 = 3.3V

LDO ApplicationIt is used when the input voltage is below 7V.

VBAT = (R0301/R0307+1)*1.24 = 3.88VThe recommended load current is greater than 10mA.

Power Supply for SGMII and SD Card

VBAT = (R0314/R0318+1)*1.24 = 3.3VNote:

DC-DC LDO

LDODC 1.8V

LDO DC 3.3V

Codec

LDODC 3.3V 3.0A

EG21-G

SD Card

DC 5V OUT DC 3.8V 2.0Ae.g. DC12V IN

3. The recommended operating voltage of VBAT is 3.3V～4.3V.

The recommended load current of MIC29302WU is greater than 10mA.

Notes:1. CODEC_POWER_EN must be at low level in order to ensure the normal output voltage of VDD_3.3V.

2. The following power-on/off sequences should be complied with to ensure the audio codec

Power-on Sequence: power on VDD_1V8 first, then VDD_3.3V.

Note 1

If VDD_3.3V power supply needs to be switched off, please keep CODEC_POWER_EN at high level.

SGMII

It is used when the input voltage is above 7V. Use a DC-DC converter to convert a high input voltageinto a 5V output, and then the LDOs will generate 3.8V, 3.3V and 1.8V typical voltages.

Power-off Sequence: power off VDD_3.3V first, then VDD_1V8.

works normally.

+

C0301

100μF

C0302

100nF

C0303

33pF

C0304

10pF

C0306

100nF

C0307

33pF

C0308

10pF

+

C0305

100μF

D0301

WS4.5D3HV

1 IN3 EN

5OUT4BP

2G

ND

U0303

SGM2019-ADJYN5G/TR

C0320

4.7μF

R0310

39K1%

R031275K1%

C0318

100nFC0321

100nF

C0322

33pF

C0319

1μF

C0315

4.7μF

R030573.2K1%

R030842.2K1%

C0316

100nF

C0313

1μF

C0314

100nF

1 IN3 EN

5OUT4BP

2G

ND

U0302

SGM2019-ADJYN5G/TR

C0317

33pF

R030610K

+ C0311

470μF

1E

N

2 IN

3G

ND

4OUT

5A

DJ

U0301

MIC29302WU

C0312

100nF

C0310

100nF

+ C0309

470μF

R0301100K1%

R030747K1%

R0302

51KR0303330R

Q0301DTC043ZEBTL

R0311

100K

R0309 0R

+ C0325

470μF1E

N

2 IN

3G

ND

4OUT

5A

DJ

U0304

MIC29302WU

C0326

100nF

C0324

100nF

+ C0323

470μF

R0314

75K1%

R031847K1%

R0313

51KR0315330R

Q0304

DTC043ZE

[3,5,14]VBAT

[3,5,14]VBAT

VBAT

VDD_1V8

VDD_3.3V[4,5,14] DC_5V

[4] CODEC_POWER_EN

[4,5,14] DC_5V

VBAT

[4] VBAT_EN

[4,5,14] DC_5V

[3,4,6,11,13,14] VDD_EXT

[4,5,14] DC_5VVDD3V3

[5,7,8] VDD_1V8


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(U)SIM and UART Designs

UART Translation - Transistor Solution

UART Translation - IC Solution

Notes:

(U)SIM Interface

1. There are two translation solutions: transistor solution and IC solution,

3. The transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.The 1nF capacitors C0402 and C0403 can improve the signal quality.

2. The power supply voltage of VCCA should not exceed that of VCCB.

Notes:1. U401 is recommended to be used to offer good ESD protection,

2. It is recommended to connect the (U)SIM card connector's GND to the module's USIM_GND.

3. The pull-up resistor R0401 can improve anti-jamming capability,

4. R0407～R0409 are used for debugging,

5. C0401 capacitance should be less than 1μF.4. The RTS and DTR transistor circuits are similar to that of RXD interface.

If the ground is complete on customers' PCB, USIM_GND can be connected to PCB ground directly.

and the parasitic capacitance should not be more than 15pF.

and should be placed close to the (U)SIM card connector.

6. For more information about the layout, please refer to

For more information about TXS0108E, please refer to the datasheet from TI.

The CTS, RI and DCD transistor circuits are similar to that of TXD interface.

and C0404～C0406 are used for filtering interference of EGSM900.

and should be placed close to the (U)SIM card connector.

and IC solution is recommended to be selected.

Quectel_EG21-G_Hardware_Design.

Q0401

2SC4617TLQ

Q0402

2SC4617TLQ

R040610K

R0405

10K

R040310K

R040410K

C0401 100nF

1GND

2VPP

3I/O4 CLK

5 RST

6 VCC

78 PRESENCE

J0401

(U)SIM card connector

1

2

3 4 5 6

U0401 ESDA6V8AV6

R0402

51K

C0405

33pF

C0406

33pF

C0404

33pF

R0407 0R

R0408 0R

R0409 0R

R040115K

C0407100nF

R0411120K

R041010K

C0408 100nF

6 A5

7 A6

8 A7

9 A8

10 OE

5 A4

4 A3

19VCCB

20B1

18B2

14B6

13B7

12B8

11GND

3 A2

2 VCCA

1 A1

17B3

16B415B5

U0402

TXS0108E

C0403

1nF

C0402

1nF

[4,6] RXD [3,6]RXD_EG21-G

VDD_EXTVDD_EXT

[4,6] TXD [3,6]TXD_EG21-G

VDD_EXTVDD_MCU

[3]USIM_GND

VDD_EXTUSIM_VDD

[3] USIM_RST

[3] USIM_CLK

[3] USIM_DATA

USIM_VDD

[3] USIM_PRESENCE

VDD_EXT

VDD_EXT VDD_MCU

[3,6] TXD_EG21-G

[3,6] RXD_EG21-G[3] RI_EG21-G

[3] DTR_EG21-G

[4,6]TXD

[4,6]RXD

[4]DTR

[4]RI

[4]CTS

[4]RTS

[3] CTS_EG21-G

[3] RTS_EG21-G

[3] DCD_EG21-G [4]DCD


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SIZE VER

147

1.0

DATE 2019/12/5

EG21-G

A2

Reference Design

Audio Codec Design (ALC5616)

1. ALC5616 power-on sequence: DBVDD/I2C pull-up power/AVDD/DACREF/CPVDD -> MICVDD -> software initialization.Notes:

2. ALC5616 power-off sequence: close codec function by software -> MICVDD -> DBVDD/I2C pull-up power/AVDD/DACREF/CPVDD.3. EG21-G will automatically initialize the codec via I2C interface after it is turned on successfully, so all power supplies for the codec need to be powered on before that.4. Pin AGND and DGND of ALC5616 are connected together through 0R resisitor R0703.

5. The maximum output power of the codec is 30mW when the headphone driver with 32Ω load is used.

2 IN1P/DMC_DAT

3 IN2P4 IN2N/JD2

5D

AC

RE

F6

AV

DD

7A

GN

D

10LOUTR/N

11CPN2

12CPP2

13CPN1

14CPP1

15C

PV

DD

16CPVPP

18CPVREF

19CPVEE

20HPO_L

21 ADCDAT1

22 DACDAT1

23 LRCK1

26SCL

27SDA

28 GPIO1/IRQ1

29D

BV

DD

30D

CV

DD

31M

ICV

DD

32 MICBIAS1

8VREF2

24 BCLK1

1 JD1

9LOUTL/P

17HPO_R

25 MCLK

33D

GN

DU0501

ALC5616

C0504

4.7μF

C0505

4.7μF

C0506

100nF

R0503 0R

C0502

4.7μF

C0503

100nF

C05

112.

2μF

C05

1210

0nF

C05

074.

7μF

C05

0810

0nF

C05

102.

2μF

C0514 2.2μF

C0516 2.2μF

C0513 4.7μF R0507

0R

R0516 NM_10KR05174.7K

R0518

4.7K

C0528 4.7μF

C0523 2.2μFC0524 2.2μF

R0509 0R

R0511 0RR0513 0R

R0515 0R

C0526

NM

C0525

NM

C0527

NM

C0515 2.2μFC0517 2.2μF

R05141K

R05061.5K

R05051K

R05081.5K

C051910μF

R0502 0R

C0518 1μFC0520 1μF

C0521 1μFC0522 1μF

R0510 0RR0512 0R

R05010R

R05040R

C05

09N

M_3

3pF

C0501

NM_33pF

R0519 0RR0520 0R

VD

D_3

.3V

VD

D_1

V8

VDD_3.3V[3,8]I2C_SDA[3,8]I2C_SCL

VD

D_1

V8

VDD_1V8

[3,8] CODEC_PCM_OUT[3,8] CODEC_PCM_IN[3,8] CODEC_PCM_CLK[3,8] CODEC_PCM_SYNC

[7] MIC+[7] MIC-

[8,9]SPK_P[8,9]SPK_N

MICBIAS

[8,9] MIC_P[8,9] MIC_N

MICBIAS

[7]MIC+[7]MIC-

VDD_1V8

[8,9]SPK_R[8,9]SPK_L

1.0

EG21-GPROJECT TITLE

A2

Reference Design

2019/12/5DATE8 14

VERSIZE


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Power on reset

Differential signals, and are connected to handset and audio power amplifier.

Left and right channels, and are connected to headset.

Delay Circuit

Audio Codec Design (TLV320AIC3104)

1. TLV320AIC3104 power-on sequence: IOVDD -> AVDD/DRVDD -> DVDD -> software initialization.Notes:

2. The RC delay circuit, which is assembled with C0621 and R0608, is used to ensure that the power-on time difference between AVDD and DVDD is within 5ms.

4. EG21-G will automatically initialize the codec via I2C interface after it is turned on successfully,3. The RESET pin must be driven at low level for at least 10ns after all power supplies for TLV320AIC3104 are at their specified values.

5. The AGND and DGND of TLV320AIC3104 are connected together through 0R resisitor R0703 in Sheet 7. so all power supplies for the codec need to be powered on before that.

6.The maximum output power of the codec is 15mW when the surround stereo headphone driver with 32Ω load is used, and is 30mW when the surround stereoheadphone driver with 16Ω load is used.

1M

CLK

2B

CLK

3W

CLK

4D

IN

5D

OU

T

6DVSS

7IOVDD

8S

CL

9S

DA

10 MIC1LP/LINE1LP11 MIC1LM/LINE1LM

12 MIC1RP/LINE1RP13 MIC1RM/LINE1RM

14 MIC2L/LINE2L/MICDET

15 MICBIAS

16 MIC2R/LINE2R

17AVSS1

18DRVDD

19H

PLO

UT

20H

PLC

OM

21DRVSS

22H

PR

CO

M

23H

PR

OU

T

24DRVDD

25AVDD

26AVSS2

27LE

FT_L

OP

28LE

FT_L

OM

29R

IGH

T_LO

P30

RIG

HT_

LOM

31R

ES

ET

32DVDD

33G

ND

U0601TLV320AIC3104

C0619 100nF

C0618 100nF

R06141.5K

R06161.5K

C0613

2.2μF

C06

0510

0nF

C06

1110

uF

C06

061μ

F

C06

0710

0nF

C06

081μ

F

C06

101μ

F

C06

1410

0nF

C06

151μ

F

R0613 0R

C06

1610

0nF

C06

171μ

F

C0622 1μFC0623 1μF

R0607 10K

R0605 0RR0604 0R

R0601 0RR0603 0R

C0612

100nF

C0603

NM

C0601

NM

C0602

NM

C06

0910

0nF

R06091K

R06121K

C0620

10μF

R06104.7K

R06114.7K

R061710K

G

S D

Q0601

Si2333DS-T1-E3

C0621

10nF

R0608100K

Q0602

DTC043ZEBTL

R0615 NM_0R

C0624 22μF

C0604 22μF

R0606 NM_0R

R0602 0R

R0618 0RR0619 0R

R0620 0R

R0621 0R

[7,9] MIC_P[7,9] MIC_N

MICBIAS_3104

[3,7] I2C_SCL[3,7] I2C_SDA

VDD_3.3V

VDD_1V8

[7,9]SPK_P[7,9]SPK_N

DVDD

[3,7] CODEC_PCM_CLK[3,7] CODEC_PCM_SYNC

[7,9]SPK_R

[7,9]SPK_L

[5,7,8] VDD_1V8 [8]DVDD

[5,7,8] VDD_3.3V[8]DVDD

[5,7,8] VDD_1V8

[3,7] CODEC_PCM_OUT[3,7] CODEC_PCM_IN

PROJECT TITLELorry XU

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DATE 2019/12/5

EG21-G

A2

Reference Design

Handset Application

Earphone Application

Close to earphone interface

Notes:

Audio Interfaces

CTIA OMTPR0702/R0705R0701/R0704 M

MNMNM

1. The analog output only drives earphone and headset. For larger power loads such as speakers, an audio power amplifier should be added in the design.2. In handset application, both the MIC and SPK signal traces need to be routed as differential pairs.3. In earphone application, the MIC signal traces need to be routed as differential pairs.4. All MIC and SPK signal traces should be routed with total grounding and far away from noise such as clock and DC-DC signals, etc. 5. ALC5616 and TLV320AIC3104 cannot be used simultaneously in audio codec design.

4132

J0701

D07

01

ESD9X5.0ST5G

D07

02

C07

02

33pF

C07

04

33pF

C07

05

10pF

C07

03

10pF

C07

06

33pF

C07

01

10pF

C07

09

10pF

C07

10

33pF

C07

11

10pF

C07

12

33pF

C07

08

33pF

C07

07

10pF

C0713

10pF

C0714

33pF

C0715

4.7μF

D07

03

PESD5V0S1BL

D07

04

R0703 0R

R-0805

1

2

3

45

J0702

C07

16

10pF

C07

17

33pF

D07

05E

SD

9X5.

0ST5

G

R0702 NM_0R

R0701 0R

R0704 0R

R0705 NM_0R

D07

06P

ES

D5V

0S1B

L

C07

18

10pF

C07

19

33pF

D07

07P

ES

D5V

0S1B

L

C07

20

10pF

C07

21

33pF

F0701 0R

F0702 0R

F0704 0RF0703 0R[7,8] SPK_P

[7,8,9] MIC_P[7,8,9] MIC_N

[7,8,9] MIC_N

[7,8] SPK_N

[7,8] SPK_R

[7,8] SPK_L[7,8,9] MIC_P

[7,8,9]MIC_P


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DATE 2019/12/5

EG21-G

A2

Reference Design

RF and GNSS Designs

Main Antenna Circuit Diversity Antenna Circuit

GNSS Antenna Circuit

Notes:1. It is recommended to use PI type main/Rx-diversity antenna circuit, thus ensuring convenient subsequent debugging.2. The diversity reception function is ON by default. If diversity antenna is not used, there is a need to use AT command to turn off diversity reception. For more details of the AT command, please refer to

3. If an active antenna is selected for the GNSS antenna, a VDD power supply circuit is required; if a passive antenna is selected, the power supply circuit does not needs to be mounted.

Active Antenna

4. The impedance of the RF signal traces must be controlled as 50Ω when routing.

Passive Antenna

The power supply VDD of GNSS needs to be selected according to the requirements of the active antenna.


C0801NM

R0801 0R

J0801

C0802NM C0803

NM

R0802 0R

J0802

C0804

NM

L801

47nH

C805

0.1μF

R80310R

C808 100pF

J804

C810NM

C809NM

R0805 0R

[3]ANT_MAIN [3]ANT_DIV

[3]ANT_GNSS

VDD


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EG21-G

A2

Reference Design

To minimize crosstalk, the reset trace must be at least 20mil

R916 should be placed close to AR8033.

The traces of the resistor must be away from other

and the trace width needs to be at least 25mil.

EMI filter is reserved. If LED pins are not used, please keep C0920/C0923/C0924=470pF.

SGMII_MDIO_DAT should be connected to the USIM2_VDD

MODE 2

MODE 1

MODE 0

MODE 3

Ethernet PHY Design

PH

Y_A

D2

PHY_AD1PHY_AD0

traces (especially the clock and MDI interface traces),

The two capacitors should be selected according to the actualload capacitance of crystal and the board-level test results.

Close to AR8033

Notes:1. In the following description, the SGMII data signal refers to the SGMII TX and RX differencial pair, and the SGMII control signal refers to the SGMII_MDIO_CLK, SGMII_MDIO_DATA, EPHY_RST_N and EPHY_INT_N.

3. Keep the maximum trace length of SGMII data signal less than 10 inches and keep the length difference between TX and RX signals less than 20mil.4. The differential impedance of SGMII data signal is 100Ω±10%, and the reference ground of the area should be complete.

EXT_INT_SEL

5. Make sure the trace spacing between SGMII RX and TX signals is at least 3 times of the trace width, and is the same to the adjacent signal traces.6. Module and AR8033 are recommended to be designed on the same PCB. The peripheral circuit layout of Ethernet PHY chip AR8033 should be designed on a

7. RJ45, network transformer, AR8033, and the SGMII interface should be placed as close as possible.

beside the module with a 1.5kΩ pull-up resistor.

away from other signal traces.

L0901, C0913 and C0914 need to be placed close to Pin 3.

2. SGMII data and control signals should be strictly surrounded with ground and kept away from RF, analog, clock and DC-DC signals etc.

four-layer PCB, and the second layer should be total grounded as the AR8033 reference GND.

1 MDC2 RSTN3 LX4 VDD335 INT6 XTLO7 XTLI8 AVDDL9 RBIAS

10 VDDH_REG11 TRXP012 TRXN0

13A

VD

DL

14TR

XP

115

TRX

N1

16A

VD

D33

17TR

XP

218

TRX

N2

19A

VD

DL

20TR

XP

321

TRX

N3

22N

C23

LED

_AC

T24

LED

_100

0 25CLK_25M

26LED_10_100

27RXD3

28RXD2

29VDDIO_REG

30RXD1

31RXD0

32RX_DV

33RX_CLK

34TX_EN

35GTX_CLK

36TXD0

37TX

D1

38TX

D2

39TX

D3

40W

OL_

INT

41S

D42

SO

N43

SO

P44

AV

DD

L45

SIN

46S

IP47

DV

DD

L48

MD

IO49

GN

D

U901AR8033-AL1B-R

R903NM_100K

C910 NM_1μF

R916

2.37K 1%

R908 10K

R906 NM_10K

C921

0.1μF

C9250.1μF

C92

60.

1μF

C911

10μF

C927

1μF

C928

0.1μF

FB902

BLM15AX700SN1D

C922

1μF

C916

0.1μF

C915

100pF

1XTAL

2 GND 3XTAL

4 GND

Y901

25MHz C917

10pF

C918

10pF

C924 NM/470pF

C923 NM/470pF

C919

NM

C920

NM/470pF

D901

GREEN

R915 510R

R901 0R

C908 0.1μFC909 0.1μF

R904 0R

R907 0R

+C904

100μF

C902

33pF

C901

10pF

C903

100nF

C912

0.1μF

FB901

BLM15AX700SN1D

R905 NM_10K

L9014.7μH

C913

10μF

C914

0.1μF

C905

0.1μF

R914 10K

R909 10K

R913 10K

R910 10KR911 10KR912 10K

R917 10KR918 10K

R9021.5K

C906

2.2μF

C907

0.1μF

[3] EPHY_RST_N

[3] EPHY_INT_N

AV

DD

_1V

1

[11]VDD33_SGMII

[3]SGMII_TX_M[3]SGMII_RX_P[3]SGMII_RX_M

[3]SGMII_TX_P

[11] VDD33_SGMII

[11] VDDH_2V5[12] TRXP0[12] TRXN0

[12]TRXP1

[12]TRXN1

[12]TRXP2

[12]TRXN2[12]TRXP3[12]TRXN3

[12]LED_ACT[12]LED_1000

[3] SGMII_MDIO_DATA[3] SGMII_MDIO_CLK

[11] VDD33_SGMII

CLK_25M

[11] VDD33_SGMII [5,13]VDD3V3

[3,4,5,6,13,14] VDD_EXT

[11]

VD

DH

_2V

5

[11]AVDD_1V1

[11] DVDD_1V1

[11]DVDD_1V1

[11] AVDD_1V1

[11]VDDH_2V5

[3]

US

IM2_

VD

D

AV

DD

_1V

1

[11]AVDD_1V1

[11] AVDD_1V1

An external 10kΩ pull-down resistor is required.

Application external

0 = Pull-down, 1 = Pull-up.

Mode select bit 0

Mode select bit 1

Mode select bit 2

Mode select bit 3

weak pull-up/down

01

1

0

0

0

0

0

0

0

0

0

0

0

0

configuration signal weak pull-up/down

EXT_INT_SEL

MODE 0

MODE 1

MODE 2

MODE 3

PHY_AD0

PHY_AD1

PHY_AD2

PHY core

1

Default internal

The upper two bits of the physical address are set to 00.PHY_AD[2:0] set the lower three bits of the physical address.

Description

12


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EG21-G

A2

Reference Design

Ethernet Network Port Design

Notes:1. Route MDI differential signals with 100Ω±10%, and the reference ground of the area should be complete.2. Keep skew of the MDI differential signals less than 20mil, and the maximum trace length must be less than10 inches.3. The connection method between MDI interface differential line and RJ45 line is 1/2, 3/6, 4/5 and 7/8.4. To minimize crosstalk, the distance between separate adjacent pairs that are on the same layer must be equal to or larger than 40mil.

1 TCT12 TD1+3 TD1-4 TCT25 TD2+6 TD2-7 TCT38 TD3+9 TD3-

10 TCT411 TD4+12 TD4- 13MX4-

14MX4+

15MCT4

16MX3-

17MX3+

18MCT3

19MX2-

20MX2+

21MCT2

22MX1-

23MX1+

24MCT1

U1001

FC3004

C10

03

0.1uF

C10

04

0.1uFC

1005

0.1uF

C10

06

0.1uF

1 TA+

14H

213

H1

3 TB+

5 TC-

7 TD+

2 TA-

4 TC+

6 TB-

8 TD-

9G-10G+

11Y-

12Y+

J1001

FC601-56-LED

R1001 75R 1%

R1003 75R 1%

R1004 75R 1%

R1006 75R 1%

C1001 NM_1000pF/2KV

C1002

1000pF/2KV

R1002 510R

R1007 510RR1005 0R

[11]LED_ACT

[11]LED_1000

[11] TRXP0[11]TRXN0

[11]TRXP1[11]TRXN1

[11]TRXP2[11] TRXN2

[11] TRXP3[11] TRXN3

13

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A2

Reference Design

SD Card Interface Design

6. Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals, etc, as well as noisy signals such as clock and DC-DC signals, etc.

3. To avoid the jitter of bus, resistors R1204～R1208 are needed to pull up SDIO to VDD_SDIO.

4. In order to adjust signal quality, it is recommended to add 0Ω resistors R1209～R1214 in series between the module and the SD card connector.

9. Make sure the adjacent trace spacing is two times of the trace width and the bus capacitance is less than 15pF.

5. It is recommended to add ESD protection devices near the pins of SD card connector. The parasitic capacitance of ESD protection devices should be smaller than 15pF.

2. The supply voltage range of VDD for SD card is 2.7V～3.6V and sufficient current up to 0.8A needs to be provided.1. The pin 34 (VDD_SDIO) on the module can only be used for SDIO pull-up resistors and its maximum output current is 50mA.Notes:

The bypass capacitors C1206～C1211 are reserved and not mounted by default.

The value of these resistors is between 10kΩ～100kΩ and the recommended value is 100kΩ.

7. Route SDIO signals with 50Ω±10% impedance. It is important to route SDIO signals with total grounding, and the total trace length should be less than 23mm.8. It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm.

C1203

100nF

R1209 0R

R1210 0R

R1212 0R

R1213 0R

R1214 0R

R1215120K

D1207

ESD9X3.3ST5G

R12161K

CMD

DATA3

DATA2

DATA0

DATA1

VSS

VDD

CLK

DETECT

J1201

SD card connector

C1206

NM

C1207

NM

C1208

NM

C1209

NM

C1210

NM

C1211

NM

R1204100K

R1205100K

R1206100K

R1207100K

R1208100K

R1211 0R

D1201

ESD9L5.0ST5G

D1202 D1203 D1204 D1205 D1206

R1202

10K

G

S D

Q1201

SI2333C1201

100nF

R1203100K

Q1202

DTC043ZE

R1201 0R

C1204

33pF

C1205

10pF

+

C1202

100uF

VDD_EXT

[3]SD2_INS_DET

[4] SD_PWR_EN

[3] SD2_CLK

[3] SD2_CMD

[3] SD2_DATA3

[3] SD2_DATA2

[3] SD2_DATA1

[3] SD2_DATA0

[3] VDD_SDIO

[5,11] VDD3V3

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EG21-G

A2

Reference Design

Reserved Test Points

1. Test points for both USB and debug UART interfaces are reserved for software debugging.2. Test points for USB interface also can be reserved for firmware upgrade.

Indicators

2. For more details about NET_MODE and NET_STATUS, please refer to

Notes:1. The STATUS is an open drain output pin, and its drive current is less than 1mA.

Other Designs

3. Junction capacitance of ESD protection devices on USB data lines should be less than 2pF.

Notes:

3. If the current consumption is required as low as possible when the device is in sleep, replace the power supply of indicators with controllable one.

4. The module's debug UART interface supports 1.8V power domain,

Turn off the power when the module enters sleep mode.

1. It is recommended to reserve USB_BOOT design.Notes:

2. USB_BOOT is kept open by default.When it is at high level, the module will enter download mode.

A level translator should be used if the power domain of customers' application is 3.3V.


USB_BOOT Interface

D1307

SD12

D1306

ES

D9L

5.0S

T5G

D1305

ES

D9L

5.0S

T5G

D1309

ES

D9X

3.3S

T5G

D1310

ES

D9X

3.3S

T5G

Q1303

DTC043ZEBTL

R1304

2.2K

D1302

Q1302

DTC043ZEBTL

R13032.2K

D1301

D1311

ES

D9X

3.3S

T5G

1 2

J1301

R1306 4.7K

D1304

ESD9X3.3ST5G

4

5

6

3

2

1

7

8

9

J1302

Connector

R13072.2K

D1312

[3,5,14]VBAT

[3,4]PWRKEY

[3]USB_DP_TEST

[3]USB_DM_TEST

[3,4]USB_VBUS

[3]DBG_RXD

[3]DBG_TXD

[3] NET_STATUS

DC_5V

[3] NET_MODE

DC_5V

[3,4,5,6,11,13] VDD_EXT [3]USB_BOOT

DBG_TXD_FC20

[3] STATUS

VBAT

EG21-G Reference Design - AURORA EVERNET

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