EFFECT OF PARAMETER OPTIMIZATION

EFFORT OVER MOSFET MODELS'

PERFORMANCES IN ANALOG CIRCUITS'

SIMULATION

Deepak Balodi 1, Chumki Saha2 and P. A. Govidacharyulu3 SMIEEE ISchool of Physics, University of Hyderabad, Hyderabad, India, deepakbalodi@gmail.com

2Semi-Conductor Laboratory (S.C.L.), Department of Space, Government of India, S.A.S. Nagar, India 3Vasavi College of Engineering, Hyderabad, India, pagovindacharyulu@yahoo.com

Abstract- The importances of MOSFET parameter extraction

process along with the requirements for good optimization strategy to obtain better modeling results are discussed. Scope

for achieving the flexibilities in parameter extraction process and strategy formation has also been discussed with the example of BSIM MOSFET model in 0.8 p.m CMOS technology and it is argued that with the poor extraction strategy, even the more

powerful BSIM3 (Level-49) model produces the comparable

results to that of BSIM (Level-I3) model. Finally the BSIM (Level-I3 and Level-49) modeling efforts for various geometry devices are shown in comparative manner which are followed by qualitative analysis to conclude the important aspects of these

models with optimization effects.

Keywords-BSIM, CAD, SPICE, Parameters' Extraction Strategy, Subthreshold Region, Model Binning.

I. INTRODUCTION

With the increasing need of high performance ANALOG INTEGRA TED CIRCUITS in each respect of speed, power, package density, integrity and compatibility, more stringent requirement of performance aspects are regularly being kept over the device and circuit level modeling efforts. Complementary Metal Oxide Semiconductor (CMOS) technology has been the leading IC Technology for past several years and its development has spurred the continuing evolution of computer aided design (CAD) technology for Integrated Circuit simulation. To simulate a CMOS integrated circuit, SPICE must make use of element models of the field effect transistor (FET); these FET models provide a description of how a transistor will behave in the designed circuit. Thus, the FET models, with their parameters listed, serve as the connection between the designed circuit and the underlying fabrication technology.

Parameter extraction has been an extensive process for the validation of a MOSFET model via modeling the various characteristics of different geometry devices. It does not aim

only to provide a best fit to the actual device data obtaining a list of parameter values, but also those values must be consistent and compatible with the process technology and device physics concepts behind those models's development. Thus the well optimized strategy formulation behind the extraction process is the key factor of obtaining the best values set for a particular model. A strategy formation should be always based on the physical phenomenon in devices and empirical mathematics behind models.

II. SCOPE FOR VARIOUS STRATEGIES'

FORMATION

According to the present technology and application of models and devices, the flexibility in parameter optimization can be achieved in various ways listed below.

1. Using more or less number of devices for fitting the measured data could be a good practice to obtain parameter values in a very efficient fashion. Having more number of devices for the extraction purpose is always beneficial as it produces the parameters' values satisfying a wide range of device geometries for the same technology but definitely it suffers with the modeling accuracy for each particular device compare to the strategy having lesser number of devices used.

2. Using same number of devices but selecting well optimized set of device geometries provides a better insight into the foregoing application of that model. For e.g. if in most of the applications of that model, the device sizes being used are in well above ranges than the minimum feature length of the technology, then most of the devices centered to upper ranges of the device geometries should be selected for parameter extraction and fitting purpose as then the modeling characteristics will be well matched for those devices while

suffering in accuracy for devices near the minimum feature length.

3. Interchanging, omitting or adding a new step at various extraction levels may be required to obtain a better empirical fit.

4. Selecting a better fitting target parameter helps to achieve a compatible parameter's value, such as in level-49 parameter extraction, to model the seBE (substrate current induced body effect) and DIBL (drain induced barrier lowering) effect in saturation region, gd (output conductance) is more appropriate to be selected as fitting target parameter rather than current Id, because large variations could be obtained which are helpful for a better fit to gd in comparison to Id for that region.

5. By selecting the appropriate ranges of the target fitting parameters. For e.g. using logarithmic scale for Id to fit the parameters in the subthreshold region, so that a wide range of drain current can be obtained for that very small region in linear scale.

III. PARAMETER EXTRACTION

1. Parameter extraction and strategy formation for BSIM (Level-I3) model

In BSIM (level-l3), as in the first generation models, a long and wide device is used to provide some base parameters; corrections are then included to describe short and narrow channel effects. [I ]

In the first phase, a long, wide device is used to determine a few base parameters; these parameters are used as the starting point for each of the individual extractions of the second phase[2]. The parameters needed to obtained with one of the best possible strategies as listed below.

A. Strategy 1

The Devices used in of the well optimized approaches (strategy I) used here are:

One wide-long device: wi (W=20llm, L=20llm) Three wide-short devices: wsl (W=20llm, L=O.8Ilm), ws2

(W=20llm, L=I.Ollm), ws3 (W=20llm, L=I.2llm) Two narrow long devices: nil (W=2Ilm, L=20llm), nl2

(W=3Ilm, L=20llm)

LFitting of VFB, MUZ, and UO with gate characteristics of wide-long device at zero back-bias.

II.Fitting of DL with gate characteristics of wide-short device at zero back-bias.

IILFitting of DW with gate characteristics of narrow-long device at zero back-bias.

IV.Fitting of VFB, MUZ, UO with gate characteristics of wide-long device at zero back-bias.

V.Fitting of VFB, KI, K2 with gate characteristics of wide­long device at all back-bias.

VI.Fitting of PHI with gate characteristics of wide-long device at all back-bias.

In this first phase, there is very less scope for extraction strategy's flexibility but nevertheless the variations in the steps' order and environment settings could be made according to the present technology and applications' r.

Only MUZ (low field channel mobility) has no length and width parameters and is treated as globally meaningful. Hence MUZ is left untouched throughout the rest model construction process and needs to be extracted in the very first step.

DL (Difference between drawn poly and electrical) represents a correction to the linear region slope in the second step, for a short channel device & MUZ gives the slope of the linear region curve for the wide long device with parameter DL assumes that the wide short device has the same mobility MUZ as the wide long device, hence MUZ cannot be extracted simultaneously with the DL in that step.

In the fifth step, the maximum setting for the target Id is reduced, hence this setting avoids higher Vg region where mobility degradation effects are more apparent as this is a crucial requirement for this step.

In the second phase, a BSIM parameter set is extracted independently for each device. In essence, this phase involves the fitting of each individual device to the intrinsic model structure.

• Linear region parameters with gate characteristics at all back bias for all devices (i.e. wide-long, wide-short, narrow­long): KI, K2, UO and X2UO • Saturation region parameters with drain characteristics at zero-back bias for alI devices: MUS, X3MS, ETA and UO • Saturation region parameters with drain characteristics at all-back bias for all devices: X2MS • Subthreshold region parameters with drain characteristics at all-back bias for alI devices: NO, NB, ND

In the third phase, the compiled parameters from the second phase are used to determine the geometry dependent parameters (the L and W parameters). The extrinsic model structure is created on top of the intrinsic structure. This structure contains additional geometry dependence, embodied in the expression [I]:

(\)

B. Strategy 2

Another possible but less optimized strategy with only three devices in the third phase (but in the first and second phase of extraction the same devices and steps are used). The comparative analysis of both the strategies is shown in the Table I. Devices used in the third phase of this extraction strategy

1 wide-long: 1 wide-short: 1 narrow long:

wi (W=20!lm, L=20!lm) wsl (W=20!lm, L=O.8!lm) nil (W=2!lm, L=20!lm)

C. Analysis over Extracted Results

In the second phase steps, with the present strategy, it could be observed that the results show a smooth linear­saturation transition with an accurate and detailed description of the saturation region. However, for the W IL=20/0.8 device, the model has trouble fitting the data near the linear-saturation region. This shows that the BSIM encounters difficulties for submicron channel length.

In the third phase, it is seen that the extracted data points do not describe a straight line. The resulting model is the best linear regression fit. With three data points, in strategy I(from three different channel lengths), the best results are obtained at the extremes of the data (the shortest and the longest device), while the results are quite poor in the middle region. The case is even worse with the strategy 2 as only a single short channel device is used. Of course, more devices could be used; while this would improve the results for the middle region, the accuracy for the shorter devices would suffer.

TABLE I COMAPARITIVE STUDY OF FITTING RESULTS BETWEEN STRATEGY I AND 2 FOR LEVEL-\3 PARAMETERS' EXTRACTION

FITTING RESULTS

FOR DIFFERENT

DEVICES

WIDE-LONG (W�20, L� 20)

USED FOR BOTH

STRATEGIES IN

THE THIRD PHASE

WIDE-SHORT (W�20, L�I)

USED FOR

STRATEGY I BUT NOT FOR

STRATEGY 2 1N

THE THIRD PHASE

NARROW-LONG

USED FOR BOTH

STRATEGIES IN

THE THIRD PHASE

STRATEGY I. HAVING MORENo. OF DEVICES (I WIDE-LONG,3 WIDE­

SHORT, 2 NARROW-LONG) FOR FITTING IN THE THIRD PHASE

DraIn:flnaI nt

8 ,.,crt. ", . . .. r rrTT'TTTTTTnTUlIllrml"I"mn

u. W - Z.uutMlUl;-U:' I .1J1ClIlOOflF ns

8 �: :��)04150.15 O.l O.z5

20' VI1(Vnltl!l)

'" ." , 00

Fig. 1. Id-V d Fitting curves for W /L=20/20 with Strategy I

0.00 1.00

Fi

OraIn: Anal At

2.00 3.00

Vd (Volts)

4.00 5.00

curves for W/L=20/1 with Strate

\Itt (Volts)

Curves for W IL=2/20 with Strate

STRATEGY 2. HAVING LESS No. OF DEVICES (I WIDE-LONG, I WIDE­

SHORT, I NARROW-LONG) FOR FITTING IN THE THIRD PHASE

g PloU,

� W _ Z.OOOOOOE-OS l- Z.OOOOOOE-05 vo. 0 0.05 0. 1 0.150.2 0.25 :s. VG.01234 5

... VB. 0-5

,. Plott Z b Q W'"' Z.OOOOOOE-05 -; c::>: l- Z.OOOOOOE-O �M VO-DO.USa.1 i VG-Ol _g V8-0

:gN

g

g

0.00 1.00

Thursday March 20, 2008 13:21

Drain: Anal At

2.00 3.00 Vel (Volt!!)

4.00 5.00

curves for W/L=20/20 with Strate 2 Drain: Fhlal At

L_l.000000E_06 ��_����:::::::� VO'"' 0 0.05 0.1 0.15 0 VG.01234 5 VB _ 0-5 ""':!! Ploll Z � � �:

lZ

.

.oooo00E

.... VO-

l ��: "g N

� .................... . 0.00 1.00 Z.OO 3.00 4.00 5.00

Vd (Volts)

Thursday ""arch ZO, ZOO8 13:2:1

Fig. S. ld-Vd Fitting curves for W/L=20/20 with Strategy 2

� �.�.�OOOE-06 L. Z.OOOOOOE-05 VD. 0 0.05 0.1 0.15 O.Z O.Z VG_01 Z345

� � ����-5 � �: :::::::_

-006

.... VD_00.050. �� �::

01Z3

"

TIlursday March ZO, ZOO6 1321 VII (Volts)

Fig. 6. Id-Vd Fitting curves for W/L=2/20 with Strategy 2

2. Parameter extraction and strategy formation for

BSIM3v3(Level-49) model

BSIM3v3 does not have the twofold model structure as in BSIM 1 model; hence the complete extraction strategy is performed in a single continuous phase like the first generation models.

One of the good strategies for level-49 is as follows (Table 2):

1. The oxide thickness (TOX), along with the difference between the drawn and effective channel dimensions are provided as process input.

2. A base set of parameters is extracted from a long, wide FET. 3. Parameters describing the behavior of short and narrow devices at low drain bias are extracted. 4. Parameters describing the effect of the substrate bias at low drain bias are extracted. 5. Parameters related to high drain bias operation are extracted. 6. The subthreshold parameter is extracted. 7. If available, the temperature dependent parameter is extracted.

TABLE 2 LEVEL-49 PARAMETERS EXTRACTION STEPS WITH ONE OF THE GOOD OPTIMIZED STRATEGY

1'1 step: fit for VTHO, UO, UA, UB Device: wide long: gate characteristics (zero back bias)

3'd step: fit for VTHO, UA, UB, ow Device: narrow long: gate characteristics (zero back bias) 51h step: fit for VTHO, K 1, K2 Device: wide long: gate characteristics (all back bias)

7lhstep: fit for LINT, RDSW, PRWG, PRWB, DVTO, DVT2, NLX Device: Wide-all lengths: gate characteristics (all back bias)

91h step: fit for VSAT, AO Device: wide long: drain characteristics (zero back bias)

I Ilh step (repeating Sih step) : fit for WINT, K3, WO, K3B, DWG, DWB Device: All narrow-long: gate characteristics (all back bias)

(3lh step (repeating Sih step): fit for PCLM, PDIBLCI, PDIBLC2, DROUT) Device: Wide-all lengths (except wide long): drain characteristics (zero back bias)This optimization step takes account of the DIBL(drain induced barrier lowering) effects.

151h step : fit for PSCBE I, PSCBE2 Device: Wide-all lengths (except wide long): drain characteristics (zero back bias)This optimization step takes account of the SCBE(substrate current induced body effect) effects

vd (Vtllts) MonIlayMarchI7.Z1J08 12:11

Fig. 7. Gd Fitting Curves for W/L=2010.S (Level-49)

171h step : fit for ETAO, ETAB, DSUB Device: Wide-all lengths (except wide long): gate characteristics-high drain bias (all back bias)

• Analysis over Extracted Results for Level-49

L...ilim: fit for VTHO, UA, UB, DL Device: wide short: gate characteristics (zero back bias)

41h step: fit for VTHO, UA, UB, UO Device: wide long: gate characteristics (zero back bias)

61h step: fit for Kl, K2, UA, UB, UC Device: wide long: gate characteristics (all back bias)

Sih step: fit for WINT, K3, WO, K3B, DWG, DWB Device: All narrow-long: gate characteristics (all back bias)

lO' step (repeating 71 step) : fit for LINT, RDSW, PRWG, PRWB, DVTO, DVT2, NLX Device: Wide-all len ths: ate characteristics (all back bias)

Ith step: fit for VSAT, PCLM Device: Wide-all lengths (except wide long): drain characteristics (zero back bias).This optimization step takes account of the CLM(channel length modulation) effects.

141 step (repeating step (31 ): fit for PCLM, PDIBLCI, PDIBLC2, DROUT) by targeting Gd instead of Id. Device: Wide-all lengths (except wide long): drain characteristics (zero back bias)

161h step : fit for NF ACTOR, VOFF Device: Wide-all lengths (except wide long): gate-subthreshold characteristics (zero back bias) This performs the optimization for the parameters with subthreshold related characteristics.

CI.oo 1.00 2.DD l.llO ... .00 5.110 VV(Vulb)

Fig. S. Log Id-Vg Fitting Curves for W/L=20/I. 2 (Level-49) in Subthreshold Re ion

� : fit forKETA Device: Wide-all lengths (except wide long): drain characteristics (all back bias)

The BSIM3v3 (Level-49) parameters optImization process defines the transition region of subthreshold-superthreshold

very accurately, hence chances of eXlstmg discontinuity reduces very much. A huge effort has been put on the saturation region Gds (output conductance) fitting, which is a unique feature of this model.

In the present extraction procedure, the output conductance fitting at SCBE effect region has been deteriorated (especially for the wide short devices), which could make a serious impact on the final model playback for this region shown later.

IV. EXTRACTION STRATEGY' S POTENTIAL ANALYSIS OVER BSIM (LEVEL-13) AND BSIM-

3V3 (LEVEL-49) MODELS

A.Test-l: Triode Saturation (Output) and Gate (linear) Characteristics

A good model will show smooth transitions from below to above threshold, with no kinks, glitches or discontinuities. A discontinuity in the small-signal quantity is translated into the kink problem in the drain current.

a 6.DIlE-a:! E � 9 5.DIlE-aJ

Measured Data 0000 Level - 13 Level-49

1 df§in vo;tage'VD(v��s) J.'

Fig. 9. Modeled Id-Vd Characteristic for W/L=2010.8

Measured Data 0000 Level -13

gate voltage Vg(vols)

Fig. 10. Modeled Id-Vg Characteristic for W/L=2010.8

During level-49 parameter extraction procedure, the fit was not good enough for wsI(W=20, L=O.8) device particularly over saturation region (describing DIBL and SCBE effect),

hence a very important subsequence can be seen in the modeling results as the device modeled characteristic does not match well over the same regions with actual one.

Though both the modeled results from level- 13 and level-49 are almost comparable, the results particularly for level-49 are not good enough as were expected according to its capability. This shows the effect of poor optimization effort and puts more stringent requirement over the development of a better strategy for a particular model.

a : UiIJ&m "

§ C UJJE-m �

Measured Data 0000 Level -13 Level-49

gale YOltage VI3(YOKs)

Fig. 11. Modeled Id-Vg Characteristic for W/L=2/0.8

Though the minimum feature length and width devices are rarely used in circuit design, the above results for device W /L=2/0.8 explains the effect of poor selection of device geometries for the parameter extraction purposes as the Id-Vg characteristic (Fig. 1 1) is badely modeled, but defenitily level-49 shows its better modeling capabilities by having a generalized model structure and hence takes care for a wide geometry range of the devices.

B. Test-2: Tsividis-Suyama Test Characteristics for

Transconductance (Gm) [3]

Cl .Q

---. -. -,"

Vb=Ov

gate -.oltage VG(volts)

Fig. 12. Modeled gm Characteristic for W/L=20/20

The overall results for all the devices clearly explains the kink problems with level-I3 as the transconductance (Gm) has a severe discontinuity at the threshold transition region, whereas the modeled results for level-49 are very smooth and

continuous over the complete range; this manifestation has been achieved by the use of smoothing functions modeled in drain current equations of level-49. Again the survival of level-49 modeling results with level-I3 could be seen much clearly for the device W IL=2010.8.

gate voltage Vg (vols)

. .. ... .. ....

Measured Data 0000 Level - 1 3 Level-49

Fig. 13. Modeled gm Characteristic for Level-I 3 and Level-49 for W/ L=2010. 8

D. Test-5: Tsividis-Suyama Test Characteristics for Output

Conductance (Gds) [3]

Measured Data 0000 Ldel-13

'1 Level-49

drain valta;e 'VO(vllltl!;)

Fig. 14. Modeled gd C characteristic for Level-\3 and Level-49 for W/ L=20/20

Meaiured Data 0000 Level �-13

"

Vg=4v

Vg='N

drainvo.age VO(votIS)

Fig. 15. Modeled gd Characteristic for Level-13 and Level-49 for W I L=2010. 8

Again the kink problems with level-I3 in the drain­conductance (Gds) could be observed in comparison to level-49 which is very smooth and continuous, though the complete results are not good for level-49 also, the capability of smoothening the transition regions must be appreciated.

v . ANALYSIS OF RESULTS OVER MODELS

ASPECTS

Model binning [1] is a very helpful technique when one needs to optimize the parameters very accurately as well as for a wide range of device geometries; but an extreme caution is required selecting the devices' geometry boundaries so that each parameter set fits well within its specified geometry range.

The type of circuit and its final application also influences the selection choice between models as DIGITAL and ANALOG applications have their different scopes and requirements. Hence parameter extraction process may also get influenced due to the device number size selection for the extraction purpose.

One particular interest of analog circuit design is the

accurate fit of the small signal parameters such as gm, gds and

gmb, whereas for digital application only drive current is the

main parameter. The relaxed requirement of accuracy in

fitting the device J-V characteristics allows the digital model

to be fairly crude and obviously the simulation time will be

less.

VII. CONCLUSIONS

Parameter extraction plays a very important role in formulation of a model structure and its modeling capabilities. Hence one must be very cautious while extracting the parameters and choosing number of the target devices as well as their specific geometries.

In a generalized view, level-49 always gives a better performance in respect of accuracy, mathematical conditioning, circuit simulation and parameters' physical impact. But selecting a better model is not only sufficient to obtain well matched device characteristics, as we have seen that the selection of a good parameter optimization technique is also very important. With a poor set of optimized parameters, even a better model also behaves as a poor model.

REFERENCES

[I] Daniel Foty, "MOSFET Modeling with SPICE, Principles and Practice," Prentice Hall PTR. [2] AURORA-SYNOPSYS Parameter Extracter Mannul. [3] Yannis P. Tsividis and Ken Suyama, "MOSFET modeling for analog circuit CAD: Problems and Prospects," JEEEjournal ofSOLJD-STATE circuit, vol. 29, No. 3, March 1994. [4] Y. Tsividis, "Operations and Modeling of MOS transistor," 2nd edition Oxford, U.K. Oxford University Press 2003. [5] AVANT-Star HSPICE manual, Volume 111- MOSFET models, Release 1999. 2, June 1999 [6] Henok Abebe, Vance C. Tyree, "BSIM3v3. 1 Model, Parameters­Extraction and Optimization," October' 2007, The MOSIS Service- USC-lSI