Design & Verification Languages and Methodologies in HSE ...

Design & Verification Languages and Methodologies in HSE-RP-IL

Katharina Ceesay-Seitz,

Hamza Boukabache

on behalf of HSE-RP

28/04/2022

28/04/2022 Design & Verification Languages and Methodologies in HSE-RP-IL 2

HSE-RP-IL: Some of our designs

Atto to miCro CoURAnt meTEr -ACCURATE 2 Mixed signal ASIC

CERN RadiatiOn Monitoring Electronics - CROME

S. K. Mohanan, H. Boukabache, V.Cruchet, D. Perrin, S.Roesler, and U. Pfeiffer, “An Ultra

Low Current Measurement Mixed-Signal ASIC for Radiation Monitoring Using Ionisation

Chambers”, (IEEE sensors)

Prototype for new read-out

front end for CROME

Analog/Digital Mixed signal

ASIC for measuring ultra-low

current

Design Language: VHDL

Simulation test benches: VHDL

Formal Verification: SystemVerilog Assertions

Ceesay-Seitz, K., Kundumattathil Mohanan, S. Boukabache, H., Perrin, D.:

Formal Property Verification of the Digital Section of an Ultra-Low Current Digitizer ASIC.

Proceedings of Design and Verification Conference and Exhibition Europe, DVCon Europe, Munich (2021)https://crome.web.cern.ch/

Based on

Xilinx Zynq 7000 System-on-Chip

Application software: C

Remote testing: C, Python

Operating system: Linux

Design Language: VHDL, Verilog

Designer test benches: VHDL, SystemVerilog

Cosimulation: QEMU, UVM, C

Functional Verification:

Simulation: SystemVerilog UVM, C/C++/Python

Formal Verification: SystemVerilog Assertions


Our Functional Verification Methodology

Ceesay-Seitz, K., Boukabache, H., Perrin, D.:

A Functional Verification Methodology for Highly Parametrizable, Continuously Operating Safety-Critical

FPGA Designs: Applied to the CERN RadiatiOn Monitoring Electronics (CROME).

In: Proceedings of Computer Safety, Reliability, and Security - 39th International Conference (2020)

Designer Test

Benches**

VHDL Design**

Simulation - Universal Verification Methodology (UVM)

Language: SystemVerilog (SV) – IEEE Standard 1800 - 2017

UMV is IEEE Standard 1800.2 – 2020

+ Built on industry best-practices, widely used in industry

+ Object-oriented SV Library

+ Agnostic to DUT’s HDL

+ SV: constrained random stimulus generation, functional coverage

+ SV: simulator independent interface (DPI) to connect with C/C++ (Python), …

- SV is not yet widely supported by open-source tools

- Mixed-language simulation (with a VHDL DUT) requires specific license

- Time consuming to get started (learning curve, test bench setup)


Is used in HSE-RP-IL for verifying the CERN RadiatiOn Monitoring Electronics (CROME).

uvm-python is under

development

https://uvm-python.

readthedocs.io/en/latest/


DUVDesign under Verification

(VHDL)

UVM Test (SystemVerilog = SV)

UVM Environment

Test

Configuration

Object Log FilesUVM Sequences: generate constrained-random transactions

UVM Active Agent

UVM Scoreboard

UVM Sequencer

UVM Driver

UVM Input

Monitor

Reference Model Wrapper

(SV)

Coverage Collector

Properties

Virtual Interface

(SV)

UVM Passive Agent

UVM Output

Monitor

UVM

Transaction

Output comparison

TEST RESULTSReference

Model

(C)

DPI Interface

(SV)

Function

calls

Signals

UVM Top module (SV)

Interface (SV)

DUV Instantiation

Test entry function

COVERAGE DATA

Simulation – Open Source VHDL Verification Methodology (OSVVM)

Language: VHDL – IEEE Standard 1076

+ If design language is VHDL, no need to learn a new language

+ No additional licences needed

- Less flexible than SystemVerilog:

- No constraints solving

- Built-in coverage only for value ranges (no transitions, conditions, …)

- Interfacing with reference model in C, … requires simulator specific solutions

- Has only 1 contributor on github (ALDEC owner)

Was used in HSE-RP-IL for verifying a floating point core of the CERN RadiatiOnMonitoring Electronics (CROME).


Simulation – Libraries for directed testing

UVVM – Universal VHDL Verification Methodology

VUnit

CocoTB (Python)

We have not used them so far.



Goal: Model checkers mathematically prove properties of design+ Exhaustive proofs for all verification scenarios

(within chosen constraints)+ Quick generation of counter examples (usually corner cases)+ No test cases/bench, can get started quickly- State space explosion (depending on size of data inputs and

sequential depth)

Language: SystemVerilog Assertions+ Very expressive (LTL and sequential regular expressions)+ Same code usable in formal tool & simulation- Expensive licenses for commercial tools necessary, so far only few

open source options (e.g. SymbiYosys)

Formal Property Verification with SystemVerilog Assertions (SVA)


Formal Property Verification – Model Checking

VHDL / Verilog /

SystemVerilog

Design

Model

Checking

Tool

Formal

Properties

(SVA, PSL)

Proof reportCounterexample

Waveform

Commercial tools:

• Cadence Jasper Gold

• Siemens

Questa Formal

• Synopsis VC Formal

• …

Open-source tools:

• SymbiYosys,

• EBMC, …

by verification engineer


Full System Simulation with QEMU and RTL

Simulator

4/26/2

022

Processing

System

Programmable

Logic

Embedded Userspace

AppSoftwa

reWatc

hdogHardwar

e

Process

Supervi

sion

Process

IP-Network

ROMULUS-

Protocol

TCP

AXI-

BUS

(BRAM)

Linux-Kernel

UserspaceEmbedded

Userspace

App

Emulated Hardware Devices

GPIO BRAM Interrupt-Controller

QUESTA RTL-Simulator

Simulation Top-Level

PL VHDL-Code

ADC

IVC

Temp

HW-Model

Zynq-7000 PS Wrapper

Remote-Port (TLM)

Control

Calculation

...

UVM Testbench

generate stimuli

monitor interface

receive results

generate stimuli

J. Bodingbauer’s presentation at:

https://indico.cern.ch/event/1090205/

Training attended by different members of HSE-RP-IL over the past 4 years


Training: Comprehensive Digital IC Implementation & Sign-Off by Europractice

• Length: 5 days

• Location: UK

• Rating of necessary previous experience for attending: HDL knowledge

• Quality of content: very good

• Amount of content: fine

• Practical exercises? Yes

• Were they useful? Extremely

• Would you recommend the training? YES

• Our impression about the training: Gives you good idea to learn digital ASIC design. The provided scripts gives a kickstart to make your own for any technology nodes.

• Advantage: Europractice trainings are relatively cheap compared to industry trainings


Training: Expert VHDL for FPGA Design by Doulos

• Length: 5 days

• Location: CERN

• Rating of necessary previous experience for attending: working knowledge of VHDL

• Quality of content: good, but we had different expectations about content

• Amount of content: too many different topics


• Were they useful? somewhat

• Would you recommend the training? NO, unless interested in an overview

• Our impression about the training: Big focus on design & verification methodologies. From the title we expected more background on synthesis, optimizations, … There were several short exercises for UVM, OSVVM, UVVM. Training was fine to get an overview, but not for in-depth knowledge gain.


Training: UVM Adopter Class by Doulos

• Length: 5 days

• Location: UK

• Rating of necessary previous experience for attending: SystemVerilog knowledge was necessary, OOP knowledge helpful




• Were they useful? Yes

• Would you recommend the training ? YES

• Our impression about the training: Very comprehensive. Started with the basics of UVM and moved on to advanced topics in a very understandable way. Examples were useful and could serve as base for your own testbench.


Training: Essential formal verification by Doulos

• Length: 3 days, self-paced

• Location: Online

• Rating of necessary previous experience for attending: RTL and SVA basics






• Our impression about the training: Provides a jump start to Formal verification. Very useful for designers too.


FREE Training: SystemVerilog Assertions by Cadence, through Europractice tool license

• Length: 2 days

• Location: online

• Rating of necessary previous experience for attending: 0






• Your impression about the training: Great to get started with formal verification and learn the Syntax of SVA


Training: Advanced course in formal verification methodology by Axiomise

• Length: 2 days

• Location: online (company is located in UK)

• Rating of necessary previous experience for attending: need a good base in formal verification with SystemVerilog Assertions, SVA


• Amount of content: good



• Would you recommend the training? YES, if you are familiar with formal verification.

• Our impression about the training: The exercises were very interesting. Covered new techniques for typical verification problems and for designs that are typically considered as ‘not suitable for formal’.

• Note: Since it consists of many exercises, it is better to be either in a small group (we were only 4) or do it in person.


FREE Training: JasperGold Formal Expert by Cadence, through Europractice tool license

• Length: 2 days, self-paced

• Location: online

• Rating of necessary previous experience for attending: SystemVerilog Assertions knowledge






• Your impression about the training: Great advanced examples and concepts for practical formal verification.


Interesting FREE resources

• https://verificationacademy.com/ (UVM, SystemVerilog, Coverage, SystemVerilog Assertions, very active forum)

• https://cluelogic.com/ (UVM tutorial)

• https://www.chipverify.com/uvm/uvm-tutorial (UVM tutorial)

• https://zipcpu.com/tutorial/formal.html (Formal verification with SystemVerilog and the open source tool SymbiYosys)

• https://blog.verificationgentleman.com/ (Lot’s of useful tips on UVM)

• https://www.axiomise.com/webinars/ (Formal verification)

• https://www.onespin.com/resources/resources-overview (Formal tool vendor, has interesting presentations from conferences)

• With the Europractice program we have access to some online trainings by Cadence, Siemens EDA (and maybe Synopsys as well). You need to be eligible (no open source designs) and sign the license agreement with CERN's Europracticerepresentative, Wojciech Bialas.

• Xilinx training (some are included in our license): https://xilinxprod-catalog.netexam.com/

• Zynq-7000 HW-SW Co-Simulation QEMU-QuestaSim (https://blog.reds.ch/?p=1180) , https://github.com/Xilinx/qemu

• QEMU: https://wiki.qemu.org/Documentation

• QEMU: https://www.qemu.org/docs/master/


https://verificationacademy.com/

https://cluelogic.com/

https://www.chipverify.com/uvm/uvm-tutorial

https://zipcpu.com/tutorial/formal.html

https://blog.verificationgentleman.com/

https://www.axiomise.com/webinars/

https://www.onespin.com/resources/resources-overview

https://mmm.cern.ch/owa/redir.aspx?C=uqcuPam0irYEBVRcdju_Pp2s0BqOIpOZ3B4QNHKKCRAN_1GTCR7aCA..&URL=https%3a%2f%2fxilinxprod-catalog.netexam.com%2f

https://blog.reds.ch/?p=1180

https://github.com/Xilinx/qemu

https://wiki.qemu.org/Documentation

https://www.qemu.org/docs/master/

Conclusion

• Many different methodologies and languages

with their unique advantages

• Trainings

• provide a good base,

• allow fast adoption of new methodologies.

• “Training tomorrow's scientists and engineers and promoting the uptake of careers in STEM is part of CERN’s mission”


https://home.cern/about/what-we-do/train-educate-engage

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