Design Analysis of Optical Loop Memory

JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 27, NO. 21, NOVEMBER 1, 2009 4821

Design Analysis of Optical Loop MemoryRajiv Srivastava, Student Member, IEEE, Student Member, OSA, Rajat Kumar Singh, Member, IEEE, and

Yatindra Nath Singh, Senior Member, IEEE

Abstract—This paper describes the fiber optic loop buffer-basedswitch in which contention is resolved in the time and wavelengthdomain. In the loop buffer, tunable wavelength converters (TWCs)are placed in place of semiconductor optical amplifiers (SOAs) asin conventional loop buffer-based architectures. The placement ofTWCs inside the buffer facilitate simultaneous read/write opera-tion and dynamic re-allocation of wavelengths and improves theswitch performance significantly. It is a well known fact that there-circulating type buffer structure suffers from circulation limit(maximum revolutions that data can take in the buffer) due to theloss and noise accumulation in the switch. This paper presents amathematical model to obtain a maximum number of allowed cir-culations of the data in loop buffer-based switch architecture. Thismodel is derived for various configurations (transparent, noisy, andregenerative) of TWC. The detrimental effect of crosstalk and fourwave mixing are shown, and the affect of dispersion on the max-imum allowed bit rate is discussed. The minimum length of theloop is also evaluated. Finally, the bounded region is shown (bit rateversus number of wavelengths graph) where memory can workefficiently.

Index Terms—FWM, optical loop buffer, tunable wavelengthconverters (TWC).

I. INTRODUCTION

T HE demand for higher bandwidth is ever increasing dueto continuous evolution in the network services. To cater

to this demand, fiber optic and photonic technology can be usedin communication networks. The network structure is composedof core and clients networks. The edge routers act as an interfacebetween clients and core network. These edge routers lie on theperiphery of the core network cloud and are capable of packetaggregation. The motivation to build the optical packet switch iswhen ingress routers (edge routers) aggregate the large numberof packets optically for a very high bit rate payload and a low bitrate header can be attached to aggregated data and pushed intocore network. The switch in the core network will convert theheader of the packet in electronic domain and keep the payloadin optical form. The information stored in the header is used toroute the packet. As packet reaches the egress node (edge routerwhere traffic exists the core network), the aggregated packetscan be separated out optically and passed onto the client net-work. Ideally, all optical switching in core network will requireoptical implementation of all the switch functions. The control

Manuscript received September 05, 2008; revised June 07, 2009. First pub-lished June 30, 2009; current version published September 10, 2009.

R. Srivastava and Y. N. Singh are with the Indian Institute of Technology,Kanpur, India (e-mail: rajivs@ iitk.ac.in; ynsingh@ iitk.ac.in).

R. K. Singh is with the Indian Institute of Information Technology, Allahabed,India (e-mail: rajat.singh@ gmail.com).

Digital Object Identifier 10.1109/JLT.2009.2026493

and processing logic implementations in optical domain are nottechnically feasible. Therefore, most of the optical switch archi-tectures are hybrid in nature, where buffering and switching ofpackets is done in optical domain while control is done by elec-tronics. The important functions of photonic packet switching[1] are control, packet routing, packet synchronization, clockrecovery, contention resolution, buffering and packet header re-placement. This paper investigate the aspects of buffering. In theoptical packet switching, buffering will be required when two ormore packets arrive for the same destination in same time slot.Then except one all other packets have to be stored. Until now,all optical memory for photonic packet switching has not beendeveloped. However, as an alternative fiber delay lines in trav-eling or recirculating configuration are used [2]. This bufferingis made possible by incorporating components such as opticalgate switches, optical couplers, optical amplifiers and wave-length converters.

In the past two decade, extensive research has been done onthe implementation of the optical packet switch architectures[3]–[7]. The main limitation in these architectures is the splittingloss of the signal that is compensated by the optical amplifier.The amplifier increases the buffering time of the signal, but thiscannot be arbitrarily large as it is also limited by the ASE noiseaccumulation of the amplifier. In these architectures [3]–[7],this limit is not considered, which is an important parameter inswitch design. A comparative analysis of these switches is per-formed in [8] where it was found that switch architecture con-sidered in this paper performs better than other compared archi-tectures. Generally the performance of the switches is measuredin terms of packet loss probability and average delay; these pa-rameters can only provide behavior of the switch at the networklayer. But parameters related to physical layer have not been dis-cussed which also plays an important role in the performanceof the switch architectures. In this paper, impact of physicallayer parameters is investigated on the switch and a mathemat-ical model is developed to obtain maximum number of allowedcirculation of the data in the buffer. In this model three con-figurations (transparent, noisy and regenerative) of TWC havebeen considered. The detrimental effect of four wave mixing(FWM) and components crosstalk are also shown, and limita-tions in terms of buffering capability are also discussed. Finally,bounded region is shown in which memory can work efficiently.The paper is organized as follows. In Section II, related workand description of the switch is given. Physical layer constraintsare discussed in Section III. Analysis of switch is presented inSection IV. The suggested design analysis is presented in Sec-tion V of the paper. The conclusions of the paper are discussedin Section VI.

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4822 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 27, NO. 21, NOVEMBER 1, 2009

Fig. 1. Description of architecture A1.

II. RELATED WORK AND ARCHITECTURE DESCRIPTION

In general, the optical switch with multiwavelength fiber loopas memory element has a very simplified structure and it usessingle fiber delay line for the storage of the packets on differentwavelengths. Packets from all the inputs use WDM technologyto share the loop buffer [1]. The number of buffer wavelengths(size of memory) depend on the desired traffic throughput,packet loss probability, various component parameters and sizeof the switch [9]. The first loop buffer based optical packetswitch (OPS) architecture as shown in Fig. 1 was proposed byBendelli [5] and later on modifications are suggested in thearchitecture to improve its performance. In the similar context,recently Choa proposed an architecture [4] which has lesserphysical loss as compared to architecture A1. However, in termsof packet loss probability architecture A1 performs better thanChoa’s architecture [8]. In both of these architectures, packetsin the buffer are controlled by the set of SOAs which acts asgate switches. The advantages of SOAs are fast tunability andcompact size. Disadvantages are limited input power dynamicrange and thus limited cascadability due to accumulated noiseand gain saturation. In addition, the tunability of tunable filters(TFs) which is required at the output of the switches is anotherconstraint parameter in these switches. These parameters limitthe fundamental buffer depth (number of wavelengths usedinside the buffer), and the accumulated ASE noise limits thenumber of packet re-circulations.

A. Switch Architecture Description

In the architecture A1, two modifications are suggested in [8],1) in the buffer, replacement of SOAs with TWCs, and 2) at theoutput of the switch replacement of the combination of splitterand TF by a demux and the resulted structure (Architecture A2)is shown in Fig. 2. The TWCs at the inputs of the switch aretuned at every time slot either to place packets in the loop bufferto avoid contention or to direct them to appropriate output ports.For reading/removing a packet from the buffer, the respectiveTWC inside the buffer, tunes the wavelength of the packet asper the desired output port. The packets to be buffered are con-verted to the wavelengths available in the buffer; if memory isfull then packets cannot be stored and are considered as lost.The advantages of placement of TWCs inside the buffer are,

1) Simultaneous Read/Write Operations: In architectureA1, in case of contention, packets are placed in the buffer by

Fig. 2. Description of architecture A2.

tuning their wavelengths appropriately and SOAs are switched‘ON’ to accept the packets. In order to read out the packet fromthe buffer, the buffered packets which are also broadcast tothe output are selected by the output filter by tuning itself topacket wavelength and the corresponding SOA gate is switched‘OFF’ to remove the packet from the buffer. Hence, writingto same buffer wavelength as being read from, cannot be donesimultaneously; it is possible only after two-cell periods. In thearchitecture A2, the loop SOAs gates are replaced by TWCs.Here, the buffer TWCs can be tuned to any of the buffer oroutput wavelengths. Suppose a packet at is written intobuffer, by tuning the input TWC to buffer wavelength in theslot ‘ ’. It takes one cell period for writing a packet. Assumingthat contention is only for one slot duration; therefore, thepacket also has to be read out form the buffer in the next slot

. This will also be the minimum storage time for abuffered packet. For the read out operation, the buffer TWCis tuned to . After conversion, as complete packet crossesthe TWC, in process of being buffered out, the TWC bufferwavelength becomes free. Hence, the writing of a newpacket on this wavelength can take place simultaneously inthe slot ‘ ’ while the packet from buffer is being read out.The placement of the TWCs inside the buffer reduce the packetloss probability significantly [8] as it facilitates simultaneousread/write operation in the same time slot.

2) Dynamic Wavelength Re-Allocation: In the architectureA2, as TWCs are used as a buffer gates, it is possible to dy-namically modify the channel spacing while packets are circu-lating in the buffer to minimize the crosstalk. This will give flex-ibility of operation by tuning a packet wavelength to any otheravailable wavelength in the buffer, and, hence, adjacent packetscan be separated out in wavelength domain. Therefore, dynamicwavelength re-allocation will reduce the noise due to crosstalkand may in turn results in an increase in maximum bufferingtime.

3) Control Points and Controller Structure: In the architec-ture A1, input TWCs, buffer SOAs and TFs at the output needto be controlled. However, in architecture A2, only input andbuffer TWCs need to be controlled. Hence, control points getreduced. The complete operation of the switch is controlled by acentralized electronic controller as shown in Fig. 3. At the inputof the switch a small fraction of power is tapped and after O/Econversion is fed to the electronic control unit where the routeidentifier circuit identifies the routes (buffer/direct path). In the

SRIVASTAVA et al.: DESIGN ANALYSIS OF OPTICAL LOOP MEMORY 4823

Fig. 3. Schematic of the electronic controller.

next step the write controller decides the tuning wavelength ofthe packets by analyzing the buffer status. Then controller sendsthe appropriate control signal at the right instant to all the activedevices like input TWCs and buffer TWCs in the switch. Theheader and payload of the packet are separated by guard bandas they may be modulated at different bit rates. The further de-tailing and for the comparison of loop buffer based architecturesrefer to [8]. Overall, the architecture A2 may be interpreted asmost viable loop buffer based architecture. In the next sectiondesign analysis of architecture A2 is presented.

III. PHYSICAL LAYER DESIGN CONSTRAINTS

The physical layer limitations in the design of any opticalpacket switch architecture are due to dispersion and attenua-tion of the signal. Dispersion limits the maximum possible bitrate for a given length. Length of the fiber limits the minimumpossible storage in terms of number of bits at a fixed bit rate.This is because length of the fiber cannot be less than minimumpossible physical length. Buffer depth (number of wavelengthsavailable in the buffer) is limited by the physical loss, which in-creases with scaling of buffer and switch size.

A. Minimum Length Constraints

The minimum length of the fiber loop can be calculated byconsidering single wavelength buffer. Under this assumption,there will be no requirement of the demux and combiner insidethe buffer. The devices can be connected as shown in Fig. 4.The use of EDFA in the loop is optional for single wavelengthbuffer. If EDFA is used in the buffer, then minimum length ofthe loop is limited by the length of the EDFA. But if EDFA isnot used in the buffer, then head (‘ ’) and tail (‘ ’) end fiberlengths of devices which are used to realize the buffer will limitthe minimum possible length of the loop buffer.

The loss of the loop (expressed in the fractional units) for thesimplified buffer structure (Fig. 4) can be evaluated as

(1)

while assuming that splices are required to connect these de-vices. Here, , , and are losses due to 3-dB

Fig. 4. Schematic of the simplified architecture for one wavelength only.

coupler, tunable wavelength converter, isolator and splice re-spectively. Although, we call it min loop loss, any loss valuehigher than this implies a numerical value less than . Theloss of the loop is assumed to be compensated by the gain ofEDFA, i.e.,

(2)

This condition maximizes the SNR and thus allowed morenumber of re-circulations of the packets in the buffer [10].Also,

(3)

Here, is the gain coefficient has unit of per unit length. There-fore

(4)

If EDFA is not used, then minimum length of the buffer will bedecided by the head and tail length of the devices and can bewritten as

(5)

while assuming ‘ ’ devices in the buffer. The total minimumlength will be given by

(6)

This equation gives the minimum length constraint on the loop.Therefore, the length of the loop cannot be less than .

B. Buffer Constraints

In the buffer, it is not possible to increase the buffer space ar-bitrarily, because as the buffer depth (maximum number of al-lowed wavelengths in the buffer) increases, maximum numberof allowed circulations of the data in the buffer decreases. Inthis sub-section buffer constraints analysis is presented. Refer-ring to Fig. 5, the loop buffer can be modeled as cascaded EDFA


Fig. 5. Schematic of the Cascaded EDFAs.

with length between the adjacent amplifiers is a few tens of me-ters. Thus, EDFA can be treated as lumped element [11]. In thelumped model, when a signal pass through an EDFA, it gets am-plified and ASE noise is added to it. Therefore

(7)

Here, and is the input and output power respectively‘ ’ is the gain and is the ASE noise power of the am-plifier. In the loop, gain is always maintain equal to theloop loss this condition maximize the SNR [10]. Therefore,to estimate the gain of the amplifier, in the next paragraph lossanalysis of the switch is presented.

1) Loss Analysis: For the mathematical ease, switch can bedivided into three parts—input unit, buffer unit and output unit.The loss of input unit which consist of TWCs and combiner isgiven by

(8)

The loss of loop buffer can be calculated by breaking the loopinto two parts. Let us consider loss from input of the 3 dB cou-pler to entry port of EDFA to be and that from the EDFAoutput to the input of 3 dB coupler to be . The and aregiven by

(9)

(10)

Here, , , , , , and are lossesdue to 3 dB coupler, de-multiplexer, combiner, tunable wave-length converter, splice and isolator loss respectively.

is the total fiber loss; here is the loss of fiber seg-ment from coupler to EDFA and is the loss of fiber seg-ment from EDFA to coupler. Throughout the paper, maximumnumber of allowed circulations of the data inside the buffer isassumed to be ; then the total loss suffered by a packet in theloop buffer can be written as . Here isthe loss of the loop buffer in one circulation. Similarly, the lossof output unit which consist of coupler and AWG demux can beobtained as

(11)

Here, the loss of 3 dB coupler is considered because as datacomes out of the loop buffer it again passes through the coupler.By combing all the above losses, total loss of the switch can bewritten as

(12)

As the loss of the buffer unit is compensated by the EDFA, theabove equation can be written as

(13)

Here, is the gain of the amplifier in re-circulationat wavelength . The number of channels passing through theEDFA will vary in different slots because in reality traffic arrivalis corelated and composed of ‘ON’ and ‘OFF’ periods. These‘ON’ and ‘OFF’ periods (in units of slots) follows the Paretodistribution with

and (14)

where the parameters and controls the burstiness ofthe traffic is the floor function and is a random numberuniformly distributed in the interval [0,1]. In the ‘OFF’ periodsno power is transmitted; therefore, large variation in power oc-curs and swings the OSNR due to the variability of the traffic.Therefore to stabilize the gain, a gain clamping scheme as pre-sented in [12] is assumed which keeps the gain of the EDFAto a constant value irrespective of number of channels passingthrough it.

2) Power Analysis: In this sub-section, power of the signalis computed after each circulation. In the analysis, three con-figurations of TWCs (transparent, noisy and regenerative) areconsidered. It is necessary to include these features of TWCs asdifferent type of TWCs shows different characteristics.

a) TWC as a transparent device: In the first configuration,TWC is assumed to be a transparent device, i.e., it will tune thewavelength of the incoming signal without affecting the prop-erty of the signal. Hence, the power entering the loop buffer forbit at wavelength is

(15)

The extinction ratio is assumed to be infinite.The signal power after first circulation will be

(16)In the above equation, the second termrepresents the ASE noise power added to the signal in the firstcirculation [13]. The corresponding TWC inside the buffer willremain transparent for first circulations and tunes thewavelength of the packet in the circulation. Thus, the powerof the signal after and circulations for bit is given by

(17)


and

(18)

respectively. In these expressions, indices ‘ ’ and ‘ ’ are usedfor buffer and directly transmitted wavelengths. The term

is the signal power just before the 3 dB couplerin the beginning of the circulation at wavelength ,

is the gain of EDFA in circulation, at wavelengthand the term represents the ASE

noise power added to the signal in the circulation.The power for bit at the output of switch is

(19)

b) TWC as a noisy device: In the second configuration,TWC is assumed to be a noisy device, i.e., when TWC tunesthe wavelength of the incoming signal, noise is added to thesignal [14], [15]. Model given in [14] is considered for theTWC noise. In the buffer, packet will keep on revolving on thesame wavelength (assuming no re-allocation of wavelengthsinside the buffer) until contention resolves. As wavelengthconversion is not required while packet keeps re-circulatingin buffer, TWC will not introduce any noise. But, during theread-out/write-in process, TWC does wavelength conversion,and accordingly adds noise to the signal.

The power entering into the loop buffer for bit at the wave-length will be

(20)

where

In the (20), the first term is the converted signal power and thesecond term represents noise due to the wavelength conversionprocess [14]. Here, is the gain of the SOA used inside TWCand is the conversion efficiency. The term and are ob-tained by solving the set of equations given in [14]. The para-metric values used in the calculations are defined in Table II.The corresponding TWC placed inside the buffer will performtuning in the circulation. Since the TWC will not be tuneduntil circulations so the power for bit after first and

circulations will be

(21)and

(22)

respectively.

Similarly the signal power after circulations is

(23)

where

and is loss between input of 3-dBcoupler to buffer TWC. The power for bit at the output ofswitch is

(24)

The above equations can be simplified as the gain of the EDFAis almost flat with respect to wavelengths in the region of in-terest (1530–1570 nm), and in the loop, automatic gain controlscheme is assumed [23], and, hence, constant gain ‘ ’ in eachcirculation can be considered. Therefore, the (18) can be writtenin modified form as

(25)

or

(26)

Here

.(27)

Similarly, (23) can be simplified as

(28)

Considering full conversion, i.e. , and gain-loss productequal to one, the (26) and (28) can be further simplified

as

(29)

and

(30)

respectively. In both the cases power at the output of the switchis

(31)

c) TWC as a regenerative device: In the third case TWCis assumed to be a regenerative device. When the wavelength of


the signal is tuned, its gets regenerated. This regeneration is as-sumed to be 3R regeneration [16] which removes the circulationlimit and data can remain in the buffer for longer durations. Theperformance of the switch under regenerative TWC is exploredin [17]. Therefore, it will not be further discussed in this paper.

3) Noise Analysis: The optical amplifiers not only amplifythe signal but also add amplified spontaneous emission (ASE)noise to the signal. Due to the square law detection by the photo-detector of receiver, various noise components are generated bythe beating. These noise components are shot noise, ASE-ASEbeat noise, sig-ASE beat noise, ASE-shot beat noise and thermalnoise with variances given by [13] , , , ,and , respectively. These noise variances for bit ‘ ’, afterperforming re-circulations, are given by

and

(32)

Here, and for TWC as a transparent device willbe given by

(33)

For TWC as a noisy device, the expression for will remainsame as in (33), and the will be given as

(34)

The total noise variance for bit ‘ ’ will be

(35)

The bit-error rate [13] can be obtained as

(36)

where is known as the error function and is defined as

(37)

The terms and are photocurrent,sampled by the receiver during bit ‘1’ and bit ‘0’, respectively,and is the responsivity of photo-detector.

C. Crosstalk Analysis

In optical communication nearly all the components intro-duce crosstalk. The optical crosstalk generated by the opticaldevices can leads to significant system degradation. Let, is

the total power of the of co-propagating signal shared with de-sired signal at wavelength in the components and be thecomponents crosstalk ratio. The crosstalk power generated atwavelength by the component can be written as

(38)

The total crosstalk power assuming ‘ ’ components in the bufferwill be given by

(39)

However, in the loop buffer, demux/mux has relatively highercrosstalk in comparison to other components. Hence, after ne-glecting the crosstalk of other components the total crosstalkpower generated (under simplified conditions) in the loop after

circulations will be given by

(40)

The crosstalk power arriving at the output of the switch whileneglecting higher order term will be given by

(41)

where, and is the crosstalk ratio of bufferand output demux, respectively. Assuming, that the buffer andoutput demux have same crosstalk ratio , then the aboveequation can be written as

(42)

As this is a noise power it will be added to in (33), and,hence, total noise power will be given by

(43)

Now, using (32), noise variances can be evaluated by usingin place of . The BER can be computed using

(36). As we explained in the Section II of the paper that thepackets can be dynamically re-allocated in the buffer to reducethe crosstalk. Hence, in that case nonadjacent channel crosstalkratio has to be considered which is below 55 dB. However,the effect of adjacent channel crosstalk will only be consideredwhen more than 50% of the buffer is occupied otherwisepacket will be placed alternatively in the buffer to reduce thecrosstalk. The effect of crosstalk on the number of circulationsis presented in Section IV of the paper.

1) Four-Wave Mixing Analysis: In the optical communica-tion system, as the power of the signal increases, the nonlineareffects start to dominate and affect the system performance ad-versely. In this sub-section, affect of FWM on the system is pre-sented. In deriving the expression for power generation due toFWM, following assumptions have been made, 1) it is assumedthat FWM components do not interact within EDFA, and 2) alsothere is no interaction between FWM and ASE of the ampli-fier which can be further explored in [18], [19]. Therefore, totalnoise of the system is modeled as summation of ASE and FWM.


In a system with channels, the total light amplitudes at fre-quency is the sum of all the light amplitudes of allthe frequency components satisfying the relation

(44)

Each of these components is generated from different fields thatare emitted from different sources. Therefore, there is no cor-relation among them. So the total FWM power at fre-quency can be expressed as

(45)

The contribution from and have to be neglected, asthey correspond to self phase and cross phase modulations andnot for FWM generations [19]. The efficiency of FWM stronglydepends on the phase mismatch , which is defined as

(46)

In [19], a simplified expression for the power generated dueFWM is presented for cascaded EDFA systems. Considering themodel, the power of the generated components at frequencywhich corresponds to wavelength is

(47)

Here

and

Under the exact phase matching condition ,the above (47) can be further simplified as

(48)

(49)

The above mentioned values of ‘ ’ include all the possible com-binations of generated components on different frequencies.However, in the analysis only those many values of ‘ ’ will beconsidered in which wavelength of the generated signal exactlymatches with the channel under investigation. Therefore, theabove (48) will be modified as [20]

(50)

In the equation power of different signal will be given by

(51)

The degeneracy factors will be given as

(52)

Assuming under the condition, , componentsare generated with degeneracy ; with condition

; components are generated with degeneracy andwith ; components are generated with degen-eracy . Thus, total numbers of generated components are

(53)

Finally, power of these components using (50) can be evaluated.Since the ASE noise has random phase, it is valid to add FWMspectral components in term of power [18]

(54)

where average FWM power generated for bit one and zero isgiven by [18]

(55)

Similarly additional noise variances, generated due to the FWMwill be given as [18]

(56)

(57)

where will be given by

Similarly noise variance for bit 0 will be given by

(58)

where the value of and is obtained from (33).The other noise variances will remain same as in (32). Thus,total noise variance for bit is

(59)

The BER under the influence of FWM can be evaluated usingexpression

(60)

The generation of FWM components can be understood fromFig. 6. The column index ‘ ’ and row index ‘ ’ represents thevalues of ‘ ’ and ‘ ’ respectively as in expression (44) and cor-responding allowed values of index ‘ ’ are shown. The table


Fig. 6. Total number of generated components at frequency 4 in 8 channelsystem.

TABLE INUMBER OF GENERATED COMPONENTS ON THE CENTRAL FREQUENCY FOR

DIFFERENT NUMBER OF BUFFER WAVELENGTHS

has been prepared for eight channels and has values of ‘ ’leading to FWM output at channel 4. ‘ ’ entry implies that nopermitted value of ‘ ’ exist which will generate FWM outputat channel 4 which is worst affected channel in the buffer. Thenumber of generated components for the condition ,are along the diagonal and components for other two conditions

and for are off diagonalelements. The number of waves generated due to the FWM, in-creases rapidly with number of channels (Table I). For example,in 4 channels system, 5 components are generated at the centerfrequency and in 8 channels system, 33 components are gen-erated. The strength of each component depends up on phasematching conditions and the effect of FWM is most detrimentalunder exact phase matching condition. Referring to upper tri-angle including diagonal elements in table shown in Fig. 6,

, , , and ,Thus, total number of generated components are . Intable shown in Fig. 6, one need to consider only upper trian-gular values because lower triangular values can be taken careof with degeneracy factor, e.g., the frequency components canbe obtained from the two combinations and

. Thus, this is equivalent of writing one termwith degeneracy 2.

2) Dispersion Constraints: The maximum bit rate is limitedby the dispersion and can be written as [21]

(61)

Here, is the total length traversed by the data in the buffer.is the second order dispersion coefficient and is the spectralsource width. In terms of loop length the total traversed

Fig. 7. Schematic of the bounded regimes.

length can be written as with . Thelength of the fiber loop can be evaluated from the formula

(62)

Here, is the speed of light, is number of equivalent bits inone packet slot which are to be stored in the fiber loop, is therefractive index and is the bit rate. After combining (61)and (62), it can be deduced that the maximum possible storagein terms of number of bits is

(63)

D. Design Rules

In brief, the switch design rules can be summarized as,1) The length of the loop must be greater than the minimum

loop length, i.e.,

(64)

2) The selection of switch size should be such that at least. If the condition is satisfied, than search for the

minimum power level for which while consideringthe detrimental effect of FWM.

3) The bit rate should be such that the dispersion relation mustbe obeyed

(65)

where with4) The storage in terms of bits also follows the relation:

(66)

These, conditions are shown in the Fig. 7. All the equa-tions are drawn on the logarithmic scale, so they appearas straight line with negative slopes. The lines are not tothe scale, but they show the behavior of the constraintequations.


TABLE IIVALUE OF DIFFERENT PARAMETERS

TABLE IIILENGTH OF THE EDFA TO PROVIDE THE REQUIRED GAIN

IV. ANALYSIS OF THE SWITCH

For switch of size and , the wavelengthsthat are used for direct transmission ranges from 1550.12 nmto 1552.52 nm, and corresponding buffer wavelengths are from1534.25 nm to 1536.61 nm. Similarly for the higher values of

and the wavelengths selection can be done by followingthe ITU-T grid with a channel spacing of 0.8 nm. The valuesof the different parameters used in the calculations are shownin Table II. In the table, loss of the demux is represented by afitted formula which is true only for [24]. Since loopbuffer is considered with capacity , 8, and 16, the gain ofthe EDFA has to be modified to maintain the conditioninside the loop buffer. The gains for different buffer capacitieshave been computed by considering the loss through each com-ponent of the loop. The corresponding doped fiber length shownin Table III have been taken from [22].

TABLE IVMAXIMUM NUMBER OF ALLOWED RE-CIRCULATIONS AT DIFFERENT

POWER LEVELS (WHILE CONSIDERING ASE NOISE AND FOR

TWC AS A TRANSPARENT DEVICE)

TABLE VMAXIMUM NUMBER OF ALLOWED RE-CIRCULATIONS AT DIFFERENT POWER

LEVELS (WHILE CONSIDERING ASE NOISE AND FOR TWC AS A TRANSPARENT

DEVICE AND WITH DEMUX CROSSTALK)

In Tables IV and VI, maximum number of allowed re-circu-lations of the data have been presented for various values ofand at various input power levels, for TWC as a transparentand noisy device respectively. In Table VII, maximum numberof allowed re-circulations are shown while considering the ef-fect of ASE and FWM noise in the buffer. The signal power ofeach of the channels is assumed to be same. The acceptable BERis considered to be less than . System model discussed ear-lier is used for calculating maximum allowed re-circulations. Inthe buffer, two scenarios can arise, in the first scenario, eachpacket can stay in the buffer for number of re-circulations.This happens when . In this case, there will be no ef-fect of the circulation limits. In the second case, each packetcan stay in the buffer for number of re-circulations.Under severe circulation limit if the condition isachieved in the buffer, then there will be no advantage of in-creasing of the buffer space as shared buffer behaves like anoutput buffer, with buffering of maximum packets for eachoutput. In general the maximum number of packets that canbe stored for a particular output port will beand total maximum number of packets stored in the buffer is

. The circulation constraint can be re-laxed using higher power levels (Tables IV and VI) such that thenumber of packets that can be stored for a particular outputport will be and also total number of packets stored in thebuffer, i.e., . It is evident from the Tables IV andVI as the signal power increases the maximum number of al-lowed re-circulations of the data inside the buffer increases, butwith the increment in the buffering capacity, maximum numberof allowed circulation decreases. It can be observed form theTables IV and VI, that at the lower power level, there is an ef-fect of the TWC noise, but at the higher power level this effectis negligible. The effect of crosstalk on the number of circula-tions is shown in Table V while considering the adjacent channelcrosstalk ratio of the demux as 40 dB and it can be observed


TABLE VIMAXIMUM NUMBER OF ALLOWED RE-CIRCULATIONS AT DIFFERENT

POWER LEVELS (WHILE CONSIDERING ASE NOISE AND FOR

TWC AS A NOISY DEVICE)

TABLE VIIMAXIMUM NUMBER OF ALLOWED RE-CIRCULATIONS AT DIFFERENT POWER

LEVELS (WHILE CONSIDERING ASE, FWM NOISE AND TRANSPARENT TWC)

Fig. 8. � � � and � � � while number of channels presents in the buffervarying from 5 to 8.

that the effect of demux crosstalk is negligible and can be ne-glected in the calculations. In contrast to this, it can be moni-tored from Tables IV and VII that at the lower power level thereis no effect of FWM, but at the higher power level the effectof FWM is detrimental. For fixed ‘ ’, increase in power levelleads to increase in FWM. For fixed power level, increase in ‘ ’also increases FWM. This is expected as FWM is nonlinear ef-fect increases with number of channels as well as with powerlevels. It is evident from the tables that for the larger values ofthe and , there will be no advantage of increasing the signalpower. In Fig. 8, maximum number of allowed circulations isplotted at different power levels while considering the effect ofASE noise and FWM. In this figure, power level is considered inmW to clearly visualize the effect in small power range. It can beclearly observed from the figure that the optimum power level

is 1 mW (0 dBm), because when all the channels are present,the maximum number of allowed circulations are nearly same.The another important conclusion that can be drawn is that forthe higher values of ( 8) the optimum power level will beless than 0 dBm, because as the number of signals increases thesignal under consideration will be affected by the large numberof FWM generated components (Table I), and as shown in Fig. 8,and the maximum number of allowed circulations will decrease.Therefore, there is an upper limit also on the power level of thesignal which depends on the switch and buffer size.

V. SUGGESTED DESIGN

In this section, a suggested design is presented by consideringall the constraints. The optimal switch design is and

. As will provide very less buffering andcan not be used for severe circulation limits (refer to tables inSection IV). From the minimum length constraints, minimumpossible length of the loop is 11 m. This is the length of theEDFA to provide sufficient gain with buffering capacity of 8(Table III). Referring to Table IV, 10 dBm power level cannotbe used because at this power level , and, therefore,

buffer space will remain effectively unused. To achievethe condition , minimum power level is 5 dBm andat the power level of 0 dBm the circulation limit can be removed(Tables IV–VII). Referring to Fig. 8, this is also the maximumpower that can be used. Therefore, 0 dBm is the optimum powerlevel for this configuration. Using (63), the maximum possiblestorage is 6458 bits. Therefore, for the loop length of the 11 mthe maximum possible data rate supported by the memory is110 Gbps (62). Assuming minimum storage of 10 bits [21], thenthe minimum possible data rate supported by the memory is170 Mbps.

In short, the optimal design parameters for the switch of sizeand are as follows.

Minimum power level dBm.Optimal power level dBm.Minimum length of the loop m.Maximum storage in terms of number of bits is .Minimum storage considered bits.Maximum possible bit rate Gbps.Minimum possible bit rate Mbps.

Finally, it can be summarized that the various attribute whichrestrict the scaling of the buffer are, attenuation of the compo-nents, limited range of the SOA, foot print, ASE noise of theEDFA, and nonlinear effect, etc. However, the most critical lim-itations are, the unavailability of simultaneous read/write oper-ation in SOAs and ASE noise of the EDFA. Hence, the regen-erative property of TWC is essential for the cascadability of theswitches.

VI. CONCLUSION

In this paper design modeling of the loop buffer based ar-chitecture is presented. It has been found that the design of theloop buffer based architecture is bound by many constraints andmore importantly the scaling of the buffer cannot be done arbi-trarily because of physical layer constraints. It is shown that fora specific switch combination there are optimal designparameters, e.g., for and , the minimum power


level is 10 dBm and to fully utilized the buffer space minimumpower level is 0 dBm. Minimum length of the loop is 11 m, min-imum and maximum possible storage is of 10 and 6548 bits re-spectively. Moreover, the minimum and maximum possible bitrate as 170 Mbps and 110 Gbps respectively. The regenerativeproperty of TWC is essential for the cascadabilty of the switchesas they suffered from the severe circulation limit. The analysispresented in the paper clearly suggest that the cross-layer opti-mization is necessary where effect of re-circulation limit shouldbe taken into account while evaluating packet loss probabilityand average delay.

REFERENCES

[1] R. S. Tucker and W. D. Zhong, “Photonic packet switching: Anoverview,” IEICE Trans. Commun., vol. E82 B, pp. 254–264, Feb.1999.

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Rajiv Srivastava (S’08) received the M.Sc. degree in physics (solid state) fromCSJM University, Kanpur (UP), India, in 1997, and the M.Tech. degree in lasertechnology from the Indian Institute of Technology, Kanpur, in 2003, where heis currently pursuing the Ph.D. degree.

His research interests are in the fields of photonic packet switching, opticalnetworks, mobile communications, and software development.

Rajat Kumar Singh (M’05) received B.Tech. degree in electronics and instru-mentation engineering from the Bundelkhand Institute of Engineering and Tech-nology, Jhansi (UP), India, in 1999, and the M.E. degree in communication engi-neering from the Birla Institute of Technology and Science, Pilani (Raj.), India,in 2001.

He is currently working as faculty in the Department of Information Tech-nology, Indian Institute of Information Technology, Allahabad. His research in-terests are in the field of photonic packet switching, telecom networking, andoptical networks.

Yatindra Nath Singh (SM’98) received the B.Tech. degree in electrical en-gineering with honors from the Regional Engineering College, Hamirpur, Hi-machal Pradesh, in July 1991, the M.Tech. degree in optoelectronics and op-tical communications from the Indian Institute of Technology (IIT), Delhi, inDecember 1992, and the Ph.D. degree from the Department of Electrical Engi-neering, Indian Institute of Technology, Delhi, in 1997.

He was with the Department of Electronics and Computer Engineering, IITRoorkee, India, as faculty from February 1997 to July 1997. He is currentlyworking as faculty in the Department of Electrical Engineering, IIT, Kanpur. Hisacademic interests include optical networks, photonic packet switching, opticalcommunications, telecom networks, network managements, e-learning systems,and open-source software development. He is actively involved in developmentof open source e-learning platform tools codenamed Brihaspati.

Dr. Singh was given the AICTE young teacher award in 2002. He is a Fellowof Institution of Electronics and Telecommunication Engineers (IETE), India.

Design Analysis of Optical Loop Memory

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