CODEC for echo-canceling, full-rate ADSL modems

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 12, DECEMBER 1999 1973

CODEC for Echo-Canceling,Full-Rate ADSL Modems

Richard K. Hester,Fellow, IEEE, Subhashish Mukherjee, Darryl Padgett, Donald Richardson,Member, IEEE,William Bright, Member, IEEE, Maher M. Sarraj,Member, IEEE, Joseph T. Nabicht,Member, IEEE,

Michael D. Agah, Abdelatif Bellaouar,Senior Member, IEEE, Irfan Chaudhry,Member, IEEE,James R. Hellums,Senior Member, IEEE, Kazi Islam,Member, IEEE, Arash Loloee,Member, IEEE,

Ching-Yuh Tsay,Member, IEEE, and Glenn Westphal,Member, IEEE

Abstract—A CODEC, fabricated in 3.3-V CMOS, providesthe low-voltage transmitter and receiver interfaces between themodem digital signal-processing engine and the high-voltage hy-brid circuitry for either the central office or the remote terminalends of the subscriber loop, configurable by metal mask option.Extensive use of digital interpolation filters in the transmitter,decimation filters in the receiver, and oversampled data convert-ers minimize the complexity of analog filters. On-chip filteringand 14-bit data converters support echo-canceling modems with-out requiring external filters. With additional external filters,frequency-division duplexing is also supported. The die area is67.5 mm2. The power dissipation in the central office and remoteterminal are 600 and 760 mW, respectively.

Index Terms—Asymmetric digital subscriber loop (ADSL),analog-digital conversion, analog integrated circuits, broadbandcommunication, CMOS analog integrated circuits, Codecs,digital-analog conversion, digital filters, mixed analog-digitalintegrated circuits, subscriber loops.

I. INTRODUCTION

A SYMMETRIC digital subscriber loop (ADSL) modemsprovide high-speed data over the telephone twisted wire

pair up to 5.5 km. The system employs discrete multitone(DMT) modulation with subcarrier frequencies located at mul-tiples of the baud frequency kHz. Full-rate down-stream signals (from central office to subscriber) may employthe 25–1104-kHz band and support data rate up to 8 Mb/s.“ADSL Lite” downstream signals do not use the 552–1104-kHz portion of this band, and the corresponding data rate islimited to 1.5 Mb/s. In either system, the allowed upstreamband is 25–138 kHz, supporting data rate up to 800 kb/s.

The overlap of the upstream and downstream bands is leftto the discretion of the modem vendor. When there is overlap,echo cancellation is used to salvage the signal-to-noise ratio(SNR) of the signal in the presence of the local transmitterecho. When there is no overlap [frequency division duplexing(FDD)], filters are used to reject the echo. A third approachthat employs both echo canceling and nonoverlapping bands

Manuscript received April 15, 1999; revised July 26, 1999.R. K. Hester, S. Mukherjee, D. Richardson, W. Bright, M. M. Sarraj, J.

T. Nabicht, A. Bellaouar, I. Chaudhry, J. R. Hellums, K. Islam, A. Loloee,C. -Y. Tsay, and G. Westphal are with Texas Instruments Incorporated, Dallas,TX 75243 USA.

D. Padgett is with Star*Core, Atlanta, GA USA.M. D. Agah is with Texas Instruments Incorporated, San Jose, CA 95124

USA.Publisher Item Identifier S 0018-9200(99)09041-1.

relaxes the required performance of both the echo-cancelingalgorithm and the filter rejection. This is sometimes calledpseudo-FDD. Interoperability is achieved between modemsemploying different duplexing approaches using an initializa-tion protocol that assigns data only to that subset of subcarrierscompatible with the spectrum allocations of modems at bothends.

Spectrum allocation affects more than just the corner fre-quencies of the filters in the analog front end [1]. FDD-based modems require high-order filters to reduce the localtransmitter echo power spectral density (PSD) to a levelat or below the inherent subscriber loop noise floor in thecorresponding receiver frequency band. In contrast, echo-canceling modems require CODEC’s with less filtering butmore data converter resolution.

Only a few analog front ends have been reported to date[2]–[5]. The first [2], predating even the first issue of thestandard, employed fourteenth-order - bandpass filters inseries with active RC filters in both the transmitter and receiverto separate the upstream and downstream bands in an FDD-based modem. This large amount of analog circuitry resultedin high levels of noise, distortion, and power dissipation.Subsequently reported CODEC’s have much less on-chipactive filtering and require either off-chip passive filters ordigital filtering in the digital signal-processing (DSP) engine,or both.

The prototype device reported here supports a slightlydifferent system partitioning than its precursors. While its usein FDD-based modems is not precluded, its application toecho-canceling systems is particularly convenient, requiringno off-chip filtering and very little digital processing overhead.A highly simplified view of the target system partitioning isshown in Fig. 1. ADSL transmitters produce relatively highpeak-to-peak voltages, nearly 37 V downstream and 15 Vupstream, so high-voltage line drivers and transformers withnonunity turn ratios are typically employed in the modemline interface. ADSL receivers must operate under a widevariety of signal conditions produced by the universe ofsubscriber loops. High-voltage compliant receivers are nec-essary to enable connections over short subscriber loops thatproduce very little signal attenuation. Variable gain early in thereceiver signal path is extremely beneficial because it reducesthe dynamic range requirement of all subsequent circuits.

0018–9200/99$10.00 1999 IEEE

1974 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 12, DECEMBER 1999

Fig. 1. Simplified view of echo-canceling modem illustrating functionalityof CODEC. Additional external filters are required when using the CODECin a modem employing frequency-division duplexing.

Therefore, a system partitioning is chosen that employs acompanion programmable gain amplifier in the receiver paththat is fabricated in the same high-voltage technology as theline driver. The prototype CODEC is intended to provided thecomplete analog interface between the DSP engine and thehigh-voltage line interface components.

The CODEC architecture is described in the next section.Sections III–V describe the data converters, the analog cir-cuits, and the digital filters, respectively. Fabrication detailsand performance of this prototype device are presented inSection VI, and the work is summarized in Section VII.

II. A RCHITECTURE

The system’s asymmetric spectrum allocation means thatthe analog front ends at each end of the loop are unique.This prototype comprises a superset of all subcircuits requiredfor operation in either the central office or the remote termi-nal. During the final stages of fabrication, the metal levelsconfigure the device for one or the other.

In each configuration, the transmitter and the receiver filtersare tuned to the desired spectrum allocation. The transmittershapes its PSD to comply with limits dictated by the ITUstandard and to minimize the corrupting effect of the trans-mitter echo on the receiver SNR. Receivers are designed toaccommodate the wide range of signal and echo power en-countered. In all cases, the signal path architectures maximizethe use of digital filters and employ oversampled (not noiseshaped) data converters and low-order analog filters. By doingso, the sources of noise, distortion, and sensitivity to processvariations are minimized.

There are two digital interfaces to the DSP. One is a 16-bitbidirectional port that transfers signal data to the transmitterand from the receiver. The other is a bidirectional serial portthat transmits data to control the programmable features ofthe signal path as well as input to the VCXO digital-to-analogconverter (DAC) (remote terminal configuration only) andvarious test modes of operation.

A. Central Office

The block diagram of the signal paths in the central officeconfiguration is shown in Fig. 2. The input signal to thetransmitter is sampled at either 2208 or 4416 kS/s, selectableby external pin. The signal is interpolated by copy inser-tion to 4416 kS/s, if necessary, and filtered by a first-orderdigital high-pass sampling at 4416 kS/s. The signal is then

interpolated to 8832 kS/s and filtered by a seven-tap FIRlow-pass prior to entering the 14-b DAC. The output of theDAC is filtered by a third-order Chebyshev low-pass filter andpasses through a programmable attenuator on its way to thetransmitter output.

The purpose of the high-pass filter is to aid in the PSDshaping required for standards compliance [6] in the dc 25-kHzfrequency band. Its corner frequency is 10.3 kHz. When usedin conjunction with judiciously chosen coupling capacitorsbetween the hybrid and the subscriber loop, shown in Fig. 1,compliance is achieved. When the CODEC is ac-coupled tothe line driver, also shown in Fig. 1, the on-board high-passmay be unnecessary and can be bypassed by software control.

Standards compliance above 1104 kHz is provided by thecombination of the copy-insertion interpolation, the seven-tap low-pass filter, and the third-order analog filter. Theuntrimmed analog filter corner frequency may vary25%about its nominal 1390-kHz value without affecting compli-ance. The 3.9-dB signal droop through the ADSL passband,caused by the copy-insertion interpolation, is precompensatedin the DSP prior to the IFFT computation.

The programmable attenuator adjusts the transmitter powerlevel under software control. This is used on short loops wherethe standard dictates that the central office transmitter powerlevel must be decreased by 2 dB for every 1 dB that the centraloffice receiver input signal exceeds 2 dBm. By attenuating thesignal in the analog domain, the magnitude of the noise fromsources preceding the attenuator are also attenuated.

The central office receiver block diagram is also shownin Fig. 2. The first fine programmable gain amplifier (PGA),controlled by the DSP software, has a 0–3-dB gain range in 1-dB steps. When combined with the external PGA, it maintainsthe input signal to the low-pass filter within 1 dB of its full-scale input power, 1.44 dBm (or 3 Vpp), for all subscriberloop conditions. The low-pass filter, a third-order Chebyshevactive RC, has 6-dB gain, and its corner frequency is trimmedto within 13% of its nominal 155 kHz. A second PGA with2.5–5.5-dB gain range spanned in 1-dB steps amplifies thefilter output signal to 1 dBm (or 4 Vpp), the input signal rangeof the analog-to-digital converter (ADC). The ADC is a 14-b pipeline converting at 4416 kS/s. Its first five stages aretrimmed to achieve the desired linearity. Following the ADC,a four-tap FIR filter decimates the ADC output to 2208 kS/s,and a 13-tap FIR filter provides most of the antialias filteringrequired for subsequent decimation to 276 kS/s in the DSP.

ADSL receivers must eliminate as much echo power aspossible so that maximum amplification can be applied to thesignal. In echo-canceling modems, filtering cannot completelyeliminate echo power because the upstream and downstreamfrequency bands overlap. Fortunately, in the central office,since the echo bandwidth is much greater than the signalbandwidth, the analog low-pass filter can reduce the echopower by about 10 dB. However, since the relative magnitudesof the upstream signal power and the echo vary significantlyfrom one subscriber loop to another, the total power lossincurred at a low-pass cannot be predicted. For example, whenthe signal power is much greater than the echo power, thefilter gain results in a 6-dB total power gain. In order not to

HESTERet al.: CODEC FOR ECHO-CANCELING, FULL-RATE ADSL MODEMS 1975

Fig. 2. Block diagram of central office configuration.

Fig. 3. Block diagram of remote terminal configuration.

saturate the filter output, its input level must be reduced to7.44 dBm. When the reverse is true, a much more likely

scenario, the filter will produce a total power loss of roughly3 dB that is recovered with the gain of the second PGA. The6-dB low-pass filter gain is chosen to minimize the gain rangeand noise performance requirements of the second PGA.

B. Remote Terminal

The remote terminal transmitter block diagram, shown inFig. 3, is very similar to that of the central office. Both itsinput sample rates and the digital high-pass filter are identical.The digital third-order elliptic low-pass filter is employed toprovide a steep PSD rolloff beginning at 138 kHz. The 14-b DAC is also identical to that used in the central officeconfiguration except that it converts at half the rate, 4416 kS/s.The DAC is followed by a second-order Chebyshev analogfilter to remove signal images. A replica of the transmitter pathis included in the receiver to improve the echo suppression(described below). This echo-cancellation path requires ananalog programmable attenuator for fine adjustments in power,so to replicate the transmitter as accurately as possible, aprogrammable attenuator is also included in the transmitterpath with 0 to 24-dB gain range spanned in 1-dB steps.

Standards compliance at frequencies above 138 kHz isprovided by the combination of copy-insertion interpolation,the elliptic low-pass filter, and the second-order analog re-construction filter. It is anticipated that the DSP inverse fastFourier transform (IFFT) sample rate will be 276 kS/s and

that interpolation to 2208 kS/s or 4416 kS/s is performedby the DSP using either copy insertion or a filter witha similar transfer function. The passband droop that thiscauses is assumed to be compensated prior to the IFFTcomputation. The elliptic low-pass filter preceding the DACprovides much steeper PSD rolloff than is possible in anFIR filter of similar complexity. (The steep rolloff is dictatedby the standard.) Because the ADC conversion rate is 16oversampled, there is a very relaxed transition band for thesubsequent reconstruction filter, so a second-order Chebyshevlow-pass filter with corner frequency of 172.5 kHz25% isadequate.

Unlike the central office scenario, at the remote terminal,the echo frequency band is much smaller than the downstreamsignal frequency band. Thus, it is impossible to filter out anyportion of the echo without also removing some portion ofthe signal. An alternative to receiver filtering that can reducethe echo power employs a DSP algorithm in conjunctionwith a replica of the transmitter path. During modeminitialization, the impulse response of the echo is measuredand the tap weights of an FIR filter defined. During normaloperation, the transmitter signal is passed through this FIRfilter and output to the replica transmitter path, where ananalog representation is generated and subtracted from thereceiver input at the hybrid amplifier. A typical echo returnloss improvement of 15–20 dB is obtained.

The remainder of the remote terminal receiver is shown inFig. 3. The analog input signal comes from the external high-


Fig. 4. Architecture of the 14-b analog-to-digital converter.

Fig. 5. Schematic diagram of trim array used in the first two stages of the pipeline. The CMOS transmission gate symbol in Fig. 4 is also used here.

voltage programmable gain amplifier to the equalizer/low-passfilter. The equalizer provides six software-selectable high-frequency gain boost settings that may be used to increase theSNR of the subcarriers at the upper end of the downstreamspectrum and to reduce the channel impulse response lengthand the corresponding intersymbol interference. A fourth-orderelliptic analog filter after the equalizer provides the antialiasingfor the 14-b, 4416-kS/s ADC that is followed by a very simpledigital low-pass filter that provides the necessary antialiasingfor sample rate decimation to 2208 kS/s.

III. D ATA CONVERTERS

A. ADC

The ADC employs the fully differential pipeline architecture[7] shown in Fig. 4. The reference levels arerefand ref providing a differential input signal rangeof 4 Vpp. Each of the first 12 stages comprises a sub-ADC employing two comparators and a switched capacitorinterstage amplifier with a nominal gain of two. The final stageis a 2-b flash, employing three comparators only.

The redundancy in the digital code enables digital cor-rection for sub-ADC errors caused by comparator offsets orequivalently errors in the dividers producing the ref

ref inputs to the comparators.

In the first two stages, the nominal capacitances of andare 2 pF. This drops to 1 pF in stages 3–5 and 0.5 pF in

the remainder of the pipeline. Ideally,and

ADC nonlinearity results from errors in the interstage amplifiergains, due largely to process variations in theseratios. Within the switched-capacitor amplifiers of the firstfive pipeline stages, there are capacitor arrays andused to trim the ratio errors to acceptable levels. A trimmingcoefficient for each of the five stages is determined during thefinal test of the device. Each coefficient controls the magnitudeand effective sign of the corresponding capacitor array. Thetransfer function of the interstage amplifier is

where in inref ref , and is the sign of the trim coefficient.

The coefficient sign bit determines whether the top plate ofsamples in and ref in or ref

or in and ref in or ref The trimming coef-ficients are stored in nonvolatile registers employing fusiblepolysilicon links [8].

Fig. 5 shows a schematic diagram of one-half of the dif-ferential capacitor array used in the first two stages. Identical


Fig. 6. Simplified schematic diagram of amplifier used in the ADC.

Fig. 7. DAC array layout strategy and current source cell schematic diagram.

104-fF unit capacitors are used throughout. When any trimbit is true, the corresponding capacitance is connectedto the sign multiplexer. When it is false, the correspondingcapacitance becomes a parasitic connected to The totaleffective trimming capacitance is approximately100 fF inroughly 0.8-fF steps. The capacitor arrays employed in stages3–5 have only 6 bits plus sign resolution. Trim bit and itscorresponding capacitance do not exist there.

The residue amplifier is designed with adequate margin ingain and bandwidth so that process variations and changes intemperature will not affect the ADC linearity. A simplifiedschematic is shown in Fig. 6. It consists of a straightforwarddifferential folded cascode first stage followed by a pseudo-differential, NMOS common source second stage. No cascodedevices are used in the second stage to achieve 4-Vpp differen-tial output swing. It has more than 105-dB open-loop gain and100-MHz gain-bandwidth product with a 65phase margin.

B. DAC

The 14-b DAC employs the calibrated current steeringapproach first reported in [9]. At its core, in the area labeledmain current source array in Fig. 7, is an arrangement of130 calibrated current sources, each delivering about

A. All but two of these consist of four transistors.Two parallel PMOS devices and form the currentsource, with conducting roughly ten times the currentof Transistor is a cascode included to maintain ahigh output impedance and isolate the PMOS current sourcesfrom the current-steering switch transients. PMOS transistor

is a switch that is closed when the current source iscalibrated (described below). The cascode device in each of theremaining two current sources is subdivided into 33 devicesto create least significant bit (LSB) current sources, 31 withcurrent one with and two with The


Fig. 8. DAC current cell biasing and calibration.

66 cascode devices from the two subdivided current sourcesare physically interleaved in the arrangement in Fig. 7 labeledcascode array. While this arrangement costs extra die area, iteliminates switching between the subdivided cascode and itscurrent source. Thus it removes adverse effects that may becaused by capacitively coupling between the gate and drain ofthe calibrated device and any errors due to a change in drain-to-source voltage between the calibration and normal operationstates of the current source.

On a given conversion, the currents from 127 of the undi-vided current sources and one subdivided current source areswitched to either the positive output Iout or the negativeoutput Iout through NMOS switches located outside thephysical areas of the main current source and cascode arrays.Thermometer code generated by the seven most significant bits(MSB’s) of the DAC input, bits 8–14, controls the switchesfor the undivided currents. Thermometer code generated bythe next five most significant bits, bits 3–7, controls theswitches for the 31 identical subdivided currents. Currents

and are controlled directly by the two DAC inputLSB’s. At the same time, either the one remaining undividedcurrent source or the other subdivided current source is beingcalibrated.

Fig. 8 illustrates the current source biasing and calibrationscheme. For given bias voltages and four currentsource cells in a common centroid arrangement in the currentsource array are used to derive bias voltage and anotherfour current source cells similarly arranged produce biasVoltages and bias the NMOS reference current as wellas feed back to derive the PMOS cascode bias When acell is calibrated, the feedback path from the reference currentcell output to the gate of is active. The gate bias settlesto the level that produces a total calibrated current equal to thatof the reference current cell when its output node is biased to

the common-mode input voltage of the analog filterfollowing the DAC.

This DAC bias generator will start up properly if ispulled sufficiently low to turn on the current source cascodedevices. To accomplish this, a startup circuit (not shown inFig. 8) connected to sinks current until is at least

below This guarantees that the closedloop producing is active and that the mirror on the far leftside of Fig. 8 sources current to derive

The full-scale output current is set by the resistance in thefeedback loop around the 8replica cell. The resistor layoutmatches that of the resistors in the subsequent analog filter, butprocess variations across the device affect the matching andthus the full-scale output of the transmitter. The DAC is de-signed to accommodate7% trimming of its nominal 2.5-mAfull-scale current, so that matching variations in polysiliconresistors may be compensated. While the DAC full-scaleoutput is measured during final test, the 16-to-1 multiplexersetting is chosen to adjust such that the peak-to-peakoutput of the transmitter is 3 V. Given that the polysiliconresistors have a very low temperature coefficient and thefeedback loop forces the multiplexer output to a bandgap-derived voltage, the transmitter output remains essentiallyconstant over temperature.

All 130 current sources are calibrated continuously in asequence designed to minimize the DAC error energy at thecalibration cycle frequency. In the remote terminal configu-ration, eight DAC conversion cycles are required to calibrateone undivided source, and 16 cycles are required to calibratea subdivided source. In the central office configuration, boththe DAC conversion rate and the required number of conver-sion cycles for calibration are doubled, keeping the completecalibration cycle frequency constant at 4.182 kHz, a frequencychosen to minimize interference with both POTS and ADSLservice.

The DAC directly drives the input of the first integrator inthe analog low-pass filter. The Norton equivalent integrator isused, as shown in Fig. 9. The cascode devices in the DACcurrent sources increase the output impedance and increasethe isolation between the calibrated floating node and theclocked signals on the current-steering switches, but also lowerthe optimum common-mode output voltage of the DAC to1.1 V. This is within the input common-mode range of theamplifier, but somewhat at odds with its 1.65-V common-modeoutput since there is dc feedback around the amplifiers. Theincompatibility is handled by scaling the passive devices in


Fig. 9. Norton equivalent input to transmitter analog filters.

the first stage of the filter. This solution forces the amplifier tosupply a total of about 1-mA common-mode current throughits output stage.

IV. A NALOG CIRCUITS

All analog circuits are continuous time, fully differential,and employ the same two-stage amplifier shown in Fig. 10.The amplifier architecture is a differential folded-cascodefirst stage driving a pseudodifferential class AB output stage

– The output-stage NMOS device is driven directly,and the PMOS device is driven through a PMOS source-follower in series with a common-gate NMOS to a PMOScurrent mirror. Pole splitting compensation is accomplishedby connecting series RC networks across the gate-to-drainof both M1p and M1n. This output stage can drive a 500-

load within 0.75 V of either supply rail, and it maintainsgood high-frequency power-supply rejection ratio fromgreater than 90 dB at 1 MHz. The common-mode output isforced to by a differential amplifier feeding back to theNMOS loads of the first stage. To take advantage of their lower1 noise and to maximize signal swing, low- devices areused throughout the amplifier. Low- transistors are not usedin digital circuits or as analog switches. The average input-referred noise density in the ADSL frequency band is 2.3nV/rt-Hz. The distortion driving 500 at maximum signallevels and at 1.1 MHz is 94 dBc. The power dissipation is32 mW.

The input receiver PGA in the central office configurationis built into the first stage of the analog low-pass filter.This differential half-circuit is shown in Fig. 11. With thefeedback resistance around the first amplifier fixed, the inputresistance is selected by one of three signalsderived from a software-controlled 2-b gain coefficient. Thecapacitively coupled input of the central office receiver inseries with the input impedance of PGA creates a pole that issensitive to the input impedance. To reduce the dependence ofpole frequency on PGA gain, a tapped resistor, also controlledby signals is inserted between the receiver input and theinput common-mode voltage source.

The central office receiver filter shown in Fig. 11, like allother analog filters, employs an active-RC leapfrog topology.As described in Section II, the CODEC signal path architec-tures are designed to minimize the required precision of theanalog filter corner frequencies so that process variations maybe tolerated. However, this central office low-pass filter isan exception. Because the digital decimation filter following

the ADC is relatively simple, some additional filtering in theDSP engine is required in order to lower the sample rateto 276 kS/s. By trimming the analog filter corner frequencyto within a few percent of 138 kHz, the DSP processingburden is considerably reduced. Trimming is accomplishedusing trim bits that control the magnitudeof the integrating capacitors at each of the three filter stages.The trim bits are determined at final test by measuring thefrequency response of the filter. They are then stored innonvolatile memory using the same fusible polysilicon storagetechnique that is used for the ADC calibration coefficientstorage. Low temperature coefficient polysilicon resistors andcapacitors maintain nearly constant filter corner frequency overthe operating temperature range.

The remote terminal receiver incorporates an equalizer intoits analog low-pass filter. The equalizer provides increasinggain with increasing frequency at software selectable rates.It can partially compensate for the increasing loop attenuationthat occurs with increasing frequency. This helps in the overallsystem performance in two ways. First, it reduces the dynamicrange requirement of the ADC by lifting the high-frequencyportion of the signal above its quantization noise floor. Second,it reduces the length of the impulse response of the channel,thereby simplifying the signal processing required to manageintersymbol interference.

The equalizer approximates the inverse line attenuation withtwo stages of bandpass filtering, providing a total of two zerosand four poles. Since the line attenuation varies widely withdistance and wire gauge, six selectable equalizer boost settingsare available. The composite transfer functions of each areshown in Fig. 12. Note that the noise PSD above 3312 kHzthat will alias into the baseband when sampled by the ADC at4416 kHz is attenuated by at least 16 dB with respect to thecorresponding baseband PSD.

V. DIGITAL FILTERS

The digital filters are implemented in standard cell logic.Multiplication is performed by shift/add operations. Filtercoefficients are crafted to minimize the number of nonzerobits when expressed in canonical signed digit form.

The first-order high-pass transfer function is

where

kHz

When combined with a second-order off-chip high-pass, pro-duced by capacitively coupling the hybrid transformer to thesubscriber loop, it assures standards compliance at frequenciesbelow 25 kHz. In the central office, a seventh-order, FIRinterpolation filter precedes the DAC. Its transfer function is


Fig. 10. Schematic diagram of the amplifier used in all analog circuits. Devices drawn with shaded channels are lowV t transistors.

Fig. 11. Half schematic of combination of programmable gain amplifier and low-pass filter used in receiver in the central office configuration.

where

andkHz

Note that this filter is implemented using a total of 11 adders.In combination with the analog low-pass filters, it producesthe required rolloff of the PSD above 1104 kHz.

The equalizer schematic diagram is shown in Fig. 13 to-gether with the fourth-order elliptic low-pass filter that followsit. The analog low-pass filter, corresponding to the equalizerbypass setting, is a fourth-order elliptic continuous-time filterwith 0.5 dB ripple in a nominal 1.325-MHz passband. It isimplemented in a leapfrog arrangement.

The digital filter following the ADC in the central officeconfiguration provides most of the antialiasing required toallow decimation to 276 kHz in the DSP. Only a simplerunning average DSP algorithm is necessary. The digitaldecimation filter is implemented in two stages. The first stageprovides the antialiasing required to decimate the sample rate

Fig. 12. Transfer functions of the six equalizer/low-pass filter settings.

to 2208 kS/s. It is a simple running average filter with transferfunction


Fig. 13. Half schematic of combination of equalizer and antialiasing low-pass filter used in the remote terminal configuration.

where

kHz

The second stage is a 13-tap FIR filter implemented with21 adders. Its transfer function is

where

and

kHz

The combination of this filter and a running average filterimplemented in the DSP is sufficient antialiasing to allowsample rate decimation to 276 kS/s.

The ADSL standard requires a steeper PSD rolloff rateof the remote terminal transmitter than that of the centraloffice. An FIR filter providing the necessary rejection in theremote terminal is excessively long, so a third-order ellipticapproximation is employed. It is realized as a combination offirst-order and biquad sections. The transfer function is

where

Fig. 14. Die photo.

where

kHz

The remote terminal receiver may or may not requiredecimation of the sample rate of the ADC output signal,depending upon the DSP algorithms used. When decimation to2208 kS/s is required, antialiasing is required only to attenuateADC quantization above 1104 kHz by about 6–10 dB. This iseasily done with a simple IIR filter with transfer function

where

kHz


Fig. 15. Static DNL and INL of the transmitter channel in the remote terminal configuration.

Fig. 16. Remote terminal missing tone test where the missing tone issubcarrier number 20 located at 86.25 kHz. Ratio of spur to adjacent carrieris about 69 dB.

VI. FABRICATION AND PERFORMANCE

The prototype device was fabricated in a 3.3-V, mixed-signal CMOS. The process employs a epitaxial layergrown on a high-resistivity substrate. Prior to epitaxial growth,selective areas are defined that may be used as collectorsin vertical NPN transistors or may be combined with rings of

-well to junction-isolate the -epi within, and therefore theNMOS transistors located on that isolated epi. The processoffers both high- (0.6 V) and low- (0.2 V) CMOS.Their minimum gate lengths are 0.55 and 1.6respectively.Polysilicon resistors are available with three selectable sheetresistivities, one of which boasts a near zero nominal tempera-

Fig. 17. Central office missing tone test where the missing tone is subcarriernumber 240, located at 1035 kHz. Ratio of spur to adjacent carrier is 65.6 dB.

ture coefficient. A second polysilicon layer is used to fabricatepoly-poly capacitors. Three levels of metal with 2.1-pitchare also offered. A die photo is shown in Fig. 14. The die areais 67.5 mm

Transmitter path performance was measured both staticallyand dynamically. Fig. 15 shows the static performance largelylimited by the DAC. The integral nonlinearity (INL) is lessthan 0.5 b and the differential nonlinearity (DNL) below 0.4b. The increase in DNL at both the largest and smallest codesis indicative of a small amount of excess noise on the referencesupply, not a characteristic of the DAC itself.

Fig. 16 displays the remote terminal transmitter spurious-free dynamic range (SFDR) using a missing tone test. Thismeasurement was made by continuously applying a constant,


Fig. 18. ADC integral nonlinearity after factory trim. Maximum INL error is below 1.5 b.

Fig. 19. Two-tone test of receiver in the central office configuration.

full-power DMT signal to the entire transmitter path, includingthe line driver. Initially, the signal has zero energy in subcarriernumber 20, at 86.25 kHz. Intermodulation distortion productsof the other subcarriers produce measurable power at themissing tone frequency. The ratio of the spur to the adjacentsubcarrier power is a measure of the maximum SNR thatthe transmitter can produce. In this case, the ratio is about69 dB. Fig. 17 contains an identical test in the central officeconfiguration where subcarrier 240 is missing. In this case, theSFDR is 65.6 dB. For comparison, the ITU standard indicatesthat the maximum subcarrier data load, 15 b per symbol,requires an SFDR of 65 dB.

Receiver performance was also characterized both staticallyand dynamically. Fig. 18 shows the static integral nonlinearityof the ADC. The maximum INL is less than 1.5 bits. Figs. 19and 20 display the results of a two-tone test where SFDR isobserved to exceed 80 dB in both the central office and remoteterminal configurations. The vertical scale of both figures is setsuch that 0 dB corresponds to a full-scale ADC input, 4 Vpp,or 13 dBm. The resolution bandwidth of the spectrum is 1.078Hz, so the noise floor of 100 dB on the plots correspondsto an input-referred receiver noise of119.8 dBm/Hz. This isconsistent with the previously described system partitioningthat includes a programmable gain amplifier in the high-voltage hybrid circuitry.

Fig. 20. Remote terminal receiver two-tone test.

VII. CONCLUSION

We have presented the design details and characterizedthe performance of a CODEC that is the complete interfacebetween the high-voltage hybrid circuits and the DSP engine ofthe full-rate echo-canceling ADSL modem. Only ac couplingbetween the CODEC and the subscriber loop is required toachieve full compliance with the standard in effect at thetime of the design completion [6]. The CODEC architectureemploys oversampled data converters and includes virtually allof the decimation and interpolation filters required in the signalpath between the DSP engine and the data converter. Oneimportant consequence of the use of oversampled converters isthe relaxation in the analog filter precision required. Another isthat digital filters are used to produce the precision transmitterPSD shaping for standards compliance. Not only is the PSDshaping invariant but it is also easily modified with digitaldesign tools to track the unexpected and frequent changes inthe standard.

REFERENCES

[1] R. Hester, “Designing CODEC’s to minimize DSP computational bur-den,” in Dig. Advanced Analog Circuit Design Workshop, Opio, France,Apr. 1999, to be published.

[2] Z. Chang, D. Macq, D. Haspeslagh, P. Spruyt, and B. Goffart, “A CMOSanalog front-end circuit for an FDM-based ADSL system,”IEEE J.Solid-State Circuits, vol. 30, pp. 1449–1456, Dec. 1995.


[3] D. Langford, B. Tesch, B. Williams, and G. Nelson, “A BiCMOS analogfront-end circuit for an FDM-based ADSL system,”IEEE J. Solid-StateCircuits, vol. 33, pp. 1383–1393, Sept. 1998.

[4] J. Cornil, Z. Chang, F. Louagie, W. Overmeire, and J. Verfaille,” A 0.5mm CMOS ADSL analog front-end IC,” inISSCC Dig. Tech. Papers,Feb. 1999, pp. 238–239.

[5] C. Conroy, S. Sheng, A. Feldman, G. Uehara, A. Yeung, C.-J. Hung,V. Subramanian, P. Chiang, P. Lai, X. Si, J. Fan, D. Flynn, and M. He,“A CMOS analog front-end IC for DMT ADSL,” inISSCC Dig. Tech.Papers, Feb. 1999, pp. 240–241.

[6] Network and Customer Interfaces—Asymmetric Digital Subscriber Line(ADSL) Metallic Interface, ANSI Standard T1.413-1995.

[7] S. Lewis, H. Fetterman, G. Gross, R. Ramachandran, and T.Viswanathan, “A 10-b 20 Msample/s analog-to-digital converter,”IEEEJ. Solid-State Circuits, vol. 27, pp. 351–358, Mar. 1992.

[8] M. de Wit, K.-S. Tan, and R. Hester, “A low-power 12b analog-to-digital converter with on-chip precision trimming,”IEEE J. Solid-StateCircuits, vol. 28, pp. 455–461, Apr. 1993.

[9] D. Groeneveld, H. Schouwenaars, H. Termeer, and C. Bastiaansen,“A self-calibrated technique for monolithic high-resolution D/A con-verters,” IEEE J. Solid-State Circuits, vol. 24, pp. 1517–1522, Dec.1989.

Richard K. Hester (M’80–SM’88–F’94) receivedthe B.A. degree in physics from George WashingtonUniversity, Washington, DC, in 1968 and the M.S.and Ph.D. degrees in physics from The College ofWilliam and Mary, Williamsburg, VA, in 1970 and1974, respectively.

He was a Postdoctoral Research Associatein theChemistry Department of the Massachusetts Insti-tute of Technology, Cambridge, until 1976, whenhe joined Texas Instruments to work on design andfabrication of charge-coupled devices. He became

interested in analog signal processing, and with the exception of a two-yearleave of absence to teach at Iowa State University from 1992 to 1994, he hasworked thereafter on analog interfaces to DSP-based systems.

He has served the IEEE and the Solid-State Circuits Society in variouscapacities, including as a member of the Program Committees of ISSCCand the Symposium on VLSI Circuits, Guest Editor and Associate Editorof the IEEE JOURNAL OF SOLID-STATE CIRCUITS, and Program Chair of the1997 ISSCC. He is currently a member of the SSCS Adcom and the ISSCCExecutive Committee. He is a TI Fellow.

Subhashish Mukherjee received the B.E. degreein electronics and telecommunication engineeringfrom Jadavpur University, India, in 1988 and themaster’s degree in electrical engineering from theIndian Institute of Technology, Kanpur, in 1990.

He joined Texas Instruments, India, in 1990 asa Design Engineer in the Mixed Signal IC DesignCenter. Since then he has been involved in designingdata converters and analog front-end IC’s for voice-band modems, DSL modems, and digital imagingsystems.

Darryl Padgett received the B.S. and M.S. degreesin electrical engineering from Tuskegee University,Tuskegee, AL, in 1986 and 1990, respectively, andthe Ph.D. degree from the University of Alabama,Tuscaloosa, in 1996.

He joined Texas Instruments, Dallas, in theSpeech Products Group. He joined the Mixed SignalDesign Group working on digital filters for wirelessand ADSL chips. He recently joined Star*Core,Atlanta, GA, where he currently manages a designteam working on next-generation DSP’s.

Donald Richardson (S’76–M’78) received theB.E.E. degree from Auburn University, Auburn,AL, in 1977.

In 1979, he joined the Data Systems Group ofTexas Instruments, Houston, where he designedcircuits for switched-capacitor modem IC’s. In1986, he joined the Texas Instruments Semicon-ductor Group in Dallas, where he has designedmixed-signal circuits for data acquisition, audio,and telecommunications IC’s. He is presently aSenior Member of Technical Staff in the CentralOffice Products Design Section.

William Bright (M’94) received the B.S. and M.S.degrees in electrical engineering from Iowa StateUniversity, Ames, in 1992 and 1994, respectively.

In 1993, he joined Texas Instruments, Dallas,where he began his career working on analog-to-digital converters in CMOS technologies. He cur-rently works in the Mixed Signal Circuit Group de-veloping digital-to-analog converters in both CMOSand BiCMOS technologies for various end applica-tions.

Maher M. Sarraj (M’97) received the B.S.E.E.degree from the American University of Beirutin 1985, the M.S.E.E. degree from the Univer-sity of Michigan at Ann Arbor in 1986, and thePh.D. degree in electrical engineering from SouthernMethodist University, Dallas, in 1998.

From 1987 to 1990, he was with the Universityof Michigan Physics Electronics Lab, developingboard- and chip-level designs. From 1990 to 1995,he worked at Fermilab in Batavia, IL, develop-ing high-speed/resolution mixed-signal products for

high-energy physics research. In 1995, he joined the Data Converter Groupat Texas Instruments, Dallas. At present, he is the Section Manager in theData Converter Product Division. His research interests include high-speed,high-resolution data conversion, solid-state devices, and materials.

Joseph T. Nabicht (S’89–M’90) was born March9, 1964, in South Bend, IN. He received the B.A.degree in physics from Indiana University, SouthBend, in 1987 and the M.S.E.E. degree from theUniversity of Louisville, Louisville, KY, in 1990.He is currently pursuing the Ph.D. degree in electri-cal engineering at Texas A&M University, CollegeStation.

He has been a member of the Mixed-Signal Prod-ucts Design Group at Texas Instruments, Dallas,since 1993, designing analog circuits for voice-bandand ADSL CODEC’s.

Michael D. Agah was born in Detroit, MI, in 1965.He received the B.S.E.E. degree from MichiganState University, East Lansing, in 1988.

He was with Amati Communications Corp. from1993 to 1998, when it was acquired by TexasInstruments. He has worked in the area of DSLanalog front-end design and architecture for the pastsix years and currently leads the AFE system designefforts at Texas Instruments, San Jose, CA. He isa Senior Member of the Technical Staff at TexasInstruments.


Abdellatif Bellaouar (SM’96) received the doc-torate degree in electrical engineering from theUniversity of Paul-Sabatier, Toulouse, France, in1985.

He was a Research Associate Professor at theVLSI Research Group of Waterloo University, Wa-terloo, Ont., Canada, for more than five years. Hejoined Texas Instruments, Dallas, in 1996, wherehe currently works in the area of RF IC design. Hiscurrent research includes low-power RF transceiversdesign for wireless communication systems and RFfractional frequency synthesizers.

Irfan Chaudhry (S’91–M’92) was born in Lala-musa, Pakistan, on November 15, 1966. He re-ceived the B.S.E.E. and M.S.E.E. degrees from theUniversity of Idaho, Moscow, in 1992 and 1994,respectively.

From 1992 till 1994, he did research for theNuclear Safety branch of Sandia National Labs,Albuquerque, NM, which involved designing andtesting of reliable fail-safe current limiter circuitsfor use in nuclear weapon testers. In 1995, he joinedthe Mixed Signal Products Department of Texas

Instruments, Inc., Dallas, where he worked for the Data Acquisition DesignGroup. Currently, he is a Senior Design Engineer in Texas Instruments’Data Converter Products Department. Since joining TI, he has designedseveral high-speed data converter IC’s for different applications such as video,communications, and imaging. His main design and research interests are inanalog and mixed-signal IC designs related to data conversion. His otherinterests include antenna design, electromagnetics, microwave engineering,and aircraft model building.

James R. Hellums (S’75–M’77–SM’96) receivedthe B.S.E.E. (highest honors) and M.S.E.E. degreesfrom the University of Texas at Arlington in 1976and 1983, respectively. He currently is pursuing thePh.D. degree from the University of Texas at Dallas.

His research topic is quantum transport theory. InJanuary 1978, he joined MOSTEK as an IntegratedCircuit Design Engineer, where he worked on 5MOS analog IC’s for telecommunications. He leftin 1981 to cofound Nova Monolithics, where hewas involved in consulting and custom IC designs,

which included mixed-signal chips with analog filtering and A/D conversion.He joined Texas Instruments, Dallas, in 1984 as a Senior IC Design Engineer.Since joining Texas Instruments, he has worked on the design of 24 analogand mixed-signal IC’s, of which 17 required A/D conversion. He is the authoror coauthor of 21 papers. He has given five conference talks. He has receivedten U.S. patents and seven foreign patents with 12 patents pending.

He was elected Group Member, Senior Member, and Distinguished Memberof Technical Staff in 1987, 1989, and 1996, respectively. He was elected TIFellow in 1997. He is a member of the American Physical Society, Eta KappaNu, Tau Beta Pi, and Alpha Chi.

Kazi Islam (S’90–M’98) received the B.Sc. degreefrom the University of Engineering and Technology,Lahore, Pakistan, and the master’s degree fromTexas A&M University, College Station, both inelectrical engineering.

Since 1995, he has been an IC Design Engi-neer in the Mixed Signal Design group at TexasInstruments, Dallas. There, he has concentrated onthe design of analog circuits for mixed-signal audioapplications.

Arash Loloee (M’97) was born in Tehran, Iran, inMay 1964. He received the B.S. degree in physicsfrom North Texas State University, Denton, in 1990and the M.S. and Ph.D. degrees in electrical engi-neering from Southern Methodist University, Dallas,in 1992 and 1995, respectively.

His Ph.D. dissertation dealt with analog/digitalcircuits and systems for monitoring action potentialsof live neuronal networks. In 1995, he joined TexasInstruments and worked as a Design Engineer inthe Data Converter Department. Since 1995, he has

been involved in designing high-speed ADC’s and DAC’s. His area of interestis analog integrated circuits.

Ching-Yuh Tsay (S’83–M’83) received the B.S.degree in communication engineering from NationalChiao Tung University, Hsinchu, Taiwan, in 1979and the M.S. and Ph.D. degrees in electrical engi-neering from Texas Tech University, Lubbock, in1983 and 1986, respectively.

He joined the VLSI Design Laboratory at TexasInstruments Inc., Dallas, in 1986, where he workedon design automation and high-performance analog-to-digital converters. In 1989, he joined AdvancedMemory Development of the Semiconductor Group,

responsible for analog circuit designs for 0.5�m DRAM development. Since1992, he has been working in Mixed Signal Product Development, where hehas been involved with DPS-based mixed-signal products, analog front end forvideo/imaging applications, and data converter designs. He has received nineU.S. patents. He is currently a Design Manager for data converter products.

Dr. Tsay is a registered professional engineer in the state of Texas.

Glenn Westphal (M’99) received the B.A. andPh.D. degrees in physics from the University ofUtah, Salt Lake City, in 1973 and 1979, respec-tively.

Since then, he has worked at Texas Instruments,Dallas, on a wide variety of materials and elec-tronics problems. He is currently Manager of theDesign Group at TI responsible for the design ofhigh-speed modem, xDSL, and other central officeapplication integrated circuits. His interests includefilter design, converter design, and communicationssystem analysis.

CODEC for echo-canceling, full-rate ADSL modems

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