Building-in ESD/EOS reliability for sub-halfmicron CMOS processes

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 6, JUNE 1996 99 1

Building-In ESD/EOS Reliability for Sub-Halfmicron CMOS Processes

Carlos H. Diaz, Member, IEEE, Thomas E. Kopley, Member, IEEE, and Paul J. Marcoux, Member, IEEE

Abstract-MOSFET design in high performance CMOS technologies is driven primarily by performance requirements and reliability issues such as hot carrier degradation. These requirements generally lead to processes that are inherently weak in terms of ESD and EOS. This paper presents a case of building- in ESD/EOS reliability through nMOSFET drain design for a 0.35 bm CMOS process that compromises neither the performance nor the hot carrier reliability. Three process options were considered: nLDD or nDDD ESD implants, and a silicide-block option. The nDDD option for the U 0 transistors was chosen as it complied with the performance and reliability (ESD and HCI) specifications and its implementation cost was lower than a silicide-block option. The paper presents data demonstrating the advantages of the nDDD solution over the other alternatives. Particularly, pulsed-EOS and HBM-ESD data, the impact of layout parameters on ESD performance, and hot-carrier data are reviewed.

I. INTRODUCTION

OSFET design in high performance CMOS technolo- M gies is driven primarily by performance requirements and reliability issues such as hot carrier (HCI) degradation. This can lead to processes that are inherently weak in terms of Electrostatic Discharge (ESD) and Electrical Overstress (EOS) due to the shallower junctions and the impact of the LDD regions on the breakdown characteristics of the nMOS transistors [l]. Since the inception of LDD and silicides, work has been done to enhance the ESD robustness of nMOS output transistors. The techniques to improve ESD include masked implants and blocking the silicide formation. The improvement of ESD performance with the addition of a selective drain/source phosphorus implant in nMOS transistors for 1 pm and older technologies was the subject of several publications cf. [2]-[5]. For similar technologies, other researchers have proposed un-silicided nMOS transistors for 1/Os in order to restore the spreading resistance that prevents current localization[6]-[8]. The work presented in this paper addresses the ESD performance of an advanced 0.35 km process in conjunction with its performance metrics and hot-carrier reliability. In contrast to previous work, devices are characterized for EOSESD using both pulsed high- current wafer-level measurements and package-level HBM-

Manuscript received March 28, 1995; revised February 9, 1996. The

C. Didz is with ULSI Research Laboratory, Hewlett-Packard Company,

T. Kopley is with Siemens Corporate R&D, Munich, Germany. P. Marcoux is with the Integrated Circuits Business Division,

Publisher Item Identifier S 0018-9383(96)04023-3.

review of this paper was arranged by Editor J. R. Hauser.

Palo Alto, CA 94303 USA.

Hewlett-Packard, Palo Alto, CA 94303 USA.

Second f Breakdown 1 I Region

I Drain Voltage

Fig. 1. transistor.

Typical I-V breakdown characteristics of a grounded-gate nMOS

ESD stressing. Furthermore, the correlation between the two stress methods is presented.

Fig. 1 shows a typical I-V breakdown characteristics for a gate-grounded nMOS transistor. Here Vtl is the drain junction breakdown voltage. During an EOSESD event, the device operates in the snapback mode where the holding voltage V,, is determined mainly by the characteristics of the parasitic lateral npn transistor and its level of self-heating. At high currents, the device goes into second breakdown which is a positive feedback process that causes device failure due to current localization. The current required to induce second breakdown (It2) has been used as a predictor of the HBM-ESD failure threshold [9], [IO]. In this work, building-in ESDEOS reliability focused on providing the technology with an ESD robust nMOS U0 transistor design while maintaining HCI reliability and good drive capability under normal operation.

Three process options were considered: nLDD (lightly doped drain) or nDDD (double diffused drain) ESD implants, and a silicide-block option. The nDDD option for the I/O transistors was chosen as it complied with the performance and reliability (ESD and HCI) specifications and the process is simpler to implement than the silicide-block alternative. This paper presents data demonstrating the advantages of the nDDD solution over the other alternatives. Particularly, pulsed-EOS and HBM-ESD data, the impact of layout parameters on ESD performance, and hot carrier data are reviewed. Section I1 gives an overview of the process technology used for this study. It also discusses the device design constraints and how process/device simulations were used to determine a basic experimental set. Section I11 describes the experimental results pertaining to the device parametrics and the outcome from EOSESD and HCI stress measurements. Section IV

0018-9383/96$05.00 0 1996 IEEE

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 6, JUNE 1996

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discusses how a sub-set of device electrical parameters and reliability characteristics were incorporated into a desirability analysis [ 111, [ 121 in order to determine the best device design for a given set of constraints.

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11. DEVICE DESCRIPTION

The devices were fabricated in a 3.3 V, 0.35 pm titanium salicide CMOS process with 80 A gate oxide. Standard drain design had a phosphorus implant followed by an arsenic implant after side-wall spacer (SWS) formation. Simulated nMOS device cross-section and doping profiles are shown in Fig. 2(a) and (b) for an LDD transistor with a 0.35 pm polysilicon gate. The effective junction depth is approximately 0.20 pm for this technology.

The basic LDD nMOS transistor was optimized for high performance and HCI reliability. These requirements were such that the inclusion of an additional reliability constraint such as EOS was not compatible with the high performance nLDD drain design. The need for a robust ESDEOS technology prompted the development of a second nMOS transistor for the I/O frame circuits. The design of this ESDEOS robust device was guided by the following constraints:

1 ) not to alter thermal cycles of established process flow, 2) minimize the number of additional process steps re-

quired (minimize cost),

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maintain a competitive current drive capability (Idsat) when compared with baseline nLDD devices of similar channel lengths, maximize the HCI reliability, and provide the technology with a self-protecting nMOS 1/0 transistor (e.g., 200 pm wide nMOSFET capable of surviving a 1.5 kV ESD-HBM event which translates approximately into better than 5 mA/pm grounded-gate nMOS second breakdown current).

Two types of process options were considered to build-in ESDEOS reliability, namely the addition of an ESD implant to modify the drain design[2]-[5], [13] and a silicide block option [6]-[SI. In the first approach, the addition of an ESD implant aims to reduce local power density under breakdown conditions by reducing both the current density and the snapback voltage, i.e., to have abrupt deep junctions as opposed to shallow LDD junctions. On the other hand, the tendency of the stress currents to localize in an nLDD transistor can also be prevented by using a large draidsource ballasting (spreading) resistance, a feature that the silicide-block option provides.

Two kinds of ESD implants were considered. One was a selective, heavier and deeper phosphorus implant performed at the nLDD step. The other type of implant involved selective masking the nLDD and replacing it with a heavy and deep phosphorus implant performed after SWS formation and before the source/drain oxidation step. This later approach creates what is called a doubly-diffused drain (DDD) nMOS device.

Process and device simulations using TMA's SUPREM and MEDIC1 [ 141 were used to select the ESD implant conditions to be implemented in the experiment. Table I summarizes the simulation results for nMOS devices with = 0.45pm. The values are expressed as per unit quantities of the nLDD (5E13 @25) transistor design. The key electrical parameters that were considered in the design of the experiment were the peak power and current density under snapback conditions (i.e., the point of zero dynamic resistance beyond the drain breakdown), current drive capability and off-state leakage at normal operating conditions (i.e., @vds = 3.3 V), and peak electric field at maximum substrate current with V,, = 3.3 V. Note the simulations predict substantial savings in terms of 2D cross-sectional current density under stress conditions and at the same time predict an increase of the drive capability, the later attributed to the smaller effective channel length and reduced drain resistance. Note also that the substrate current

DIAZ et al.: BUILDING-IN ESDEOS RELIABILITY FOR SUB-HALFMICRON CMOS PROCESSES

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and peak electric field values suggest that HCI reliability is being reduced.

No simulations on the silicide-block option were performed since nonsilicided diffusions effect ESDEOS robustness by spreading out the stress current, a 3D phenomenon that can not be simulated with MEDICI.

111. EXPERIMENTAL RESULTS Based on the simulation results presented above, a first lot

containing the ESD implant splits and silicide-block experiments was run, see Table 11. Data gathered from devices in this lot indicated that the optimal solution for a robust nMOS I/O transistor should be around the DDD 7E14060 split. A second lot was then run to explore the DDD device design space around that implant condition using a statistical designed experiment. The experimental design information for this lot is also included in Table TI. The following sections will highlight the main results from these two lots.

A. Device Parametria

Key device parameters measured under normal operating conditions are given in Table I1 for nMOS devices with 0.45 pm poly channel length. The device performance measured in terms of Idsat was observed to monotonically increase as the P implant energy and dose increased. This effect is explained in terms of the smaller effective channel lengths and reduced drainhource resistance resulting from heavier implants. Data indicated that the threshold voltage monotonically decreases as both the implant dose and energy increased. It was also found that all but the 1E15@65 implant condition rendered 0.45 pm nMOS devices with off-state leakage well under control. Regarding the nonsilicided split, the performance specifications were degraded to some extent as a result of the higher drainlsource resistance.

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Subthreshold leakage control was an issue for devices in the second experiment having Lpoly = 0.40 pm and a phosphorus dose greater than 6E14. In contrast, devices with Lpolv = 0.45 pm had well-behaved subthreshold characteristics with very good control on the off-state leakage current. This is shown in Figs. 3-10 pm/0.45 pm DDD nMOSFET's. In this figure, the solid line corresponds to an nLDD MOSFET of identical geometry. The saturation subthreshold slope was observed to monotonically decrease as the phosphorus dose increased. The average subthreshold slope of 10/0.45 nMOS- FET's in the second experiment ranged from 86.6-91 mV/dec.

Fig. 4 compares typical I-V characteristics of the standard nLDD device with respect to those for DDD nMOSFET's from various splits in experiment number two. In this figure, all the devices are 10 pm/0.45 pm and V,, was swept from 1.3 V in

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Fig. 4. Standard LDD nMOSFET I-V characteristics compared to those for nDDD devices from various splits in the second experiment. The devices are 10 pm wide with L,,l, = 0.45pm.

0.5 V steps. Notice that the DDD devices outperform the LDD nMOSFET by at least 5%. Also note that the DDD device with heavier implant begins to show the onset of nMOS breakdown when V& z 3.8 V.

B. EOS/ESD Experiments Wafer-level (WL) EOS measurements were done using the

stress configuration schematically shown in Fig. 5. The high current pulse generator is used to deliver pulses up to 1 A while the transmission line pulse set-up (TLP) [ 151 is used to stress the devices with greater than 1 A current pulses.' Stress current and voltage waveforms are captured in real-time with a 2 GSa digitizing scope (HP54720). Post-stress leakage measurement is performed using an HP4142B. The stress sources, digitizing scope, and leakage measurement instruments are built into an automated WL EOS system [16]. The system computes the stress current level, delivers a current pulse to the device, measures the post-stress leakage, and logs the amplitudes of the stress waveforms and the value of the leakage measurement to a data file. All devices are stressed from the sub-breakdown region with current pulses of increasing amplitude up to the point of second breakdown. The system loops with increasing levels of stress current until the failure criteria is met. Device EOS failure was defined as a leakage greater than 1 nA at V d s = 4 V. The EOS data reported here was taken using 150 ns pulses.

The ESD data was taken on packaged devices using a Keytek- 128 tester with an HBM-ESD discharge head. The failure criteria for these devices was set to more than 10% relative change of the I-V leakage characteristics or more than 0.1 p A leakage current at 4 V.

Let us first consider the nonsilicided split from the first experiment. Fig. 6 shows the WL second breakdown current plotted versus the contact-to-gate spacing (CGS) for a typical nMOS output transistor (300 pm wide with 0.45 pm physical channel length). In this figure, the square symbols correspond

' A 470 nH inductor was placed in series with the TLP in order to match the slew rates of pulses from the TLP to those of the HP81 14A.


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Fig. 5. EOS stress source configuration. The source is an HP8114A pulse generator for current pulses up to 1 A or a coaxial cable charged to a high voltage for pulses greater than 1 A.

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Fig. 6. nonsilicided 30010.45 nMOS LDD devices from lot no. 1.

Plot of the It2 versus drain contact-to-gate spacing (dcgs) for

to devices that had equal drain and source CGS values whereas the diamond symbols represent data for devices with source CGS of 1 pm. The data indicates that for devices with symmetrical drain and source contacts, the optimum spacing required to meet the EOS robustness goal (5 mA/pm) is approximately 4 pm in agreement with previous findings for nonsilicided technologies. What is more important from Fig. 6 is the data for the devices with asymmetrical drain and source CGS values. Device-level electrothermal simulations show that nMOSFET's with large drain CGS and minimum source CGS should outperform devices with symmetrical CGS values in terms of EOS [17]. The underlying constraint for multi-finger structures is that the drain and source areas remain equal in size with the source fully populated with contacts [17]. This layout style limits the degree of thermal coupling between fingers and provides for additional heat sink capability under severe EOS events (7 > 1 ps). The diamond symbols in Fig. 6 are the first time proof of this concept to the best of our knowledge. Asymmetrical CGS nMOSFET's should be a useful technique suitable for grounded-substrate chips that are fabricated in any nonsilicided technology.

Fig. 7 is a plot of the average second breakdown current I,, versus the phosphorus implant condition (both LDD and DDD). The data was taken using 300 pm wide nMOS devices

DlAZ et al.: BUILDING-IN ESDEOS RELIABILITY FOR SUB-HALFMICRON CMOS PROCESSES

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Fig. 7. Contour plot of the average second-breakdown current It2 versus phosphorus implant condition for 300/0.45 salicided nMOS devices. (No data to the right of diagonal.)

with 0.45 pm polysilicon gate laid out in six fingers. The figure includes data from splits in both lots. The worst EOS performance is that of the standard nLDD devices (5E13@25, front corner of the figure) with 1 mA/pm. The LDD splits from the first lot did improve the EOS performance, particularly the 8E13@65 split increased it by about a factor of three. The figure also indicates that regardless of the implant condition, all the DDD splits in both lots were capable of meeting the It2 goal of 5 mA/pm. It was found that the 8E14@55 implant condition provided the best EOS performance with a mean Itt2 = 6.3 mA/pm (a = 0.4). Then next best EOS performance was attained with the 7E14@50 implant condition having It, = 5.7 mA/pm (g = 0.02).

As previously pointed out at the beginning, EOS reliability optimization relies on assuring the lowest possible values of current and power density for a device working in snapback. This translates into minimizing the device self-heating effects under stress conditions. Fig. 8 is a plot of the average snapback voltage versus the implant conditions for single finger, 50 pm wide nMOS devices with 0.45 pm physical gate length. Notice that the snapback voltage is fairly independent of the implant energy as expected. As the implant dose increases, the junctions become more abrupt. This is reflected in the almost 2 V reduction of the snapback voltage when moving from devices with LDD type of implants to DDD devices. It was found that the minimum value of the snapback voltage was attained by the 8E14@55 implant condition in agreement with the findings from the It2 data presented in Fig. 7.

An important question regarding process intrinsic ESD reliability is how do the WL EOS measurements correlate with the package level HBM-ESD experiments. Ideally, the HBM- ESD failure voltage should be related to the pulsed second breakdown current according to the relation

Vfazl = 150052 x It,

where 1500R is just the value of the HBM-ESD source resistance [ 1 81. Several devices from the first experiment

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Fig. 8. for 50/0.45 salicided DDD devices from the second lot.

Plot of the average snapback voltage T/Sp versus implant condition

were packaged and stressed according the HBM-ESD Mil- Spec [19]. Fig. 9 is a plot of the package-level HBM-ESD failure voltage versus the WL It, for salicided, 0.45 pm nMOS devices from the 7E14@60 split. In this plot, the error bars extend & one standard deviation and the solid line represents the ideal correlation. Note that as the device width increases, the spread of the data grows as indicated by the error bars. This is a result of the random nonuniform multifinger turn-on phenomena common to grounded-gate salicided nMOS devices [201, [21]. The data also indicates that pulsed second-breakdown current measurements correlate with the HBM-ESD failure voltages indicating that the failure mechanisms remained the same in both cases. Failure analysis indicated that the failure mechanism was drain-to-source melt filaments. Fig. 10 exemplifies such a failure. The fact that all the data lies above the solid line suggests that WL experiments were more stressful to the devices than the corresponding ESD measurements. It is likely that if narrower pulses, e.g., 100 ns, would have been used for the WL EOS test then the data would have come closer to the ideal correlation line. Regardless of this, it is important to note that WL measurements can be used as predictors of the intrinsic ESD/EOS robustness of a particular process.

Fig. 11 shows the package-level HBM-ESD failure voltage versus the WL It, for nonsilicided, 300 pm wide, 0.45 pm grounded-gate nMOS transistors. These devices were all designed with six fingers. The data clearly indicates that the silicide-block option provides a feasible solution to building-in ESD and EOS robustness if large enough draidsource contact- to-gate spacing is used. Notice that having large CGS in nonsilicided devices not only boosts up the average failure threshold, but also tightens the distribution as suggested by the size of the error bars. Also, it is important to note that using large drain CGS and minimum source CGS boosted up the average ESD performance by about I kV compared to devices with symmetrical CGS. This in agreement with the

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Fig. 9. Plot of the package-level HBM-ESD failure voltage versus WL It2 for salicided, 0.45 pm nMOS devices from lot no. 1, 7E14 @ 60 DDD split.

Fig. 10. ESD-HBM stressing in a 6 x 50/0.43 salicided DDD nMOS device.

SEM microphotograph of a typical drain-source failure induced after

EOS WL measurements as explained above.

C. Hot Carrier Data

Hot-carrier data was taken in two ways. To compare different drain designs from the same lot, we used a fast, wafer level (WL) test developed for assessing HCI reliability during process development [22]. The test, which runs on an HP4062 parametric tester, measures relative differences in HCI reliability between experimental splits at accelerated DC voltages in a short time. The test was run for 115 s at V d = 4.0

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Fractional degradation in linear Ids versus initial Is& after 115 s

V, V, = 1.75 V for the first experiment and for 1000 s at V, = 4.5 V, V, = 2.0 V for the second experiment (both at peak substrate current stress). All WL measurements were at room temperature.

While the WL test is useful for rapid measurement of relative HCI reliability, it does not allow extrapolations to operating conditions, which is ultimately needed for a true benchmark of reliability. Long term HCI measurements, which do allow extrapolations, were performed with packaged devices stressed in parallel on an automated system. The system consists of a HP4142B connected to multiple devices through a HP3488A switch box. The packages, which expose the silicon to ambient air, are seated in an environmental chamber with a controlled temperature of 25 * 1°C.

Fig. 12 shows the fractional degradation of nMOS linear I d s

(V, = 3.3 V, V d = 0.05 V) after the 115 s WL test. For each experimental split, the average value and %o range is plotted. Here we show final degradation because the LDD and DDD splits have such small degradation before 100 s. This causes all except the last few data points of their degradation versus

997 DfAZ et al.: BUILDING-IN ESDIEOS RELIABlLITY FOR SUB-HALFMICRON CMOS PROCESSES

5E3 1 ~ 4 1

1 5 10 Initial lsub a1 stress (uAIum)

Fig. 13. stress for 7E14@60 DDD nMOS transistors from lot no. 1.

Forward linear Ids lifetime versus initial I S T L b / W after 62 h of

510

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5 10 15 20 Initial lsub at stress (uNum)

Fig. 14. micron width after 1000 s of stress for all implant conditions in lot no. 2.

Forward Idsat lifetime versus the initial substrate current I I v b per

time curve to be in the system measurement noise, making extrapolations to 10% degradation (typical lifetime definition) unreliable. Notice that the standard device's final degradation (2%) is about an order of magnitude more than that of the DDD and LDD devices (0.2%). The DDD devices, although they have the largest I sub values, have final degradations between the LDD and standard devices. This experimental data confirms the simulated trends in peak E , IslLb, and Id,,,

shown in Table I. The vastly different drain designs may produce devices with

degradation versus time curves having much different slopes and intercepts, If this is the case, the final degradation WL- data of Fig. 12 may be misleading. Fig. 13 presents long term (62 h) package level HCI data for nMOS devices from the firct DDD drain design. The lifetime is defined as the time to 10% change in the linear I,, and a least squares fit is shown. The data compares favorably to that of the process's nLDD (5E13@25) nMOSFET (data not shown), indicating that this drain design will not adversely effect hot-carrier lifetimes.

The DDD optimization in the second experiment was as-

lsub Dk contours [~.tA/pm]

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60

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4 5 6 7 a Dose [ 1 El 4/cm2]

Fig. 15. the DDD implant condition for 10/0.45 nMOS transistors from lot no. 2.

Contour plot of the average peak substrate current at stress versus

sessed for HCI reliability using the 1000 s version of the WL HCI test. We increased the test time and the stress voltage to give larger degradation in these DDD devices, which we know from the first experiment, have much longer HCI lifetimes. It also allows us to monitor saturation Id,5, which is a key parameter in digital logic applications.

Fig. 14 shows the saturation Id,5 (Vd = Vg = 3.3 V) lifetime as a function of substrate current at stress. The lifetime is defined as a 5% change in saturation Ids. Time to 10% linear I d , degradation shows little appreciable difference in relative lifetime trends. Devices with larger dose show larger substrate current and Isub/Ids ratio because their junctions are more abrupt (see Table I1 for a summary of these values). Fig. 15 shows the contour plot of Isub/W at stress, while Table I1 lists I s u b at Vd, = 3.6 V for different implant conditions. As one can see from Fig. 15, implant energy has less of an effect on Isub and lifetime than implant dose.

In terms of HCI reliability, there is not much difference in lifetimes between the splits. But since the lower dose devices have a lower Isub at V d = 3.3 V, they would have better HCI reliability at operating conditions.

IV. DEVICE OPTIMIZATION The primary goal of this project was to develop a low

cost, ESD-robust I/O nMOSFET design compatible with the existing 0.35 km process flow. The data presented above indicated that none of the nLDD drain designs investigated was capable of meeting the ESDEOS goal except for the nonsilicided devices. Due to cost and timing considerations the silicide-block option was no longer considered. The DDD nMOSFET designs achieved the ESDEOS goal, required only one additional masking step, and were fully compatible with the thermal cycles in place.

The selection of the optimum DDD device design was done using desirability analysis techniques [ 1 11, [ 121. This technique uses the desired process performance (minimum, target, maximum) for a given electrical parameter in order to

998 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 6 , JUNE 1996

Desirability contours [a.u.] 65

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Fig. 16. of the phosphorus implant conditions.

Contour plot of total desirability for DDD nMOSFET’s as a function

define the parameter’s desirability function. The function is then used to normalize the measured values of the parameter such that a value of 0 indicates an unacceptable response while a value of 1 indicates and optimum response. The general form for a desirability function is given by

where T and s are parameters (typically within 0.1 and 10) that control the shape of the desirability functions, and ymln. yopt, and ymax are the minimum, optimum, and maximum specs, respectively for the parameter under optimization y. The overall desirability is defined as a geometric mean of desirability functions of each parameter. The total desirability function ( D T ) used for the DDD nMOSFET design was

where D( ) are the individual desirability functions, I,,, is the MOSFET drain current, I o f f is the off-state leakage current, IQ is the second breakdown current, Isub is the peak substrate current, and HCTlt is the HCI reliability constraint measured in terms of the forward saturation current lifetime.

Fig. 16 is a plot of the DDD nMOSFET total desirability function. The figure indicates that the device design which best meets all the design constraints corresponds to the 5E14@60 phosphorus implant condition. The overall desirability was found to be most sensitive to the HCI lifetime constraint. If this constraint could be relaxed, then desirability of the nMOSFET’s fabricated with implant energies lower than 55 keV would increase substantially. Similar behavior of the

overall desirability was observed when the IS,b constraint is relaxed. Finally, it was also found that the desirability penalty increases as the implant dose decreases if more demanding drive current constraints are imposed.

V. CONCLLJSIONS

In this paper we have analyzed two different approaches to building-in ESDEOS reliability for advanced CMOS processes. Particularly, we investigated nLDD-like and DDD drain designs as well as a silicide-block option.

In terms of drain designs, simulation was used to design the experiments using a set of technology constraints. From the EOSESD point of view the selection criteria for the implant conditions was based on reducing the peak power and current density under snapback conditions. Two experimental lots were run and it was found that the DDD drain style provided a wider design window where performance, HCl and EOSESD reliability constraints could all be satisfied. Among the splits that we ran, the DDD with a 5E14@60 phosphorus implant after side-wall spacer etch was the device design of choice. Note also that the results presented in this work regarding the second breakdown current agree with the findings in [I31 for a similar technology.

It was found that silicide-block is also a feasible alternative to building- in EOSESD reliability in a process. Furthermore, it was demonstrated that using asymmetrical draidsource contacting schemes substantially improves the ESDEOS performance over the conventional symmetrical designs. Note also that the required CGS values for nonsilicided devices are detrimental to the device performance under normal operating conditions.

This work rendered an ESDEOS robust 0.35 pm process that supports two types of nMOSFET designs, namely the standard high performance nLDD transistor with 0.35 pm minimum physical channel length and a performance competitive, ESDEOS robust I/O nMOS DDD device with 0.4Spm minimum physical gate length.

Finally, this work also demonstrated that wafer-level EOS (pulsed) testing does correlate with package-level HBM-ESD measurements for nMOS transistors. The correlation is an indication that both stress methods induce the same failure mechanism. For this to be the case, i t is important that rise- times of the wafer-level EOS waveforms match those of the HBM-ESD test system.

ACKNOWLEDGMENT

The authors are grateful to Dr. C.-H. Lin, Dr. P. Vande Voorde, Dr. D. Vook, and Dr. K. Young for many helpful dis- cussions and comments. The authors also acknowledge the fab and test support provided by K. Felix, Dr. B. Langley, and U. Yoon. The authors appreciate the continuous encouragement and advice of Dr. K. Chiu and Dr. A. Wang.

REFERENCES

[l] C. Duvvury, R. Rountree, Y. Fong, and R. McPhee, “ESD phenomena and protection issues in CMOS output buffers,” in Proc. ZEEE h t . Reliability Physics Syrrp., 1987, pp. 174-179.

DfAZ e t al.: BUILDING-IN ESDEOS RELIABlLITY FOR SUB-HALFMICRON CM(

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)S PROCESSES 999

Carlos H. Diaz (S’90-M’93) received the B S and M S degrees in electrical engineering, and the B S degree in physics from Universidad de Los Andes, BogotB, Colombia, in 1983, 1985, and 1984, respectively He received the Ph D degree in electrical engineering from the Univeryity of Illinois at Urbana-Champaign in May 1993.

In 1986, he joined the faculty of the Universidad de Los Andes as d professor in the Department of Electrical Engineering From 1988 to 1989, he was the Undersecretary of Information Sciencea in the

Presidencia de la Repliblica de Colombia. He was a rebearch assistant at the Coordinated Science Laboratory, University of Illinois at Urband-Chdmpdign from January 1990 to May 1993 He held summer positions in IC reliability at National Semiconductor Corporation, Santa Clara, CA, and Texas Instruments Incorporated, Dallas, TX, in 1990 and 1991-1992, respectively He joined the Integrated Circuits Business Division of Hewlett-Packard CO , Palo Alto, CA, in July 1993, working on IC reliability Currently, he is a member of the technical staff in the ULSI Research Laboratory, Hewlett-Packard Company, working on advanced device design and procesa integration He has published more than 15 papers in technical journals and conferences He holds two US patents.

Dr Diaz received the SRC Inventor Recognition Award in 1993 He is d member of the Asociacicin Colombiana de Ingeniero\ EICctricos, Mecinicos y Afine\ (ACIEM)

Thomas E. Kopley (M’89) received the B.S. degree in electrical engineering from the University of Rochater, Rochester, NY, in 1983 and the M.S. and Ph.D. degrees in applied physics from Yale University, New Haven, CT in 1985 and 1989, respectively.

In the summer of 1983, he worked on superconducting quantum interference devices for use as magnetic susceptometers at the IBM T. J. Watson Research Center, Yorktown Heights, NY. In 1989, he joined Hewlett-Packard’s In- tegrated Business Division R&D Center, Palo Alto, CA, where he studied hot-carrier reliability in CMOS technologies. In the spring of 1995, he was a visiting scientist in the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, where he studied AC hot-carrier effects in CMOS circuits. He is now a visiting scientist at Siemens Corporate R&D, Munich, Germany, studying sense amplifier techniques for Chit DRAM’S.

Dr. Kopley is a member of the APS.

Paul J. Marcoux (M’79) received the B.S. degree in chemistry from Vil- lanova University, Villanova, PA, and Ph.D. in chemistry from Kansas State University, Manhattan.

He joined Hewlett Packard Company, Palo Alto, CA, in 1978. He has worked in the areas of plasma processing: etch, end point detection for plasma etching and dielectric deposition. He developed multilevel metal processes for submicron CMOS processes. He worked in the area of yield improvement in submicron CMOS. He is presently manager of the reliability physics department, which is also the area of his research interests. He has published more than 30 research papers.

Building-in ESD/EOS reliability for sub-halfmicron CMOS processes

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