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0167-9260/$ - se

doi:10.1016/j.vl

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authors that ha�CorrespondE-mail addr

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INTEGRATION, the VLSI journal 40 (2007) 503–515

www.elsevier.com/locate/vlsi

Analysis of missing and additional cell defects in sequentialquantum-dot cellular automata$

J. Huang�, M. Momenzadeh, F. Lombardi

Department of Electrical and Computer Engineering, Northeastern University, USA

Received 27 October 2005; received in revised form 30 August 2006; accepted 30 August 2006

Abstract

The defect characterization of sequential devices and circuits, implemented by molecular quantum-dot cellular automata (QCA), is

analyzed in this paper. A RS-type flip–flop is first introduced; this flip–flop takes into account the timing issues associated with the

adiabatic switching of this technology and its requirements. It is then shown that a D-type flip–flop can be constructed with an embedded

QCA wire which extends over multiple clocking zones. The logic-level characterization of both flip–flop devices is provided. A single

additional and missing cell defect model is assumed for molecular implementation. For sequential circuits, defect characterization is

pursued. It is shown that defects affect the functionality of basic QCA devices, resulting mostly in unwanted inversion and majority voter

acting as a wire at logic level. In this paper, it is shown that a device-level characterization of the defects and faults can be consistently

extended to a circuit-level analysis.

r 2006 Elsevier B.V. All rights reserved.

Keywords: QCA; Defect; Sequential circuit; Emerging technology

1. Introduction

In recent years, so-called emerging technologies havebeen investigated to implement new computational para-digms with extremely small feature size and very highdevice density. One of the promising emerging technologiesis quantum-dot cellular automata (QCA) [2]. QCA relies onnovel design concepts to exploit new physical phenomena(such as Coulombic interactions), and implement uniqueparadigms (such as memory-in-motion and processing-by-

wire [3,4]). In QCA, gates (such as the inverter, INV andmajority voter, MV) and other devices (such as the binarywire and the INV chain) have been proposed as primitivesfor INV combinational circuit design. As a combinedmethodology for computation and communication [3,5],various designs of combinational as well as memorycircuits have been proposed for QCA implementation

e front matter r 2006 Elsevier B.V. All rights reserved.

si.2006.08.001

script is an extended version of the paper by the same

s appeared in [1].

ing author. Tel.: +1617 373 7780; fax: +1 617 373 8970.

esses: hjing@ece.neu.edu (J. Huang), mmomenza@ece.-

omenzadeh), lombardi@ece.neu.edu (F. Lombardi).

[3,6,7]. Recent developments in QCA manufacturinginvolve molecular implementations [8]. It is anticipatedthat either self-assembly, or large scale cell deposition oninsulated substrates will be utilized for manufacturing.QCA cells are arranged in a dense layout and computationoccurs among adjacent cells [9].Defect tolerance and characterization of QCA for metal

and molecular implementations have been reported in earlyworks [10–12]. Ref. [11] has analyzed the effects of missingcell defects on a QCA wire that has been assembled by amolecular implementation. While an extensive literatureexists on combinational and memory systems [3,7,13],sequential circuits in QCA have not received muchattention. Recently, a methodology for designing sequen-tial circuits in QCA has been proposed [14]. Thismethodology relies on a timing and synchronizationprocedure in its operation to allow the paradigm ofprocessing-by-wire of QCA to be readily incorporated intoa sequential design. This methodology is also applicable toa CAD environment because it can be readily mapped to aconsistent maximum path problem for delay matching inthe underlying graph model of the QCA circuit [14].

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InverterMajority Voter

B

C

A

F=AB+AC+BC

Binary Wire

Inverter Chain

(a)

(c)

(d)

(b)

Fig. 1. Basic QCA devices.

J. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515504

This paper analyzes the defect characterization ofsequential devices and circuits for a molecular implementa-tion of QCA. Initially, a novel RS-type flip–flop (FF)amenable to a QCA implementation is proposed. This FFextends the threshold-based configuration of [15] to QCAby taking into account the timing issues associated with theadiabatic switching of this technology. Using a defectmodel by which single additional and missing cells areconsidered in a molecular implementation [11], simulationresults are provided for a logic-level characterization of thedefects. This analysis is also presented for QCA sequentialcircuits. Using a semaphore as an example, the injection ofmolecular-based defects is pursued. Using the so-calledtime stretching technique of [14], it is shown that sequentialdesign can be also accomplished using QCA wires asequivalent to D-type FFs. Also for sequential circuits,defects are shown to affect the functionality of basic QCAdevices, resulting mostly in unwanted inversion andmalfunctioning MV (becoming a wire) behavior at logiclevel. This characterization is extended to sequentialcircuits in QCA; it is shown that under a single cell defectmodel, the behavior of defective circuits can be consistentlyestablished by using a device-level analysis.

This paper is organized as follows: Section 2 describesthe basic preliminaries inclusive of QCA technology,timing and defect model. Section 3 reviews the previousworks on sequential devices in QCA. A QCA FF isproposed. Section 4 presents the defect characterization ofthe RS FF, while Section 5 extends the defect analysis tosequential circuits, such as the semaphore and the lock.Discussion of the results and conclusion are given inSection 6.

2. Preliminaries

A QCA cell can be viewed as a set of four chargecontainers or ‘‘dots’’, positioned at the corners of a square.The cell contains two extra mobile electrons that canquantum mechanically tunnel between dots, but not cells.The electrons are forced to the corner positions byCoulombic repulsion. The two possible polarization statesrepresent logic ‘‘0’’ and logic ‘‘1’’. Unlike conventionallogic circuits in which information is transferred byelectrical current, QCA operates by the Coulombicinteraction that connects the state of one cell to the stateof its neighbors. This results in a technology in whichinformation transfer (interconnection) is the same asinformation transformation (logic manipulation).

One of the basic logic gates in QCA is the MV with logicfunction MajðA;B;CÞ ¼ ABþ AC þ BC. MV can berealized by five QCA cells, as shown in Fig. 1(b). LogicAND and OR functions can be implemented from the MVby setting an input (the so-called programming or control

input) permanently to logic 0 or logic 1. The INV is theother basic gate in QCA and is shown in Fig. 1(a). Thebinary wire and INV chain (as interconnect fabric) areshown in Fig. 1(c) and (d).

Two types of switching arrangement are possible in theoperation of QCA: abrupt switching and adiabatic switch-

ing. In abrupt switching, the inputs to the QCA circuitchange suddenly and the circuit can be in an excited state;subsequently, the QCA circuit is relaxed to ground state bydissipating energy to the environment [16]. This inelasticrelaxation is rather uncontrolled and may cause the QCAcircuit to enter a metastable state (that is determined by alocal, rather than a global energy ground state). Therefore,adiabatic switching is usually preferred. In adiabaticswitching, the system is always kept in its instantaneous

ground state.A clock signal is introduced to ensure adiabatic switching

of QCA. The clock signals for QCA generate an electricfield that is applied to the cells to either raise, or lower thetunneling barrier between dots of a QCA cell. When thebarrier is low, the cells are in a non-polarized state; whenthe barrier is high, the cells are not allowed to change state.Adiabatic switching is achieved by lowering the barrier,removing the previous input, applying the current inputand then raising the barrier [16]. If transitions are carriedout gradually, the QCA system will remain close to theground state.This clocking scheme that was introduced in [16],

consists of four phases: switch, hold, release and relax, asshown in Fig. 2(a). The QCA circuit is partitioned into so-called clocking zones, such that all cells in a zone arecontrolled by the same clock signal. Cells in each zoneperform a specific calculation; the state of a zone is thenfixed so that it can serve as input signals to the next zone[4]. At the beginning of the switch phase, the cells in a zoneare in an unpolarized state. During the switch phase, thebarrier is raised, and the cells in a zone begin to polarizeaccording to the value of the input (as provided by theoutput of the previous zone). At the same time, theadjacent zone is in an unpolarized state, thus not affectingthe computational state. Then, the cells are placed in thehold phase, in which the barrier is sufficiently high suchthat the state is unchanged and can be used as input to thenext zone. After lowering the barrier, the cells are placed in

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Switch Hold Release Relax

E f

ield

bar

rier

Time

Time

Sign

al tr

ansf

er

subarray4clockzone4

subarray3clockzone3

subarray2clockzone2

clockzone1subarray1

Switching of a Binary Wire

fixed polarizationinput

4 Phase Clocking(a)

(b)

Fig. 2. Clocking in QCA.

J. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515 505

a release phase in which they relax to an unpolarized state.The last clock phase is the relax phase in which the cells areagain unpolarized. The QCA binary wire in Fig. 2(b) canbe used to illustrate this clocking scheme. Initially,subarray1 is switching as according to the fixed input.Then, subarray1 enters the hold phase; at this time,subarray2 starts switching. As subarray3 is in the relaxedstate, then it will not influence the computational state ofsubarray2. At the next phase, subarray1 is moved to arelease phase; subarray2 is in the hold state and providesthe input to subarray3 (that is in the switch phase). Thus,information transfers in a pipelined fashion. The clocksignals (through an induced electric field) can be generatedby CMOS wires embedded below the QCA plane [16].

Clocking not only permits control of the informationflow, but it also provides true power gain to QCA devices.As information moves from cell to cell, signal energy is lostto the environment due to dissipative processes. In clockedQCA, this energy is originated from the clock with no flowof current. The four phased clocking scheme has been usedfor designing various QCA combinational circuits [5,7,13].In a clocked QCA circuit, information is transferred andprocessed in a pipelined fashion. All cells within the samezone are allowed to switch simultaneously, while cells indifferent zones are isolated. Consider the binary wire inFig. 2(b); initially, subarray1 switches according to thefixed input, and subarray2 shows no definite polarization at

this time. The signal is ‘‘latched’’ when subarray1 enters thehold phase and acts as input to subarray2. subarray2processes its information, i.e. effectively a latch is presentbetween the two subarrays and they perform independentcomputation in the cells.A QCA circuit operates by mapping the ground state to

the logic solution that the circuit is designed to generate[16]. In this system, thermodynamic effects must beconsidered. If thermal fluctuations excite QCA cells abovethe ground state, erroneous computation may appear at theoutputs of the circuit. For robust operation, the excitationenergy must be well above kBT , where kB is Boltzmann’sconstant and T is the operating temperature. As cell sizedecreases using molecular implementations [17], then theenergy separation between states increases and highertemperature operation is possible [17].Thermodynamic effects thus impose limitation on the

number of cells that can operate correctly in a QCA circuit.Consider a binary wire of N cells. Let Ekink be the energyrequired for a QCA cell to be affected by kink (i.e. to aligndifferently from its expected polarization). As Ekink isindependent of location, then for large values of N, Ekink

remains the same while the number of kinks increases. Somultiple kinks may be possible [16]. Therefore, theprobability of having kink is a function of N. As shownin [16], for fixed values of T and Ekink, the maximumnumber of cells in a zone of the layout to prevent kink tooccur is given by expEkink=kBT ; therefore, a QCA circuitmust be partitioned into smaller subsystems (or zones) toreduce the value of N.A model that characterizes defects in QCA devices and

circuits, must consider [18] the unique fabrication andassembly processes of this technology such as at molecularlevel [11]. According to [9], in the present stage of QCAmanufacturing, defects are possible in both the synthesisphase, in which the individual cells (molecules) aremanufactured, and the deposition phase in which the cellsare placed in a specific location on the surface. Manufac-turing defects may cause a cell to have missing or extra dotsor/and electrons. These defects are fatal to the correctoperation of a QCA cell and easy to detect. However,defects are much more likely to occur in the depositionprocess than in the synthesis process. These defects areusually categorized as cell misplacement. A missing dot (oradditional dot) is very unlikely due to the ease ofpurification of small inorganic molecules [9]. For example,nuclear magnetic resonance (NMR) has an estimatedminimum purity of 99% for model compounds such asthe Creutz-Taube (CT) Ion (a two-dot model or dipole forhalf of a QCA cell). Moreover, electrochemical measure-ments for the CT Ion have shown that fewer than onemolecule in 105 are in the incorrect charge state [19]. Yetplacing the individual cells during deposition is difficult,various types of cell misplacement may occur (such as cellmisalignment, missing cell, additional cell, etc.).

Molecular QCA presents unique challenges [11]: bondingof the array surface requires complexes by spectroscopic

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0

R

Q_old

1

0

Q_old1 1

01

0

0

Q

S

Q

QbarMVR

1

S

Fig. 3. Schematic diagram of the QCA RS flip–flop.

J. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515506

and electrochemical techniques [17]; moreover, the pre-sence of strongly bound, chemically robust, mixed valencecomplexes in the required chemistry has been extensivelytreated. Perturbation of the chemical complex by surfacebinding using a gold electrode by an electrochemicalmethod has been investigated resulting in an assembly ofbiased, vertically oriented two-dot structures (dipole)sandwiched between two electrodes [17]. The assembly ofa symmetric square cell containing two ferrocene and twoferrocenium moieties with measured properties that makeit suitable as a component for charge-coupled QCA circuitshas been shown in [19]. However, deposition defects arestill widely reported and they must be carefully consideredbecause they may affect the correct operation of QCAcircuits. This has a stronger influence when a celldeposition defect occurs either within or very near to adevice, thus creating unwanted interactions [18].

In this paper the following types of single cell depositiondefect are considered for a molecular implementation ofQCA [20]:

�

An extra or additional cell is a defect in which anadditional cell is deposited on the substrate; this extracell is erroneously deposited along the device perimeter(adjacency boundary) of the original (defect-free)configuration. � In a missing cell deposition defect, a particular cell is

missing in the original (defect-free) configuration of thedevice or circuit [11].

A single cell defect is assumed at circuit level as well. Theanalysis hereby presented considers QCA cells to be grownover a Cartesian plane. In a molecular implementation,three-dimensional (3D or volumetric) growth is possible[17]. The proposed analysis can be extended also to the 3Dcase with no loss of correctness. Through simulation, asingle defect is injected in each device; subsequently, eachof these defects is mapped to logic-level faults in theoperation of the QCA devices and circuits. All simulationshave been performed using QCADesigner V1.4.0 [21] withits coherence vector engine. QCA cell size is set to be2 nm� 2 nm with dot size of 0:25 nm. The cell-to-celldistance used is 0:25 nm. These values were selected inaccordance with molecular QCA technology [8]. The radiusof effect of the simulator is set to 8 nm.

3. RS FF and sequential design in QCA

Initially in this section, the novel QCA design of a RSFF is presented. This new device is shown in Fig. 3 andrepresents a novel QCA extension of the original schemegiven in [15]. The basic component in the RS FF is the MV.If the setting input S is 1 and the resetting input R is 0, thenthe stored value of the FF is 1. The output value is changedto 0 if R is 1 and S is 0. When both S and R have the samevalue, then the output value remains unchanged. Fig. 4shows the QCA layout of the RS FF. The threshold based

scheme of [15] requires a three-phase synchronizationprocess; although it is possible to use three-phasesynchronization in QCA, the traditional (four-phase)clocking scheme is employed (in QCA a clock cyclerequires four clocking zones). In this design, the numberof phases for synchronization is limited by the inner loop inthe RS FF. The delay of the inner loop must be a multipleof a full clock cycle, i.e. the number of clocking zones in theinner loop must be a multiple of four. In this case, the oldvalue of Q can be made available during the nextcomputation, i.e. after k full clock cycles (where k is aninteger). In the RS FF of Fig. 4, the x and y coordinates areused to identify the QCA cells in the Cartesian layout. Theinner loop of the FF has a delay of one clock cycle;therefore at the output, Q is available six clocking zonesafter R and S have been applied.The proposed FF represents the basic device by which

sequential designs can be built in QCA. In conventionallogic design, synchronous operation is usually implementedin a sequential circuit. This circuit can be represented by aMealy machine that consists of two parts: the FFs and thecombinational logic. This general model can also be usedfor a QCA implementation of sequential logic [14].However, in QCA the four-phase clock signals controlnot only the FFs, but also the combinational gates. Asdescribed previously, the entire QCA circuit is pipelinedand latched by the clock signals. An important timingconstraint in a QCA design is that for every logic gate allinputs must arrive at the same time, i.e. all inputs must bein the same clocking zone (time matching). In synchronoussequential logic, all FFs compute at the same time;therefore when designing this type of circuit in QCA, it isnecessary to ensure that all paths from the outputs of theFFs (passing through the combinational logic) to theinputs of the FFs have the same delay (i.e. the number ofclocking zones), thus enforcing the condition that signalsarrive at the inputs of the FFs at the same time (strictmatching).This timing constraint is illustrated in the example

shown in Fig. 5. This circuit is a 2-bit Grey code counterwhose state transition diagram is shown in Fig. 5. Two RSFFs are employed in the design. For the two FFs tocompute at the same time, MV1 and MV2 must be placedin the same clocking zone, i.e. Q1 and Q2 are also in the

ARTICLE IN PRESS

MV2Q1Q2=10 Q1Q2=01

Q1Q2=11

Q1Q2=00

MV1

RSFF2

RSFF1

S1

R2

S2

p1

p2

p3

p4

p6

p5

Q2

Q1

R1RESET

Fig. 5. Schematic diagram of devices in QCA 2-bit grey code counter.

R

S

1 2 4 76 9 12 13 14 15 16 17 18 19 20 21

1

2

3

4

5

8

9

12

1110

11

7

0 1Clocking Zone

Q

Qbar

3 5 8

2 3

Fig. 4. QCA layout of the RS flip–flop.

P= 1

RESET

Q2

Q1

Clock Zone0 1 2 3

Fig. 6. QCA layout of 2-bit grey code counter.

J. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515 507

same clocking zone. The timing constraint that must beapplicable for correct sequentiality, consists of ensuringthat for each MV, all three inputs must arrive at the sametime. This corresponds to the condition by which the pathsp1, p2, p3, p4, p5 and p6 must have the same delay (givenby the number of clocking zones). Two of these paths (p1and p2) are the inner (feedback) loops of the RS FF. As theinner loop must have a delay that is a multiple of the clockcycle (one clock cycle consists of four clocking zones), thena timing arrangement must be implemented in QCA design.

The RS FF shown in Fig. 3 has one clock cycle delay forthe inner loop. However, the number of QCA cells that can

be placed in the same clocking zone, is bounded. In acomplex design, a path that goes through a number ofcombinational logic gates, may require more than oneclock cycle. In this case, the delay is determined by thelongest path; the other paths must be increased through aso-called stretching process by which these paths match thedelay (including the inner loops of the FFs). If all pathshave a delay of k cycles, then a valid output will beproduced every k cycles.

ARTICLE IN PRESSJ. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515508

As an example, consider again the 2-bit Grey codecounter of Fig. 5. When RESET ¼ 0, Q1Q2 ¼ 11; whenRESET ¼ 1, Q1Q2 counts the Grey code sequence: 00!01! 11! 10! 00::::::: Two RS FFs and one AND gateare used in this design. The corresponding QCA layout isshown in Fig. 6, where the active devices (MVs) arehighlighted by dotted squares. There are six paths (asindicated in the schematic diagram) with a delay of one fullclock cycle. As all paths can be routed using only one clockcycle, no stretching of the paths is needed for delaymatching.

The details of the clock zone assignment (clock floor-planning) have been described in our companion paper[14]. The paper first identifies the unique timing constraintsin QCA sequential logic design. An algorithm for assigningappropriate clocking zones to a QCA sequential circuit is

Table 1

Test sequence for RS flip–flop

Current state Qn Test vector (RS) Operation

d 01 Set

1 00 Hold 1

1 11 Hold 1

1 10 Reset

0 00 Hold 0

0 11 Hold 0

0 01 Set 1

1 d Check next state Qnþ1

Fig. 7. QCA RS flip–fl

then proposed. A technique referred to as stretching is usedin the algorithm to ensure timing and delay matching. Thisalgorithm relies on a topological sorting and enumerationstep to consistently traversing only once the edges of thegraph representation of the QCA sequential circuit.Examples of QCA sequential circuits are provided in [14].

4. Defect characterization of the RS FF

Single missing and additional cell defects are analyzed inthis section for the QCA RS FF of the previous section.The layout of Fig. 4 is used.For detecting the effects of a defect, a test sequence is

utilized; at logic level, this sequence detects stuck-at faults(s-at-1, s-at-0) and up/down transition faults (";#). Thetest pattern for the RS FF is shown in Table 1. It has beenshown in our previous work [10] that at physical level,defects in QCA devices and combination circuits cannot beaccurately modeled by stuck-at faults. In many cases, QCAdefect behaves as unwanted inversion [10]. For example,defect may turn a QCA wire into an INV. However, it isshown that test sets developed based on the stuck-at (s-at-0/1) fault set have excellent coverage of actual QCA defects[10]. Therefore in this paper, the test sequence of Table 1 isused. As the initial value of the RS FF (Q0) is not known,the input value RS ¼ 01 is utilized for setting Q to 1. Thevectors RS ¼ 00 and RS ¼ 11 test for a # transition fault.Note that RS ¼ 00 (or RS ¼ 11) can also detect the s-at-1fault of the output. The vector RS ¼ 00 tests for a s-at-1

op (fault-free case).

ARTICLE IN PRESSJ. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515 509

fault at the R input, because this fault is not detectable bythe first test vector RS ¼ 01 (Q could be 1). With Qn ¼ 1,RS ¼ 10 detects s-at-1 and RS ¼ 00 and RS ¼ 11 test forany " transition fault. Therefore, if the previous tests(RS ¼ 00 or RS ¼ 11 with Qn ¼ 1) result in a s-at-1 fault atthe output, the next tests (RS ¼ 00 and RS ¼ 11) willdetect these stuck-at faults. Finally, RS is given by 01 totest for a s-at-0 fault. Fig. 7 shows the fault-free simulationresults using the test sequence. It can be seen that in thefault-free case, the circuit behaves as an RS FF, accordingto the state transition table in Fig. 3.

As per the assumed model (applicable to molecularimplementations [1,11]), single missing and additional celldefects have been simulated. The RS FF block diagramshown in Fig. 8 is used. The simulation results (at faulty

INV1 INV2

L shaped

Wire4

L shaped

Wire2

L shaped

Wire3

L shaped

Wire1R Q_bar

MV Fanout QS

F1

F3

Fig. 8. Schematic diagram of devices in QCA RS flip–flop.

Table 2

Simulation results for RS FF, single missing cell defect

Faulty device Missing cell Output, fault-free

INV1 4; 9 d1011011

INV1 4; 10 d1011011

INV1 4; 11 d1011011

MV 9; 5 d1010011

MV 9; 6 d1010011

MV 9; 7 d0010010

L-shaped 1 9,10 d0011011

L-shaped 2 or 4 9; 2 or 14; 2 d1010101

L-shaped 3 14; 10 d1110001, Qbarn

Fanout 14; 6 d1010101, Qbarn

INV2 17; 9 d1110001, Qbarn

INV2 17; 10 d1110001, Qbarn

INV2 17; 11 d1110001, Qbarn

Table 3

Simulation results for RS flip–flop, single additional cell defect

Faulty device Additional cell Outpu

INV1 6; 10 d10110

INV1 7; 9 d10110

INV1 7; 11 d10110

INV2 19; 10 d11100

INV2 20; 9 d11100

INV2 20; 11 d11100

sites given by the different devices) are shown in Table 2 (ddenotes ‘‘don’t care’’). All other single missing cell defects(not reported in this table) result in no faulty output. Notethat in the table A0 denotes the logic inverse of A. Singleadditional cell defects have also been simulated; the resultswhich cause an erroneous output, are presented in Table 3.All additional cell defects not reported in the table result infault-free output. It can be seen from these results thatdefects at the INV and L-shape wire behave as unwantedinversion at logic level. A defective MV behaves either as awire or performs the MV function with an unwantedinversion at some inputs. These results are in agreementwith our previous defect characterization on individualQCA devices and combinational circuits published in [10].

5. Defect characterization of QCA sequential circuits

In this section, the defect characterization of sequentialcircuits designed using QCA FFs are presented; twoexamples are provided.A sequential circuit in QCA relies on the paradigm of

memory-in-motion through devices such as the RS-type FFof the previous section. Memory-in-motion employs QCAwires to store information over multiple clocking zones inthe QCA layout. For memory-in-motion, data are circu-

lated in a loop, so the same defect may have different

implications on the operation of a QCA circuit. In the

: Qn ¼ d1110001 Fault

INV1 behaves as a wire

INV1 behaves as a wire

INV1 behaves as a wire

MV as a horizontal wire

MV as a horizontal wire

Extra INVs at the vertical inputs of MV

MV performs Maj(A0;B;C0)Extra INV in L-shaped 1

Extra INV in L-shaped 2/4

¼ Qn Extra INV in L-shaped 3

¼ Qn Extra INV for F1 and F3

¼ Qn INV2 behaves as a wire

¼ Qn INV2 behaves as a wire

¼ Qn INV2 behaves as a wire

t, fault-free: Qn ¼ d1110001 Fault

11 INV1 behaves as a wire

11 INV1 behaves as a wire

11 INV1 behaves as a wire

01, Qbarn ¼ Qn INV2 behaves as a wire

01, Qbarn ¼ Qn INV2 behaves as a wire

01, Qbarn ¼ Qn INV2 behaves as a wire

ARTICLE IN PRESS

P=1

w

Clock Zone0 1 2 3

Fig. 10. QCA layout of the semaphore.

J. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515510

presence of a cell defect (as assumed in this paper), thebehavior of a QCA sequential circuit must be analyzedtogether with its timing features: clocking through thezones basically achieves latching of logic values. Hence,differently from combinational circuits an additional ormissing cell defect can result in an erroneous signal (due toa new functionality of a device) to be propagated only aftera delay. This means that robustness of the QCA circuit is afunction of the layout and its timing organization. Twoexamples of sequential circuits in QCA are analyzed next.

Semaphore: The first circuit is the so-called semaphore ascommonly used for resource access. This circuit has beenpresented in our previous paper [1]. The schematic diagramand the state transition diagram of the semaphore areshown in Fig. 9. w is the input signal, w ¼ 1 denotes arequest for resource access, while w ¼ 0 denotes no request.Q ¼ 0 denotes a granted access, while Q ¼ 1 denotes thatthe resource is being accessed. This circuit operates asfollows: (1) when the resource is released (Q ¼ 0), and thereis a request for access, the request will be granted; next, theresource is accessed (Q ¼ 1). If no request is present, theresource remains in the non-accessed (or released) state; (2)when the resource is accessed (Q ¼ 1), next the resource isreleased (Q ¼ 0) to wait for the next request. Thecorresponding QCA layout is shown in Fig. 10; the activedevices (MVs) are highlighted by dotted squares. In thislayout, p3 is the longest path and its delay consists of twoclock cycles. As per the timing constraint discussedpreviously, paths p1 and p2 are stretched to two clockcycles, such that the three paths will have the same delay(strict matching).

In this particular case, stretching is not strictly required;as the top input of the MV in the RS FF is Q and thebottom input is Q0 (where Q0 is the logic inverse of Q), thendue to the voting nature of the MV, the top and bottominputs complement each other. Therefore, the output of theMV follows the horizontal input and as long as p1 and p2have the same delay, the circuit will function correctly. TheMV basically operates as a wire, so it is possible to removep1 and p2 by replacing the MV in the RS FF with a QCA

W

MV1

RSFF

p1

p2

p3

W=1

W=0

W=1,0

Q=1Q=0

Fig. 9. Schematic diagram of the QCA semaphore.

wire without changing the functionality of the circuit. Theresulting QCA layout is shown in Fig. 11(a); the circuitconsists of a QCA loop with one INV and one OR gate.Simulation has confirmed that this circuit operates asdesired. Moreover, this layout can be further simplified tooperate within a single full clock cycle, i.e. a valid output isproduced every clock cycle. This new circuit is shown inFig. 11(b); this circuit effectively shows that in QCA, abinary wire traversing zones in one full clock cycle (fourclocking zones) behaves as a D-type FF. This is the simplest

instance of processing-by-wire as D is propagated to Q

every clock cycle. Hence, the design shown in Fig. 11 is alsoan example of designing a sequential circuit using a QCAD-type FF. Note that here inversion is achieved with twocells (cell (2,7) and cell (3,8)) placed in a 45� orientationinstead of using the INV gate. This arrangement reducesarea overhead, however, it is not as defect tolerant as theINV gate. The choice of a particular QCA structure forachieving inversion relies on a tradeoff between defectavoidance and area overhead.Single missing as well as additional cell defects have been

simulated. For the semaphore shown in Fig. 11(b), defectswere injected using the x and y coordinates of the celllayout. The results are given in Table 4. All cell defects not

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P=1

W

Q

1 2 4 76 9

1

2

3

4

5

8

9

7 Q

P=1

6

W

0 1

Clock Zone

3 5 8

2 3

(a) (b)

Fig. 11. Simplified QCA layout of the semaphore.

Table 4

Simulation results for single missing and additional cell defect in semaphore

Missing cell Output Q Comment

Input W ¼ 1100; 0001; 1; Fault-free output Q ¼ 0010; 1010; 02; 7 0000; 0010; 0 Signal unable to propagate through the gap

3; 8 0000; 0010; 0 Signal unable to propagate through the gap

4; 8 0000; 0000; 0 Signal unable to propagate through the gap

5; 8 0000; 0000; 0 Signal unable to propagate through the gap

6; 8 1111; 1111; 1 Additional INV in the loop

6; 5 0000; 0000; 0 MV acts as a horizontal wire, MV output s-at-1

6; 4 0000; 0000; 0 Extra INVs at the vertical inputs of MV

6; 3 0000; 0000; 0 MV acts as a horizontal wire, MV output s-at-1

2; 4 1111; 1111; 1 Extra INV in the loop

Additional cell Output Q Comment

2; 8 1111; 1111; 1 Missing INV in the loop

J. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515 511

reported in the table result in fault-free output. The testsequence that has been applied for fault detection in thepresence of a single defect, is given by W ¼ 110000011.The first vector resets the circuit to Q ¼ 0 using W ¼ 11.Then, the sequence W ¼ 00000 is used to test the circuit’soperation to toggle between Q ¼ 0 and Q ¼ 1. Finally,W ¼ 11 resets the circuit to Q ¼ 0. From the results inTable 4 it can be seen that again many QCA defects behaveas unwanted inversion at logic level. The defect in whichthe MV behaves as a wire (i.e. it follows the horizontalinput) is again observed, that confirms our previous resultsin [10].

Lock: As a second example, consider the QCA imple-mentation of the so-called lock; this circuit effectivelytoggles between two states until it remains in a lockedposition (as dependent on the input signal w ¼ 1). Theinitial state is defined by the signal Reset ¼ 1. The output isforced to 0 when Reset ¼ 1. The schematic and the statetransition diagram are shown in Fig. 12. One D-type FF,

two AND gates and one OR gate are used; the QCA layoutis shown in Fig. 13.Single missing/additional cell defects have also been

considered for the lock. The test sequence is given byReset ¼ 0011; 1111; 1111; 11 and W ¼ 1111; 0011; 0000;0000; 11. As this circuit has a delay of two clock cycles, avalid input is applied every two cycles (and therefore, avalid output is also observed every two cycles). Initially, thetest sequence resets the circuit to Q ¼ 0 by Reset ¼ 00.Then, W ¼ 11 forces the circuit to lock on Q ¼ 0. Then,W ¼ 00 causes the circuit to toggle to Q ¼ 1. The circuit isthen locked on Q ¼ 1 when W ¼ 11. Therefore, W ¼

0000; 0000 is used to toggle the circuit between Q ¼ 0 and 1.Finally, W ¼ 11 locks the circuit to Q ¼ 1. The fault-freeoutput sequence is given by Q ¼ 0000; 1111; 0011; 0011; 11.The simulation waveform of the fault-free circuit is given inFig. 14, in which the valid output is generated every twocycles; the lock works as specified in the state transitiondiagram in Fig. 12. The output Q is first reset to 0, then it is

ARTICLE IN PRESSJ. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515512

forced to remain at 0 with W ¼ 11. Afterwards when W ¼

0000; 0000 Q toggles. Finally when W ¼ 11, Q is forced toremain in state 1. The simulation results for single missing/

W

Q

Q_bar

Reset

W=1 Q=0 Q=1 W=1

W=0

W=0

lock

Fig. 12. Schematic device and state diagrams of the QCA lock.

P=1

P=1W

P=1

6

10

13

14

15

16

17

18

19

20

21

22

1 2 4 76 9

1

2

3

4

5

8

9

12

1110

11

7 INV1

AND1

AND2

OR

3 5 8

Fig. 13. QCA layo

additional cell defects are shown in Table 5 (all cell defectsnot reported in this table result in a fault-free output). Notethat W 0 denotes the logic inverse of W . The results againindicate a large portion of QCA defects manifest asunwanted inversion. These include the following cases:(1) INV behaves as a wire, (2) the L-shape wire behaves asINV, (3) unwanted inversions on one or more inputs to anMV (AND gate/OR gate). Another defect that is observedfor the MV is the case when the MV behaves as a wire.When the MV is programmed to act as an AND/OR gateusing fixed polarization cells, this defect sometimesmanifests as s-a-0/s-a-1 fault at logic level.

6. Discussion and conclusion

Defect characterization of sequential QCA circuits inmolecular implementations has been pursued in this paper.It has been shown that sequential elements in QCA haveunique properties as related to processing-by-wire char-acteristics: timing in each path must be closely monitoredto synchronize all signals. Two types of FFs has beenintroduced and analyzed. A RS-type FF is constructed

Clock Zone0 1

P=1

Reset

Q_bar

Q

12 13 14 15 16 17 18

Output

INV2

AND3

2 3

ut of the lock.

ARTICLE IN PRESS

Fig. 14. Simulation results of the fault-free QCA lock.

Table 5

Single missing and additional cell defect results for the lock

Missing cell Output Q Comment

Reset input ¼ 0011,1111,1111,11; W ¼ 1111,0011,0000,0000,11; Fault-free output ¼ 0000,1111,0011,0011,11

4; 3 0111; 0011; 0000; 0000; 11 Extra INV from INV1 to AND1

3; 8 0111; 0011; 0000; 0000; 11 INV1 behaves as wire

4; 8 0111; 0011; 0000; 0000; 11 INV1 behaves as wire

5; 8 0111; 0011; 0000; 0000; 11 INV1 behaves as wire

4; 13 0110; 1001; 0101; 0101; 10 W !W 0

4; 19 0000; 1100; 1111; 1111; 00 Extra INV from W to AND1

9; 19 0000; 1100; 1100; 1100; 00 AND1 behaves as a vertical wire, output s-at-0

10; 19 0000; 1100; 1100; 1100; 00 Extra INVs at horizontal inputs of AND1

11; 19 0000; 1100; 1100; 1100; 00 AND1 behaves as a vertical wire, output s-at-0

10; 14 0111; 1111; 1111; 1111; 11 OR gate behaves as horizontal wire, output s-at-1

10; 13 0111; 1111; 1111; 1111; 11 Extra INVs at vertical inputs of OR gate

10; 12 0111; 1111; 1111; 1111; 11 OR gate behaves as wire, output s-at-1; So Q s-at-1

16; 19 0110; 0110; 0110; 0110; 01 Extra INV from AND3 to AND1

9; 3 0000; 0000; 0000; 0000; 00 AND2 behaves as a vertical wire, output s-at-0

10; 3 0000; 0000; 0000; 0000; 00 Extra INVs at horizontal inputs of AND2

11; 3 0000; 0000; 0000; 0000; 00 AND2 behaves as a vertical wire, output s-at-0

13; 14 0101; 1010; 0110; 0110; 10 AND3 behaves as a horizontal wire

13; 12 0101; 1010; 0110; 0110; 10 Extra INVs at vertical inputs of AND3

13; 13 1111; 0000; 1100; 1100; 00 AND3 behaves as a horizontal wire

15; 8 0000; 0000; 0000; 0000; 00 INV2 behaves as wire

16; 8 0000; 0000; 0000; 0000; 00 INV2 behaves as wire

17; 8 0000; 0000; 0000; 0000; 00 INV2 behaves as wire

16; 13 0110; 1001; 0101; 0101; 10 Extra INV on vertical fanout wires

16; 3 0000; 0000; 0000; 0000; 00 Extra INV from INV2 to AND2

Additional cell Output Q Comment

4; 6 0111; 0011; 0000; 0000; 11 INV1 behaves as wire

3; 5 0111; 0011; 0000; 0000; 11 INV1 behaves as wire

5; 5 0111; 0011; 0000; 0000; 11 INV1 behaves as wire

15; 5 0000; 0000; 0000; 0000; 00 INV2 behaves as wire

17; 5 0000; 0000; 0000; 0000; 00 INV2 behaves as wire

16; 6 0000; 0000; 0000; 0000; 00 INV2 behaves as wire

J. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515 513

ARTICLE IN PRESSJ. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515514

using a MV with an additional feedback path. A D-typeFF is basically a binary wire that spans multiple clockingzones. With both FFs, robust sequential design requirestight synchronization and clocking zone adjustments. Thesefeatures are also evident for characterizing defect toleranttechniques for QCA. Using a molecular-based model [20], adefect model which include a single additional or missingcell has been considered in this work. Simulation resultshave shown that in QCA devices and circuits, these defectsare mostly evidenced at logic level by stuck-at andinversion faults. For the proposed RS FF, the INVs arethe most defect sensitive devices to single additional cells.The results presented in this paper have also confirmedearlier results [10,12,18] that for the MV, the center inputsignal (B) is the strongest. It has also been shown that adefect occurring in the corner cell of the L-shaped wireresults in an erroneous inversion. It has been demonstratedthat the RS-type FF as well as the D-type FF proposed inthis paper for QCA implementation are robust and can beefficiently used in designing sequential circuits.

Sequential QCA presents unique features both inoperation and defect characterization at circuit level. Asdetailed in the presented examples, sequential circuits inthis technology require strict timing and delay matching. Insome cases, stretching must be enforced to equalize thedelay among paths. Defect characterization of sequentialelements (i.e. the FFs) in QCA has shown the same logicfaults that are encountered in basic combinational gates,such as the MV and INV. Furthermore, it has been shownthat under the assumed defect model [20] QCA sequentialcircuits have the same faulty behavior as the FF. Thischaracteristic results in logic faults that change thefunctionality of QCA devices. Overall, this paper hasdemonstrated that device-level defective behavior can beextended to circuit level; consistent results have beenobtained under the assumed single cell defect model [20].

References

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and tolerance of QCA sequential devices and circuits, in: IEEE

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[21] QCADesigner Home Page: hwww.qcadesigner.cai

Jing Huang recieved her B.S. degree in electronics

engineering from Fudan University, Shanghai,

China in 2001 and M.S. degree in electrical

engineering from Northeastern University, Bos-

ton. She is currently a Ph.D. student and research

assistant in ECE department, Northeastern Uni-

versity, Boston. Before that she has worked in the

Computer Aided Test Lab in EE Department,

Fudan University as research assistant from 1999

to 2001. She also worked for Huawei Technolo-

gies Inc. China as hardware design engineer from 2001 to 2002. Her

research interests include testing, design for testability and fault tolerance

of VLSI, reconfigurable systems and nanotechnologies.

ARTICLE IN PRESSJ. Huang et al. / INTEGRATION, the VLSI journal 40 (2007) 503–515 515

Mariam Momenzadeh was born in Tehran, Iran.

She received her B.Sc. degree in Electrical

Engineering from Sharif University of Technol-

ogy, Tehran, Iran in 1999 and M.Sc. degree in

Computer Engineering and Science from Uni-

versity of Connecticut, Storrs in 2003. She

recieved her Ph.D. degree in Electrical and

Computer Engineering department at Northeast-

ern University, Boston in 2006. Her research

interests lie in testing, design for testability and

fault tolerance issues in digital systems, ATE systems and nano-

technologies .

Fabrizio Lombardi graduated in 1977 from the

University of Essex (UK) with a B.Sc. (Hons.) in

Electronic Engineering. In 1977 he joined the

Microwave Research Unit at University College

London, where he received the Master in Micro-

waves and Modern Optics (1978), the Diploma in

Microwave Engineering (1978) and the Ph. D.

from the University of London (1982).

He is currently the holder of the International

Test Conference (ITC) Endowed Professorship at

Northeastern University, Boston. At the same Institution during the

period 1998–2004 he served as Chair of the Department of Electrical and

Computer Engineering. Prior to Northeastern University he was a faculty

member at Texas Tech University, the University of Colorado-Boulder

and Texas A&M University.

Dr. Lombardi was an Associate Editor (1996–2000) of IEEE Transac-

tions on Computers and a Distinguished Visitor of the IEEE-CS

(1990–1993). Since 2000, he has been the Associate Editor-In-Chief of

IEEE Transactions on Computers. Currently he is also an Associate

Editor of the IEEE Design and Test Magazine and a Distinguished Visitor

of the IEEE-CS; he is also the chair of the committee on nanotechnology

devices and systems of the Test Technology Technical Council of the

IEEE.

His research interests are testing and design of digital systems, quantum

computing, ATE systems, configurable/network computing, defect toler-

ance and CAD VLSI. He has extensively published in these area and

edited six books.