Advance Oscilloscope Triggering

944 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 56, NO. 3, JUNE 2007

Advance Oscilloscope TriggeringShakeb A. Khan, A. K. Agarwala, D. T. Shahani, and M. Mahfooz Alam

Abstract—In this paper, we present an advanced triggeringmethod for digital oscilloscopes for measurements involving com-plex waveforms that are challenging even today. Based on theassociative-memory technique and on utilizing a new weighted-hamming-distance parameter, this technique is capable of pro-viding stable oscilloscope triggering, even for complex waveformswhere the commonly used voltage level triggering method failsto perform adequately. The proposed technique has been verifiedby exhaustive software simulations using MATLAB and Xilinxfoundation series softwares. Furthermore, the technique has beenimplemented and validated on a XCV300EPQ240 field-program-mable gate array device and has given successful initial resultsusing several different kinds of test waveforms.

Index Terms—Associative memory, complex waveform, field-programmable gate array (FPGA), oscilloscope triggering,weighted hamming distance (whd).

I. INTRODUCTION

THE KEY to the oscilloscope’s value for viewing time-varying periodic signal waveforms is synchronization of

the horizontal sweep with the input signal, which is achieved bycorrect triggering of the sweep. For a stable continuous display,the horizontal sweep must begin at exactly the same instant(epoch) within the input signal’s period. The instant at whichthe horizontal sweep begins is normally determined by thesignal crossing a set triggering voltage level at a specified slopepolarity. Once the sweep is completed, the trigger circuit waitsfor the next trigger instant determined by the signal crossingthe set trigger level again [1], [2]. This technique works well ifthe epoch in the signal can be uniquely decided by its voltageamplitude level, where the horizontal sweep can be periodicallyinitiated. However, when the signal contains a burst of fasterasynchronous pulses embedded in the signal with a much largerrepetition period or has multiple crossings of the desired triggervoltage level within one period, then this simple method resultsin unstable triggering. Modern digital oscilloscopes offer differ-ent facilities including hold-OFF feature. The hold-OFF featurein conventional oscilloscopes works well if the signal contains asignificant portion where triggering can be avoided by suitablyadjusting the trigger level. Then, adjustment of hold-OFF timecan prevent triggering on nonsynchronous instants. The hold-OFF facility requires frequent user intervention to generate thestable triggering in case of complex waveforms, whereas the

Manuscript received June 15, 2005; revised September 24, 2006.S. A. Khan was with the Indian Institute of Technology-Delhi, New Delhi

110016, India. He is now with Jamia Millia Islamia, New Delhi 110025, India(e-mail: [email protected]).

A. K. Agarwala and D. T. Shahani are with the Indian Institute ofTechnology-Delhi, New Delhi 110016, India.

M. M. Alam is with Infineon Technologies Pvt. Ltd., Bangalore 560066,India (e-mail: [email protected]).

Digital Object Identifier 10.1109/TIM.2007.894198

Fig. 1. Example of complex waveform.

advanced triggering scheme described in this paper requiresminimum human intervention to accomplish the same function.Therefore, all existing techniques have significant limitations ingenerating repetitive trigger signals that are locked to a complexinput waveform.

With the advent of superior hardware capabilities, morerobust and, perhaps, somewhat more processing-intensive tech-niques become desirable and possible. Using a Hamming mem-ory network, the distance between the captured waveform andthe reference waveform could be measured on real-time basis,and a trigger is generated if the measured distance is within ac-ceptable range. In this paper, we propose a Hamming-memory-network-based oscilloscope-triggering technique which cancircumvent the problems associated with the level triggeringmethod. The Hamming memory network is essentially a neuralrealization of an associative memory. The output of the networkis determined by the stored vector (reference waveform) thatis nearest in hamming distance (number of differing bits) tothe input vector. The Hamming memory network is credited to[3] and [4] and was later independently discovered by severalscientists [5]–[8]. Recurrent correlation associative memoriesare discussed in [9]. In [10], an efficient single-shot algorithmto implement associative memories is described, which utilizesa two-layer feed-forward neural network.

The proposed technique is based upon detection of the wave-form’s base period, as determined by repetition of the waveformpattern, so that a trigger pulse can be generated every time thepattern repeats, thereby leading to a stable display. To achievethis objective, the concept of weighted hamming distance (whd)function has been introduced [11]. In the proposed technique,n samples of the incoming signal at a suitably chosen samplingrate are captured and stored, thus generating a reference patternvector. Subsequently, a moving window of “n” samples is suc-cessively captured, with a corresponding increment of a samplecount register, and compared with the stored reference patternvector in terms of the whd parameter, which does not involvecomplex computations. A low value of whd indicates repetitionof the input signal with respect to the reference pattern, andthe delayed sample count indicates the period of the waveform.

0018-9456/$25.00 © 2007 IEEE

KHAN et al.: ADVANCE OSCILLOSCOPE TRIGGERING 945

Fig. 2. Proposed triggering scheme as conveyor belt.

This technique has been simulated and then implemented on afield-programmable gate array (FPGA) device and successfullyverified with selected test waveforms. The robustness of thetechnique has also been evaluated by simulated addition of ran-dom noise to a test complex signal waveform and by observingjitter in the trigger generation. In all cases, the technique hasbeen proven to be robust and accurate. Simulation-based testingof the technique and hardware implementation details alongwith the validation results have been reported earlier in [11]and [12], respectively. This paper integrates the simulation andhardware testing results for the technique.

In this paper, in Section II, the advanced triggering tech-nique has been explained in brief. Simulation-based testingof the technique along with simulation results is presentedin Section III. To prove the robustness of the technique, astatistical analysis of the simulation results is presented inSection IV. The experiment setup for the hardware implemen-tation and the complete block diagram of the implementationmodules has been presented in Section V. Validation results arealso presented in Section V. Finally, Section VI summarizesand concludes this paper with a scope for future research inthis area.

II. ADVANCE TECHNIQUE FOR

OSCILLOSCOPE TRIGGERING

The conventional level triggering scheme along with itsextensions has limitations in handling complex waveforms. Onesuch waveform is shown in Fig. 1. This is basically a frequency-modulated signal with base time period of T . For a stabledisplay of this kind of signal waveform, we require a triggerpulse after every base period of T . In this case, the conventionaltechnique will generate a trigger at every point where a signalcrosses the set level in a specified direction, which will resultin more than one trigger within a base period T and, hence,an unstable display of the waveform, whereas the single shottechnique can take care of such a signal or even an aperiodicsignal, but the problem of initiating the sweep reproduciblywithin the signal’s period would remain. In this paper, we areprimarily addressing the problem for repetitive triggering.

To achieve the objective of a stable display of the abovewaveform, a trigger signal after every base time period T isrequired. Therefore, the solution lies in the detection of baserepetition rate of a complex waveform. This could be doneby capturing and storing a frame of the test waveform, as areference waveform, whose length must include at least onebase period of the test waveform. Furthermore, the “distance”between this captured reference waveform and the incomingwaveform could be measured on real time basis, and a triggeris generated if the measured distance is within an acceptablerange. The previous discussion explains the concept behind theproposed scheme. The exact procedure adopted to implementthis oscilloscope triggering scheme is explained in the succeed-ing discussion.

To implement the previously described concept, theHamming-memory-network-based neural topology is used, anddistance is measured in terms of the newly proposed whdparameter, which is defined in [11].

The proposed technique can be compared to a conveyorbelt of data, with samples acquired from the test signal asboxes on the conveyor belt, as shown in Fig. 2. R samples ofthe incoming signal, which are sampled at a suitably chosensampling rate, are captured and stored in an array as a referencepattern vector ref, which is shown as the upper row of boxesin Fig. 2

ref = [x(t1), x(t2), x(t3), . . . , x(tR)]

where x(ti) is the N -bit sample at time instant ti.Subsequently, a moving window of R samples is maintained

in the buffer register buf by shifting out the oldest sample fromone end and adding a new one at other end. With reference toFig. 2, the same could be visualized as new boxes being placedat one end of the belt sequentially, and each time a new box isplaced, the oldest box falls off the other end. The R samples inthe moving window after a time increment of Ts units can berepresented as

buf1 = [x(t1 + Ts), x(t2 + Ts), x(t3 + Ts), . . . , x(tR + Ts)]


where Ts is the sampling period, and

(t1 + Ts) = t2, (t2 + Ts) = t3, . . . , (tR + Ts) = tR+1

buf1 = [x(t2), x(t3), x(t4), . . . , x(tR+1)].

Therefore, the nth input vector will be given by

bufn = [x(tn+1), x(tn+2), x(tn+3), . . . , x(tR+n)].

Now, the proximity of ith input pattern vector bufi with thestored reference pattern vector ref is computed in terms of whd,as illustrated in Fig. 2. In this way, the moving window ofR-samples, where each sample is of N -bits, is compared withthe reference pattern vector, and a low value of computed whdwould indicate a repetition of the reference pattern. Continuingwith the conveyor belt analogy, this triggering scheme is similarto someone standing near the conveyor belt who has been toldto look for a set of special boxes on the conveyor belt and tosend a signal when the set of boxes matches the desired pattern.The complete flow chart of the proposed technique is shownin Fig. 3.

III. SOFTWARE DESIGN VERIFICATION

The proposed technique is coded in Verilog HDL, synthe-sized by Synopsys FPGA Express, and functional and timingsimulation has been carried out using the Xilinx foundationseries 3.1i software [13]. The block diagram shown in Fig. 4explains the exact process involved in the simulation. Here,test waveforms are generated using an arbitrary waveformsynthesizer. Binary samples of the test waveforms are capturedand stored in a data file using a PCI-1711 data acquisitioncard [14], and these captured samples are used as input testvectors for the simulation. The simulation is carried out ona host computer using Xilinx foundation series 3.1i, whichgenerates output in the form of timing diagrams. Specifically,in this paper, sine, triangular, damped-sine, periodic burst ofpulses, and composite waveforms are used for the testing of thetechnique.

In each case, the input waveform is sampled in such a waythat there are 10 or 20 samples per cycle. Therefore, for propertriggering, we require a triggering pulse after every 10 or 20sample count delays. In this method, in the beginning, theselected numbers of samples (10 or 20 in the present simula-tion examples) are captured and stored both in the referenceand input buffer registers. Subsequently, at each succeedingsampling instant, a new sample is captured and added to thebuffer register, and the oldest one is rejected. Following this,the whd for the contents of the current input buffer register andthe reference register is computed and is compared with a setvalue of the whd whdmin. The output signal “Out1” is forcedhigh for one sampling interval when the computed whd is lessthan or equal to whdmin. “Out1” can then be used as a trigger,indicating matching of the current buffer pattern with the storedreference pattern.

The test waveforms are shown in Figs. 5(a), 6(a), 7(a), and8(a). In the case of the damped-sine waveform, as shown inFig. 6(a), if the desired triggering voltage level is much less

Fig. 3. Flow chart of the proposed oscilloscope triggering technique.

than the peak value, then stable triggering cannot be obtainedbecause of multiple crossing of the trigger level. In the case ofperiodic burst of pulses, as shown in Fig. 7(a), stable triggeringcannot be achieved because of the asynchronous waveform,unless the oscilloscope’s time base can provide suitable hold-OFF delay. The last waveform used to test the technique is acomposite waveform shown in Fig. 8(a). The level triggeringmethod also fails to provide stable triggering in this case.From Fig. 5(b), we can see that for the triangular waveform,the triggering pulses are being obtained on desired triggeringinstances T1, T2, T3, T4, . . . . The computed whd for the


Fig. 4. Block diagram of the simulation process.

Fig. 5. (a) Input waveform. (b) Simulation result when testing waveform is a triangular wave. (c) WHD function.

triangular waveform is plotted as a function of the number ofsample shifts in Fig. 5(c).

The detailed simulation result of the proposed triggeringalgorithm for triangular test waveform case has been shown inFig. 5(a)–(c). The test signal frequency is 100 KHz, and thesampling frequency is 1 MHz; therefore, for proper triggering,a triggering pulse after each ten clock periods is required. Inthis case, the chosen length of the input and reference vectors is13 samples each.

From Figs. 6(b), 7(b), and 8(b), we can see that the triggeringpulses are being obtained on desired triggering instances T1,T2, T3, T4, . . . for the given test waveforms (the traces arenot synchronized because the waveform is captured on a scope,while the trigger pulses are produced by the FPGA tool runningon a PC, and the figure is a composite of the two). Thecomputed whd for the test waveforms is plotted as a functionof the number of sample shifts in Figs. 6(c), 7(c), and 8(c).From these figures, it is quite clear that at desired triggering


Fig. 6. (a) Input waveform. (b) Simulation result when testing waveform is a damp sine. (c) WHD function.

Fig. 7. (a) Input waveform. (b) Simulation result when testing waveform is a periodic burst of pulses. (c) WHD function.


Fig. 8. (a) Input waveform. (b) Simulation result when testing waveform is composite. (c) WHD function.

Fig. 9. (a) Test waveform. (b) WHD function.


Fig. 10. Probability density curves. (a) Size of data set: 10 000. (b) Size of data set: 15 000.

instances, the value of the computed whd is either zero oris a finite minimum value, which indicates the repetition ofreference signal.

IV. ROBUSTNESS TESTING

In the aforementioned results, since the incoming test wave-forms are largely free from noise, an ideal match betweenreference and input is therefore possible, which is indicatedby zero whd value, but in the presence of noise, the waveformof the signal will vary slightly in time, and therefore, an idealmatch will not occur; so, the computed whd will acquire insome minimum value when the patterns, in fact, match in time.Nevertheless, the lowest value of the whd could be used toindicate the basic repetition rate of the signal. To test howmuch the minimum whd varies in the presence of noise, theminimum whds have been computed by introducing variouslevels of random noise in the original signal. The amounts ofnoise levels introduced are 5%, 10%, and 15% of the peak-to-peak value of the test signal. Test signal chosen for thispurpose is shown in Fig. 9(a). The size of the reference andinput vector is 37 samples, whereas number of samples/cycle

is 20. The whd function for the noiseless waveform and forthe waveform with noise that is 10% of the peak-to-peak valueof the test signal is shown in Fig. 9(b). From Fig. 9(b), itis quite clear that the minimum value of whd for noiselesstest waveform is zero, whereas the minimum whd for the testwaveform with noise is some positive nonzero value.

To check the variation in minimum value of the whd, whdmin

is computed for 10 000 and 15 000 cycles of the test waveformfor three different levels of the random noise. Probability distri-bution curves for whdmin for the different levels of noise and forthe different sizes of the data set are shown in Fig. 10(a) and (b).Mean values of whdmin and their spread around the mean valueare indicated in Fig. 10. In each case, the percentage jitter is alsocalculated. Acceptable criterion for jitter is one sample period.In the first case, when the level of noise is 5% of the peakvalue of the signal, the computed value of the jitter is 0.75%of one sample period, whereas in second case, when the levelof noise is 10% of the peak value of the signal, the computedvalue of the jitter is 1.5% of one sample period. Finally, whenthe level of noise is 15% of the peak value of the signal, thecomputed value of the jitter is 2.4% of one sample period.Therefore, it is evident that the whd method could lead to a


Fig. 11. Implementation block diagram of the oscilloscope triggering scheme.

robust determination of the repetition period of the signal. Theaforementioned results indicate that the proposed techniquecan provide a method for generating repetitive trigger signalslocked to a complex input waveform.

V. HARDWARE VALIDATION

The proposed technique is coded in Verilog HDL, synthe-sized by Synopsys FPGA Express, and then implemented usingXilinx foundation series 3.1i software [13]. A block diagram ofthe internal synthesis is shown in Fig. 11, where the functionof each block is indicated in bold letters. The target device isXCV300E240PQ, which is 240-pin plastic quad flat packagethat belongs to the Xilinx Virtex-E family of FPGAs.

The maximum frequency obtained as a result of the timinganalysis within the FPGA development tool was 16.47 MHz.The high value of maximum frequency was achieved by intro-ducing constraints on the setup and hold times of the signals.

The complete block diagram of the implementation modulesis shown in Fig. 11. One of the inputs is the clock input,which is interfaced with the output of a 50-MHz oscillatorSG531PCVC mounted on the AFX PQ240-100 proto board.Eight-bit data bus data(7:0) is another input to the top-levelmodule. This 8-bit data bus is interfaced with the output ofADS930 high-speed pipelined ADC. The output is 1-bit out-put x, which is basically the required oscilloscope trigger-pulse output. The block diagram, which is shown in Fig. 12,

Fig. 12. Hardware setup.

explains the hardware test setup. The clock frequency used is1 MHz. This scheme is successfully verified with numerousselected test waveforms. Some typical examples of complexwaveforms along with generated triggering pulses have beenshown in Figs. 13–15. As mentioned earlier, test waveforms aregenerated using Tektronix arbitrary function generator. In allthe cases, the signal frequency is 100 kHz, so we require outputtrigger pulses at the same frequency to get a stable display of thesignals. In the first case, the test waveform is not a complex one,but it is a simple triangular waveform of 100-kHz frequency,as shown on channel 2 in the captured scope diagram shownin Fig. 13. The trigger signal obtained is shown on channel 1in the same diagram. It is seen to be time coherent with thetriangular test waveform, thus verifying the operation of ourtrigger-generation scheme. The results for 100-kHz complexwaveforms are shown in Figs. 14 and 15. In these figures, thecoherent trigger signals are also clearly seen. It can also be seenthat the internal frequency measuring algorithm of the scope isunable to correctly compute the frequency of the test signal,but the frequency of the trigger signal is reported correctlyas 100 KHz. Therefore, we may conclude that the proposedscheme of oscilloscope triggering is equally effective for simplewaveforms as well as for complex waveforms.

VI. CONCLUSION

In this paper, an artificial neural network (ANN)-basedtriggering technique for oscilloscopes has been proposed, andits hardware and software performance verification for certainselected waveforms has also been described. The main conclu-sions emerging from this work can be summarized as follows.

1) The proposed technique, which is based upon a newlyproposed whd function, overcomes the problem of unsta-ble triggering in an existing level triggered technique. Theeffectiveness of the technique has been validated both bysimulation and hardware implementation. A major util-ity of this technique could be to embed it inside the“autoscale” function, making it feasible to identify andtrigger on the base period of even complex waveforms,thus reducing the need for hold-OFF adjustments.

2) The robustness of the technique has been evaluated byadding noise to a test complex signal waveform andobserving jitter in the trigger generation by simulation. Itis shown that when the level of noise is as high as 15% ofthe peak value of the signal, the estimated value of triggerjitter is only about 2% of one sample period.


Fig. 13. Triangular waveform and triggering pulses.

Fig. 14. Complex test waveform and triggering pulses.

Fig. 15. Complex test waveform and triggering pulses.

3) The proposed technique has been implemented on amedium-scale FPGA device and successfully verified inhardware with many test waveforms. The results indi-cate that the technique is a useful alternative to theexisting ones.

Implementation of this ANN-based technique requires anappropriate choice of sampling rate so that the sample sizeencompasses at least one full cycle of the test waveform.This choice can be made automatic via a “search” techniqueimplemented using the host oscilloscope’s intelligence.


REFERENCES

[1] B. A. Gregory, An Introduction to Electrical Instrumentation and Mea-surement Systems. New York: Macmillan, 1981.

[2] Advanced Triggering With the TLA700 Series Logic Analyzers. [Online].Available: www.tektronix.com

[3] K. Steinbuch and U. A. V. Piske, “Learning matrices and their applica-tions,” IEEE Trans. Electron. Comput., vol. EC-12, no. 6, pp. 846–862,Dec. 1963.

[4] W. K. Taylor, “Cortico-thalamic organization and memory,” Proc. R. Soc.Lond. B, vol. 159, no. 976, pp. 466–478, Feb. 1964.

[5] E. B. Baum, J. Moody, and F. Wilczek, “Internal representations forassociative memory,” Biol. Cybern., vol. 59, no. 4/5, pp. 217–228,Sep. 1988.

[6] E. Domany and H. Orland, “A maximum overlap neural network forpattern recognition,” Phys. Lett. A, vol. 125, no. 1, pp. 32–34, 1987.

[7] R. P. Lippmann, “An introduction to computing neural nets,” IEEE ASSPMag., vol. 4, no. 2, pp. 4–22, Apr. 1987.

[8] R. P. Lippmann, B. Gold, and M. L. Malpass, “A comparison of Hammingand Hopfield neural nets for pattern classification,” Lincoln Lab., Mass.Inst. Technol., Lexington, MA, Tech. Rep. 769, 1987.

[9] T. D. Chiueh and R. M. Goodman, “Recurrent correlation associativememories,” IEEE Trans. Neural Netw., vol. 2, no. 2, pp. 275–284,Mar. 1991.

[10] Y. Wu and S. N. Batalama, “An efficient learning algorithm for associativememories,” IEEE Trans. Neural Netw., vol. 11, no. 5, pp. 1058–1066,Sep. 2000.

[11] S. A. Khan, A. K. Agarwala, and D. T. Shahani, “A new triggering methodfor oscilloscope based on associative memory technique,” in Proc. IEEEInt. Workshop SCIMA, Provo, UT, May 2003, pp. 20–25.

[12] S. A. Khan, A. K. Agarwala, and D. T. Shahani, “Implementation ofadvance oscilloscope triggering scheme on FPGA,” in Proc. IEEE IMTC,Ottawa, ON, Canada, May 2005, vol. 2, pp. 407–411.

[13] Foundation Series 3.1i Quick Start Guide, XILINX The ProgrammableLogic Company, San Jose, CA, 2000.

[14] PCI-1711/1731 User’s Manual. [Online]. Available: www.advantech.com

Shakeb A. Khan received the B.Sc. Eng. degreein electrical engineering and the M.Sc. Eng. de-gree in instrumentation and control from AligarhMuslim University, Aligarh, India, in 1992 and 1994,respectively. He received the Ph.D. degree in instru-mentation from the Indian Institute of Technology,Delhi, India, in 2005.

He has been with Jamia Millia Islamia (a centraluniversity), New Delhi, India, since 1995, where heis currently a Reader in the Department of ElectricalEngineering. His research and teaching interests in-

clude electronics instrumentation, artificial neural networks applications, andfield-programmable-gate-array-based design.

A. K. Agarwala received the B.Sc. (Hons) andM.Sc. degrees in physics from Delhi University,Delhi, India, in 1971 and 1973, respectively, andthe M.S. degree in electrical engineering fromRensselaer University, Troy, NY, in 1978.

After a short stay at Philips India’s R&D Center,he has been with the Indian Institute of Technology,Delhi, since 1979. His research and teaching inter-ests include instrument technology, power electron-ics, and neural networks. He is also very active inworking with industries in India in developing newproducts and technologies.

D. T. Shahani received the B.Tech. degree in elec-tronics and communication engineering from IndianInstitute of Technology, Kharagpur, India, in 1973and the Ph.D. degree in the field of electromagneticsfrom the Indian Institute of Technology, Delhi, India,in 1979.

He has been with Indian Institute of Technology,Delhi, since 1973, where he is currently a Professorand Head of the Instrument Design DevelopmentCentre. His research and teaching interests includeelectronics instrumentation, electromagnetic trans-

ducers, and electromagnetic interference/electromagnetic compatibility. He isalso very active in working with industries in India to develop new productsand technologies.

M. Mahfooz Alam received the B.E. degree inelectrical engineering from Rajeev Gandhi TechnicalUniversity, Bhopal, India, in 2000 and the M.E.degree in instrumentation and control from the DelhiCollege of Engineering, Delhi, India, in 2003.

Currently, he is working at Infineon TechnologiesIndia Pvt. Ltd., Bangalore, India, as a Senior DesignEngineer. He has been engaged in the research anddevelopment of high-speed IO circuit design andsilicon verification. His research interest has beenin low power and high-speed application-specified

integrated circuit implementation of DSP algorithms.

Advance Oscilloscope Triggering

Documents

Transcript of Advance Oscilloscope Triggering