AD9284-250EBZ User Guide - Analog Devices

AD9284-250EBZ User Guide UG-178

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the AD9284 Analog-to-Digital Converter

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | of 24

FEATURES Full featured evaluation board for the AD9284 SPI interface for setup and control Support LVDS output mode option External or on-board oscillator options Balun/transformer or amplifier input drive options Switching power supply VisualAnalog™ and SPIController software interfaces

EQUIPMENT NEEDED Analog signal source and antialiasing filter Sample clock source (if not using the on-board oscillator) Two switching power supplies (6.0 V, 2.5 A),

CUI EPS060250UH-PHP-SZ, provided PC running 32-bit Windows® XP, Window Vista, or Windows 7 USB 2.0 port, recommended (USB 1.1-compatible) AD9284 evaluation board HSC-ADC-EVALCZ FPGA-based data capture kit

SOFTWARE NEEDED VisualAnalog SPIController

DOCUMENTS NEEDED AD9284 data sheet HSC-ADC-EVALCZ data sheet AN-905 Application Note, VisualAnalog Converter Evaluation

Tool Version 1.0 User Manual AN-878 Application Note, High Speed ADC SPI Control Software AN-877 Application Note, Interfacing to High Speed ADCs via SPI AN-835 Application Note, Understanding High Speed ADC

Testing and Evaluation

GENERAL DESCRIPTION This user guide describes the AD9284 evaluation board, which provides all of the support circuitry required to operate the AD9284 in its various modes and configurations. The application software used to interface with the device is also described.

The AD9284 data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at the FIFO page. For additional information or questions, send an email to [email protected].

TYPICAL MEASUREMENT SETUP

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9284EE01REV A

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Figure 1. AD9284 Evaluation Board and HSC-ADC-EVALCZ Data Capture Board

http://www.analog.com/AD9284?doc=ug-178.pdf




http://www.analog.com/AD9284



http://www.analog.com/AN-905?doc=ug-178.pdf









http://www.analog.com/fifo?doc=ug-178.pdf

mailto:[email protected]


UG-178 AD9284-250EBZ User Guide

Rev. A | of 24

TABLE OF CONTENTS Features .............................................................................................. 1 Equipment Needed ........................................................................... 1 Software Needed ............................................................................... 1 Documents Needed .......................................................................... 1 General Description ......................................................................... 1 Typical Measurement Setup ............................................................ 1 Revision History ............................................................................... 2 Evaluation Board Hardware ............................................................ 3

Power Supplies .............................................................................. 3

Input Signals...................................................................................3 Output Signals ...............................................................................3 Default Operation and Jumper Selection Settings ....................4

Evaluation Board Software Quick Start Procedures .....................5 Configuring the Board .................................................................5 Using the Software for Testing .....................................................5

Evaluation Board Schematics and Artwork ...................................9 Ordering Information .................................................................... 22

Bill of Materials ........................................................................... 22

REVISION HISTORY 6/14—Rev. 0 to Rev. A

Changes to Figure 13 ........................................................................ 9 Changes to Figure 14 ...................................................................... 10 Changes to Figure 15 ...................................................................... 11 Changes to Figure 16 ...................................................................... 12 Changes to Figure 17 ...................................................................... 13 Changes to Figure 18 ...................................................................... 14 Changes to Figure 19 ...................................................................... 15

5/11—Revision 0: Initial Version


Rev. A | of 24

EVALUATION BOARD HARDWARE The AD9284 evaluation board provides all of the support circuitry required to operate the AD9284 in its various modes and configurations. Figure 2 shows the typical bench charac-terization setup used to evaluate the ac performance of the AD9284. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance.

See the Evaluation Board Software Quick Start Procedures section to get started, and see Figure 13 to Figure 25 for the complete schematics and layout diagrams. These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using the AD9284.

POWER SUPPLIES This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to the 240 V ac wall outlet at 47 Hz to 63 Hz. The output from the supply is provided through a 2.1 mm inner diameter jack that connects to the printed circuit board (PCB) at J101. The 6 V supply is fused and conditioned

on the PCB before connecting to the low dropout linear regulators (default configuration) that supply the proper bias to each of the various sections on the board.

INPUT SIGNALS When connecting the clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA, or HP8644B signal generators or an equivalent. Use a 1 m shielded, RG-58, 50 Ω coaxial cable for connecting to the evaluation board. Enter the desired frequency and amplitude (see the specifications in the AD9284 data sheet). When connecting the analog input source, a multipole, narrow-band, band-pass filter with 50 Ω terminations is recommended. Analog Devices, Inc., uses TTE and K&L Microwave, Inc., band-pass filters. The filters should be connected directly to the evaluation board.

If an external clock source is used, it should also be supplied with a clean signal generator as previously specified. Typically, most Analog Devices evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave input for the clock.

OUTPUT SIGNALS The default setup uses the Analog Devices high speed converter evaluation platform (HSC-ADC-EVALCZ) for data capture.

6V DC2A MAX

6V DC2A MAXSWITCHING

POWERSUPPLY

SWITCHINGPOWERSUPPLY

WALL OUTLET100V TO 240V AC

47Hz TO 63Hz

PC RUNNINGVisualAnalog

AND SPIControllerUSER SOFTWARE

SIGNAL GENERATOR

CLOCK SOURCE

SIGNAL GENERATOR

ANALOG FILTER

SIGNAL GENERATOR

ANALOG FILTER

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Figure 2. Evaluation Board Connection















Rev. A | of 24

DEFAULT OPERATION AND JUMPER SELECTION SETTINGS This section explains the default and optional settings or modes allowed on the AD9284 evaluation board.

Power Circuitry

Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and J101.

Analog Input

The A and B channel inputs on the evaluation board are set up as simultaneous channel sampling using a single transformer (per channel) analog input with a 50 Ω impedance. The default analog input configuration supports analog input frequencies of up to ~200 MHz. This input network is optimized to support a wide frequency band. See the AD9284 data sheet for additional information on the recommended networks for different input frequency ranges. The nominal input drive level is 10.5 dBm to achieve 1.5 V p-p full scale into 50 Ω. At higher input frequencies, slightly higher input drive levels are required due to losses in the front-end network.

VREF

The AD9284 operates with a fixed 1.0 V reference. This sets the analog input span to 1.5 V p-p.

RBIAS

RBIAS has a default setting of 10 kΩ (R206) to ground and is used to set the ADC core bias current. Note that using a resistor value other than a 10 kΩ, 1% resistor for RBIAS may degrade the performance of the device.

Clock Circuitry

The default clock input circuit on the AD9284 evaluation board uses a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T501) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped by CR501 before entering the ADC clock inputs. The AD9284 board has on-chip circuitry to distribute a single clock to both ADC channels.

Non-SPI Mode

For users who want to operate the DUT without using SPI, remove the shorting jumpers on J302. This disconnects the CSB, SCLK, and SDIO/PWDN pins from the SPI control bus, allowing the DUT to operate in non-SPI mode. In this mode, the SDIO/PWDN pin takes on an alternate function to enable power down functionality.

To enable the power-down feature, add a shorting jumper across J202 at Pin 2 and Pin 3 to connect the SDIO/PDWN pin to DRVDD.














Rev. A | of 24

EVALUATION BOARD SOFTWARE QUICK START PROCEDURES This section provides quick start procedures for using the AD9284 evaluation board. Both the default and optional settings are described.

CONFIGURING THE BOARD Before using the software for testing, configure the evaluation board using the following steps:

1. Connect the evaluation board to the data capture board, as shown in Figure 1 and Figure 2.

2. Connect one 6 V, 2.5 A switching power supply (such as the CUI, Inc., EPS060250UH-PHP-SZ) to the AD9284 board.

3. Connect one 6 V, 2.5 A switching power supply (such as the supplied CUI EPS060250UH-PHP-SZ) to the HSC-ADC-EVALCZ board.

4. Connect the HSC-ADC-EVALCZ board to the PC with a USB cable.

5. On the ADC evaluation board, confirm that six jumpers are installed as described as follows: • J103, Pin 2 and Pin 3 (clock with regulator) • J104, Pin 2 and Pin 3 (amp with regulator) • J105, Pin 2 and Pin 3 (DRVDD with regulator) • J106, Pin 2 and Pin 3 (AVDD with regulator) • J201, Pin 1 and Pin 2 (SCLK SPI) • J202, Pin 1 and Pin 2 (SDIO SPI)

6. On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal to the desired A and/or B channel(s). Use a 1 m, shielded, RG-58, 50 Ω coaxial cable to connect the signal generator. For best results, use a narrow-band band-pass filter with 50 Ω terminations and an appropriate center frequency. (Analog Devices uses TTE, Allen Avionics, and K&L band-pass filters.)

USING THE SOFTWARE FOR TESTING Setting Up the ADC Data Capture

After configuring the board, set up the ADC data capture using the following steps:

1. Open VisualAnalog on the connected PC. The appro-priate part type should be listed in the status bar of the VisualAnalog – New Canvas window. Select the template that corresponds to the type of testing to be performed (see Figure 3). Note that once power is applied to the AD9284 evaluation board, the device is powered down. To wake up the device, the SDIO/PWDN pin must be pulled low. This occurs automatically by VisualAnalog after you complete Step 1.

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Figure 3. VisualAnalog, New Canvas Window

2. After the template is selected, a message appears asking if the default configuration can be used to program the FPGA (see Figure 4). Click Yes to close the window.

0 92 2

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4

Figure 4. VisualAnalog Default Configuration Message

3. To change features to settings other than the default settings, click the Expand Display button, located on the bottom right corner of the window, to see what is shown in Figure 6. Detailed instructions for changing the features and capture settings can be found in the AN-905 Application Note, VisualAnalog Converter Evaluation Tool Version 1.0 User Manual. After the changes are made to the capture settings, click the collapse display button (see the collapsed display in Figure 5).

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Figure 5. VisualAnalog Window Toolbar, Collapsed Display




















Rev. A | of 24

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Figure 6. VisualAnalog Main Window


Rev. A | of 24

Setting Up the SPIController Software

After the ADC data capture board setup is complete, set up the SPIController software using the following procedure:

1. Open the SPIController software by selecting Start > SPIController or by double-clicking the SPIController software desktop icon. If prompted for a configuration file, select the appropriate one. If not, check the title bar of the window to determine which configuration is loaded. If necessary, choose Cfg Open from the File menu and select the appropriate file based on your part type. Note that the CHIP ID(1) field should be filled to indicate whether the correct SPIController configuration file is loaded (see Figure 7).

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Figure 7. SPIController, CHIP ID(1) Box

2. Click the New DUT button in the SPIController window (see Figure 8).

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Figure 8. SPIController, New DUT Button

3. In the ADCBase 0 tab of the SPIController window, you can access all global register settings (see Figure 9). See the AD9284 data sheet; the AN-878 Application Note, High Speed ADC SPI Control Software; and the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, for additional information.

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Figure 9. SPIController, ADC Base0

4. Note that other settings can be changed on the ADCBase 0 page (see Figure 9) and the ADC A and ADC B pages (see Figure 10) to set up the part in the desired mode. The ADCBase 0 page settings affect the entire part, whereas the settings on the ADC A and ADC B pages affect the selected channel only. See the AD9284 data sheet; the AN-878 Application Note, High Speed ADC SPI Control Software; and the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, for additional information on the available settings.

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Figure 10. SPIController, ADC A Page















Rev. A | of 24

5. Click the Run button in the VisualAnalog toolbar (see Figure 11).

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Figure 11. Run Button in VisualAnalog Toolbar, Collapsed Display

Adjusting the Amplitude of the Input Signal

The next step is to adjust the amplitude of the input signal for each channel as follows:

1. Adjust the amplitude of the input signal so that the funda-mental is at the desired level (examine the Fund Power reading in the left panel of the VisualAnalog Graph - AD9284 FFT window). See Figure 12.

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Figure 12. Graph Window of VisualAnalog

2. Repeat this procedure for Channel B. 3. Click the disk icon within the Graph window to save the

performance plot data as a .csv formatted file.

Troubleshooting Tips

If the FFT plot appears abnormal, do the following:

• If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce the input level, if necessary.

• In VisualAnalog, click the Settings button in the Input Formatter block. Check that Number Format is set to the correct encoding (offset binary by default). Repeat for the other channel.

If the FFT appears normal but the performance is poor, check the following:

• Make sure an appropriate filter is used on the analog input. • Make sure the signal generators for the clock and the

analog input are clean (low phase noise). • Change the analog input frequency slightly if noncoherent

sampling is being used. • Make sure the SPI configuration file matches the product

being evaluated.

If the FFT window remains blank after Run is clicked, do the following:

• Make sure the evaluation board is securely connected to the HSC-ADC-EVALCZ board.

• Make sure the FPGA has been programmed by verifying that the DONE LED is illuminated on the HSC-ADC-EVALCZ board. If this LED is not illuminated, make sure the U4 switch on the HSC-ADC-EVALCZ board is in the correct position for USB configuration.

• Make sure the correct FPGA program was installed by selecting the Settings button in the ADC Data Capture block in VisualAnalog. Then select the FPGA tab and verify that the proper FPGA bin file is selected for the part.

If VisualAnalog indicates that the FIFO Capture timed out, do the following:

• Make sure all power and USB connections are secure. • Probe the DCOA signal at RN601 on the evaluation board

and confirm that a clock signal is present at the ADC sampling rate.



Rev. A | of 24

EVALUATION BOARD SCHEMATICS AND ARTWORK

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Rev. A | of 24

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Rev. A | of 24

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00

0

SC

LK_D

UT

CS

B_D

UT

SC

LK_D

UT_

1P8

CS

B_D

UT_

1P8

SD

IO_D

UT_

1P8

SD

IO_D

UT

US

B_S

CLK

SP

I_D

VD

D

3.3V

_CLK

SP

I_D

VD

D

US

B_S

DI

US

B_C

SB

NC

7WZ1

6P6X

0.1U

F

US

B_S

DO

0.1U

F

NC

7WZ0

7P6X

VC

CY

1A

1

A2

GN

D

Y2

Y2

Y1

A2

A1

GN

D

VC

C

Figure 15. SPI Interface Circuit


Rev. A | of 24

09228-016

AIN

_AM

P

PA

SS

IVE

PA

TH B

AC

TIV

E P

ATH

A A

ND

B

SH

AR

E P

AD

S

LAY

OU

T: S

MA

'S S

HO

ULD

BE

540

MIL

S C

EN

TER

TO

CE

NTE

R

PA

SS

IVE

PA

TH A

THE

SE

0 O

HM

S A

RE

TH

ER

E F

OR

ALI

AS

ES

.W

E D

ON

'T R

EQ

UIR

E T

HE

SE

CO

MP

ON

EN

TS

LAY

OU

T: S

MA

'S S

HO

ULD

BE

540

MIL

S C

EN

TER

TO

CE

NTE

R

SH

AR

E P

AD

S

AIN

_A +

AIN

_A -

AIN

_B +

AIN

_B -

SH

AR

E P

AD

S

SH

AR

E P

AD

S

R45

0

R44

9

R45

1

54

32

1J4

06

R44

7

R44

6

R44

4

R44

5

C41

6

C41

7

R44

1

R44

0

R43

9

R43

8R

442

R44

3

C419C418

9 12P

AD

1 4

13141516

113

87

65

102

U40

1

R43

7

R43

65

43

2

1J4

05

54

32

1J4

03

R41

8

R42

0C

409

R42

2

54

32

1J4

04

R41

9

R42

1C

410

6 42

3 1T404

5 431

T405

5

43

1

T406

R42

6

C41

2R

425

C41

1

R42

3 R42

4

R42

9C41

3

R42

8

R43

0

R42

7

R43

2

C414

C415

R43

1

R43

4

R435

R43

3

R41

6

R41

7R

415

R41

4

C407

C406

C40

4

C40

3

R40

6

R448

R41

2

R41

3

R41

0 C40

5

R40

7

R41

1

R40

9R40

8

5

43

1

T403

5 431

T402

6 42

3 1T401

R40

5

C40

1R

403

C40

2

R40

1

R40

4

R40

2

54

32

1J4

01

54

32

1J4

02

0 DN

I

0

0 0 DN

I

DNITBD0402

DNITBD0402

AD

A49

37-1

YC

PZ-

R7

0.1U

F

0.1U

F

AIN

_B-

AIN

_B+

AIN

_A+

AIN

_A-

ETC1-1-13

2.7PFDNI

4.7PF

0.1U

F

3.3V

_AM

PV

DD

0.1UF

ETC1-1-13

AD

T1-1

WT+

DNI

ETC

1-1-

13

DNI

0.1U

F

4.7PF

2.7PF

AD

T1-1

WT+

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1UF

0.1U

F

DN

I

DN

I

0.1U

F

ETC

1-1-

13

0.1U

F

DNI

DNI DNI

DN

I

DN

I

DN

I

DN

IDN

I

10U

F

0

0

0 000

0

0DN

I

AM

P_O

UT_

B+

0

0DN

I

AM

P_O

UT_

B-

DN

I

0 AM

P_O

UT_

A+

0

0DN

I

AM

P_O

UT_

A-

0 0

0 0

0

DN

I0

AM

P_O

UT_

A+

DN

I0

AM

P_O

UT_

A-

DN

I0A

MP

_OU

T_B

-

DN

I0

AM

P_O

UT_

B+

0C

MV

_OU

T

0

CM

V_O

UT

0C

MV

_OU

T

3333

3333 33 33

33 33

24 DN

I

24 DN

I

49.9

DN

I

49.9

DN

I

49.9 DN

I49.9

DN

I

200

200

200

200

61.9

DN

I

DN

I27

.4

SE

CP

RI

SEC PRI

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

SEC PRI

GN

D

SE

CP

RI

GN

D

GN

D

GN

D GN

D

GN

D

GN

DP

AD

PD

_N

VO

CM

-VS

+VS

-IN+IN

FB+O

UT

+OU

T-O

UT

FB-O

UT

GN

D

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

D

Figure 16. Analog Input Circuits


Rev. A | of 24

09228-017

OPT

ION

AL C

LOC

K B

INPU

T

CLK

_B +

CLK

_B -

SHAR

E PA

DS?

2ND

CR

IS T

O M

AKE

LAYO

UT

AND

PAR

ASIT

IC L

OAD

ING

SYM

MET

RIC

AL

CLK

_A +

CLK

_A -

LAYO

UT:

SM

A'S

SHO

ULD

BE

540

MIL

S C

ENTE

R T

O C

ENTE

R

OPT

ION

AL C

RYS

TAL

OSC

IALL

ATO

R C

LOC

K SO

UR

CE

SHARE PADSSHARE PADS

OPT

ION

AL T

ERM

INAT

ION

NEA

R D

UT

SHAR

E PA

DS?

XFM

R /

BALU

N C

LK C

IRC

UIT

RY

OPT

ION

AL T

ERM

INAT

ION

NEA

R D

UT

2ND

CR

IS T

O M

AKE

LAYO

UT

AND

PAR

ASIT

IC L

OAD

ING

SYM

MET

RIC

AL

42 3

1CR

503

42 3

1CR

501

R51

1

R51

3

R52

7

R52

9

R52

6

R52

8

C50

3

C51

1

R524

C51

5R

522

R52

0

C51

4

R51

8

C51

6R

523

R52

1

R51

9

C51

3

64 2

31 T503

R51

6

R51

7

C50

9

C51

0

R51

45

43

2

1J5

03

54

32

1J5

04

1 3

6 4 52

T504

C51

2

TP50

2R

515

C50

6

R50

6

R50

5

R50

9C

507

R512

C50

8R

510

R50

7

R50

8

C50

56 42

3 1

T501

T502

R50

3C

501

R50

4

C50

4

C50

2 TP50

1

R50

15

43

2

1J5

01

54

32

1J5

02

R50

2

R52

5

C51

7

6

154

2

3

Y505

130

130

24.9

24.9

24.9

24.9

100DNI

100DNI

49.9 DN

I

49.9

DN

I49

.9

49.9

HM

PS-2

822-

BLK

3.3V

_CLK

0.1U

F

ENC

_A+

0.1U

F

XSTA

L_IN

+

ENC

_A-

XSTA

L_IN

-

0.1U

F

0.1U

F

0.1U

FD

NI

DN

I

ADT1

-1W

T+

0.1U

F

1000

PFM

ABA-

0071

59-0

0000

0

0.1U

F

DN

I

0.1U

F

0.1U

F BLK

0.1U

F

0.1U

F

1000

PF

XSTA

L_IN

-

XSTA

L_IN

+

ENC

_B+

ENC

_B-

DN

IAD

T1-1

WT+

HM

PS-2

822-

BLK

MAB

A-00

7159

-000

000

DN

I0.

1UF

DN

I

0.1U

F

0.1U

F BLK

0.1U

F

500M

EGH

Z

DN

I

DN

I

0

DN

I0

00

00

0

DN

I0

00

00

DN

I0

DN

I0

7575

1K

GN

D

GN

D

GN

D

GN

D

SEC

PRI

-(NC

)-

GN

D

GN

D

GN

D

GN

D

GN

D

SEC

PRI

-(NC

)-

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

Q_N

QVD

D

GN

D

NC

TRIS

TATE

Figure 17. Default Clock Path Input Circuits


Rev. A | of 24

0922

8-01

8

0 AND 47

CH

AN

NE

L B

CH

AN

NE

L A

0 OHM RESISTOR NETWORK FOR LVDS MODE

0 AND 47

47 OHM RESISTOR NETWORK FOR CMOS MODE

DCO

152RN602

143RN602

134RN602

125RN602

116RN602

107RN602

R601

R602

98RN601

107RN601

98RN602

161RN602

116RN601

125RN601

134RN601

143RN601

152RN601

161RN601

0

DCO_A O_DCO_A

0

DCO_B O_DCO_B

0

D7A_D7P O_D7A

0

D6A_D7M O_D6A

0

D5A_D6P O_D5A

0

D4A_D6M O_D4A

0

D3A_D5P O_D3A

0

D2A_D5M O_D2A

0

D7B_D3P O_D7B

0

D0B_D0M O_D0B

0

D1A_D4P O_D1A

0

D0A_D4M O_D0A

0

D1B_D0P O_D1B

0

D2B_D1M O_D2B

0

D3B_D1P O_D3B

0

D4B_D2M O_D4B

0

D5B_D2P O_D5B

0

D6B_D3M O_D6B

Figure 18. Output Buffer Circuits


Rev. A | of 24

0922

8-01

9

C10C9C8C7C6C5C4C3C2C1

P1

D10D9D8D7D6D5D4D3D2D1

P1

B10B9B8B7B6B5B4B3B2B1

P1

A10A9A8A7A6A5A4A3A2A1

P1

BG10BG9BG8BG7BG6BG5BG4BG3BG2BG1

P2

DG10DG9DG8DG7DG6DG5DG4DG3DG2DG1

P2

C10C9C8C7C6C5C4C3C2C1

P2

D10D9D8D7D6D5D4D3D2D1

P2

A10A9A8A7A6A5A4A3A2A1

P2

B10B9B8B7B6B5B4B3B2B1

P2

BG10BG9BG8BG7BG6BG5BG4BG3BG2BG1

P1

DG10DG9DG8DG7DG6DG5DG4DG3DG2DG1

P1

O_DCO_B

O_D0B

O_D2B

O_D4B

O_D6B

O_D0A

O_D2A

O_D4A

O_DCO_A

O_D1B

O_D3B

O_D5B

O_D7B

O_D1A

O_D3A

SDIO_DUT_1P8SCLK_DUT_1P8

O_D5A

6469169-1

O_D6A

6469169-1

USB_CSB USB_SCLKUSB_SDIUSB_SDO

6469169-1

CSB_DUT_1P8

O_D7A

6469169-1

6469169-1

6469169-1

6469169-16469169-1

6469169-16469169-1

6469169-1

6469169-1GND

PLU

G H

EAD

ER

PLU

G H

EAD

ER

PLU

G H

EAD

ER

PLU

G H

EAD

ERPL

UG

HEA

DER

PLU

G H

EAD

ER

GND

PLU

G H

EAD

ER

PLU

G H

EAD

ER

PLU

G H

EAD

ER

PLU

G H

EAD

ER

PLU

G H

EAD

ER

PLU

G H

EAD

ER

GNDGND

Figure 19. FIFO Board Connector


Rev. A | of 24

09228-020

Figure 20. Top Side


Rev. A | of 24

09228-021

Figure 21. Ground Plane (Layer 2)


Rev. A | of 24

09228-022

Figure 22. Power Plane (Layer 3)


Rev. A | of 24

09228-023

Figure 23. Power Plane (Layer 4)


Rev. A | of 24

09228-024

Figure 24. Ground Plane (Layer 5)


Rev. A | of 24

6

09228-025

Figure 25. Bottom Side


Rev. A | of 24

ORDERING INFORMATION BILL OF MATERIALS

Table 1. Qty Reference Designator Description Value Manufacturer/Part No. 1 Not applicable PCBZ 9284CE01A 15 C101, C102, C103, C105,

C106, C108, C110, C111, C113, C115, C116, C125, C127, C129, C417

Ceramic, 0805, X7R capacitor 10 µF Murata/GRM21BR70J106KE76L

3 C104, C117, C416 Ceramic, mono, 0402 capacitor 1 µF Murata/GRM155R60J105KE19D

4 C107, C109, C112, C114 Ceramic, 0805, X7R capacitor 1 µF Murata/GRM21BR71H105KA12L

18 C126, C128, C130, C225, C226, C301, C302, C401, C403, C404, C410, C411, C412, C502, C506, C507, C508, C510

Ceramic, +80/−20%, 16 V, Y5V, 0402 capacitor

0.1 µF Murata/GRM155F51C104ZA01D

11 C202, C204, C206, C208, C210, C212, C214, C216, C218, C220, C222

Ceramic, ±10%, 6.3 V, X5R, 0201 capacitor

0.1 µF Murata/GRM033R60J104KE19D

2 C406, C414 Ceramic, ±0.25 pF, 50 V, COG, 0402, capacitor

4.7 pF Murata/GRM1555C1H4R7CZ01D

1 C504 Ceramic, 50 V, 10%, X7R, 0402 capacitor

1000 pF Murata/GRM155R71H102KA01D

2 CR101, CR102 Recovery rectifier diode, DO214AA3 S2A-TP Micro Commercial Comp Corp/ S2A-TP

1 CR103 Green surface-mount 0603 LED LNJ308G8TRA (green) Panasonic/LNJ308G8TRA

1 CR501 RF Schottky diode, MINIPAK1412 HMPS-2822-BLK Avago/HSMS-2812BLK

7 E101, E102, E105, E107, E109, E111, E112

Inductor 0805 ferrite bead 100 MHz Panasonic/EXC-ML20A390U

1 F101 Fuse F1812 polyswitch PTC device 1.6 A Tyco Electronics/MINISMDC160F-2

1 FL101 Filter noise suppression LC combined type, FLBNX01

BNX016-01 Murata/BNX016-01

1 J101 PCB powerjack mini 0.08 in R/A T/H connector

PJ-102A CUI/PJ-102A

1 J102 PCB header 6 position connector Z5.530.3625.0 Wieland/Z5.530.3625.0

5 J103, J105, J106, J201, J202 PCB berg header ST male 3 position connector

TSW10608GS3PIN Samtec/TSW-103-08-G-S

3 J401, J404, J502 PCB SMA ST edge-mount connector SMA-J-P-X-ST-EM1 Samtec/SMA-J-P-X-ST-EM1

2 L101, L103 Shielded power inductors LSMSQ154H47

2.2 µH Coilcraft/LPS4012-222MLC

2 L102, L104 SMD L9075 inductor 110 nH Bourns/CW201212-R10J

2 P1, P2 PCB 60-pin RA connector CNTYCO1469169-1

6469169-1 Tyco Electronics/6469169-1

1 R101 1%, 1/16, SMD, 0402, thick film resistor

300 Ω Panasonic/ERJ-2RKF3000X

2 R102, R103 Precision thick film chip 0603 resistor 100 kΩ Panasonic/ERJ-3EKF1003V

2 R104, R105 Jumper SMD 0805 (SHRT) resistor 0 Ω Panasonic/ERJ-6GEYJ0.0

25 R405, R407, R408, R414, R415, R416, R417, R422, R424, R425, R431, R432, R433, R434, R449, R451, R504, R507, R508, R509, R510, R516, R517, R601, R602

Film SMD 0402 resistor 0 Ω Panasonic/ERJ-2GE0R00X


Rev. A | of 24

Qty Reference Designator Description Value Manufacturer/Part No. 4 R301, R306, R307, RBIAS Precision thick film chip R0402

resistor 10 kΩ Panasonic/ERJ-2RKF1002X

3 R302, R303, R305 Film SMD 0402 resistor 1.1 kΩ Panasonic/ERJ-2GEJ112X

3 R304, R308, R309 Precision thick film chip R0402 resistor

100 kΩ Panasonic/ERJ-2RKF1003X

2 R403, R421 Film SMD 0603 resistor 0 Ω Panasonic/ERJ-3GEY0R00V

8 R410, R411, R412, R413, R427, R428, R429, R430

Film SMD 0402 resistor 33 Ω Panasonic/ERJ-2GEJ330X

4 R438, R439, R440, R441 Precision thick film chip R0402 resistor

200 Ω Panasonic/ERJ-2RKF2000X

2 R505, R506 Precision thick film chip R0402 resistor

24.9 Ω Panasonic/ERJ-2RKF24R9X

2 RN601, RN602 Network 16-pin/8res RESNET16 surface-mount resistor

0 Ω Panasonic/EXB-2HVR000V

2 T401, T404 XFMR RF MINICD542 ADT1-1WT+ Minicircuits/ADT1-1WT+

1 T502 XFMR RF 1:1 (6-pin special) ETC1-6P MABA-007159-000000 Macom/MABA-007159-000000

1 U101 Compact, 600 mA, 3 MHz, TSOT-5, step-down dc-to-dc converter

ADP2108AUJZ-3.3-R7 Analog Devices/ ADP2108AUJZ-3.3-R7

1 U102 Compact, 600 mA, 3 MHz, TSOT-5, step-down dc-to-dc converter

ADP2108AUJZ-1.8-R7 Analog Devices/ ADP2108AUJZ-1.8-R7

1 U201 LFCSP analog-to-digital converter AD9284BCPZ-250 Analog Devices/ AD9284BCPZ-250

1 U301 IC SC70 tiny logic UHS dual buffer NC7WZ07P6X Fairchild/NC7WZ07P6X

1 U302 IC SC70 tiny logic UHS dual buffer NC7WZ16P6X Fairchild/NC7WZ16P6X




Rev. A | of 24

NOTES

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

©2011–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG09228-0-6/14(A)

AD9284-250EBZ User Guide - Analog Devices

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Transcript of AD9284-250EBZ User Guide - Analog Devices