A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects

1656 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 8, AUGUST 1999

A Compact Double-GateMOSFET Model Comprising

Quantum-Mechanical and Nonstatic EffectsGiorgio Baccarani,Fellow, IEEE, and Susanna Reggiani

Abstract—In this work, we investigate the electrical propertiesof the Double-Gate MOSFET (DG-MOSFET), which turn outto be very promising for device miniaturization below 0.1��m. Acompact model which accounts for charge quantization within thechannel, Fermi statistics, and nonstatic effects in the transportmodel is worked out. The main results of this investigationare: 1) the ideality factor in subthreshold is equal to unity,i.e., the slope of the turn-on characteristic is 60 mV/decadeat room temperature; 2) the drain-induced barrier lowering isminimized by the shielding effect of the double gate, whichallows us to reduce the channel length below 30 nm; and 3)the device transconductance per unit width is maximized by thecombination of the double gate and by a strong velocity overshootwhich occurs in response to the sudden variation of the electricfield at the source end of the channel, and which can be furtherstrengthened near the drain in view of the short device length.As a result, a sustained electron velocity of nearly twice thesaturation velocity is achievable. The above results prove thatthe potential performance advantages of the double-gate devicearchitecture may be worth the development effort.

Index Terms— Double-Gate MOSFET’s, nMOS transistors,quantum-mechanical effects, very-large-scale integration.

I. INTRODUCTION

T HE Technology Roadmap worked out by the Semicon-ductor Industry Association [1] identifies a likely path

of the foreseeable evolution of Microelectronics in the nextdecade. According to such a prediction, the current trend ofdevice miniaturization is expected to progress at the same rateas in the past (i.e., a new technology generation every threeyears with the minimum feature size scaled by a factor of

0.7) and will continue until year 2009, when a 70-nm CMOStechnology becomes available.

The scaling process beyond the limit of 70-nm channellength, however, will have to overcome formidable techno-logical, financial, and conceptual hurdles. First, it is currentlyunknown what lithographic approach can, in principle, allowfor the manufacturability of such miniaturized MOSFET’swith the throughput required by production needs; next, the in-creasing cost of the manufacturing facilities, which is predictedto reach $10 billion at the 0.1-m technology, [2] could makethe financial returns of such an investment rather problematic

Manuscript received June 15, 1998; revised February 18, 1999. The reviewof this paper was arranged by Editor A. H. Marshak.

The authors are with the Dipartimento di Elettronica, Informatica e Sis-temistica (DEIS) of the University of Bologna, 40136 Bologna, Italy (e-mail:[email protected]).

Publisher Item Identifier S 0018-9383(99)05098-4.

and, finally, it is currently unclear if the performance gainwhich can be achieved at the extreme miniaturization limits isreally worth the effort of such a development.

From the standpoint of device physics, one of the mostimportant problems to be overcome is the nonscalability of theoxide thickness below about 1.5 nm. This practical limit doesnot allow us to keep the ratio between channel length and oxidethickness at about 50, as it is with the current technologies.This has a double impact.

1) A severe short-channel effect may be expected as thelateral dimensions are scaled below 70 nm.

2) the current density and the device transconductance perunit width will not increase as a result of scaling, evenif the supply voltage is kept constant at about 1 V.

In order to face the above problem, new device architecturesare being devised which are more effective in preventing theshort-channel effect. Among the various proposals, the SOIDouble-Gate MOSFET (DG-MOSFET) appears to be one ofthe most promising [3]–[8] due to the shield-effect playedby the double gate, which strongly reduces drain-inducedbarrier lowering and minimizes threshold sensitivity to channellength. A previous Monte Carlo simulation of such a device[6] provided convincing evidence that the channel length canbe reduced down to 30 nm for a silicon-film depth of 5 nmand an oxide thickness of 3 nm, with an acceptable short-channel effect. Also, the predicted device transconductanceturned out to be as large as 2.3 mS/m and 1.3 mS/m forn- and p-channel DG-MOSFET’s. The above results make theDG-MOSFET very attractive for sub-0.1-m technologies.

In this paper, we address the problem of developing acompact model for the DG-MOSFET which fully accountsfor quantum mechanical effects, including motion quantizationnormal to the Si–SiO interface, band splitting into subbandsand velocity overshoot of the channel carriers. The paperis organized as follows: in Section II we find a suitableexpression for the electron charge within the channel basedon the gradual-channel approximation; in Section III we derivethe device characteristics in strong inversion based on the drift-diffusion model; Section IV addresses the device behaviorin subthreshold. Section V is devoted to the developmentof a model which holds both in subthreshold and stronginversion, and ensures a smooth transition between the tworegions. In Section VI a simplified energy-balance transportmodel is worked out which allows us to compare the drain-

0018–9383/99$10.00 1999 IEEE

BACCARANI AND REGGIANI: COMPACT DOUBLE-GATE MOSFET MODEL 1657

Fig. 1. Double-Gate SOI MOSFET cross section. In this work, we considerd = 5 nm, dox = 3 nm, and the source-drain impurity concentrationND = 10

20 cm�3.

current calculations with Monte Carlo data; the main resultsof the present study are discussed in Section VII. Finally,conclusions are drawn in Section VIII.

II. ELECTRON CHARGE WITHIN THE CHANNEL

The structure of the Double-Gate SOI MOSFET is depictedin Fig. 1. In our notation, the depth of the semiconductor filmis ; the channel length , and the channel width . Ourreference frame has its origin at the source end of the channeland is located midway between the two gates. Carriers flowalong the -axis from source to drain; represents the verticalcoordinate, normal to the gates, while the device width extendsalong the -axis. The band diagram of the DG-MOSFET isillustrated in Fig. 2, under the assumption of a positive gate-source voltage . From the above figure, it turns out thatthe following equation holds

(1)

where

Fermi level in the gate;work function of the gate material;electron affinity of the semiconductor;voltage drop across the gate insulator;conduction band edge at the central sectionof the channel;conduction band edge at the Si–SiOin-terface.

By dividing both sides of (1) by the electronic charge andrearranging, one finds

(2)

where is the gate voltage, is theelectric potential at the center of the channel, andis the surface potential.

The terms on the r.h.s. of (2) can be expressed as a functionof the charge density per unit area , ,

, and being the electron, acceptor, and donor densitiesper unit area, respectively,

(3)

Fig. 2. Band diagram of DG-MOSFET.EFG andEFn represent the Fermilevels in the gate and the silicon channel, respectively.

(4)

where is the oxide capacitance per unit area andis the depletion capacitance per unit area. Equation (4)

is based on the assumption of a uniform charge distributionwithin the channel. From (2) to (4) we find

(5)

where represents the gate capaci-tance per unit area andis the effective gate voltage. In the above expression,

and are the contribution to thegate voltage due to the channel doping. If the semiconductoris undoped and the gate material is polycrystalline siliconwith the Fermi level at the conduction-band edge, then

and .Due to the confinement of electron motion normal to the

Si–SiO interface, the conduction band within the transistorchannel is split in several subbands, each of which is associatedwith the corresponding energy eigenvalue. Hence, the channelcharge per unit area may be expressed as

(6)

where represents the density of statesin the subband at energy ; is the density-of-stateseffective mass, is the number of subbands generated byeach minimum of the silicon conduction band, isthe number of minima, and is the electron quasi-Fermi


level within the channel region. More specifically, for a siliconcrystal with orientation, two energy eigenvalues withdegeneracy factor and are created by the sixminima in the conduction band. Also,

(7)

(8)

where and .The charge distribution within the channel is expressed by

(9)

(10)

and is shown in Fig. 3, where the first ten subbands areaccounted for. The accuracy of (8) and (10), which are derivedunder the assumption of a box-like potential, thus neglectingthe coupling between Schrodinger and Poisson’s equations,is discussed in Appendix A. Here we can anticipate thatthe above equations are expected to become less and lessaccurate for large values of the electron density andfor increasing values of the silicon thickness. Also, (9)and (10) are clearly inconsistent with the assumption of auniform space charge within the channel, which leads to (4)and to the subsequent depletion capacitance . Amore accurate integration of Poisson’s equation based on (9)and (10) would lead to the conclusion that

. By defining the electron quasi-Fermi potential, (6) can be rewritten as follows:

(11)

and, by equating (5) and (11), we find

(12)

Equation (12) establishes a relationship betweenandfor any given value of , as shown in Fig. 4. It is worthpointing out that in weak inversion, where ,

. In strong inversion, instead, where ,.

By defining the semiconductor capacitance, as shown in(13) at the bottom of the page, the differential gate capacitanceper unit area is thus

(14)

Fig. 3. Electron charge distribution within the silicon layer for different biaspoints.

Fig. 4. Numerical calculation of the electron potential at the center of thechannel (z = 0) as a function of the electron quasi-Fermi potential fordifferent bias points, following (10).

From the last equation in (14), it turns out that

(15)

so that

(16)

Equation (16) shows that, as for the ordinary MOSFET, thesemiconductor capacitance is in series with the gate capaci-tance . In this case, however, the latter already accounts forthe extended space distribution of the channel charge within

(13)


Fig. 5. Normalized differential gate capacitanceCgd=2CoxversusV 0

G fordifferent values of the quasi-Fermi potential�Fn. The curves show thatCgdnever reaches the oxide capacitance.

the semiconductor film, which never allows to reach, evenasymptotically, the oxide capacitance . This is shown inFig. 5, where the normalized differential gate capacitance isplotted against for different values of the quasi-Fermipotential . Here, we assume that . Itshould be noticed that, for small values of the silicon thickness

, the curves of Fig. 5, which fully account for quantum-mechanical effects and Fermi statistics, are rather general.However, for increasing values of the channel thickness,a self-consistent solution of the Schrodinger and Poisson’sequations would lead to a depletion capacitancelarger than

in strong inversion, due to the splitting of the chargedensity in two near-surface modes. Hence, the asymptoticvalue of the differential capacitance would become largerthan that represented in Fig. 5, ultimately leading towhen two separate MOSFET channels develop at the twointerfaces.

In the limit of Boltzmann statistics, (11) can be simplifiedto give

(17)

having defined the effective density of states in conductionband

(18)

From (17), (13) may be considerably simplified to provide

(19)

which holds true only under weak-inversion conditions.

III. D EVICE CHARACTERISTICS

The present analysis is carried out under the drift-diffusionmodel of current transport within the DG-MOSFET channel.

Fig. 6. Drain I–V characteristics. The numerical form is given by (23),while the analytical expression follows (25). The results have been obtainedwith �no = 200 cm2/Vs, vsat = 10

7 cm/s andL = 30 nm.

Also, Shockley’s gradual channel approximation is assumedto hold. Under such conditions, the drain current may beexpressed as

(20)

where and the electron mobility is assumedto be given by

(21)

Accounting for (21) and separating the variables gives us

(22)

Equation (22) can be formally integrated from source to drain,giving

(23)

where is the drain-source voltage and .Equation (23) holds so long as , where ,defined below in (27), is the drain saturation voltage, i.e., thedrain voltage at which saturation of the output characteristicsoccurs. In order to solve the integral on the r.h.s. of (23),we need an explicit relationship . Unfortunately,(12) provides such a relationship only in implicit form, sothat the drain current cannot be extracted in closed form.However, (23) can be numerically integrated, and leads to thedevice characteristics shown in Fig. 6. Here again we stressthat (23) accounts for quantum mechanical effects and Fermistatistics, and is therefore quite general within the gradual-channel approximation.

We define the device threshold as the gate-source voltageat which the semiconductor capacitance equals the gatecapacitance . This corresponds to the intersections of the


Fig. 7. Threshold voltage versus temperature for differentd values.

curves in Fig. 5 with the horizontal line drawn at .At these intersections, the potential is expressed by

(24)

We further assume that, in strong inversion, is pinned atthe threshold value (25), which allows for an easy integrationof (23). We find

(25)

where , and the threshold voltage is definedas

(26)

Equation (25) is similar to the standard form of the MOSFETcharacteristics. Two main features, however, make (25) dif-ferent from the well-known MOSFET current. First, the DG-MOSFET is a three-terminal device, as opposed to the bulkMOSFET which is a four-terminal device; hence, the thresholdvoltage is not influenced by the body effect, as it appears from(26). Next, for the standard MOSFET, the quadratic form ofits characteristics results from the assumption of a uniformdepletion charge along the channel. In this case, instead, thedepletion charge is strictly constant, and (25) is rigorous fromthis standpoint.

The threshold voltage is plotted in Fig. 7 against temper-ature for different semiconductor depths. It is worth pointingout that, for nm, the temperature coefficient of thethreshold voltage is only about 0.5 mV/K and that the latterdecreases with decreasing values of.

Equation (25) holds up to the saturation of the drain current,i.e., for , which can be obtained by taking thederivative of versus and equating to 0. One finds

(27)

When , the drain current takes the form

(28)

By accounting for (27), the drain current may also be expressedas

(29)

Equation (29) may be interpreted by observing that the draincurrent saturates at some point within the channel, where

. At the same point, the channel charge is. It should be noticed that, sometimes,

is omitted in (29) for standard MOSFET’s. This isobviously erroneous, as it would lead to roughly the samecurrent for n- and p-channel MOSFET’s in view of theirsimilar saturation velocity. This is not the case, however, as itturns out that the drain current in p-MOSFET’s is roughlyone half of the drain current in n-MOSFET’s for similarbias conditions. Equation (29) accounts for such a differentbehavior via , which is a strong function of and istherefore markedly different for n- and p-channel MOSFET’s.

Equations (23) and (25) are shown in Fig. 6 under stronginversion conditions. They only deviate when approaches

.

IV. SUBTHRESHOLD CONDITION

If the channel charge , then the electricpotential and is thus uniform along the channel.Therefore,

(30)

where . The drain current

(31)

can easily be integrated after separation of the variables

leading to

(32)

where is the electron diffusivity.From (26) and (32), it turns out that the DG-MOSFET

current in subthreshold can also be expressed as

(33)

which is formally similar to the standard MOSFET currentunder the same operating conditions. Equation (33), however,exhibits an ideality factor equal to one (Fig. 8). Thus, the


Fig. 8. I–V characteristics. The numerical form is given by (23), while theanalytical expressions for strong inversion and subthreshold follow (25) and(33), respectively. The inversion-layer charge model is presented in Section V,(41)–(43).

slope of the DG-MOSFET current in subthreshold is about60 mV/decade at room temperature, which represents anoptimum performance for MOSFET’s and, in general, for anysemiconductor device.

V. THE INVERSION-LAYER CHARGE MODEL

In the previous sections, different operating regimes areinvestigated by taking suitable simplifying assumptions, thusintroducing models with limited validity ranges. On the otherhand, the definition of a compact model needs a continuousfunction that provides the correct transition between the weakand strong inversion regions.

To this purpose, the channel charge within the DG-MOSFETis determined by integrating the differential gate capacitanceper unit area . From (16), we find

(34)

In subthreshold conditions, the electric potentialcan be setequal to , and the semiconductor capacitance becomes

(35)

By substituting the above expression in (34) and integratingwe find

(36)

Equation (36) is not only valid in weak inversion, where, beingthe exponential much less than unity

(37)

but is also valid in strong inversion, where

(38)

The reason for this is that, although (36) breaks down in stronginversion, the integrand function in (34) is nearly equal to

, because . As a consequence, (36) provides acorrect result both in weak and strong inversion, giving thecorrect transition between the two regions. The drain-sourcecurrent is therefore

(39)

The solution of the integral is carried out in Appendix B. From(75) and (76) the drain current can be expressed as

(40)

where is given by

(41)

for ;

(42)

for , and

(43)

for .Although the present model expresses the drain current as a

series, under both strong inversion and subthreshold conditionsonly a few terms suffice to reach convergence. Furthermore,due to a well-known property of the series with alternatingsigns, the magnitude of the last evaluated term sets an upperlimit to the global error in the computation of the sum.

Equations (41)–(43) are shown in Fig. 8 along with the sim-plified forms (25) and (33). A slight discrepancy is observedbetween the latter model and the numerical integration of (23)under moderate inversion conditions. This is thought to be dueto the Boltzmann statistics, which makes the growth of thesemiconductor capacitance (35) againstsubstantially fasterthan (13), based on Fermi statistics. The current at thresholdturns out to be

(44)

when the device operates in saturation.


Equations (41)–(43) are continuous and differentiable func-tions with respects to both and . In order to extendsuch a property to the drain current (40), the mobility function

must be a continuous and differentiable function aswell. To comply with this requirement, we define

(45)

which continuously varies from to . Next, we set, and replace to

in (41)–(43). An additional problem is that , asdefined by (27), does not provide a differentiable transitionbetween subthreshold and strong inversion. Although the sat-uration voltage in subthreshold is somewhat undefined dueto the exponential dependence of the drain current, wetake . A function which ensures a smoothtransition between the above weak inversion limit and (27) isthe following:

(46)

Here, (27) is extended to the case of as follows,in order to ensure the differentiability of (45):

(47)

for and

(48)

for .

VI. NONSTATIC EFFECTS

Due to the extremely short channel of the investigated DG-MOSFET, the carrier behavior within the channel is expectedto be quasi-ballistic, thus allowing a strong velocity overshootto be reached. In order to estimate the influence of velocityovershoot on the device performance, we start with a simplifiedenergy-balance model.

The energy-balance equation for a two-dimensional electrongas (2-DEG) can be written in general form as follows:

S J E (49)

where the energy flowS, the current densityJ, and the electronenergy are defined as follows:

S (50)

J (51)

(52)

In (49)–(52),E is the electric field, is the electron tempera-ture, is the carrier velocity, is the average energyof the carriers in equilibrium, is the energy relaxation time,and is the electron thermal conductivity.

By neglecting the heat flow in (50) and the convective termin (52), the one-dimensional (1-D) form of (49) becomes

(53)

and, by remembering that in a 1-D geometry const.,(53) takes the form

(54)

where the energy-relaxation length . Equation (54)can be formally integrated under the assumption of constant

to give

(55)

If and , we find

(56)

By introducing the temperature profile (55) in the drain-currentmodel, the influence of nonstatic effects on the DG-MOSFETperformance is accounted for. The model we start with is givenby (20) combined with the assumption (24), which holds instrong inversion. We may thus write

(57)

Also, the electron mobility is now given by

(58)

The value of is chosen in accordance with (21) and (54) instatic conditions, i.e., with . We find

(59)

In order to evaluate the temperature profile of the carriers,the coupled system of (54) and (57) ought to be solved.Accounting for (58) and (56) and separating the variables,(57) gives us

(60)

which can be integrated from 0 to, leading to

(61)

By extracting from (54) and substituting it into(61), we obtain

(62)


The introduction of (56) into (62) gives the integral equation

(63)

From (63) the drain current can be formally expressed as

(64)

In order to calculate the drain current, however, the integralequation (63) must be solved, because thedependence onthe channel position is required in the above calculation.

It is of interest to notice that the nonlocal effect relatedwith the gradual heating of the carriers along the channel isaccounted for by a convolution integral involving the potentialdistribution along the channel and an exponential kernel with acharacteristic attenuation length given by the energy relaxationdistance.

Using a simplified solution of (63), given by the first-orderapproximation for , the final result is

(65)

where

(66)

It may be worth pointing out that in (66) differs fromin (23) by the factor , which becomes importantwhen the channel length is of the same order of magnitude asthe energy-relaxation length . This is in fact the case when

m.Equation (65) holds so long as , where

is the drain saturation voltage

(67)

The influence of nonstatic effects is shown in Fig. 9, where(65) is compared with previous results. As expected, theenergy-balance model gives higher currents compared with thedrift-diffusion model, due to the electron velocity overshootwithin the channel. Thus, nonstatic effects are accounted forby a modified mobility expression which allows the carriervelocity to exceed the saturation velocity if the channel lengthbecomes comparable with the energy-relaxation length.

VII. RESULTS

A wide set of Monte Carlo data have been collected byrunning a number of simulations using DAMOCLES [9].More specifically, the – characteristics of an n-channel DG-MOSFET with 30-nm gate length, 5-nm semiconductor depth,

Fig. 9. Comparison between the drift-diffusion and the energy-balance mod-els: the current equation is calculated with the same parameter values as inFig. 6; also,�w = 0:3 ps.

Fig. 10. Longitudinal particle energy profile in a DG-MOSFET channel. Thelines show DAMOCLES conduction band edge energy (averaged across thethickness of the channel). We can define an effective channel length of 20nm, starting from 8 nm inside the channel.

and 3-nm gate-oxide thickness were computed at different biaspoints. One of the main problems when fitting numerical datawith a compact model is the extraction of the electrical channellength, which differs from the metallurgical one due to theenergy barrier experienced by the carriers at the source endof the channel. Fig. 10 plots the potential distribution alongthe channel for various drain voltages. From inspection ofthe figure, it turns out that the effective channel length isapproximately 20 nm, irrespective of the drain voltage. Thus,we assumed nm in our plots.

As far as the low-field electron mobility is concerned,the latter is a function of the transverse field at the interface.In order to incorporate the transverse-field dependence into thecarrier mobility model, we consider that the transverse field at


Fig. 11. Comparison of the DG-MOSFET output characteristics. Solid lines:analytical model; symbols: Monte Carlo simulations.�no = 220 cm2/Vs,vsat = 8 � 106 cm/s,� = 0:2 V�1, � = 80 mV/V.

the interface is proportional to the channel charge [given by(36)] and define the effective mobility as

(68)

where is a parameter that can be estimated with a fittingprocedure on the– characteristics. From (68), a modifieddefinition of and results. We find

(69)

Moreover, in the saturation regime, the drain-induced barrierlowering is accounted for in order to reproduce the moderaterise of the current with in saturation. More specifically, alinear variation of the threshold voltage with is accountedfor by simply substituting with ( ). A theoreticalevaluation of the factor requires the two-dimensional (2-D)Poisson equation to be solved within the device. We did notattempt any analytical solution of the 2-D Poisson equation;rather, we treat as a fitting parameter. In the followingfigures, a factor mV/V has been assumed. The outputcharacteristics of the DG-MOSFET are compared with self-consistent Monte Carlo simulations in Fig. 11, showing a veryreasonable agreement.

By introducing the inversion-layer charge model presentedin Section V, the drain current model can be used to correctlyevaluate the transition between weak and strong inversion,as shown in Fig. 12. The DG-MOSFET intrinsic transcon-ductance is plotted in Fig. 13. It may be noticed that theintrinsic transconductance exceeds 5 mS/m at

V. It is worth pointing out that the above plotis based on the assumption that the carrier mobility within

Fig. 12. Log-plot of drain current versus(VGS � VT ).

the DG-MOSFET is similar to the MOSFET mobility for thesame effective transverse field. According to a recent study[10], the channel mobility in SOI-MOSFET’s decreases forfilm thicknesses below about 10 nm, due to the excessivestress in the film, which would cause defect formation. Suchan effect is not accounted for in our computation, for thelatter seems to be more related to the fabrication processthan to fundamental physical problems. Furthermore, the in-trinsic transconductance might be practically offset by theparasitic source/drain resistance , unless the latter is muchsmaller than . This implies that the spe-cific source resistance m.This goal may be technologically difficult to achieve. On theother hand, if the technology of the source/drain contacts doesnot improve in direct proportion to the increase in devicetransconductance, much of the advantage in device scalingwill be lost. By the way of example, if the specific sourceresistance m, the device transconductanceturns out to be halved. The Monte Carlo simulation [6], whichincluded a fair estimate of the source resistance, led indeed toa transconductance estimate of 2.3 mS/m.

VIII. C ONCLUSIONS

In this work we have developed a compact model of theDG-MOSFET which accounts for charge quantization, Fermistatistics and nonstatic effects within the channel region.Rather surprisingly, the device equations can be reducedto a formalism which is similar to the standard MOSFETmodels, although some important differences affect, evensubstantially, the device behavior. One of the key points isthe definition, and the related expression, of the thresholdvoltage. We define the threshold voltage as the valueat which the semiconductor capacitance equals the gatecapacitance . With this definition, we nicely account forthe silicon thickness dependence of the threshold voltage. Ourmodel provides a continuous transition of the MOSFET currentbetween weak and strong inversion, and accounts for nonstatic


Fig. 13. Calculated transconductance atVDS = 0:1, 0.2, 0.4, and 0.8 V.

effects which occur within the channel due to the comparablevalues of the channel and the energy-relaxation lengths.

Our analysis confirms some previous findings that the DG-MOSFET is very promising for miniaturization below 0.1m.The main reasons behind this conclusion are the following.

1) Due to the elimination of the bulk contact, the draincurrent increases in subthreshold as

, with an ideality factor equal to 1. Thisis extremely important to reduce the leakage current atlow threshold voltages: as an example, withV, the leakage current at V turns out to be

1 pA/ m.2) The shield effect of the double gate makes the DG-

MOSFET more immune to the short-channel effect thanany bulk or SOI MOSFET, thus relaxing the need for aratio . In our example, and thedrain-induced barrier-lowering factor mV/V.

3) The shield effect of the double gate prevents punch-through to occur even at zero doping concentrationwithin the channel, which is important to prevent degra-dation of the output characteristics and excess leakagecurrents at zero .

4) The current increase due to velocity overshoot is verysubstantial at the dimensional limits afforded by theDG-MOSFET, with improved intrinsic device transcon-ductance, which exceeds 5 mS/m atV. Also, the transit time across the channel can be keptbelow 0.2 ps, which exceeds the performance of a BJTwith a corresponding base thickness.

5) For any given device size, the DG-MOSFET transcon-ductance is at least twice as large as that of any standardMOSFET, because of the action of the double gate.

In view of the above considerations, the DG-MOSFET isexpected to offer outstanding performance in digital logic,provided the source/drain resistance can be kept below theintrinsic device resistance. Besides, the rather conservativeoxide thickness used in our model makes us believe that an

even more aggressive design featuring nm andnm is possible, with further enhanced performance.

Many practical hurdles must be overcome in order to makethis device feasible.

1) The selection of the gate material, most probably arefractory metal with a suitable work function, is akey point to allow for an undoped silicon film, whichis expected to be beneficial for carrier mobility andthreshold uniformity. An added advantage of a metalgate is that no transconductance degradation due to thegate depletion would occur.

2) The problem of self-aligning the lower gate to thesource/drain regions is very difficult to solve. Yet, thisself-alignment is essential in order to reduce the gate-drain and gate-source parasitic capacitances.

3) The silicon film sandwiched by two oxide layers must bedefect free and should exhibit a good-quality interface.

4) Last, but not least, the lithographic tools and processesneeded to support nanofabrication at these extreme limitsare yet to be developed.

From the above considerations, it is quite clear that thedevelopment of a suitable technology to fabricate the DG-MOSFET is the key problem to overcome in order to takeadvantage from this extremely-interesting device concept.

APPENDIX A

In this Appendix, we discuss the validity of (8) and (10),which are derived under the assumption of a box-like potentialwell with an infinite barrier height, and neglect, therefore, thecoupling between Schrodinger and Poisson’s equations. It isexpected that such a simplifying assumption may break downin the limit of large electron densities and thicker silicon films.In order to estimate the validity range of the above assumption,we have computed the first-order correction to the energyeigenvalues using the time-independent perturbation theory.In doing so, we assumed, as a perturbation potential energy

(70)

where is the average space chargedensity within the potential well. Thus, we find

(71)

From (71) it turns out that meV for an electrondensity cm and nm. For larger values of

, meV. Although represents a substantialfraction of meV, the corresponding change inelectron density , accounting for the correction terms (71)turns out to be smaller than 2% for any value of V.Also, it should be noticed that cm is a ratherlarge carrier density which leads to a field oxide of 2.5 MV/cm.For smaller values of , decreases in direct proportion


with . We may thus conclude that, for the purpose ofestimating the performance of the dual-gate MOSFET, the useof (8) and (10) may be justified.

On the other hand, if the electronic charge grows above10 cm , the fundamental energy eigenvalue may becomesmaller than . Hence, the space-charge density per unitvolume would exhibit a relative minimum at the center ofthe channel, until the splitting of the fundamental state intwo surface modes would occur. At these extreme limits, theeffective depletion capacitance is expected to grow above

, thus leading to a higher current for a given gatevoltage than predicted by the model.

APPENDIX B

In this Appendix we evaluate the integral (39). First, let usdefine

(72)

(73)

Substituting (72) and (73) in (39), we find

(74)

where if andif . The above

integral cannot be solved in closed form, but requires a seriesexpansion of the integrand function. The primitive is

(75)

for , and

(76)

for . The integration constant at the r.h.s. of(76) is meant to ensure continuity of the primitive function at

. This conclusion comes from limit of the series in(75) and (76) for , which turns out to be .

REFERENCES

[1] The National Technology Roadmap for Semiconductors,SemiconductorIndustry Assoc., San Jose, CA, 1995.

[2] A. Yu, “The future of microprocessors,”IEEE Comput., vol. 16, pp.46–53, Dec. 1996.

[3] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa,“Double-gate silicon-on-insulator transistor with volume inversion: Anew device with greatly enhanced performance,”IEEE Electron DeviceLett., vol. EDL-8, pp. 410–412, Sept. 1987.

[4] S. Venkatesan, G. V. Neudeck, and R. F. Pierret, “Double-gate operationand volume inversion in n-channel SOI MOSFET’s,”IEEE ElectronDevice Lett.,vol. 13, pp. 44–46, Jan. 1992.

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Giorgio Baccarani (S’68–M’80–SM’92–F’98) re-ceived the Dr. Ing. degree in electrical engineeringin 1967 and the Dr. degree in physics in 1969, bothof them from the University of Bologna, Bologna,Italy.

Currently, he is a Full Professor in charge ofan annual Course on Digital Systems Design atthe University of Bologna. He has devoted his re-search work to various aspects of microelectronics,including processing technology, device physics andcharacterization, current transport in semiconductor

materials and devices, submicron MOSFET scaling and optimization, numer-ical analysis of semiconductor devices, analog design and, more recently,cognitive systems architectures. He has authored or coauthored about 130papers, and his activity is the result of an extensive cooperation with National,European, and American companies, as well as with a number of researchinstitutions in Italy and abroad. He was a Visiting Scientist at the AT&TBell Telephone Laboratories, Murray Hill, NJ , in 1969 and 1970; at theIBM T.J. Watson Research Center, Yorktown Heights, NY, in 1981, 1982,1983, and 1988. He is currently chairman of the Scientific Boards of theNational Institute for Microelectronics Technology (CNR-IMETEM) and ofthe Joint Laboratory for Innovative System Design recently set up by ST-Microelectronics and the University of Bologna. At the European level he is,or has been, a member of the Long-Term Research Advisory Group, the JointNSF-CEC Strategy Group, and the Pathfinder Committee.

Susanna Reggianireceived the Dr. Ing. degree inelectrical engineering in 1997 from the Universityof Bologna, Bologna, Italy, where she is currentlypursuing the Ph.D. degree in electrical engineering.

Since April 1997, she has been working in theDepartment of Electronics (DEIS) of the same uni-versity in the field of the numerical simulation ofsemiconductor devices.

A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects

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