A 0.18µm CMOS low-power charge-integration DPS for X-ray imaging

IEEE BioCAS 2009 Intro ADC Dark Gain Bias Results Conclusions 1/23

A 0.18µm CMOS Low-PowerCharge-Integration DPS

for X-Ray Imaging

Roger Figueras1, Justo Sabadell2, Josep Maria Margarit1, ElenaMartín1, Lluís Terés1 and Francisco Serra-Graells1

[email protected]

1Integrated Circuits and Systems (ICAS)Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC)

2X-Ray Imatek S.L.

November 2009

R. Figueras et al. IMB-CNM(CSIC) and X-Ray Imatek S.L.


1 Introduction

2 Lossless A/D Conversion

3 Dark Current Cancellation

4 Gain Programmability and Built-in Test

5 Local Bias Generation

6 CMOS Integration and Results

7 Conclusions



1 Introduction






7 Conclusions



Introduction

I Hybrid X-ray digital imagersI Low-energy (<20keV) medical

applications: mammography

Si or CdTeX-raysensor

Vcom

CMOScircuit

X-rayparticlehit

bumpbonding

digital X-rayimager

DPS

e/hcloud

- +

Isens

Isens

time

I DPS circuits for visible spectrum:

8 e−/h+ collection8 Pulsed X-ray input current

(typ. 15ke−/hit@10µs)8 Dark current + gain FPN8 Built-in test

I Few DPS for X-ray based onphoton-counting:

8 Saturation due to pile-up8 Losses from charge sharing

with neighbors



Introduction

I Hybrid X-ray digital imagersI Low-energy (<20keV) medical

applications: mammography

Si or CdTeX-raysensor

Vcom

CMOScircuit

X-rayparticlehit

bumpbonding

digital X-rayimager

DPS

e/hcloud

- +

Isens

Isens

time

I Novel X-ray DPS proposal based oncharge-integration to solve all plus:

4 Self-biasing4 Lossless A/D conversion

Isens

Vcom

digitalread-out

digitalprogram-in

A/Dconversion

bin

Darkcurrent

cancellation

Built-intest Local bias

generation

DigitalI/O

Gainprogramming

bout

Iadc

Idark

Itest

. . . subthreshold operation and circuit reusefor a low-power and compact DPS!



1 Introduction






7 Conclusions



Lossless A/D ConversionI Predictive scheme:

Pulse density modulatorLow-pass

digital filter

Iadc

Vpulse

qadcVint

+

-

0

binit

V -Vref th

Vref

qadc = bnadcidealc

nadcideal = Tframe

Tpulseideal= Tframe

CintVthIadc

e.g. 10bit and Tframe=10msrequire Tres<5ns!

I Under real low-power operation:

Vint

Vpulse

Vref

Vref

binit

Vint

Vpulse

Tframe

Tpulseideal

(a) V -Vref th

V -Vref th

1 2 3 4 5 6 7

1 2 3 4 5 6 7

VrefVint

Vpulse Tres

V -Vref th

1 2 3 4 5 6

(b)

(c)

nadcreal = nadcideal

1 + TresTframe

nadcideal

Tres <Tframe

2q2fullscale

for <0.5LSB error



Lossless A/D ConversionI Predictive scheme:

Pulse density modulatorLow-pass

digital filter

Iadc

Vpulse

qadcVint

+

-

0

binit

V -Vref th

Vref

Vint

Cint

Vref

Creset/CDS

Iadc

Vpulse

binit

Vpulse

V -Vref th

I Under real low-power operation:

Vint

Vpulse

Vref

Vref

binit

Vint

Vpulse

Tframe

Tpulseideal

(a) V -Vref th

V -Vref th

1 2 3 4 5 6 7

1 2 3 4 5 6 7

VrefVint

Vpulse Tres

V -Vref th

1 2 3 4 5 6

(b)

(c)

nadcreal ≡ nadcideal

4 Tres independent4 min(Tres) for charge redistribution4 max(fpulse)= 1

2Tres



Lossless A/D ConversionI CMOS proposal:

Vint

Cint

Vref

Creset/CDS

Iadc

Vpulse

M1

M3 M4

M2

Ibias

M8

M10

Ibias

M5 M6

M7

M11 M13

Ibias

M14

M9

M12

M15

binit

breset

breset

breset

breset

V Vref th+(-1)bh e/

bh e/I Capacitive

TransImpedanceAmplifier (CTIA) =M1-4 + Cint

I Non-overlapped resetby M6-7

4 bh/e for controllingcollection polarity

4 Inherent CorrelatedDouble Sampling(CDS)



1 Introduction






7 Conclusions



Dark Current Cancellation

Isens

M3

Vref

M1

M8

M4

M5M6

PDM parts

Cdark1

Cdark2

Vint

M9M10

M11

M12M2

M7M13

M14

M15

M16

Cint

Vdark1

Vdark2

Á1

Á1

Á2

Á3

Á4

Á2

Á1

Á2

Á1

I >sens 0bh e/ I <sens 0

coarse fine hold

Á2

Á3

Á4

fine holdcoarseVref

Isens

M3 M4

M5M6

PDM parts

Cdark2

Vint

Cint

Vdark2

M1

Cdark1

M2Vdark1

S1

S2S3

S4I Current copiers based

Idark auto-calibration

4 Coarse + fine for chargeinjection compensation

4 Composite switches forlong retention time(up to 1s)

4 Dual operation for bh/e

4 ADC PDM parts reused4 CTIA offset independent



1 Introduction






7 Conclusions



Gain ProgrammabilityI FPN compensation via individual Vth control:

Vint

Cint

Vref

binitPDM parts

V Vref th+(-1)bh e/

M1

Csamp

Cmem

Á2 Á2Á3

bin

Á1

Á1 Á1

Á1

I >sens 0bh e/ I <sens 0

programming

Á2

Á3

samplehold programming

samplehold

bin

Á2 3+Á

binit

init init

qdac B(0... -1) qdac B(0... -1)

Vprog

I SC DAC based4 Serial program-in

during read-out (nospeed losses), forCsamp≡Cmem :

Vprog = VDD

B−1∑i=0

qdac(i)2B−i ≥ 0

4 Polarity + storage:

Vth = Cmem

CintVDD

B−1∑i=0

qdac(i)2B−i

4 ADC PDM reused4 Built-in test through

charge injection. . .



1 Introduction






7 Conclusions



Local Bias Generation

I Ibias and Vref DPS generatorI PTAT core M1-M4 in weak inversion

saturation:

Vbias = Ut ln P

I M8 and M9 in strong inversionsaturation and conduction:

Ibias = QIS9 IS9 = 2nβ9U 2t

Q =

[ln P

2(M + 1)

(√MN +

√MN + M + 1

)]2

I M12 in strong inversion saturation:

Vref = 2n√

QXY Ut + VTO

Vbias

Ibias

M6

M1 M2

M7

P 1

M3 M4

P 1

1M

M8

M5

1

N

M9

1

M11

X

M12

Y

Vref

M10

1

4 IS -based Ibias for lowdependence on technology

4 Vref thermal compensation



1 Introduction






7 Conclusions



CMOS Integration

I DPS cell layout:

20 m¹X-ray sensorbumping pad

Local biasgeneration

A/D conversion(PDM-CTIA)

A/D conversion(PDM-comparator)

A/D conversion(filter-counter)and digital I/O

Dark currentcancellation

Gain programmingand built-in test

A/D conversion(PDM-control)

I Ibias=250nAI Vref=670mVI Cint , Creset/CDS ,

Cmem andCsamp=100fF

I B=(10+1)bitI 40mV<Vth<400mV



CMOS Integration

I DPS test oriented circuit:

500 m¹

DPS singleexperiments

DPS matrixfor crosstlak

studies

I Ibias=250nAI Vref=670mVI Cint , Creset/CDS ,

Cmem andCsamp=100fF

I B=(10+1)bitI 40mV<Vth<400mV

I Single transistorIsens emulators

I 0.18µm 1P 6Mtriple-well CMOStechnology



Experimental Results

I PDM transfer function:

1p 10p 100p 10n 100n

10

100

1k

10M

1

fpulse[H

z]

Isens [A]

1n

10k

100k

1MT ¹res=0.4 s

. . . for Vth=0.4V (’00010010110’).

I DPS performance:

Parameter Value UnitsSupply voltage 1.8 VDark current range 0.01 to 20 nATransfer gain <1/50 LSB/ke−

Equivalent noise charge 1.5 to 18 ke−rmsIntegration time 10 to 1000 msOutput dynamic range 10 bitCrosstalk <0.5 LSBProgram-in/read-out speed 50 MbpsStatic power consumption 5 µWBias mismatching (±σ) <10 %Silicon area 100×100 µm2



Experimental Results

I Overall transfer function:

1p 10p 100p 1n 10n

10

100

1k

10k

1

Npulse[L

SB

]

Isens [A]

1023

Tframe=10ms

. . . for Vth=0.4V (’00010010110’).

I DPS performance:

Parameter Value UnitsSupply voltage 1.8 VDark current range 0.01 to 20 nATransfer gain <1/50 LSB/ke−

Equivalent noise charge 1.5 to 18 ke−rmsIntegration time 10 to 1000 msOutput dynamic range 10 bitCrosstalk <0.5 LSBProgram-in/read-out speed 50 MbpsStatic power consumption 5 µWBias mismatching (±σ) <10 %Silicon area 100×100 µm2



1 Introduction






7 Conclusions



Conclusions

I Novel charge-integration DPS for X-ray digital imagingI In-pixel lossless A/D conversionI Dark current automatic compensationI FPN cancellation through digital gain programmabilityI Built-in test capabilitiesI Local analog bias and references for low crosstalkI Very low-power CMOS circuitsI Preliminary test results in 0.18µm 1P 6M triple-well

CMOS technology



Future Work

I Scaling, scaling and scaling!20 m¹

100 m£¹ 100 m

tested

¹

70 m 7£ 0 m (50%)

being integrated

¹ ¹

50 m 5£ 0 m (25%)

under development

¹ ¹

. . . thanks foryour attention.


A 0.18µm CMOS low-power charge-integration DPS for X-ray imaging

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