7.2 Hardware stereo trigger - Archivo Digital UPM

7. Trigger Interface Board. 151

RJ45 connectors between the clock board and the TIB, and the ones of the RJ45 connectors of thelinks between the TIB and the backplanes, are assigned as it is shown in table 7.1. The signal namedas CABLE DETECT, not yet mentioned, is used to ensure that the plug is connected properly andjust consists on a 1 kΩ resistor to ground in the reception side, and an input pin of the FPGA witha weak pull-up in the transmission side. So, the FPGA detects if it is properly connected or not.

to clock board from clock board to/from central to-from not centralbackplane backplane

Pin Signal Signal Signal Signal1 CAMERA TRIGGER + CLK 10MHZ + L1 TRIGGER + TRGTYPE CLK +2 CAMERA TRIGGER - CLK 10MHZ - L1 TRIGGER - TRGTYPE CLK -3 TRGTYPE0 + SOFT ARRAYTRIG + CAMERA TRIGGER + TRGTYPE DATA +4 TRGTYPE1 + SPARE 1+ BUSY + RES TOPO1 +5 TRGTYPE1 - SPARE 1- BUSY - RES TOPO1 -6 TRGTYPE0 - SOFT ARRAYTRIG - CAMERA TRIGGER - TRGTYPE DATA -7 CABLE DETECT CABLE DETECT SPARE + RES TOPO2 +8 GND GND SPARE - RES TOPO2 -

Table 7.1: Pinout definition of the RJ45 connectors between the TIB and the clock board and thecentral backplane

Apart from these RJ45 connectors, others will be available in the TIB as spares, or with the aimto be used to implement advanced features like the ones explained in section 7.3. It is important topoint out that the TIB is compatible with two different front-end boards (NECTAr and Dragon),two different clock boards (MUTIN and White Rabbit) and will work in LSTs and MSTs. A lot ofcoordination work has been required to achieve this compatibility.

7.2 Hardware stereo trigger

As was explained in section 3.2.8.1, the hardware stereo trigger function consists of looking forsimultaneous triggers in neighbour telescopes, inside a time window of a few tens of nanoseconds,with the aim to readout only the events which triggered more than one telescope. As the probabilityof having more than one telescope triggered by NSB inside this short time window is rather low, thestereo trigger detects most of the events caused by Cherenkov showers, while rejecting most of theNSB events. The rejected events are never digitized, not contributing to the dead time. Thus, thetelescope readout rate is reduced, so it is possible to reduce the Level 1 thresholds and increase thesensitivity to low energy γ-rays4.

7.2.1 Timing restrictions

In order to look for coincidences inside the mentioned time window (typically 50 ns), the TIB ineach LST camera must receive the Level 1 trigger signals from its neighbour LSTs plus its local Level1 trigger. However, as the neighbour LSTs are far away (at distances of around 100 m), their triggersignals will reach the TIB some time after the local Level 1 trigger. In this way, the local trigger mustbe delayed a time equivalent to the propagation delay before looking for coincidences. The situation

4To optimize the sensitivity to low energy γ-rays, the thresholds must be as low as possible, while maintaining asustainable readout rate.

152 7. Trigger Interface Board.

becomes more complicated if we take into account that each neighbour LSTs can be separated adifferent distance. Moreover, the time of flight of the Cherenkov light is different depending on thepointing direction. At the end, all these delays mean that the data must be stored in the analogmemory buffers until all the triggers from the neighbour LSTs reach the local telescope, the TIBdecides if there has been a coincidence or not and, in the positive case, the camera trigger signalis distributed to all the clusters in the camera. Therefore, the analog memory buffer must be longenough to keep the signal stored until the trigger arrives.

The Dragon front-end boards are equipped with four DRS4 [56] chips with 1024 analog memorycells in each channel, which means that it is able to store up to 4096 ns with a sample frequency of1 GHz. This is required to implement the hardware stereo trigger in the LST subarray, and thusachieving the best sensitivity to low energy γ-rays. In the next subsections the different sources oftime delay are analyzed and how the Dragon front-end board buffer can cope with them.

7.2.1.1 Compensation of the fixed delays

The approximate fixed delays which contribute to the minimum length of the memory buffers,considering optical fibers with a refraction index of 1.5, are the following:

• 220 ns corresponding to Level 0, Level 1 and the distribution through the clusters until reachingthe TIB (break down in table 3.1).

• 500 ns for the 100 m optical fiber between the TIB and the LST basement (see figure 7.5).

• 500 ns if the neighbour LST is placed at 100 m from the local one, or 700 ns if it is 141 maway (see figure 7.6).

• 500 ns for the 100 m optical fiber between the LST basement and the TIB.

• 170 ns for the trigger distribution of the camera trigger signal down to the clusters

This means that all the inputs must wait for the trigger from the furthest telescope, which needsat least 2090 ns to reach the telescope which we are considering as local.

7.2.1.2 Compensation of the Cherenkov light time of flight

The Cherenkov showers are generated at ca. 10 km height, which is far enough to consider thephotons as forming a plane wave front. Thus, if all the telescopes are pointing to the zenith, the wavefront will reach them at the same time and only the fixed delays explained in section 7.2.1.1 needto be taken into account. However, in real operation the telescopes will not be generally pointingto the zenith, but to a certain location defined by specific azimuth and elevation angles. In thisconditions the distance travelled by the photons is not the same for each telescope, and thereforethe shower images will be formed at different times. The delay differences due to the different timeof flight of the Cherenkov photons must be compensated in order to perform the coincidences of theimages caused by the same shower.


Figure 7.5: Sketch of the optical fiber from the camera to the basement, with an estimated lengthof 100 m

100

m

100 m

100 m

100

m141 m

Figure 7.6: Expected LST layout, in a 100 m square rectangular grid

As it is easy to understand from picture 7.7, when two telescopes are aligned with the pointingdirection, the different distances travelled by the Cherenkov photons depends on the elevation angleθ as defined by equation 7.1:

∆d = d cos θ (7.1)

However, as the telescopes are not usually aligned with the pointing direction, the additionaldistance at ground level that the Cherenkov photons must travel through (d in equation 7.1) dependson the the azimuth angle ϕ.


∆d

θ θ

d

Figure 7.7: Different distance travelled by the Cherenkov photons depending on the elevation angleθ

ϕ

2

3 4

π/2

d lϕ

1

(a) Light path difference between IACTs alignedparallel to the axis ϕ = 0

ϕ

1 2

3 4

π/2

d

l

ϕ

ϕ

(b) Light path difference between IACTs alignedparallel to the axis ϕ = π/2

Figure 7.8: Different time of flight depending on the azimuth angle

Considering four LSTs placed at the corners of a square, and oriented with respect to the coor-dinate system as shown in figure 7.8, the distance d used in equation 7.1 for telescopes 3 and 4 withrespect to 1 and 2 respectively, are defined by equation 7.2, for ϕ < π/2.

d = l cosϕ (7.2)

On the other hand, the distance d for LSTs 2 and 4 with respect to LSTs 1 and 2, is given byequation 7.3, for ϕ < π.

d = l sinϕ (7.3)


Thus, for θ < π/2 and ϕ < π/2, the different time of flight of the Cherenkov photons coming toLST 3 with respect to LST 1 will be given by equation 7.4, while for LST 4 with respect to LST 3it will be given by 7.5.

∆time of flight31 =l

ccosϕ cos θ (7.4)

∆time of flight43 =l

csinϕ cos θ (7.5)

Similar equations can be obtained in a similar way for any two pair of telescopes. It is easy tosee that the maximum time difference to be compensated in the TIB will be the one required by thephotons to travel a distance equivalent to the maximum telescope separation in ground, i.e. 141 m.In fact, the telescopes will never point at elevation angles lower than 155, so the maximum distancedifference is 136 m, corresponding to 454 ns. This time should be added to the 2090 ns due tofixed delays, so a buffer of at least 2544 ns is required. Moreover, some more time should be addedto perform the logic operations in the TIB, generate the optical pulses, send the different signalsthrough the RJ45 cables in the camera or just as a safety margin. Therefore 3 µs can be consideredas the minimum time difference required6, so the 4096 cells of the Dragon front-end board, operatingat 1 GHz sampling rate, should be enough.

It is worth to mention that in normal operation the IACTs will be tracking the γ-ray sourcesthrough the sky during some time, from several minutes to hours. During this time the azimuthand elevation angles change, and therefore the delay differences to be compensated. Thus, thepointing direction must be updated quite often and the compensation times must be recalculated.As an example, in order to compensate time errors lower than 2 ns, the pointing direction shouldbe updated for every change of 0.34, corresponding to 82 s in the worst case, when the IACTs arepointing near the zenith. The pointing direction is provided by the slow control system.

7.2.1.3 Synchronization with local trigger

The delay adjustments explained in sections 7.2.1.1 and 7.2.1.2 are useful to verify if the Level1 triggers generated in the local LST and its neighbours are happening inside the coincidence win-dow, and thus fulfilling the stereo trigger condition. Due to statistical fluctuations in the showerdevelopment, there is a certain jitter in the arrival times of the Cherenkov photons, which makes theoptimum duration of the coincidence window to be around 50 ns. This effectively means that, forevery single event, the stereo condition can be accomplished at any time during inside the window,with an uncertainty of several tens of nanoseconds. Due to this uncertainty, it is rather inconvenientto generate the camera trigger signal synchronized with the time at which the trigger condition isfulfilled (see figure 7.9). As it was briefly mentioned in the introduction of chapter 3, one of thetargets of the trigger system is to minimize the jitter to reduce the amount of samples required foreach event (and, as a consequence, the dead time) and to allow the calibration of the DRS4 cells.Therefore, a jitter of up to 50 ns in the trigger time is not acceptable.

5For lower angles, the length of the path in the atmosphere which the Cherenkov photons must travel through, isvery long and the telescope response is degraded.

6CTA consortium specified 3500 ns


(a) Early trigger condition

(b) Late trigger condition

Figure 7.9: If the camera trigger signal is synchronized with the trigger condition, the time requiredto generate the trigger command is variable

Nevertheless, the time uncertainty in the compliance with the trigger condition is not a realproblem. In fact, every LST has to read its local data, and these local data are synchronized withthe local trigger, not with the trigger condition. So, the camera trigger signal must be generated afixed and precise time after the local trigger, as shown in figure 7.10, whenever the trigger conditionwas satisfied. This fixed time must be somewhat longer than the longest time required to compensatethe delay differences and to finish the coincidence window.

7.3 Advanced features

Interfacing with the other trigger generating subsystems and implementing the hardware stereotrigger for four LSTs are the two basic functionalities of the trigger interface board. However, thereare other interesting features that can be implemented in the trigger interface board, which aredescribed in this section.


(a) Early trigger condition

(b) Late trigger condition

(c) No trigger condition

Figure 7.10: If the trigger command is synchronized with the local trigger, the time required togenerate the camera trigger signal is fixed


7.3.1 More LSTs

In principle, there will be four LSTs in the CTA array, both in the north and south hemispheres.However, in the future more LSTs could be built if there were a special interest in improving evenmore the sensitivity or reducing the observation time at low energies7. In anticipation of this possibleenlargement, the trigger interface board is able to handle up to nine LSTs and perform the stereotrigger algorithm with all its inputs.

100 m

100 m100 m

100 m

100

m10

0 m

100

m10

0 m

100 m

100 m

100

m10

0 m

282 m

141 m

Figure 7.11: 9 LST possible layout

With a layout like the one showed in figure 7.11, the required buffer size needs to be increasedin 700 ns corresponding to the additional 141 m of optical fiber between the most separated LSTs(eq. 7.6), plus 470 ns corresponding to the increment in in the time of flight (eq. 7.7). Thus, thebuffer must be able to store at least 3714 ns of signal, and there would be 382 ns of margin for theTIB logic operations, distribution, etc, considering 4096 memory cells and a sampling frequency of1 GHz.

∆toptical fiber =141m

c1.5

= 700 ns (7.6)

∆tmaximum time of flight =141m

c= 470 ns (7.7)

7The higher the number of LSTs, the larger the number of recorded low energy events and, at the end, the shorterthe time required to obtain statistics and scientific results.


7.3.2 MSTs contributing to the LST stereo trigger

The readout of the MSTs will be based on NECTAr chips8, which only have 1024 memory cells,so it cannot store more than 1024 ns in its buffer if sampling at 1 GHz. This means that the MSTcameras can not wait for the trigger information from the neighbour IACTs, nor be triggered in ahardware stereo mode. However, they can contribute to the stereo trigger algorithms running ontheir LST neighbours, as sketched in figure 7.12. Provided that the distances are short enough, theMSTs can use their trigger interface boards to broadcast their local Level 1 trigger pulses to theirneighbour LSTs, which can wait for them and thus take this information into account in their stereotrigger algorithms. This idea can take advantage from the TIB capability to handle up to 9 triggerinputs, without requiring to build more expensive LSTs. Nevertheless, as the MSTs and LSTs areoptimized for different γ-ray energy ranges, the gain in performance of the LST will be minor.

Figure 7.12: A possible stereo trigger scheme with LSTs and MSTs

7.3.3 Slow controllable functionalities

As will be described in section 7.4, the TIB is a flexible system essentially implemented in anFPGA and with a micro-PC used for slow control. This architecture makes possible to implementadditional functionalities in a straightforward way, as well as to control important parameters dy-namically. For instance:

8In fact, only some MSTs will be based on NECTAr, while others will follow different architectures. Anyway, if theTIB would be used in this other MSTs, the situation would be the same.


• The duration of the coincidence window can be changed by the slow control system.

• The trigger condition can be changed, in order to choose to look for coincidences of 2, 3, 4 oreven more telescopes. Disabling the stereo mode and triggering only in mono mode is also anoption.

• The local Level 1 trigger rate, stereo trigger rate and the trigger rates from the neighbours canbe monitored by the slow control system, which can take decisions based on this information(change Level 1 thresholds, change Level 1 trigger region size, change stereo trigger condition,etc.).

• The temperature and the status of the optical links can also be monitored, generating alarmsif a failure is detected.

7.3.4 Busy state

One of the additional functionalities foreseen in the TIB is a busy state, to avoid distributingnew camera trigger signals to the clusters while the readout is still digitizing. This can be requiredif the readout system is not able to discard these triggers by itself, and it would be as simple asignoring all the triggers produced during the dead time started after a trigger command.

This scheme could be more complex if different dead times among clusters are considered. Forinstance, if a scheme like Colibri is used, only the clusters which are effectively read-out would sufferdead time and, as they would start digitizing at slightly different times, their dead times would alsofinish at slightly different times. In this case, a BUSY signal (already considered in section 7.1),obtained as the global OR of the busy state of all the clusters, would be required.

7.3.5 Topologic stereo trigger

The next step to improve the stereo trigger performance and the noise rejection in an stereoscheme consists on using not only the information about when an IACT was triggered but alsowhat part of the camera caused the trigger. This information can be used by the stereo systemto check if the local triggers are compatible with the expected patterns for single γ-ray-like eventsor, on the contrary, they correspond to different events which occurred at the same time just bychance. In the last case, it is very likely that some of these events were caused by NSB, so theyshould be discarded[143]. Figure 7.13 show several examples of stereo trigger patterns compatiblewith Cherenkov showers or not.

The implementation of a topolologic stereo trigger working as described in the previous paragraphis much more complex than the basic functionality, requiring to send to the neighbours not just thetrigger pulse, but also a piece of information containing which cluster was fired, or at least in whichpart of the camera was placed the cluster that was fired. Nevertheless, the optical links betweentelescopes can be used to broadcast this information, and the FPGA firmware can be improved tohandle it, so in principle it is not impossible to implement the topologic stereo scheme with the TIB.An important difficulty would be how to send the number of the local fired cluster to the TIB. Thediscussion about this is still an open issue, and the topologic stereo trigger will be an important lineof work during the next years.


(a) (b) (c) (d)

Figure 7.13: Several topologic stereo trigger patterns. 7.13(a), 7.13(b) and 7.13(c) would fire thestereo trigger, but not 7.13(d)

7.4 Technical description

7.4.1 General architecture

The TIB is implemented in a single PCB housed inside a 19” 1U rack box, as shown in figure 7.14.This rack box will be placed inside the camera, connected to the central backplane, the slow controlunit, the clock board, the calibration box, the TIBs in other neighbour IACTs and the power supplyunit, as was described in section 7.1. At the same time, the Trigger Interface Board is composed ofseveral electronic subsystems, most of them handled by an FPGA as it is shown in figure 7.15.

Figure 7.14: Trigger Interface Board prototype inside the 1U rack box

The different subsystems are described in the following subsections.

7.4.2 Optical links

Some essential hardware elements of the Trigger Interface Board are the optical links. Even in thecase of MSTs triggering in mono, where no communication with neighbours would be required, some


FPGA

RJ45Connectors

OpticalSFP Drivers

Raspberry Pi

External Short Delay Unit

External Long Delay Unit

Power Supplies

Thermometer

Figure 7.15: Internal block diagram of the Trigger Interface Board

optical links are needed for the communication with the calibration box (calibration and pedestaltriggers), or as an alternative possibility to implement fixed delays with optical fibers. The maincomponents of the optical links are described in the following subsections.

7.4.2.1 Optical fibers

Between every two modules connected (TIBs of neighbouring telescopes, calibration boxes, etc.),there will be a cable containing two multimode optical fibers 50/125 OM3 [144] [145]. This kindof optical fibers are suitable for links of up to 550 m length, handling bit rates of up to 10 Gbps,corresponding to pulses as short as 100 ps. As the distance between telescopes will never be longerthan 182 m (supposing an unlikely 9 LST subarray), and the transmitted trigger signals are expectedto be around 5 ns width, this kind of optical fibers are very appropriate for our system. Additionally,as this kind of optical fiber cables are very common in LANs, they are quite cheap, with prices around0.50 AC/m.

The optical fiber cables are terminated with standard LC multimode duplex connectors, like theone shown in figure 7.16.

7.4.2.2 Transceivers

Two options were considered to implement the optical transceivers: Using standard SFP modules,or using discrete VCSELs and PiN photodiodes mounted inside LC housings.


Figure 7.16: Duplex LC connector

7.4.2.2.1 SFP modules

The first option considered for the transceivers was to use a standard SFP module like the AFBR-5715ALZ from Avago Technologies which is shown in figure 7.17(a). These transceivers consist ofa transmitter section based on a 850 nm VCSEL (Vertical Cavity Surface Emitting Laser) and areceiver section containing a PiN photodiode, together with their drivers, amplifiers and other an-cillary electronics [146]. One of the optical fibers in the cable is connected to the transmitter andother to the receiver, in order to build the bidirectional link.

The transceiver mentioned above is suitable for OM3 optical fibers, reaching a maximum datarate of 1.25 Gbps. These means that the shortest pulses will be 0.8 ns wide, still shorter thanthe expected pulses (around 5 ns). Apart from the transmitted and received trigger signals, thetransceivers generate two control electronic signals named TX Fault and LOS to indicate possiblefailures in the transmission or the reception respectively, and receive one signal TX Disable, whichswitches off the transceiver when it is set to high level. Subsection 7.4.4.7 explains how these signalsare handled by the FPGA.

Regarding the mechanics, the transceivers comply with the Small Form Factor Pluggable (SFP)standard. This allows to use housings from different suppliers, like the one shown in figure 7.17(b),able to house up to 4 transceivers inside. When some link is not in use, the transceiver can be pullout from the box, or just never being installed, saving resources.

(a) Transceiver AFBR-5715ALZ (b) 4x SFP box

Figure 7.17: Transceiver and housing for 4 SFP transceivers

Nevertheless, the SFP transceivers have a minor difficulty: the transmitter must be driven byLVPECL signals, and the receiver also provides LVPECL output signals. This logic standard cannot be managed directly by the FPGA, requiring an intermediate stage for translating the LVPECL


signals to LVDS or other standard supported by the FPGA. This translation can be implementedwith the differential translators SN65LVDS100 and SN65LVDS101, from Texas Instruments [147].SN65LVDS100 performs the conversion of the LVPECL signals into LVDS ones, while SN65LVDS101is used in the LVDS to LVPECL translation.

In spite of this inconvenient, the AFBR-5715ALZ SFP transceivers were selected to be mountedin the first TIB prototype due to their simplicity and with the aim to use standard solutions.

7.4.2.2.2 Discrete VCSELs and PiN photodiodes

Due to some problems found during the tests of the first TIB prototype (see section 7.5.9), anad hoc design for the transceivers has also been considered. Designing the optical transmitter andreceiver with discrete VCSELs and PiN photodiodes is an option which provides with great flexibilityto optimize the bandwidth, the cost or the power consumption. The drawback is that some analogprocessing stages need to be designed in order to feed the VCSEL with a signal inside its inputrange, and to recover an LVDS signal from the analog output of the photodiode. The most criticalcharacteristic is the bandwidth, which must be as large as possible in order to have pulses with verysharp edges, thus maintaining the timing information.

The design of the transmitter is shown in figure 7.18. The VCSEL chosen emits at 850 nm andhas 1 GHz bandwidth. It was provided by AFE ltd. [148] who also assembled it in an LC plastichousing. Considering a single-ended input signal between 0 and 3.3 V from the FPGA, the AD8009[149] operational amplifier is used to adjust the voltage range of the signal and to avoid overloadingthe FPGA. The AD8009 is a very fast operational amplifier (5500 V/µs and 1 GHz bandwidth), ableto drive the VCSEL. Finally the pulses are injected through a decoupling capacitor used to separatethe bias.

Figure 7.18: Schematic of the optical transmitter implemented with a discrete VCSEL

7.

Trig

ger

Inte

rface

Board

.165

Figure 7.19: Schematic of optical receiver designed with a discrete photodiode


The design of the receiver is somewhat more complicated. The photodiode chosen was theS5973-01 from Hamamatsu [150], also with 1 GHz bandwidth and assembled into the LC housing byAFE. First the current signal from the photodiode is introduced into a PACTA [95] transimpedanceamplifier. The output of the PACTA is a differential voltage signal, which is converted into single-ended with an AD8009 configured as a substractor (the scheme is similar to the one described insection 4.2). Then the single-ended output is compared with a threshold with an ADCMP604, whichgenerates the LVDS output. All the receiver circuit is shown in figure 7.19

7.4.3 External delays

As it was previously explained in sections 7.2.1.3 and 7.4.4.1, the camera trigger at the output ofthe TIB must be generated a long9 and fixed time after the local Level 1 trigger arrives. This delaymust be as accurate as possible to know in which cells of the analog memory buffer the signal is.These requirements for the Delayed local signal make inadvisble to delay it with the flip-flop chainsdescribed in 7.4.4.2: first because the accuracy with those delay lines can not be better than 2.5 ns,and second because it would be a waste of logic resources for a delay which, in principle, does notneed to be programmable.

Several options have been tested to implement the long asynchronous delay:

• The most obvious way to implement a long delay is to use a long transmission line. Usingan optical link like the ones described in section 7.4.2 and a long optical fiber, it should bepossible to obtain a very accurate fixed delay. However, this solution would be very bulkybecause a reel of around 500 m of optical fiber would be required for each telescope.

• The programmable delay line 3D3428-15 from Data Delay Devices inc. [151] can add delaysof up to 3825 ns in steps of 15 ns, in a single chip.

• The chip DS1123L-200, from Maxim Integrated [152], is able to add a delay of 512 ns in stepsof 2 ns. So, a chain of 8 of this chips connected in cascade, should be able to add up to 4 µs.

The possibility to use external chip delays was studied in depth during the first steps of the TIBdesign. Both delay chips were found to introduce long delays, with a fine precision, high accuracy,low jitter and good stability, according to their data sheets. The 3D3428-15 was preferred, but therewere no stock in Europe for this chip, so a chain of 8 DS1123L-200 was included in the first prototypeof the TIB. Whatever the solution, it must be tested and characterized, specially in which respectsto jitter, as shown in section 7.5.10.

7.4.4 FPGA and firmware

Both the interfacing and the stereo trigger functions consist of properly managing fast digitaltrigger pulses: replicating, delaying, looking for coincidences, counting, etc. These kind of functionsare the typical ones which can be performed by an FPGA, so this technology appeared as the naturaloption to develop the logic of the TIB. As the FPGAs are programmable devices, they do not onlyprovide with a high performance, but also with a great flexibility. Thus, the firmware installed in

9around 3 µs


the FPGA can evolve with the aim of improving or implementing new functionalities as the onescommented in section 7.3.

The FPGA chosen for the TIB was the Xilinx Artix-7 X7A100T-3FGG676 (figure 7.20, [153])for several reasons:

• It belongs to the newest FPGA Series at the moment of developing the TIB, which meansmore time until it will become obsolete. As the CTA telescopes will have to work during 20years, this is an important point.

• The Artix 7, being the less powerful FPGA family of the 7 Series, is the most suitable for theTIB, which does not require very high computing power. On the other hand, Artix 7 familyis optimized to reduce its power consumption, which is important for all the systems installedin the camera.

• Despite the TIB does not need high computing power, it requires high speed, specially toimplement accurate programmable delays as will be described in subsection 7.4.4.2. Thestandard synchronous logic inside the selected FPGA can work with clock frequencies as highas 500 MHz.

• The selected FPGA has 676 pins, which can be very useful to manage additional interfaces toimplement advanced features.

Figure 7.20: Xilinx Artix-7 FPGA

The firmware running in the FPGA contains several logic modules implemented in VHDL. Thecode can be consulted in [154], but in the following subsections a high level description of the mostimportant modules is presented.

7.4.4.1 High level architecture

Figure 7.21 shows a general scheme of the firmware modules implemented in the FPGA. Somefunctions are programmed directly using libraries provided by Xilinx [155]. For instance, the localLevel 1 trigger input is replicated to be sent to the neighbours by using the FPGA input and outputbuffers. In a similar way, the internal clock frequencies (4 KHz, 50 MHz, 100 MHz and 400 MHz)are obtained from the external 10 MHz input clock by means of the internal PLLs [156], properly


configured with the Xilinx Core Generator [157] and one simple frequency divider. Neverthelessmost of the specific functions of the TIB require the development of specific firmware modules.

PLLs

DelayLines Stretchers

StereoLogic

Collector

ITR counters

Optical links

controlSlowControl

Thermometer

Inputs 0..7

10 MHz

calibrationpedestalsarraytrig

Trigger output

Trigger type

400 MHz100 MHz

4 kHz

Input 0

SPI link from/to Raspberry Pi

Delayed_local

Input 0

Output 1Output 2Output 3Output 4Output 5Output 6Output 7

Output 0

Trigger output

50 MHz

ExternalDelaycontrol

Figure 7.21: TIB firmware architecture

The stereo logic involves 3 logic modules. First, the local Level 1 trigger input from the centralbackplane and the inputs from the neighbour telescopes (up to 8) are delayed a programmable num-ber of clock cycles to compensate the delays due to the cable lengths and the pointing direction,as was mentioned in section 7.2.1. The 9 delayed signals are then connected to 9 programmablestretchers, which extend the duration of the trigger pulses until making them as wide as the coin-cidence window. Then, the delayed and stretched trigger inputs are sent to the stereo logic modulewhich has a counter which is able to provide the number of active inputs for every rising edge ofthe 400 MHz clock. If the count is greater than a programmable trigger condition, a stereo triggerwill be generated. However, to be consistent with what was explained in section 7.2.1.3, the cameratrigger pulse is not generated just when the condition is accomplished but it is synchronized with adelayed copy of the local input named “Delayed local” in figure 7.21.

Once the stereo trigger is generated in the stereo logic module, it is sent to the collector, whichis essentially an OR gate that generates a trigger output when the stereo trigger or other input isactive. Depending on the input that caused the trigger output, the collector module generates thecorresponding trigger type which is sent to the central backplane and to the clock board as describedin section 7.1.1. With the aim of being also able to work only with local triggers in mono mode,or to disable the different trigger inputs, the collector also receives a mask to enable/disable eachinput.

The delay for each input, the coincidence window, the trigger condition and other parametersare configured by the slow control module, which receives these parameters from the RaspberryPi through an SPI link. Additionally, the trigger inputs and the trigger output are sent to a setof counters which monitor the trigger rates. These rates can be read by the slow control module,


providing with valuable feedback to select the thresholds, choose a suitable trigger condition or todetect failures. Finally, the slow control module is also able to monitor and control the status ofthe optical links, to configure the external delay and to monitor also the temperature from a chipthermometer.

The following subsections explain some technical details of the most complex modules:

7.4.4.2 Programmable delay lines

The programmable delay lines used to delay each input a different amount of time, are basedon chains of flip-flops as the one shown in figure 7.22. With every clock cycle, the signal presentat the input of each flip-flop passes to the output. So an input pulse requires as many clock cyclesas flip-flops in the chain to go through all the flip-flops and reach the output. This means that,with this structure, the amount of delay is as accurate as one clock cycle, so high clock frequenciesare required to get a fine delay tuning. A clock frequency of 400 MHz was chosen, obtaining aresolution of 2.5 ns in the delay adjustment. Additionally, the input pulses do not reach the outputexactly after N · Tclk ns, but introducing certain jitter. This jitter results from the fact that theflip-flop outputs can only be updated synchronously with the clock leading edge, while the inputpulses can happen at any time. Thus, the input pulse will reach the output of the first flip-flop afteran unknown amount of time between 0 and 2.5 ns depending on the arrival time of the input pulsewith respect to the rising edge of the clock. Nevertheless, as the delayed outputs from the delay linesare only used to check for coincidences inside a time window of several tens of nanoseconds, and thecamera trigger output is synchronized with the local Level 1 trigger, an uncertainty lower than 2.5ns is not very harmful for the trigger performance. It is also worth to mention that the input pulseswill never be narrower than 2.5 ns, so they will always be captured by at least one leading edge ofthe clock.

Q

QGRB

CLR

D

Q

QGRB

CLR

D

Q

QGRB

CLR

D

Q

QGRB

CLR

D OUTIN

CLK

Figure 7.22: Delay line implemented with a chain of flip-flops

The delays introduced by the delay lines can be as long as 4000 ns, which means that the chainsshould have at least 1600 flip-flops. The first obvious solution to be able to select every possibleamount of delay is to connect each flip-flop output to the input of a 1600-input multiplexer. Such amultiplexer does not exist inside the FPGA, so it should be implemented as a multilevel hierarchy of8 and 4-input multiplexers. A complicated structure like that is not a good solution from a timingpoint of view, because the output signal from the selected flip-flop would have to go through manymultiplexers in cascade and reach its destination in a single clock cycle. So in order to avoid the1600-input multiplexer, a logarithmic structure like the one shown in figure 7.23 was designed.

The amount of delay which should be added by the delay line is configured by the slow controlmodule by means of a 12 bits word. So, every bit set to “1” introduces a delay correspondent to 2p

clock cycles, being p the position of the bit in the 12 bits word. If the flip-flops in the chain are set


29cycles 28 cycles 27 cycles 2 cycles 1 cycle OUT

Bit 9 Bit 8 Bit 1 Bit 0

IN

Figure 7.23: Logarithmic delay line

in subchains of powers of 2 units as shown in figure 7.23 and the bits of the control word are used toconnect these subchains to the signal path or to bypass them, the output of the chain provides withthe desired delayed output, just with 11 2-inputs switches. Only 11 from the 12 bits of the delayword are used, providing with an adjustment capability of up to 2048 clock cycles (i.e. 5120 ns at400 MHz). Moreover, as the longest delays can only be applied to the local input (the inputs fromthe neighbours have an inherent delay due to the travel through the optical fibers), the delay linesused in the neighbour inputs only use 10 bits and comprise 1024 flip-flops instead of 2048, savinglogic resources.

7.4.4.3 Stretchers

The stretchers are used to make the pulses coming from the delay lines as wide as the coincidencewindow. The duration of the coincidence window is programmable by means of a 6 bit numberconfigured by the slow control module, which expresses the duration in clock cycles. The stretchersuse the same 400 MHz clock used for the delay lines, so the finest resolution is limited to 2.5 ns. Infact, the stretchers use a delay line like the ones described in section 7.4.4.2 to produce the stretching,but with 6 bits instead of 10 or 11. A copy of the input pulses is sent to the input of this delay line,obtaining at the output a delayed signal. Both the delayed signal and the original input feed thestate machine shown in figure 7.24.

State 0Output = 0

State 1Output = 1

Input = 1

Input = 0 & Delayed = 1

Figure 7.24: Diagram of the state machine running in the stretcher modules

After the FPGA reset, the state is 0, as well as the output of the stretcher. When the inputchanges to “1”, the state machine changes to State 1, and the output changes immediately to “1”.This situation remains until the delayed input coming from the delay line changes to “1” and onlyif the non-delayed input has already changed to “0”. This means that:

• If the input is narrower than the coincidence window (as usually expected), the output pulsewidth is the coincidence window duration.

• If the input is wider than the coincidence window, the output width is similar to the inputwidth.


If the input pulses arrive at the stretchers separated by less than the coincidence window width,this scheme does not work properly, so that the system can consider several close input triggers as asingle one, or to produce outputs shorter than the coincidence window. This situation would meanthat a high pulse rate is present at the output of the stretchers, which will be detected by the ITRcounters (see section 7.4.4.6), which in turn will be read by the slow control system, which will takethe appropriate measures.

7.4.4.4 Stereo Logic

The delayed and stretched inputs from the local and the neighbour telescopes are sent to theStereo Logic module, which generates a stereo output if the trigger condition is accomplished. Thetrigger condition consists of having coincident triggers in the local telescope and in one or moreneighbours during the coincidence window. This is implemented by connecting the inputs to a fastcounter which provides, with every leading edge of the 400 MHz clock, the number of inputs whichare set to “1”. The result of the counter is expressed as a 4 bits number, which is compared with thenumber of coincident triggers required to satisfy the trigger condition. The trigger condition can bereconfigured in a very simple way, just modifying this number by slow control. If, besides satisfyingthe required number of coincidences, one of the coincident inputs is the local one, the signal named“Stereo trigger” in figure 7.25 is generated.

Counter > trigger condition? State

Machine

Delayed and stretched

inputs

Delayed local

Armed

Count Stereotrigger

Delayed_stereo_trigger

StereoOutput

Figure 7.25: Stereo logic block diagram

However, as was previously said in subsections 7.4.4.1 and 7.2.1.3, the Stereo Output cannot besimply generated when the stereo trigger condition is accomplished. Instead, it must be generated afixed time after the local trigger, i.e. synchronized with the signal named “Delayed local” in figures7.21 and 7.25. To do this, the Stereo trigger signal is sent to a programmable delay line as the onesdescribed in section 7.4.4.2 and, once delayed it feeds a state machine which generates an “Armed”output. When this Armed signal is set to “1”, a stereo output is generated when Delayed localappears.

The delay line is required to set Armed = 1 only some tens of nanoseconds before the expectedarrival of Delayed local. Of course it is impossible to know accurately when the stereo triggercondition is going to be accomplished and therefore when Armed is going to be set to one (it canhappen at any time inside the coincidence window). However, what it is possible is to know howmuch time the local trigger is being delayed in the Programmable Delay Lines module to compensatethe neighbour’s delays before checking for coincidences and how much delay is introduced in theDelayed local path. Thus, introducing an additional delay of Tstereotrigger ns, calculated accordingto equation 7.8, it is possible to ensure that Armed will be set to “1” between Tcoincidencewindow +Tsecuritymargin ns and Tsecuritymargin ns before the arrival of Delayed local.


Tstereotrigger = Tdelayedlocal − Tcoincidences − Tcoincidencewindow − Tsecuritymargin (7.8)

Figure 7.26 illustrates this calculation. If Stereo trigger is not delayed, Armed could be activateda long time before the arrival of the corresponding Delayed local pulse and this could cause theacceptance of previous local triggers which did not comply with the coincident condition as stereoones. On the contrary, if Armed is set to “1” just a few nanoseconds before the time at whichDelayed local is expected, is very unlikely that a local trigger different from the one which causedthe coincidence could be accepted.

Tcoincidences Tstereo trigger Tcoincidence window

TDelayed _local

Armed gets activated during this

time

Delay introduced to compensate

neighbour’s delay

Additional delay applied to

stereo_trigger

Fixed delay applied to Delayed_local

Security margin

Figure 7.26: Stereo trigger delay scheme

WaitingArmed = 0

ArmedArmed = 1

Delayed_stereo_trigger = 0

ShootedArmed = 0

Delaye

d_stereo

_trigg

er = 1 Delayed_local = 1

Figure 7.27: State machine which controls the generation of the Armed signal

Regarding the state machine which controls the activation of the Armed signal, its scheme isshown in figure 7.27. It is more complicated than just setting Armed to “1” when Delayed stereo triggerarrives, with the aim to produce only one stereo trigger when the trigger condition is accom-plished during a long time. Thus, starting from the waiting state, it changes to armed whendelayed stereo trigger appears. Then, when Delayed local arrives and generates the Stereo Out-put the state changes to shooted, setting Armed to “0”. In this state, Delayed stereo trigger mustbe “0” to make the state machine go back to waiting state and then being ready to get armed again.


So, if the trigger condition is fulfilled during a long time, the state machine remains in shooted state,avoiding several triggers to be generated for a single long event.

7.4.4.5 Collector

The Collector module implements the interfacing function with the different trigger origins,generating the trigger output signal every time a trigger comes from any of the inputs. Thus, thetrigger output is implemented in a simple way with a 5 input OR gate and an AND gate, as it isshown in figure 7.28.

Input 0

Mono trigger

Stereo Output

calibrationpedestalsarraytrig

Trigger Output

Figure 7.28: Trigger output generation in the collector module

The AND gate allows to generate a trigger output directly from the local telescope trigger (Input0 signal), whenever the mono trigger mode is selected, as will be the case in the MSTs. It is importantto notice that, whatever the input, the trigger output is generated in a completely asynchronousway, keeping the timing information in the leading edge of the trigger output and introducing verylow (24ps RMS). For the trigger type generation, the input trigger signals are copied and stretchedin order to work with them synchronously with the state machine of figure 7.29.

State waitting

TXStart = 0

State transmittingTXStart = 1

Trigger Output = 1 &

Last_Trigger_Output = 0

TXDone = 1

Figure 7.29: State machine which controls the generation and transmission of the trigger typeinformation

When the stretched copy of the trigger output signal changes from “0” to “1”, the 3 bits of thetrigger type corresponding to the effective triggering input are calculated, and then a signal calledTXStart is set to “1”, indicating to the SPI module10 that there are data to transmit. From thismoment, the state machine ignores the possible new triggers, remaining in the transmitting state

10The SPI module is a free implementation.


until the SPI module finishes transmitting the trigger type. Then, The SPI sets to “1” a signalnamed TXDone, indicating to the collector module that it is ready to accept new transmissions.It is worth to say that the collector state machine works with the 400 MHz clock, evaluating thedifferent variables every 2.5 ns, while the SPI module receives a 50 MHz clock for its state machine,sending the bits at 10 MHz.

7.4.4.6 ITR counters

The Individual Telescope Rate (ITR) counters are a set of counters in charge of counting thenumber of input triggers from each telescope (local and neighbours), as well as output triggers,during a certain period of time, with the aim to provide the slow control module with informationto calculate the trigger rates. The trigger rate monitoring is very important to set the Level 1thresholds and the trigger condition to the lowest possible levels, while maintaining the trigger ratebelow the maximum telescope readout rate11.

The design of digital counters entails a compromise between the number of bits of the counterand the maximum counting speed. As it has been represented in figure 7.30, the counter is composedby a chain of 2 bit adders. The time between one addition and the next one must be long enough toallow a carry bit to ripple through the whole chain of full adders and to have the result ready at theinput of the counters to start the next addition. Thus, the more bits in the counter, the longer thetime required to propagate the carries and the lower the maximum frequency at which the countercan work12.

Full Adder

0

Out 0

Bit 0

Carry 01Full Adder

1

Out 1

Bit 1

Carry 12Full Adder

2

Out 2

Bit 2

Carry 23Full Adder

3

Out 3

Bit 3

Carry 34Full Adder

4

Out 4

Bit 4

Carry 45Full Adder

5

Out 5

Bit 5

Carry 56Full Adder

6

Out 6

Bit 6

Input pulseHalf

Adder7

Out 7

Bit 7

Carry 67

Figure 7.30: Structure of an 8 bit ripple-carry counter

In the particular case of the ITR counters, the inputs will be separated by some µs during normaloperation (i.e. the expected trigger rates are below 1 MHz). If the counters are fed with the inputpulses after going through the stretchers, the pulses to be counted will be long enough to allowthe counters to work at lower frequencies, and therefore to reach higher ranges. The coincidencewindow, and the correspondent pulse width of the stretched pulses will be around 50 ns, but it isprogrammable so, in order to have some safety margin, a minimum pulse width of 10 ns has beenconsidered. Assuming this condition, the counters have been designed to have 8 bits and beingupdated at 100 MHz. Every 10 ns each counter checks if its input has changed from “‘0” to “1”. Ifso, they increment the account, otherwise they do nothing.

In principle, the counters are read-out and reset to 0 every 250 µs (4 kHz rate), so they are usefulto monitor rates between 4 kHz and around 1 MHz. If the rate is higher, the counters maintain their

11Limited by the dead time12For this reason it is not possible to implement the delay lines described in section 7.4.4.2 by counting the number

of clock cycles.


maximum value (28 − 1 = 255), so the slow control module will know that the rate is too high andit will take the appropriate actions. If it were required to measure higher or lower trigger rates, itwould be possible to do it just by changing the frequency at which the counters are read and reset.

7.4.4.7 SFP control

The optical links used to send and receive triggers to/from the neighbours, as well as the cali-bration and pedestal signals, are implemented in the first TIB prototype by means of TX/RX SFPmodules [146], which provide with several bits to monitor and control the link status:

• TX Disable: When the FPGA sets this bit to “1”, the optical transmitter is switched off.

• TX Fault: If a laser fault happen, the SFP module sets TX Fault to “1”, and disables thelaser.

• RX LOS: A Loss of Signal (LOS) bit indicates that the received optical power is too lowto recover the signal, due to a disconnected or broken fiber, switched off transmitter or otherreason.

The SFP control module simply gathers all these bits from all the SFP modules, forming wordswhich can be read by the slow control module. Additionally, it generates a generic alarm signaldirectly connected to the Raspberry Pi if any of the control bits is indicating a failure. In this way,the slow control module does not need to read the SFP status periodically, but only when a problemis detected.

7.4.4.8 External delay control

In the first TIB prototype, the external delays described in section 7.4.3 are implemented with achain of Maxim DS1123LE-200 [152] programmable delay chips. These chips need to be configuredby sending an 8-bits word to each chip through an SPI link. All the chips share the clock, MISOand MOSI lines, while they have independent chip selects. With the aim to handle these links andsend the configuration information properly, a firmware module was implemented. This modulereceives from the slow control nine 8-bit words (one for each chip) and a signal indicating whenthe configuration of all the chips must be updated (Write ex dels). When the updating commandarrives, the module sends the 8-bit word to one chip after the other until programming all of them.Figure 7.31 shows the state machine of the firmware module.

The process of updating the configuration uses a variable n to select each chip. Thus, when com-ing from Waiting state, the chip corresponding to n=0 is updated in the Writing state (TX start=1starts the SPI communication). Then, when that message has been sent, TX done changes to “1”and the state changes to Handshaking. This state increments n and in the next step the state changesto Writing again to send the configuration message to the next chip. The process is repeated untilprogramming all the delay chips. Then the state comes back to Waiting.

With the aim to initialize all the chips with a known value after the reset of the system, the stateis set to Writing instead of Waiting, so the initial values are loaded.


WaitingTX_start=0

n=0

WritingTX_start = 1

n > amount_exdelchips

HandShaking

TX_start=0n=n+1

Write

_ex_

dels = 1 TX_done = 1n ≤ amount_exdelchips

ResetReset = 0

Figure 7.31: External delay control state machine

7.4.4.9 Thermometer

The trigger interface board is equipped with a TC77 [158] chip thermometer, readable by a SPIinterface. The thermometer firmware module is in charge of controlling this SPI interface, readingthe temperature every 250 µs and writing the data in a register accessible by the slow control module.

7.4.4.10 Slow control module

The Slow Control firmware module implements an slave SPI interface which allows the RaspberryPi to read and write 32 bit words. These words are composed of an 8-bit prefix which defines whatinformation is being read or written and 24 data bits. Table 7.2 contains the different codes and thedata corresponding to each one.

Prefix Data bits Information Read/written bythe Raspberry Pi

0x00

0x01 12 LSB Local trigger delay, in clock cycles Written

0x02 12 LSB Neighbour 1 trigger delay, in clock cycles Written








– – – –


0x11 12 LSB Output trigger duration, in clock cycles Written

– – – –

0x20 7 LSB Coincidence window, in clock cycles Written

0x21 4 LSB Trigger condition, in number of coincidences Written

0x22 8 LSB If =0xFF, mono trigger enabled Written

0x23 12 LSB Additional delay Tstereotrigger, in clock cycles Written

– – – –

0x30 8 LSB Stereo count, for rate monitoring Read

0x31 8 LSB Local trigger count, for rate monitoring Read

0x32 8 LSB Neighbour 1 trigger count, for rate monitoring Read








– – – –

0x40 10 LSB SFP enables Read

0x41 10 LSB SFP TX Fault Read

0x42 10 LSB SFP LOS, Loss of Signal Read

– – – –

0x50 13 LSB Temperature Read

– – – –

0xF0 8 LSB Unknown prefix Read

Table 7.2: Slow control registers

When an SPI message is received and its prefix does not correspond to a defined one, the slowcontrol module sets an alarm line directly connected to the Raspberry Pi to “1”, and writes theunknown received prefix in the 0xF0 address. In this way, the Raspberry Pi can read what wasreceived, which can be useful for debugging.

Another useful function of the slow control module is to write the initial values of the differentparameters, before receiving them from the Raspberry Pi. This allows to test the different func-tionalities, even without the Raspberry Pi (see section 7.4.5.2). With the aim to have the updatedinformation about the slow control always accessible, a wiki page has been created [159].

7.4.5 Raspberry Pi

The TIB contains a Raspberry Pi micro-computer (figure 7.32), which is in charge of the FPGAconfiguration during the booting of the system and the slow control communication. In spite ofits small size and very low price13, the Raspberry Pi is a complete PC running a Linux operating

13Around 30 €at the time when this thesis was written.


system14 which is stored in an SD card used as hard disk [160]. It has several buses: two USBs, oneRJ45, several general purpose pins, one audio connector and even an HDMI. In the case of the TIB,the Ethernet interface will be used to communicate with the camera slow control system, while theGeneral Purpose Input/Output (GPIO) pins are used to interface with the FPGA.

Figure 7.32: Photograph of a Raspberry Pi micro-computer

7.4.5.1 Interface with the FPGA

The Raspberry Pi have 26 pins in its GPIO interface, assigned to different signals as shown intable 7.3.

The signals can be divided in several groups:

• SPI MOSI, SPI MISO, SPI clock, SPI Chip Select 0 (CS0) and SPI Chip Select 1 (CS1)constitute an SPI interface able to control two SPI devices. In fact, all the lines are connectedto the FPGA: CS0 is active during the transmission of the FPGA configuration file in theinitialization (see section 7.4.5.2), while CS1 is used during the transmission of the slow controlparameters. In both cases the Raspberry Pi is the master, while the FPGA is the slave device,which means that the clock is generated by the micro PC.

• I2C serial data (SDA) and I2C clock implement an I2C standard link connected to the FPGA.This interface is not currently used, but the lines are reserved for future uses.

• UART TX and UART RX can be used to implement a serial communication interface betweenthe Raspberry Pi and the FPGA. As in the case of I2C, it is not currently used but reservedfor future uses.

14We choose the most popular distribution optimized for Raspberry Pi, called Raspbian [161]


Pin Function Pin Function

1 +3.3 V Power supply 2 +5 V Power Supply

3 I2C[162] Serial Data 4 +5 V Power Supply

5 I2C Clock 6 Ground

7 SPI error 8 UART15

9 Ground 10 UART receiver

11 Reset out 12 Program B

13 Temperature alarm 14 Ground

15 SFP alarm 16 INIT B

17 +3.3 V Power supply 18 DONE

19 SPI MOSI 20 Ground

21 SPI MISO 22 RESET

23 SPI clock 24 SPI Chip Select 0

25 Ground 26 SPI Chip Select 1

Table 7.3: Raspberry Pi GPIO pinout

• PROGRAM B, INIT B, RESET and DONE are used during the initialization. See section7.4.5.2

• Programmable inputs are used for managing alarms.

• Pin 11 is a programmable output used for resetting the default values in the FPGA.

• +5 V is an input power supply, while +3.3 V is an output power supply for low power de-manding devices.

7.4.5.2 FPGA-initialization

The Xilinx Artix 7 FPGAs can be configured in different ways. Taking advantage of the presenceof the Raspberry Pi, the so called “slave serial mode” has been chosen [163]. According to thisconfiguration scheme, the Raspberry Pi sends the firmware to the FPGA during the initializationby means of an SPI interface. Figure 7.33 shows the connections between the Raspberry Pi (labeledas Microprocessor or CPLD), the FPGA and the JTAG connector. CCLK, DIN and PROGRAM Bcorrespond to the 3 typical SPI lines, clock, data and chip select respectively. The Raspberry Piplays the role of master in this communication, generating the clock.

The JTAG connector provides with an alternative and effective way to load the firmware in theFPGA and run tests. In the first prototypes of the TIB an external JTAG connector is present inthe front of the box with the aim to debug problems. In the final Trigger Interface Boards it will bean internal connector.

7.4.5.3 Interface with the slow control unit

The Raspberry Pi is in charge of communicating with the central camera slow control unit, usingthe Ethernet camera network. This interface requires coordination with several CTA teams working


Figure 7.33: Slave serial mode FPGA configuration scheme [163]

on this issue and it was still under definition by the time this thesis was written. However, someguidelines have been given to develop the slow control software. The most important decision hasbeen to use OPC-Unified Architecture [164] as the base communication architecture. OPC-UA worksefficiently to control different parts, whether they are simple or complex, and is multiplattform,offering different APIs for software development. The Raspberry Pi will run an OPC-UA serverimplementation for the Java virtual machine.

7.4.5.4 Other functions in the Raspberry Pi

Apart from interfacing the FPGA and the camera slow control system, the computing power ofthe Raspberry Pi is very useful to perform certain functions and calculations locally, reducing theworkload of the camera slow control. Some of these additional functionalities are:

• Calculation of the number of clock cycles that every trigger input must be delayed, depending


on the pointing direction. The camera slow control can send the pointing direction or directlythe delay in ns, and the Raspberry Pi calculates the delays in clock cycles.

• Centralization of the alarms. The Raspberry Pi checks periodically the trigger rates, the statusof the optical links and the temperature, warning the central slow control only if necessary.

• SSH accessibility, useful for debugging.

7.4.6 Power supply

The Trigger Interface Board receives a single +24 V DC power supply from the camera powersupply system. From this voltage, the power must be provided to the different subsystems, whichrequire different supply voltages. Table 7.4 shows the power consumption requirements of the dif-ferent active hardware elements. In order to satisfy the power requirements efficiently, a two levelspower supply system has been designed, according to the diagram shown in figure 7.34.

+5 V Switched

Power Supply

+3.3 V Switched

Power Supply

+2.5 V Linear

Power Supply

+1.8 V Linear

Power Supply

+1 V Linear

Power Supply

+24 V

Raspberry Pi

LVDS to PECL

translators

Optical transceivers

FPGA Artix 7

Delay lines

Thermometer

Figure 7.34: Block diagram of the TIB power supply system

As the most demanding power supply voltages are the +5 V and the +3.3 V, two switchedDC-DC modules have been used to generate them from the +24 V general supply. This first stepfrom +24 V must be done with switched DC-DCs because the voltage drop is too high to use linearregulators efficiently. On the other hand, the +2.5 V, +1.8 V and + 1 V are generated from +3.3V by means of less noisy linear regulators. The Trigger Interface Board is not very sensitive tothe noise in the power supply because it is a digital design where the most important signals aredifferential, so the switched noise introduced by the DC-DCs is not critical. Nevertheless, the noisein the power supplies has been measured and the results are shown in section 7.5.1.

The different power supply modules have been designed with the Webench Power Designer on-line tool from Texas Instruments [165]. Their schematics, as well as the schematics of all theTIB hardware modules can be seen in appendix A.2. Table 7.5 summarizes the most importantcharacteristics of the designed power supplies.

182

7.

Trig

ger

Inte

rface

Board

.

Component +5V +3.3V +2.5V +1.8V +1V Quantity +5V +3.3V +2.5V +1.8V +1V

Raspberry Pi 700 mA 1 700 mA

Artix 7 21 mA 393 mA 191 mA 73 mA 1 21 mA 393 mA 191 mA 73 mA

Transceiver 220 mA 12 2460 mA

SN65LVDS100 35 mA 12 420 mA

SN65LVDS101 61 mA 12 732 mA

DS1123L 30 mA 9 270 mA

TC77 0.4 mA 1 0.4 mA

Total current flowing (mA) 700 mA 4083 mA 393 mA 191 mA 73 mA

Total power consumption (mW) 3500 mW 13475 mW 982 mA 239 mA 73 mA

Table 7.4: Expected power consumption according to datasheets and FPGA simulations


Output Maximumpower Type output Efficiencyvoltage current

+5 V Switched 1 A 84 %

+3.3 V Switched 6 A 93 %

+2.5 V Linear 500 mA 75 %

+1.8 V Linear 300 mA 54 %

+1 V Linear 250 mA 30 %

Table 7.5: Characteristics of the power supplies modules

Taking into account the efficiencies of table 7.5 and the power demands of table 7.4, the globalpower consumption of the TIB can be estimated according to equation 7.9.

Power consumption =

(I2.5 · 2.5V

η2.5+I1.8 · 1.8V

η1.8+I1 · 1Vη1

)· 1

η3.3+I3.3 · 3.3V

η3.3+I5 · 5Vη5

= 21.009 W

(7.9)

7.4.7 Temperature monitoring

The Trigger Interface Board includes a TC77 thermometer chip [158], which is read by the FPGAas was explained in subsection 7.4.4.9. Contrary to what it could be expected, the components withthe most restrictive operating temperature range are not the transceivers (which have a VCSEL)but the Raspberry Pi [160], the FPGA [153] and the programmable delay lines DS1123LE [152].Table 7.6 gathers the operating temperature range of the different components, showing an overalltemperature range between 0 and +70 C. The delay line is the most restrictive element, but it isstill not clear if the DS1123L will be present in the final versions of the Trigger Interface Board.

Taking into account the temperature limits from table 7.6 and the temperature measured withthe sensor, it will be possible to operate the camera cooling system [108] between safety margins.

7.4.8 TIB PCB design

The TIB is a complex board which needs to handle many input and output signals, which inmany cases consist of differential pairs. First, there are 24 differential pairs to and from the opticallinks, and other 32 differential pairs connected to the RJ45 connectors. Additionally, there are single-ended lines for the optical links monitoring, 15 lines for the communication with the Raspberry Pi,12 for the control of the external delays implemented with the DS1123L and still some more forthe JTAG interface and the reading of the thermometer. So many lines connected to the 676 padsFPGA, together with the different power supply rails described in section 7.4.6 required a complex16 layer PCB design (figure 7.35) which was developed with Altium Designer [166].

The PCB design considered several restrictions such as the delay equalization of the lines comingfrom the neighbours, the controlled impedance of the differential pairs, the coupling between adjacentlines or the noise from the power supplies. Additionally a 3D model of the board (figure 7.36(b))


Component Minimum Temperature (C) Maximum temperature (C)Raspberry Pi 0 +85

Avago AFBR5715 ALZ -40 +85SN65LVDS100/101 -40 +85

Xilinx Artix 7 FPGA 0 +100TC77 thermometer -55 +125

LP36890DT-2.5 -40 +125LM22672MR-5.0 -40 +125

CDCV304PWRG4 -40 +85DS1123L-200 0 +70

LP38691DT-1.8 -40 +125CSD18534Q5A -55 +150

B240A-13-F Schottky Diode -65 +150LP3878SD-ADJ -40 +125LM3151MHE-3.3 -40 +125

Ceramic Capacitors -30 + 85Leds -55 +85Fuses -55 +125

Inductors -40 +85Resistors -55 +125

Electrolitic capacitors -40 +85Tantalum capacitors -55 +105

Global temperature range 0 +70

Table 7.6: Operating temperature range of the electronic components in the TIB

Figure 7.35: TIB prototype PCB stack-up

was used to ensure the mechanical compatibility with the rack box. Figure 7.36 shows two views ofthe board design and a photo of the manufactured prototype.


(a) PCB layout, with the different color lines corresponding to different PCB layers

(b) 3D design

(c) Photo

Figure 7.36: Views of the TIB design and first prototype


7.5 TIB measurements

Two boards of the first prototype of the TIB have been manufactured and tested. The goal ofthis prototype is to test the different functionalities, to improve the FPGA firmware, to develop theslow control software which will run in the Raspberry Pi and finally to provide with a TIB for severalCTA camera integration tests which will take place during 2014. In order to perform the tests, theauxiliary boards shown in figure 7.37 were manufactured.

• Board in figure 7.37(a) simulates the central backplane interface.

• Board in figure 7.37(b) mimics the clock board.

• Board in figure 7.37(c) simulates an optical interface.

• Board in figure 7.37(d) is a generic adapter from RJ45 into SMA connectors.

The first three boards include an MCP2200 chip [167] each one, which can generate input pulsescontrolled by a computer through an USB interface.

The results obtained from these tests and the new requirements requested by the LST and MSTcamera developers will be taken into account for a second, upgraded, version which should be theone finally installed in the LST and MST cameras. The next sections show the main features testedin the TIB.

7.5.1 Power supplies

The first systems to be tested were the power supplies. They work as expected, providing withenough current for the different subsystems. Table 7.7 contains the measured DC voltage levels andthe noise, measured as the AC coupled RMS voltages, corresponding to the different power rails(figure 7.38). The table shows that the measured DC levels are very close to the nominal ones andthe noise power is very low. Looking at the numbers it is possible to notice that the RMS voltagesis higher in the +5 V and +3.3 V power supplies. This is because these two power supplies areswitched ones, in contrast to the others which are generated by means of linear regulators. Theonly problem related with the power supplies is that the +1 V LED indicator does not shine (figure7.38(d)) because it was not selected properly and its threshold voltage is higher than 1 V.

Nominal voltage Measured DC (V) Measured AC RMS (mV)

+5 V +5.01 4.15

+3.3 V +3.36 5.37

+2.5 V +2.55 1.97

+1.8 V +1.78 2.68

+1 V +1.09 3.74

Table 7.7: Measured DC voltage and AC coupled RMS voltage for the different voltage rails presentin the TIB


(a) Board simulating central backplane (b) Board simulating clock board

(c) Board simulating an optical interface (d) Adapter from RJ45 to SMA

Figure 7.37: Auxiliary boards used for the tests of the Trigger Interface Board

7.5.2 FPGA configuration

The next system to be tested was the FPGA. First it was tested through the JTAG interface,observing that the FPGA was properly installed and the communication was possible. The nextstep was to configure the FPGA with the Raspberry Pi, and this target was also accomplished.

7.5.3 Clock generation in the PLLs

In order to test the different firmware modules running in the FPGA, different frequencies mustbe generated in the PLLs from the original 10 MHz input clock. In the first tests a problem withthe matching of the input clock was found, which made the PLL to consider clock reflections asclock cycles and at the end to generate higher output frequencies than expected. The problem wascaused because the Xilinx core generator does not activate the internal termination of the inputbuffer, represented in figure 7.39. Once the problem was found, it was corrected by activating thetermination explicitly in the VHDL code and the output frequencies were the expected ones.


(a) +5 V and +3.3 V AC RMS measurement (b) +2.5 V and +1 V AC RMS measurement

(c) +1.8 V AC RMS measurement (d) Power Supply LEDs

Figure 7.38: Measurements of the noise in the power supplies and photo of the failing LED

Figure 7.39: Internal differential clock input buffer and first PLL, in blue

7.5.4 FPGA delay lines

Once the high clock frequencies were available, it was possible to test the other firmware modules.The next ones were the flip-flop based delay lines described in section 7.4.4.2. In order to test them,


a copy of the input and the output of a delay module were directly connected to two spare RJ45pairs which, after an adapter board like the one shown in figure 7.37(d), were connected to anoscilloscope. Delays from 0 to 1600 cycles (4 µs) were tested, observing a minimum delay of 6.2ns corresponding to 0 cycles, which behaves as an offset added to the configured delay. This offsetis due to propagation inside the TIB, and it does not mean any trouble. Regarding the maximumjitter, it was always limited to around 2.5 ns for all the delays tested, which corresponds to theminimum clock period, just as expected. Figures 7.40 and 7.41 show several delay measurements.

Figure 7.40: 0, 2.5, 12.5, 25 and 30 ns delayed outputs (blue and green) and input (yellow)

7.5.5 Stretchers

The next module to test were the stretchers. As in the case of the delay lines, the output of thestretchers was connected to an spare RJ45 connector in order to measure the width of the pulses.Figure 7.42 contains several measurements showing that the stretcher modules work as expected,i.e. stretching the pulse up to the configured width when the pulse is narrower than the coincidencewindow, and not changing the output width when the input pulse is wider than the coincidencewindow width, as it was described in section 7.4.4.3.


Figure 7.41: 4 µs delayed output (green) and input (yellow)

(a) Input width 2.7 ns, configured width 10 ns (b) Input width 2.7 ns, configured width 50 ns

(c) Input width 15 ns, configured width 10 ns (d) Input width 30 ns, configured width 10 ns

Figure 7.42: Several pulse width measurements at the output of the stretchers


7.5.6 Stereo Logic

The tests of the stereo logic were difficult to perform with the oscilloscope because there aremany signals involved, and not all of them can be represented in the screen at the same time. Theavailable oscilloscope only have 4 channels and the outputs from the RJ45 connectors consist ofdifferential pairs, so only 2 signals could be simultaneously represented without using the memories.Additionally, measuring the signals involved in the stereo logic outside the FPGA adds additionaldelays due to the cables, connectors, etc. which can distort the real situation when looking forcoincidences. In this situation, it was preferred to use a Xilinx tool named ChipScope [168]. Thistool uses the spare resources in the FPGA to implement a virtual logic analyzer, which can beused to see the internal signals, sampling them with an internal existing clock (the 400 MHz onewas chosen), triggering with a selectable signal (the local trigger input was chosen) and storing thesamples in the RAM blocks existing in the FPGA. By means of this powerful tool, all the internalsignals participating in the logic could be represented in a PC like in a logic analyzer. The figures7.43 and 7.44, in the following pages show several typical situations.

Figure 7.43(a) shows a typical situation where a trigger output is generated. The 2nd, 3rdand 4th rows in the figure (inputs< 0 >, inputs< 1 > and inputs< 2 >) correspond to the Level1 trigger signal coming from the backplane and two Level 1 trigger inputs coming from neighbourtelescopes16. These input trigger pulses are delayed and stretched, so 6th, 7th and 8th rows representthe signals coming into the stereo logic module. In real conditions the inputs would show a longerseparation in time and the delays required to compensate them would be longer too. For these tests,short delays have been selected in order to see all the signals which are important for the logic inthe same screen. In this way, the 9th signal (condition) is set to “1” when the trigger conditionis accomplished, which in figure 7.43(a) happens for 3 coincident inputs. The 10th row, namedstereo trigger requires condition to be set to “1” and also checks that one of the active inputs isthe local one. If this is the case, the stereo trigger signal can be delayed, as will be shown in figure7.44(b), or not delayed as shown in figure 7.43(a), generating in any case the 11th signal, labelledas delayed local. This signal changes the state of the state machine shown in figure 7.27, whichis represented by the signal state FSM FFd, changing from waiting to armed, which means that astereo trigger output will be generated when the delayed copy of the local input will arrive. Thisdelayed copy is named as delayed local in figures 7.43 and 7.44. When it arrives, the stereo outputsignal (stereo output) is generated, changing the state from armed to shooted during the triggeroutput duration and, finally changing to waiting again. The last signal, named Stereo T, representsthe trigger output from the FPGA.

Figure 7.43(b) shows the signals in a case in which the trigger condition is not fulfilled becausethere are never 3 coincident signals, and therefore condition is never set to “1”. On the other hand,figure 7.44(a) shows a situation in which the trigger condition requires 2 coincident telescopes, butstereo trigger is shorter than condition because the local trigger is only active during part of thetime. Finally, figure 7.44(b) shows a case in which delayed stereo is delayed with the aim to reducethe time during which armed is enabled, reducing the probability of generating a trigger output dueto a previous non-coincident local Level 1 trigger.

161st and 5th signals (stereo trigger top/inputs and ../stereo logic/inputs are 3-bit buses containing the decimalrepresentation of signals 2nd, 3rd and 4th or 6th, 7th and 8th respectively

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Figure 7.43: Measurements of the signals involved in stereo logic, requiring 3 coincident trigger inputs.

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(a) Complying condition of 2 coincident trigger inputs, but requiring also local trigger

(b) Delayed stereo used to reduce the armed time

Figure 7.44: Measurements of the signals involved in stereo logic, showing local trigger requirement and utility of delayed stereo.


7.5.7 Collector

The collector module inside the FPGA was also tested, obtaining output triggers correspondingto the different trigger inputs. The mask allows to enable or disable the trigger inputs, and thetrigger type is generated correctly. Figure 7.45 shows the output corresponding to a software triggercoming from the clock board. The corresponding code “101” is read in the leading edges of the 10MHz clock. As it was required to represent 3 differential signals with a 4-channel oscilloscope, thetrigger output was stored in memory (blue line) and, using it as trigger, the clock and data lines arerepresented with the yellow and green lines respectively.

Figure 7.45: Trigger output pulse (blue) and trigger type clock (yellow) and data (green).

7.5.8 ITR counters

The ITR counters were also measured, just by setting different input trigger frequencies andreading the accounts, which are updated every 250 µs as it was explained in section 7.4.4.6. Theresults are gathered in table 7.8, showing that the counters work as expected:

As it was expected from their implementation, the ITR counters cannot measure rates with anaccuracy better than 4 kHz (because of the updating period), or to measure rates higher than 1.02MHz, (because they are 8-bit counters). Nevertheless, the current characteristics of the counters aresuitable for the expected rates to be measured in CTA.

7.5.9 Optical links

The optical links were implemented in the first prototype with SFP transceivers, like the onesused in optical Gigabit Ethernet networks [146]. These transceivers are easy to control, and very


Input rate (kHz) Counts in a period of 250 µs Measured rate (kHz)

2 0 0

4 1 4

10 2 8

12 3 12

20 5 20

40 10 40

100 25 100

200 50 200

300 75 300

500 125 500

800 200 800

1000 250 1000

1500 255 1020

Table 7.8: Measured rates using the ITR counters

adequate for data transmission through cheap OM3 optical fibers in distances of up to 550 m length.However the tests showed that the SFP transceivers were not a suitable option for sending triggerpulses.

When testing an optical link, it was observed a high level of noise in the received signal. Thiswas caused because, in the transmitter, the differential LVPECL inputs are AC coupled as shownin figure 7.46. If the signal is changing very fast, like it is the case in the Ethernet signals17, itworks properly but, this is not the case of the digital trigger pulses. These trigger pulses sent by thecamera telescopes consists of pulses of a few nanoseconds width (around 10 ns), which are sent at amaximum rate of some hundreds of kHz. This means that the baseline is set to “0” during most ofthe time. Looking at the scheme of figure 7.46, it is easy to understand that the DC levels of such adifferential signal are removed by the capacitors, so the DC voltage is the same in the positive andnegative inputs of the receiver (points marked as TD+ and TD- in the figure). In this situation, theslightest noise fluctuations are recognized by the transmitter as “0s” or “1s”, sending noisy pulses.Real pulses are effectively sent, but together with thousands of noise pulses.

Figure 7.46: Emitter part of an SFP, transceiver, AC coupled [146].

The solution to this problem will consist of replacing the SFP transceivers of the first TIB

17Optical Gigabit Ethernet uses 8b/10b encoding, which achieves DC balance by mapping 8 bit symbols in 10 bitsymbols, where there are never more than 5 consecutive zeros or ones [169].


prototype by analog optical links implemented with discrete VCSELs and PIN photodiodes, as wasdescribed in section 7.4.2.2.2. The transceivers have been implemented in test boards and testedwith two optical fibers of 2 and 500 m. Figure 7.47 shows the measured signals corresponding tothe 2 m link. The purple line was measured with a probe18 with the aim to show that this kind oflinks can handle pulsed signals properly. On the other hand, figure 7.48 shows the input and outputwith a 500 m optical fiber, demonstrating that the optical power and the sensibility of the receptorare adequate. The bandwidth is large enough to allow sharp edges and, as a result, the jitter is verylow: only 77 ps with the 500 m optical fiber.

Figure 7.47: Inverted copy of the input signal (magenta), received analog signal at the input of thecomparator (purple) and LVDS output (yellow) of the analog optical link, with a 2 m optical fiber

7.5.10 External delays

The different ways to implement the external delays described in section 7.4.3 have been tested:

7.5.10.1 Delays with DS1123LE-200

The external delays implemented with the Maxim DS1123LE-200 chips [152] were the optionchosen for the first TIB prototype. They were tested and, in fact, used to delay the local trigger

18The length of the probe cable is longer than the one of the cable which connects the LVDS output to the oscilloscope.This is why the LVDS output appears before the analog pulse.


Figure 7.48: Inverted copy of the input signal (magenta) and received LVDS output (yellow) of theanalog optical link, with a 500 m optical fiber

and generate the delayed local signals shown in figures 7.43 and 7.44. Figure 7.49 shows the resultof delaying an input pulse 0, 50, 100, 150 and 200 steps of 2 nanoseconds with only one delay chip,and it can be seen that the delay accuracy is very good and the standard deviation of the jitter isaround 20 ps.

However, when longer delays were implemented with a chain of 8 chips in cascade the resultswere not so good. For a delay of 2.6 µs, a standard deviation of the jitter of 1.4 ns was measured.This jitter is too high, and discards these chips as an option to implement the asynchronous delayof the local input which at the end is used to read the camera, and which should have a jitter lowerthan 1 ns.

7.5.10.2 Delays with 3D3428

In spite of the difficulties with the supply of this chip, it was finally possible to get a sample andtest it. The measurement corresponding to the expected required delay is shown in figure 7.50. Asit can be see in the figure, the jitter is much lower than with the Maxim device: for a 2.7 µs delay,the std. deviation of the jitter is 606 ps. Therefore this chip will be the chosen one for the upcomingversion of the TIB.


Figure 7.49: Input signal (yellow) and delayed 0 (green), 50, 100, 150 and 200 steps of 2 ns (blue)with DS1123LE-200.

7.5.10.3 Delay with an optical fiber reel

The delay can be implemented with a long optical fiber and the analog optical links describedin section 7.4.2.2.2. The measurements shown in figures 7.47 and 7.48 show that this is a feasibleoption. With the 500 m length optical fiber, a delay of 2.53 µs with a jitter of only 77 ps standarddeviation was achieved, which is better than with any existing chip. However, this solution is verybulky and not very feasible to be implemented in an IACT.

7.5.11 Test conclusions

The tests have shown that the first prototype of the TIB can comply with most of the require-ments. Most of the concepts have been successfully tested:

• The stereo trigger and the trigger gathering functions can be implemented in an FPGA, workingat 400 MHz.

• A Raspberry Pi is very useful to configure the FPGA and perform the slow control function-alities, avoiding complex Ethernet implementations.

• The delay lines and the stretchers based in flip-flop chains work as expected, with a jitterlimited by the FPGA clock frequency.


Figure 7.50: Delay measurement with 3D3428 delay line

• A complex logic has been developed, which can generate trigger outputs which are synchronouswith a local Level 1 trigger signal, but not with the FPGA clock.

• The trigger type generation worked as expected.

• The trigger rates can be measured in the FPGA.

• The SPI control of external chips, such as the DS1123L or the thermometer worked properly.

• In spite of the board complexity, no crosstalk problems between lines were observed.

• The designed power supplies add very little noise.

In addition, there are two important points to improve in the next prototype version:

• The optical SFP transceivers must be replaced by the ones based on discrete VCSELs and PiNphotodiodes, capable of working with trigger-like pulsed signals.

• The 8 delay chips DS1123LE-200 from Maxim must be replaced by one 3D3428 from DataDelay Devices, with much lower jitter.

Anyway, it must be pointed out that the first TIB prototype fulfils the requirements for theforthcoming integration tests, with only one camera. When the improvements, which are already


tested, will be included in the second TIB prototype, it will be possible to accomplish all therequirements of CTA LSTs and MSTs.

Chapter 8

Conclusion and Outlook

8.1 Conclusions

During the last four years I have been working at GAE-UCM, together with other Spanish groupsfrom Ciemat, IFAE and UB and in coordination with other foreign institutions, specially from Franceand Japan, with the aim to build the best possible trigger system for the large and medium sizedtelescopes of the forthcoming Cherenkov Telescope Array. On the base of our previous knowledge andour experience with the MAGIC telescope, we conceived a system with a great expected performanceaccording to MonteCarlo simulations (see section 3.2), and which is feasible to be constructed andoperated.

The proposed trigger architecture follows a multi-level scheme, able to support many of themost powerful trigger techniques: majority trigger, sum trigger, variable trigger region sizes, partialreadout, sliding window, two-thresholds strategies, Colibri, PMT transit time calibration, hardwarestereo trigger and even software array trigger with the digitized data. Such a global architectureis the result of the collaboration between all the mentioned teams mentioned above. Nevertheless,each group developed a different hardware element: IFAE team designed the Level 0, Ciemat teamis in charge of the backplane, UB worked in ASICs and at UCM-GAE we designed the Level 1 andthe TIB, which are the core of my thesis.

The Level 1 implements successfully the required functionalities: it combines the inputs fromsets of clusters and decides if the camera should be triggered or not. It does it in a very short time,with a negligible jitter, complying with the bandwidth requirement and adding very low noise. Itis able to implement the sumtrigger scheme, it supports Colibri (as described in chapter 5) andincludes the necessary hardware to implement the delay compensation system described in chapter6. Several prototypes have been tested with the other systems and the current design is ready forindustrial production. Additionally, the development of the Level 1 produced 2 extra-outcomes:

• Usability of microwave techniques and technologies adapted to short pulse handling. Thetypical spectrum of a PMT output pulse ranges from low frequencies to up to 1 GHz and,at these high frequencies the RF and microwave technologies can be useful. The case of theWilkinson splitters [6] or the use of Schottky diodes are examples of this.

202 8. Conclusion and Outlook

• Patent of a new family of logic gates, able to work with LVDS and other differential logicstandards.

Regarding the TIB, two boards of the first prototype have been designed, manufactured andtested, and the results are very satisfactory. The current TIBs have been able to comply with thevery demanding requirements needed to implement the LST hardware stereo logic, gathering thedifferent trigger origins and generating the trigger type. The use of chains of flip-flops in a FPGAhave showed the expected performance in the delay lines and in the stretchers, and the RaspberryPi has been a good solution to implement the slow control communication and to configure theFPGA. Thus, the current prototypes are useful for the single camera demonstrator tests which willtake place during this year. Two problems with the optical links and the external delays have beendetected, and the solutions are ready to be implemented in the next version of the TIB, which isscheduled to be ready some time before two telescopes will be ready to work together in a stereotrigger scheme.

In short, it can be said that the work carried out during these years has made possible to presentan excellent trigger system, able to comply with the demanding requirements of CTA LSTs andMSTs.

8.2 Outlook

The CTA project is now at the end of its prototyping phase. From 2014 to 2016, prototypesfor large demonstrators and complete MSTs and LSTs will be built, tested and assessed. Thesecomplete prototype telescopes will be also used to test and adjust the trigger distribution system,check the accuracy of the different calibration algorithms (flat-fielding, trigger amplitude, delays...)and to finish the implementation of all the details required for the correct data taking, such as thoserelated with the data format, event building, time stamping, slow control, etc. In summary, all thedetails required to make CTA telescopes work, but which can not be tested without a completecamera, will be implemented and tested in this phase.

Additionally, building these first telescopes implies the first industrial production of severalelements, such as the camera front-end boards and backplanes, and their assembly in clusters withPMTs. These elements must be tested before being mounted in the camera, according to a qualitycontrol protocol which still needs to be defined. Defining the measurements to be done in each step,the acceptable values, and developing the corresponding test setups is an intensive work which alsoneeds to be done in this stage. Part of this work will be subcontracted to companies, but alwaysunder the control of the groups which developed the systems.

All this work will not leave much time for developing new ideas. However, there are two maininnovative lines to be developed, as soon as the other tasks allow us.

8.2.1 Trigger integration in ASICs

One interesting idea, with the aim of reducing the number of components, simplifying the assem-bly, reducing costs and power consumption, is to develop ASICs concentrating the different triggerfunctionalities. Our partners in ICCUB (Institute of Science of the Cosmos, University of Barcelona)

8. Conclusion and Outlook 203

in Spain and our french colleagues at IRFU (Institut de Recherche sur les lois Fondamentales del’Univers) have some experience developing ASICS ([58], [95], [98]), so that we (mainly ICC-UB andCiemat, with UCM and IFAE collaborating in the specification and testing) have taken advantageof their experience and collaboration to design and manufacture ASICs for the trigger.

In this way, one ASIC for Level 0 and other for Level 1 have been designed, and a first versionproduced and tested, while other ASIC for the Level 0 fan-out function is in the design phase.Some functionalities like the ones related with the SPI slow control used in the Level 1 to adjustthe threshold levels have been easy to include, because they have been already implemented forNECTAr. However, the ones related with differential to single-ended conversion or the addition ofanalog signals were more complicated requiring to be redesigned. This was so because several basicfunctions are easier to implement in an ASIC in a different way from how they are implementedwith discrete components. For instance, the Wilkinson splitter functionality can be implemented ina more straightforward way replicating the signals with current mirrors. In general, replicating andadding currents, is preferable when working with ASICs.

Regarding the ASICs manufacturing, Europractice [170] has allowed us to share the silicon waferwith other projects, making the prototype production much cheaper. After the production, theASICs are in the process of being fully characterized to check if they can substitute the Level 1 withdiscrete components.

The GAE-UCM group which I belong, has contributed with the Level 1 ASIC specification andwill also help with its characterization. Before being directly soldered in the front-end board, a firstbatch of ASICs will be mounted on mezzanines compatible with the ones implemented with discretecomponents. In this way, the ASICs can be tested with the front-end boards, and their behaviourcan be compared with the one obtained with discrete components. The GAE-UCM group will be incharge of the production of the L1 mezzanines with the Level 1 ASIC designed by the Ciemat team.The target is to have the ASICs characterized and ready for integration in the front-end boards andin the backplane for the massive production phase, when most of the telescopes will be built. If itis not possible, designs with discrete components are the default solution.

8.2.2 Topologic stereo trigger

In the case of the Trigger Interface Board, there are still a few improvements to include regardingfirmware debugging and software development. As was mentioned in section 7.3, there are severaladvanced functionalities which could be implemented if required, although the baseline which consistsof looking for temporal coincidences between 4 LSTs and gathering the different trigger origins isworking as expected.

One of the most promising improvements is the topologic hardware stereo trigger. As it wasbriefly described in section 7.3.5, it consists of looking not only for coincidences inside a time window,but also for images compatible with Cherenkov showers. Adding this additional condition, most ofthe NSB triggers which happen by chance inside the time window can be rejected, while keeping theγ-ray-like showers. As the trigger rate can be further reduced, it is possible to lower the thresholdsuntil reaching the maximum reading rate again at a smaller energy threshold.

A similar topologic scheme has been proposed for the MAGIC telescopes, which could serve as abaseline design for the CTA LSTs. The first simulations results, whose performance is representedin figure 8.1, show improvements above 20% in the collection area below 100 GeV [171]. In the case


of CTA LSTs, having 4 telescopes instead of only two, an even larger gain is expected. This casewith 4 LSTs is currently under study with simulations.

(a) Absolute effective area

(b) Normalized effective area

Figure 8.1: Simulation results of the topologic scheme for the MAGIC telescopes

The practical implementation of a topologic hardware stereo trigger in CTA would require someminor changes in the current trigger hardware. The trigger system presented in this thesis canhandle all the trigger information in a pulse: a trigger pulse means that the trigger threshold has


been exceeded somewhere in the camera, a known amount of time before receiving the leading edgeof the pulse. To implement the topologic scheme, the information about which cluster triggered, orat least which area of the camera was triggered, is required by the Trigger Interface Board to lookfor valid patterns.

There is only one spare line in the RJ45 interface between the TIB and the central backplane(see table 7.1), so in order to send more information to the TIB, this information must come fromother backplanes apart from the central one. Considering this second option, two schemes have beenproposed, which are described in subsections 8.2.2.1 and 8.2.2.2.

8.2.2.1 Sectorization

In these scheme the special backplanes which provide information to the TIB are the 7 onesaround the central backplane. According to the current distribution scheme for the trigger, whenone cluster is fired, it sends its trigger to a neighbour which, in turn, sends it to other neighbourand this process repeats until reaching the central cluster. The path followed by the trigger signalchanges depending on the specific cluster, but always is composed of some “diagonal” jumps untilfinding their corresponding main path (or none if the fired cluster is in the main path), and some“radial” jumps until reaching the central cluster. This is illustrated with red arrows in figure 8.2.

Figure 8.2: Sectorization scheme


This way of collecting the trigger signals means that, any of the six special backplanes surroundingthe central one receives the triggers from a triangular sector which covers 1/6 of the camera. So,once the special cluster which received the trigger is known, it is possible to deduce in which camerasector it was generated. Additionally, if the number of jumps is encoded in the pulse width of thetrigger pulse, it is possible to restrict even more the possible trigger origins to one of the areas withthe same color in figure 8.2. The clusters corresponding to the last two jumps have been colouredwith the same color (i.e. included in the same region) to avoid very small regions, however they canbe divided in other two regions corresponding to one or two jumps away from the special cluster.

With this scheme, as it is described by figure 8.2, the TIB can know in which of the the 37regions of the camera the trigger was originated. This information can be codified with 6 bits andbroadcasted through the optical links to the other LSTs. So, considering 4 LSTs, the TIB canmanage a table with 374 = 1874161 possibilities: some of them will be accepted as images producedby a γ-ray shower, while others don’t. If this granularity is not enough to get good results from thetopologic trigger, the triangulation scheme can be used.

8.2.2.2 Triangulation

The triangulation scheme is more complex, but it allows to know exactly which cluster was trig-gered. When a cluster is triggered (orange in figure 8.3), it distributes a signal to all its neighbours,which in turn send their signals to their surrounding neighbours and so on, generating a triggercircular wave front which expands throughout the camera (red circumferences). The number ofjumps is codified in the pulse width, so the special clusters (red ones in figure 8.3) can know howfar from them a trigger has happened. In this way, the TIB, which will be additionally connectedto these special clusters, also knows how far from each special cluster a trigger happened and cantriangulate the position of the trigger origin.

The propagation of the trigger wave throughout the backplanes network would be independentfrom the standard trigger propagation, and could be done using spare lines in the connectors betweenneighbour clusters. However, the way in which it could be propagated to prevent the wave fromcoming back, or how would it solve special cases like two clusters triggering at the same time is stillunder development.

Additionally, knowing which cluster from the 265 in a camera was triggered in the 4 telescopesmeans 2654 ≈ 5 · 109 possibilities to be analyzed by the TIB FPGA. This is probably too much totake the decision with a look-up table in a short time, so maybe some kind of region reduction wouldbe required, partially loosing the greatest advantage of this scheme.


Figure 8.3: Triangulation scheme

Appendix A

Schematics

A.1 Level 1 schematics

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1

CT

RLad

g901

VDD

RF

2

RF

1

CT

RL

LVD

S_A

ND O

UT

N

OU

TP

IN2N

IN2P

IN1N

IN1P

Figure A.2: L1: General Schematic

212 A. Schematics

7/03/2013DIFF2SINGLE

LUIS A. TEJEDOR 3

INPUT2_P

INPUT3_N

AGND\G

100N

-3.3V_ANALOG\G

AGND\G

2

R25

EN

AB

LE\I

OU

TPU

T1\I

OU

TPU

T2\I

OU

TPU

T3\I

INP

UT3

_N\I

INP

UT3

_P\I

INP

UT2

_N\I

INP

UT2

_P\I

INP

UT1

_N\I

INP

UT1

_P\I

200

1R2

1

200 R2

0

6565R1

7200R1

6R1

5

R14

R13

200

AGND\G

AGND\G 1

AGND\G

AGND\G 1

300

21

2

OUTPUT1

8

AGND\G

62 261

AGND\G

261 R2

3R2

4

65R2

2

R19

2

300

65

R18

2 2 AGND\G

300

300

300

300

1617

I25

100P

62

R30

2

2

R28

2

2

2

1

R29

R27

100N

10U

2

C26 2

+3.3V_DIGITAL\G

U16

2 1

C271

2 1

C22

2 1

C24 2 1

C25

2 1

C23

1324

81 6

191

142351210

20 213 15224

1 1

21

R26

211

21 1 1

21

21

221 1 1

INPUT3_P

AGND\G

10U

ENABLE

INPUT1_P

INPUT2_N

INPUT1_N

AGND\G

100P

OUTPUT2

OUTPUT3

DATE:

PAGE:

TITLE:

ENGINEER:

1

1234

234

A

B

C

D

A

B

C

D

IN

PIN

NA

ME

S

OUT

OUT

OUT IN

INININININ

ad80

03

VCC3

VCC2VCC1

VDD3VDD2VDD1

+IN3

+IN2

+IN1

-IN3

-IN2

-IN1

OUT

3

OUT

2

OUT

1

FB3

FB2

FB1

PD3

PD2

PD1

Figure A.3: L1: Differential to Single-Ended (channels 0,1,and 2)

A. Schematics 213

25/05/2012DIVIDER3

LUIS A. TEJEDOR 4, 5

OU

TPU

T1\I

OU

TPU

T2\I

OU

TPU

T3\I

INP

UT\

I

20N

2PF

20N

2PF

AGND\G

5.6PF

1P

AGND\G

2PF

49.9

49.9

INPUT

AGND\G

49.9

20N

OUTPUT3

49.9

OUTPUT1

G\DNGA

G\DNGA

OUTPUT2

DATE:

PAGE:

TITLE:

ENGINEER:

1

1234

234

A

B

C

D

A

B

C

D

PIN

NA

ME

S

LLL

OU

T

OU

T

OU

T

IN

Figure A.4: L1: 3 branches splitter

214 A. Schematics

07/03/2013ADDER4

LUIS A. TEJEDOR 6

AGND\G

2

INPUT32

EN

AB

LE\I

OU

TPU

T3\I

OU

TPU

T2\I

OU

TPU

T1\I

INP

UT1

4\I

INP

UT1

3\I

INP

UT1

2\I

INP

UT1

1\I

INP

UT3

1\I

INP

UT3

2\I

INP

UT3

3\I

INP

UT3

4\I

INP

UT2

1\I

INP

UT2

2\I

INP

UT2

3\I

INP

UT2

4\I

INPUT33

275

1

275

R59

1275

AGND\G

R60

100100100100100100100100

11

100

AGND\G

100 1100

1

2R57

11

100

100

100

100

100

100

100

100

100

100

100

100

100

1

100N

C47

26

OUTPUT3

1

100N

10U

OUTPUT1

INPUT12

R49

R50

2222

24

5

R58

+3.3V_DIGITAL\G

R43

R44

R45

R46

R47

R48

2 2 2R5

1R5

2R5

3R5

4

2

-3.3V_ANALOG\G

C45

2

100P

C44AGND\G

17204

AGND\G

2

2 1R87

1R86

1R85

1R84R83

2R56

2R55

2R34

2R11

2 1R7

2 1R6

C49

2 1

C48

2 1

C46 1

1

13

18

191

1423121082 16213 1522

U17

1

2 2

21

21

21 1

21

21 1

211

21

21

21

OUTPUT2

INPUT31

INPUT22

AGND\G10U

100P

I41

INPUT23

INPUT24

INPUT34

INPUT21

INPUT14

INPUT13

ENABLE

INPUT11

ENABLE_3\G

DATE:

PAGE:

TITLE:

ENGINEER:

1

1234

234

A

B

C

D

A

B

C

D

ad80

03

VCC3

VCC2VCC1

VDD3VDD2VDD1

+IN3

+IN2

+IN1

-IN3

-IN2

-IN1

OUT3

OUT2

OUT1

FB3

FB2

FB1

PD3

PD2

PD1

IN

PIN

NA

ME

S

INININ IN IN

OUT

OUT

OUT IN

INININ IN IN IN

Figure A.5: L1: 4 inputs adders

A. Schematics 215

07/03/2013

LUIS A. TEJEDOR

DIFF2SINGLEB

7

60

300

-3.3V_ANALOG\G C

51

1

R78

R68

INPUT2_P

INPUT2_N

INPUT3_P 1

R72261

AGND\G1

261

60300

300

60300

60 300

300

300

300

300

300 R

742

R75

AGND\G

AGND\G

INPUT1_P

6262 R71

R70

AGND\G

R77

AGND\G

INPUT3_N

2AGND\G

R64

R66

R67

12 22

R62

AGND\G

1 1

R63

AGND\G

R73

R61

1

10U

100N

C50

1

C55

100P

C53

2

13 2

100N

5OUTPUT3

OUTPUT2

OUTPUT1

U181 I21

2

C54

C52

2

2

R65

R69

AGND\G

122

R76

222

19

+3.3V_DIGITAL\G

1

1

1

2 1

21

2 2

2481 6

1

142312108

17202 16213 15224

1

2

12

1

21

21 11 1 1

2

A0YA1\G

ENABLE

ENABLE_3\G

10U AGND\G

AGND\G

100P

INPUT1_N

DATE:

PAGE:

TITLE:

ENGINEER:

1

1234

234

A

B

C

D

A

B

C

D

IN IN IN

OU

T

OU

T

OU

T IN

ad80

03

VCC3

VCC2VCC1

VDD3VDD2VDD1

+IN

3

+IN

2

+IN

1

-IN3

-IN2

-IN1

OU

T3

OU

T2

OU

T1

FB3

FB2

FB1

PD3

PD2

PD1

ININ IN

Figure A.6: L1: Differential to Single-Ended (channels 3, 4 and 5)

216 A. Schematics

DIV2


OU

TPU

T2\I

OU

TPU

T1\I

INP

UT\

I

INPUT

2PF

15NH

191

OUTPUT2

OUTPUT1

15NH

49.9

AGND\G

2P

4PFAGND\G

AGND\G

DATE:

PAGE:

TITLE:

ENGINEER:

1

1234

234

A

B

C

D

A

B

C

D

PIN

NA

ME

S

LL

OU

T

OU

T

IN

Figure A.7: L1: 2 branches splitter

A. Schematics 217

07/03/2013

10, 11LUIS A. TEJEDOR

ATENUATOR

56

OUTPUT

INPUT

AGND\G

500

INPU

T\I

OUTP

UT\I

DATE:

PAGE:

TITLE:

ENGINEER:

1

1234

234

A

B

C

D

A

B

C

D

INO

UT

PIN

NAME

S

Figure A.8: L1: Attenuator

218 A. Schematics

19/03/2013LVDS_OR

LUIS A. TEJEDO 12, 13

100N

10U

OUTP

OUTN

IN1P

10M

IN1NIN

3N

I8

10M

10M

10M

IN3P

I7

10M

10M

I9

IN2N

I12

AGND\G

100P

+3.3V_DIGITAL\G

IN2P

IN1P

\IIN

1N\I

IN2P

\IIN

2N\I

IN3P

\IIN

3N\I

OUT

P\I

OUT

N\I

IN

OU

T

OU

T

adcm

p604

VCC

Q*

VNVP

VEE

Q

IN

IN

IN

IN

IN

hsms 2855

D2A D2C

D1CD1A

hsms 2855

D2A D2C

D1CD1A

hsms 2855

D2A D2C

D1CD1A

PIN

NAM

ES

DATE:

PAGE:

TITLE:

ENGINEER:

1

1234

234

A

B

C

D

A

B

C

D

Figure A.9: L1: LVDS OR gate

A. Schematics 219

3COMPARATOR


OU

T1P

\IO

UT1

N\I

OU

T2P

\IO

UT2

N\I

OU

T3P

\IO

UT3

N\I

VTH

\IIN

AD

3\I

INA

D2\

IIN

AD

1\I

AGND\G

+3.3V_DIGITAL\G

AGND\G

+3.3V_DIGITAL\G

OUT3N

OUT3P

OUT2N

OUT1N

OUT1P

INAD1

VTH

VTH

INAD3

VTH

VTH

I3I1

+3.3V_DIGITAL\G

10U

100P

100N

INAD2

AGND\G

100N

10U

100P

10U

100P

100N

I2OUT2P

DATE:

PAGE:

TITLE:

ENGINEER:

1

1234

234

A

B

C

D

A

B

C

D

PIN

NA

ME

S

OUT

OUT

ININININ

adcm

p604

VCC

Q*

VNVP

VEE

Qadcm

p604

VCC

Q*

VNVP

VEE

Q

OUT

OUT

OUT

OUT

adcm

p604

VCC

Q*

VNVP

VEE

Q

Figure A.10: L1: comparators

220 A. Schematics

19/03/2013LVDS AND

LUIS A. TEJEDOR 16

DGND\G

OU

TN\I

OU

TP\I

IN2N

\IIN

2P\I

IN1N

\IIN

1P\I

IN1N

IN2N

R11

4

1K1K1K1K

I81

C12

6

OUTP

5

R11

2

1

R11

1

D7 2

R11

3

3D

8I5 2

4

4

DGND\G

C12

4 210UF

C12

5100NF

100PF

2

1

21

21

3

2

61

U27

234

21 1

21

1

OUTN

+3.3V_CALIB\G

IN2P

I9

IN1P

DATE:

PAGE:

TITLE:

ENGINEER:

1

1234

234

A

B

C

D

A

B

C

D

hsm

s 28

55D2A

D2C

D1C

D1A

IN

PIN

NA

ME

S

adcm

p604

VCC

Q*

VNVP

VEE

Qhs

ms

2855

D2A

D2C

D1C

D1A

ININ

OU

T

OU

T

IN

Figure A.11: L1: LVDS AND gate

A. Schematics 221

17

WIDTH2AMP

LUIS A. TEJEDOR

6/9/2012

OU

T\I

INP

\IIN

N\I

INP

1R1

161M

120P

C127

4

I4C1

28

1

D9

R115

R117

2 1M

R118

2

C133

R119

-3.3V_ANALOG\GR1

22

AGND\G

I22

U28

+3.3V_CALIB\G

7

1

65

2 3

48

21

21

21

1

1

2

2 1

2

2 1C1

31

2 1

C130

2 1

C129

2 3

1 2 1

-3.3V_ANALOG\G

AGND\G

+3.3V_CALIB\G

100P

1M

1M

AGND\G

INN

10U

100N

OUT

390K

120P

10K

10UF

AGND\G

DATE:

PAGE:

TITLE:

ENGINEER:

1

1234

234

A

B

C

D

A

B

C

D

PIN

NA

ME

S

hsms 2855

D2AD2C

D1C D1Aop

a283

0_m

sop8

+VCC

OUT

2

IN2-

IN2+

-VCC

IN1+

IN1-

OUT

1

OUT

IN IN

Figure A.12: L1: Width to Amplitude converter

222 A. Schematics

LUIS A. TEJEDOR

READ PULSE AMP 5/9/2012

18

SDATA_OUT

4U

30

6

10U

1UF

10U

100N

100N

10K

DGND\G

+3.3V_CALIB\G

DGND\G

DGND\G

CS*

I16

100P

+3.3V_CALIB\G

SCLK

100N

10U

AGND\G

I5

100P10N AG

ND\G

C13

4

12

12

12

U29

2

1

5

43

R12

6

2

12

13

4

5

2

1

C14

0 12C14

1 1 2

1 21 2

U31

3

7

62

212

12

21

2

1100P

+3.3V_CALIB\G

C13

7

C13

8 1DGND\G

C14

42100N

1

C14

5 2C

146

C14

7

DGND\G

AGND\G

1.5K

1R

12410K

R12

5

DGND\G

247P

C13

5

68P

1

I10

C13

9

58

C14

3

1

DGND\G

+3.3V_CALIB\G

C14

2

C13

6

+3.3V_CALIB\G

PULSE_IN

PULS

E_IN

\ISC

LK\I

CS*\I

SDAT

A_O

UT\I

DATE:

PAGE:

TITLE:

ENGINEER:

1

1234

234

A

B

C

D

A

B

C

D

adc7

478a

NC

2

NC

CS*

SDAT

ASC

LKVI

N

GNDVDD

adg8

01VDDNC

IN

GND

SD

ININOU

T

adcm

p600

VCCI

VNVPGND

Q

IN

PIN

NAM

ES

Figure A.13: L1: Read Pulse Amplitude circuit

A. Schematics 223

A.2 Trigger interface board schematics

224 A. Schematics

11

22

33

44

55

66

77

88

99

1010

1111

1212

DD

CC

BB

AA

Title

Num

ber

Rev

ision

Size A1

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\FP

GA

1.Sc

hDoc

Dra

wn

By:

+2.5

V

+3.3

V

+3.3

V

+2.5

V

+2.5

V

+2.5

V

+1V

+1.8

V

+1V

+3.3

V

+3.3

V

+3.3

V

4.7K

R23

Res

3

330

R24

Res

3

4.7K

R26

Res

34.

7K

R25

Res

3

+3.3

V

+3.3

V+3

.3V

+3.3

V

GN

D

GN

D

SPA

RE_

1_P

SPA

RE_

1_N

INPU

T_4_

PIN

PUT_

4_N

INPU

T_5_

PIN

PUT_

5_N

INPU

T_6_

PIN

PUT_

6_N

INPU

T_7_

PIN

PUT_

7_N

P1_7

P1_1

1P1

_13

P1_1

5

SPI_

CS_

0SP

I_C

S_1

SPI_

MIS

OSP

I_C

CLK

RES

ET

I2C

_SC

LK

CLK

_TH

UA

RT_

RX

UA

RT_

TX

I2C

_SD

A

CS_

THIO

_TH

LE_E

XT_

DEL

_9

MIS

O_E

XT_

DEL

MO

SI_E

XT_

DEL

LOS_

0LO

S_1

LOS_

2LO

S_3

LOS_

4LO

S_5

LOS_

6

LOS_

7

LOS_

CA

LIB

LOS_

PED

ESTA

L

TX_D

ISA

BLE

_1TX

_DIS

AB

LE_2

TX_D

ISA

BLE

_3TX

_DIS

AB

LE_4

TX_D

ISA

BLE

_5TX

_DIS

AB

LE_6

TX_D

ISA

BLE

_7

TOB

EDEL

AY

ED

TRIG

DEL

AY

ED

CLK

_EX

T_D

EL

TX_D

ISA

BLE

_CA

LIB

TX_D

ISA

BLE

_PED

ESTA

L

TX_F

AU

LT_0

TX_F

AU

LT_1

TX_F

AU

LT_2

TX_F

AU

LT_3

TX_F

AU

LT_4

TX_F

AU

LT_5

TX_F

AU

LT_6

TX_F

AU

LT_7

TX_F

AU

LT_C

ALI

BTX

_FA

ULT

_PED

ESTA

L

TRG

TYPE

0_C

B_P

TRG

TYPE

0_C

B_N

TRG

TYPE

0_M

WR

_PTR

GTY

PE0_

MW

R_N

TRG

TYPE

1_C

B_P

TRG

TYPE

1_C

B_N

TRG

TYPE

1_M

WR

_PTR

GTY

PE1_

MW

R_N

PED

ESTA

L_P

PED

ESTA

L_N

AR

RA

YTR

IG_P

AR

RA

YTR

IG_N

CA

LIB

_PC

ALI

B_N

OU

TPU

T_0_

PO

UTP

UT_

0_N

OU

TPU

T_1_

P

OU

TPU

T_2_

P

OU

TPU

T_3_

P

OU

TPU

T_4_

P

OU

TPU

T_5_

P

OU

TPU

T_6_

P

OU

TPU

T_1_

N

OU

TPU

T_2_

N

OU

TPU

T_3_

N

OU

TPU

T_4_

N

OU

TPU

T_5_

N

OU

TPU

T_6_

N

INPU

T_1_

PIN

PUT_

1_N

INPU

T_0_

PIN

PUT_

0_N

INPU

T_2_

PIN

PUT_

2_N

INPU

T_3_

PIN

PUT_

3_N

OU

TPU

T_7_

PO

UTP

UT_

7_N

EXTR

A_S

FP_1

1_P

EXTR

A_S

FP_1

1_N

STER

EO_C

B_P

STER

EO_C

B_N

INPU

T_8_

PIN

PUT_

8_N

CLK

_10M

HZ_

PC

LK_1

0MH

Z_N

STER

EO_M

WR

_PST

EREO

_MW

R_N

TDI

TDO

TCK

TMS

DO

NE

PRO

GR

AM

_BINIT

_B

CA

LIB

_FB

_PC

ALI

B_F

B_N

PED

ESTA

L_FB

_PPE

DES

TAL_

FB_N

REF

_EX

T_D

EL

Luis

A. T

ejed

or

Ster

eo T

rigge

r

1FP

GA

1

SPA

RE_

1_P

SPA

RE_

1_N

INPU

T_4_

PIN

PUT_

4_N

INPU

T_5_

PIN

PUT_

5_N

INPU

T_6_

PIN

PUT_

6_N

INPU

T_7_

PIN

PUT_

7_N

TRG

TYPE

0_M

WR

_P

TRG

TYPE

0_C

B_P

TRG

TYPE

0_C

B_N

TRG

TYPE

0_M

WR

_N

TRG

TYPE

1_C

B_P

TRG

TYPE

1_C

B_N

TRG

TYPE

1_M

WR

_PTR

GTY

PE1_

MW

R_N

PED

ESTA

L_P

PED

ESTA

L_N

AR

RA

YTR

IG_P

AR

RA

YTR

IG_N

CA

LIB

_PC

ALI

B_N

CA

LIB

_FB

_PC

ALI

B_F

B_N

PED

ESTA

L_FB

_PPE

DES

TAL_

FB_N

STER

EO_M

WR

_PST

EREO

_MW

R_N

STER

EO_C

B_P

STER

EO_C

B_N

INPU

T_8_

PIN

PUT_

8_N

CLK

_10M

HZ_

PC

LK_1

0MH

Z_N

EXTR

A_S

FP_1

1_P

EXTR

A_S

FP_1

1_N

OU

TPU

T_0_

PO

UTP

UT_

0_N

OU

TPU

T_1_

PO

UTP

UT_

1_N

OU

TPU

T_2_

PO

UTP

UT_

2_N

OU

TPU

T_3_

PO

UTP

UT_

3_N

OU

TPU

T_4_

PO

UTP

UT_

4_N

OU

TPU

T_5_

PO

UTP

UT_

5_N

OU

TPU

T_6_

PO

UTP

UT_

6_N

INPU

T_1_

PIN

PUT_

1_N

INPU

T_0_

PIN

PUT_

0_N

INPU

T_2_

PIN

PUT_

2_N

INPU

T_3_

PIN

PUT_

3_N

OU

TPU

T_7_

PO

UTP

UT_

7_N

IO_2

5_13

U17

IO_L

24N

_T3_

13V

17IO

_L24

P_T3

_13

V16

IO_L

23N

_T3_

13V

14IO

_L23

P_T3

_13

U14

IO_L

22N

_T3_

13U

16IO

_L22

P_T3

_13

U15

IO_L

21N

_T3_

DQ

S_13

T18

IO_L

21P_

T3_D

QS_

13T1

7IO

_L20

N_T

3_13

T15

IO_L

20P_

T3_1

3T1

4IO

_L19

N_T

3_V

REF

_13

W18

IO_L

19P_

T3_1

3V

18IO

_L18

N_T

2_13

W19

IO_L

18P_

T2_1

3V

19IO

_L17

N_T

2_13

U19

IO_L

17P_

T2_1

3T1

9IO

_L16

N_T

2_13

Y20

IO_L

16P_

T2_1

3W

20IO

_L15

N_T

2_D

QS_

13U

20IO

_L15

P_T2

_DQ

S_13

T20

IO_L

14N

_T2_

SRC

C_1

3Y

21IO

_L14

P_T2

_SR

CC

_13

W21

IO_L

13N

_T2_

MR

CC

_13

V21

IO_L

13P_

T2_M

RC

C_1

3U

21IO

_L12

N_T

1_M

RC

C_1

3V

22IO

_L12

P_T1

_MR

CC

_13

U22

IO_L

11N

_T1_

SRC

C_1

3Y

23IO

_L11

P_T1

_SR

CC

_13

Y22

IO_L

10N

_T1_

13W

23IO

_L10

P_T1

_13

V23

IO_L

9N_T

1_D

QS_

13A

C24

IO_L

9P_T

1_D

QS_

13A

B24

IO_L

8N_T

1_13

AA

23IO

_L8P

_T1_

13A

A22

IO_L

7N_T

1_13

AB

25IO

_L7P

_T1_

13A

A24

IO_L

6N_T

0_V

REF

_13

W24

IO_L

6P_T

0_13

V24

IO_L

5N_T

0_13

AA

25IO

_L5P

_T0_

13Y

25IO

_L4N

_T0_

13Y

26IO

_L4P

_T0_

13W

25IO

_L3N

_T0_

DQ

S_13

AC

26IO

_L3P

_T0_

DQ

S_13

AB

26IO

_L2N

_T0_

13W

26IO

_L2P

_T0_

13V

26IO

_L1N

_T0_

13U

26IO

_L1P

_T0_

13U

25IO

_0_1

3U

24

BANK 13

U10

A

XC

7A10

0T-3

FGG

676E

IO_2

5_14

R18

IO_L

24N

_T3_

A00

_D16

_14

R23

IO_L

24P_

T3_A

01_D

17_1

4T2

3IO

_L23

N_T

3_A

02_D

18_1

4R

22IO

_L23

P_T3

_A03

_D19

_14

T22

IO_L

22N

_T3_

A04

_D20

_14

P26

IO_L

22P_

T3_A

05_D

21_1

4R

26IO

_L21

N_T

3_D

QS_

A06

_D22

_14

T25

IO_L

21P_

T3_D

QS_

14T2

4IO

_L20

N_T

3_A

07_D

23_1

4M

26IO

_L20

P_T3

_A08

_D24

_14

N26

IO_L

19N

_T3_

A09

_D25

_VR

EF_1

4P2

5IO

_L19

P_T3

_A10

_D26

_14

R25

IO_L

18N

_T2_

A11

_D27

_14

R21

IO_L

18P_

T2_A

12_D

28_1

4R

20IO

_L17

N_T

2_A

13_D

29_1

4P2

4IO

_L17

P_T2

_A14

_D30

_14

P23

IO_L

16N

_T2_

A15

_D31

_14

N19

IO_L

16P_

T2_C

SI_B

_14

P19

IO_L

15N

_T2_

DQ

S_D

OU

T_C

SO_B

_14

N24

IO_L

15P_

T2_D

QS_

RD

WR

_B_1

4N

23IO

_L14

N_T

2_SR

CC

_14

P21

IO_L

14P_

T2_S

RC

C_1

4P2

0IO

_L13

N_T

2_M

RC

C_1

4N

22IO

_L13

P_T2

_MR

CC

_14

N21

IO_L

12N

_T1_

MR

CC

_14

M22

IO_L

12P_

T1_M

RC

C_1

4M

21IO

_L11

N_T

1_SR

CC

_14

L23

IO_L

11P_

T1_S

RC

C_1

4L2

2IO

_L10

N_T

1_D

15_1

4M

25IO

_L10

P_T1

_D14

_14

M24

IO_L

9N_T

1_D

QS_

D13

_14

L25

IO_L

9P_T

1_D

QS_

14L2

4IO

_L8N

_T1_

D12

_14

L20

IO_L

8P_T

1_D

11_1

4M

20IO

_L7N

_T1_

D10

_14

K26

IO_L

7P_T

1_D

09_1

4K

25IO

_L6N

_T0_

D08

_VR

EF_1

4N

18IO

_L6P

_T0_

FCS_

B_1

4P1

8IO

_L5N

_T0_

D07

_14

R17

IO_L

5P_T

0_D

06_1

4R

16IO

_L4N

_T0_

D05

_14

N17

IO_L

4P_T

0_D

04_1

4N

16IO

_L3N

_T0_

DQ

S_EM

CC

LK_1

4P1

6IO

_L3P

_T0_

DQ

S_PU

DC

_B_1

4P1

5IO

_L2N

_T0_

D03

_14

N14

IO_L

2P_T

0_D

02_1

4P1

4IO

_L1N

_T0_

D01

_DIN

_14

R15

IO_L

1P_T

0_D

00_M

OSI

_14

R14

IO_0

_14

M19

BANK 14

U10

B

XC

7A10

0T-3

FGG

676E

IO_2

5_15

L19

IO_L

24N

_T3_

RS0

_15

J26

IO_L

24P_

T3_R

S1_1

5J2

5IO

_L23

N_T

3_FW

E_B

_15

F25

IO_L

23P_

T3_F

OE_

B_1

5G

25IO

_L22

N_T

3_A

16_1

5G

26IO

_L22

P_T3

_A17

_15

H26

IO_L

21N

_T3_

DQ

S_A

18_1

5D

26IO

_L21

P_T3

_DQ

S_15

E26

IO_L

20N

_T3_

A19

_15

D25

IO_L

20P_

T3_A

20_1

5E2

5IO

_L19

N_T

3_A

21_V

REF

_15

F24

IO_L

19P_

T3_A

22_1

5G

24IO

_L18

N_T

2_A

23_1

5K

23IO

_L18

P_T2

_A24

_15

K22

IO_L

17N

_T2_

A25

_15

E23

IO_L

17P_

T2_A

26_1

5F2

3IO

_L16

N_T

2_A

27_1

5H

24IO

_L16

P_T2

_A28

_15

J24

IO_L

15N

_T2_

DQ

S_A

DV

_B_1

5F2

2IO

_L15

P_T2

_DQ

S_15

G22

IO_L

14N

_T2_

SRC

C_1

5H

23IO

_L14

P_T2

_SR

CC

_15

J23

IO_L

13N

_T2_

MR

CC

_15

H22

IO_L

13P_

T2_M

RC

C_1

5H

21IO

_L12

N_T

1_M

RC

C_1

5J2

1IO

_L12

P_T1

_MR

CC

_15

K21

IO_L

11N

_T1_

SRC

C_1

5G

21IO

_L11

P_T1

_SR

CC

_15

G20

IO_L

10N

_T1_

AD

11N

_15

H18

IO_L

10P_

T1_A

D11

P_15

J18

IO_L

9N_T

1_D

QS_

AD

3N_1

5J2

0IO

_L9P

_T1_

DQ

S_A

D3P

_15

K20

IO_L

8N_T

1_A

D10

N_1

5L1

8IO

_L8P

_T1_

AD

10P_

15L1

7IO

_L7N

_T1_

AD

2N_1

5H

19IO

_L7P

_T1_

AD

2P_1

5J1

9IO

_L6N

_T0_

VR

EF_1

5M

17IO

_L6P

_T0_

15M

16IO

_L5N

_T0_

AD

9N_1

5L1

5IO

_L5P

_T0_

AD

9P_1

5M

15IO

_L4N

_T0_

15L1

4IO

_L4P

_T0_

15M

14IO

_L3N

_T0_

DQ

S_A

D1N

_15

K17

IO_L

3P_T

0_D

QS_

AD

1P_1

5K

16IO

_L2N

_T0_

AD

8N_1

5J1

5IO

_L2P

_T0_

AD

8P_1

5J1

4IO

_L1N

_T0_

AD

0N_1

5J1

6IO

_L1P

_T0_

AD

0P_1

5K

15IO

_0_1

5K

18

BANK 15

U10

C

XC

7A10

0T-3

FGG

676E

IO_2

5_16

E22

IO_L

24N

_T3_

16D

24IO

_L24

P_T3

_16

D23

IO_L

23N

_T3_

16B

24IO

_L23

P_T3

_16

C24

IO_L

22N

_T3_

16B

26IO

_L22

P_T3

_16

C26

IO_L

21N

_T3_

DQ

S_16

A24

IO_L

21P_

T3_D

QS_

16A

23IO

_L20

N_T

3_16

A25

IO_L

20P_

T3_1

6B

25IO

_L19

N_T

3_V

REF

_16

C23

IO_L

19P_

T3_1

6C

22IO

_L18

N_T

2_16

D21

IO_L

18P_

T2_1

6E2

1IO

_L17

N_T

2_16

A22

IO_L

17P_

T2_1

6B

22IO

_L16

N_T

2_16

B21

IO_L

16P_

T2_1

6C

21IO

_L15

N_T

2_D

QS_

16A

20IO

_L15

P_T2

_DQ

S_16

B20

IO_L

14N

_T2_

SRC

C_1

6D

20IO

_L14

P_T2

_SR

CC

_16

E20

IO_L

13N

_T2_

MR

CC

_16

C19

IO_L

13P_

T2_M

RC

C_1

6D

19IO

_L12

N_T

1_M

RC

C_1

6C

18IO

_L12

P_T1

_MR

CC

_16

D18

IO_L

11N

_T1_

SRC

C_1

6E1

8IO

_L11

P_T1

_SR

CC

_16

E17

IO_L

10N

_T1_

16A

19IO

_L10

P_T1

_16

B19

IO_L

9N_T

1_D

QS_

16A

18IO

_L9P

_T1_

DQ

S_16

A17

IO_L

8N_T

1_16

D16

IO_L

8P_T

1_16

E16

IO_L

7N_T

1_16

B17

IO_L

7P_T

1_16

C17

IO_L

6N_T

0_V

REF

_16

G16

IO_L

6P_T

0_16

H16

IO_L

5N_T

0_16

F20

IO_L

5P_T

0_16

G19

IO_L

4N_T

0_16

F15

IO_L

4P_T

0_16

G15

IO_L

3N_T

0_D

QS_

16F1

9IO

_L3P

_T0_

DQ

S_16

F18

IO_L

2N_T

0_16

F17

IO_L

2P_T

0_16

G17

IO_L

1N_T

0_16

H15

IO_L

1P_T

0_16

H14

IO_0

_16

H17

BANK 16

U10

D

XC

7A10

0T-3

FGG

676E

IO_2

5_34

U4

IO_L

24N

_T3_

34T7

IO_L

24P_

T3_3

4T8

IO_L

23N

_T3_

34R

6IO

_L23

P_T3

_34

R7

IO_L

22N

_T3_

34P8

IO_L

22P_

T3_3

4R

8IO

_L21

N_T

3_D

QS_

34U

5IO

_L21

P_T3

_DQ

S_34

U6

IO_L

20N

_T3_

34R

5IO

_L20

P_T3

_34

T5IO

_L19

N_T

3_V

REF

_34

P5IO

_L19

P_T3

_34

P6IO

_L18

N_T

2_34

U1

IO_L

18P_

T2_3

4U

2IO

_L17

N_T

2_34

R2

IO_L

17P_

T2_3

4T2

IO_L

16N

_T2_

34T3

IO_L

16P_

T2_3

4T4

IO_L

15N

_T2_

DQ

S_34

P1IO

_L15

P_T2

_DQ

S_34

R1

IO_L

14N

_T2_

SRC

C_3

4N

4IO

_L14

P_T2

_SR

CC

_34

P4IO

_L13

N_T

2_M

RC

C_3

4P3

IO_L

13P_

T2_M

RC

C_3

4R

3IO

_L12

N_T

1_M

RC

C_3

4N

2IO

_L12

P_T1

_MR

CC

_34

N3

IO_L

11N

_T1_

SRC

C_3

4L2

IO_L

11P_

T1_S

RC

C_3

4M

2IO

_L10

N_T

1_34

H1

IO_L

10P_

T1_3

4H

2IO

_L9N

_T1_

DQ

S_34

M1

IO_L

9P_T

1_D

QS_

34N

1IO

_L8N

_T1_

34K

2IO

_L8P

_T1_

34L3

IO_L

7N_T

1_34

J1IO

_L7P

_T1_

34K

1IO

_L6N

_T0_

VR

EF_3

4M

5IO

_L6P

_T0_

34M

6IO

_L5N

_T0_

34N

6IO

_L5P

_T0_

34N

7IO

_L4N

_T0_

34K

5IO

_L4P

_T0_

34L5

IO_L

3N_T

0_D

QS_

34L4

IO_L

3P_T

0_D

QS_

34M

4IO

_L2N

_T0_

34L7

IO_L

2P_T

0_34

M7

IO_L

1N_T

0_34

J3IO

_L1P

_T0_

34K

3IO

_0_3

4N

8

BANK 34

U10

E

XC

7A10

0T-3

FGG

676E

IO_2

5_35

H3

IO_L

24N

_T3_

35G

1IO

_L24

P_T3

_35

G2

IO_L

23N

_T3_

35D

1IO

_L23

P_T3

_35

E1IO

_L22

N_T

3_35

E2IO

_L22

P_T3

_35

F2IO

_L21

N_T

3_D

QS_

35B

1IO

_L21

P_T3

_DQ

S_35

C1

IO_L

20N

_T3_

35A

2IO

_L20

P_T3

_35

A3

IO_L

19N

_T3_

VR

EF_3

5B

2IO

_L19

P_T3

_35

C2

IO_L

18N

_T2_

35E3

IO_L

18P_

T2_3

5F3

IO_L

17N

_T2_

35C

3IO

_L17

P_T2

_35

D3

IO_L

16N

_T2_

35A

4IO

_L16

P_T2

_35

B4

IO_L

15N

_T2_

DQ

S_35

A5

IO_L

15P_

T2_D

QS_

35B

5IO

_L14

N_T

2_SR

CC

_35

C4

IO_L

14P_

T2_S

RC

C_3

5D

4IO

_L13

N_T

2_M

RC

C_3

5D

5IO

_L13

P_T2

_MR

CC

_35

E5IO

_L12

N_T

1_M

RC

C_3

5F5

IO_L

12P_

T1_M

RC

C_3

5G

5IO

_L11

N_T

1_SR

CC

_35

F4IO

_L11

P_T1

_SR

CC

_35

G4

IO_L

10N

_T1_

AD

15N

_35

K6

IO_L

10P_

T1_A

D15

P_35

K7

IO_L

9N_T

1_D

QS_

AD

7N_3

5H

4IO

_L9P

_T1_

DQ

S_A

D7P

_35

J4IO

_L8N

_T1_

AD

14N

_35

K8

IO_L

8P_T

1_A

D14

P_35

L8IO

_L7N

_T1_

AD

6N_3

5J5

IO_L

7P_T

1_A

D6P

_35

J6IO

_L6N

_T0_

VR

EF_3

5G

9IO

_L6P

_T0_

35H

9IO

_L5N

_T0_

AD

13N

_35

G6

IO_L

5P_T

0_A

D13

P_35

H6

IO_L

4N_T

0_35

F7IO

_L4P

_T0_

35F8

IO_L

3N_T

0_D

QS_

AD

5N_3

5G

7IO

_L3P

_T0_

DQ

S_A

D5P

_35

H7

IO_L

2N_T

0_A

D12

N_3

5G

8IO

_L2P

_T0_

AD

12P_

35H

8IO

_L1N

_T0_

AD

4N_3

5D

6IO

_L1P

_T0_

AD

4P_3

5E6

IO_0

_35

J8

BANK 35

U10

F

XC

7A10

0T-3

FGG

676E

DX

N_0

R11

DX

P_0

R12

VR

EFN

_0N

11V

REF

P_0

P12

VN

_0P1

1V

P_0

N12

CFG

BV

S_0

AB

15PR

OG

RA

M_B

_0A

E16

INIT

_B_0

V11

DO

NE_

0W

10

M2_

0W

9M

1_0

Y9

M0_

0A

B7

CC

LK_0

H13

TMS_

0H

11TC

K_0

H12

TDO

_0J1

0TD

I_0

H10

U10

G

XC

7A10

0T-3

FGG

676E

MG

TPTX

N3_

216

C10

MG

TPTX

P3_2

16D

10M

GTP

TXN

2_21

6A

9M

GTP

TXP2

_216

B9

MG

TPTX

N1_

216

C8

MG

TPTX

P1_2

16D

8M

GTP

TXN

0_21

6A

7M

GTP

TXP0

_216

B7

MG

TPR

XN

3_21

6C

12M

GTP

RX

P3_2

16D

12M

GTP

RX

N2_

216

A13

MG

TPR

XP2

_216

B13

MG

TPR

XN

1_21

6C

14M

GTP

RX

P1_2

16D

14M

GTP

RX

N0_

216

A11

MG

TPR

XP0

_216

B11

MG

TRR

EF_2

16A

15

MG

TREF

CLK

1N_2

16E1

3M

GTR

EFC

LK1P

_216

F13

MG

TREF

CLK

0N_2

16E1

1M

GTR

EFC

LK0P

_216

F11

MG

TPTX

N3_

213

AF7

MG

TPTX

P3_2

13A

E7M

GTP

TXN

2_21

3A

D8

MG

TPTX

P2_2

13A

C8

MG

TPTX

N0_

213

AD

10M

GTP

TXP0

_213

AC

10

MG

TPTX

N1_

213

AF9

MG

TPTX

P1_2

13A

E9

MG

TPR

XN

3_21

3A

F11

MG

TPR

XP3

_213

AE1

1M

GTP

RX

N2_

213

AD

14M

GTP

RX

P2_2

13A

C14

MG

TPR

XN

1_21

3A

F13

MG

TPR

XP1

_213

AE1

3M

GTP

RX

N0_

213

AD

12M

GTP

RX

P0_2

13A

C12

MG

TRR

EF_2

13A

F15

MG

TREF

CLK

1N_2

13A

B11

MG

TREF

CLK

1P_2

13A

A11

MG

TREF

CLK

0N_2

13A

B13

MG

TREF

CLK

0P_2

13A

A13

U10

H

XC

7A10

0T-3

FGG

676E

MG

TAV

TT_G

11C

7

MG

TAV

TT_G

11C

15

MG

TAV

TT_G

11B

8

MG

TAV

TT_G

11B

14M

GTA

VTT

_G11

B12

MG

TAV

TT_G

11B

10

MG

TAV

TT_G

10A

E8

MG

TAV

TT_G

10A

E14

MG

TAV

TT_G

10A

E12

MG

TAV

TT_G

10A

E10

MG

TAV

TT_G

10A

D7

MG

TAV

TT_G

10A

D15

MG

TAV

CC

_G11

F12

MG

TAV

CC

_G11

F10

MG

TAV

CC

_G11

D9

MG

TAV

CC

_G11

D13

MG

TAV

CC

_G11

D11

MG

TAV

CC

_G10

AC

9

MG

TAV

CC

_G10

AC

13M

GTA

VC

C_G

10A

C11

MG

TAV

CC

_G10

AA

12M

GTA

VC

C_G

10A

A10

U10

I

XC

7A10

0T-3

FGG

676E

VC

CO

_35

J7V

CC

O_3

5G

3V

CC

O_3

5F6

VC

CO

_35

D2

VC

CO

_35

C5

VC

CO

_35

A1

VC

CO

_34

T6V

CC

O_3

4P2

VC

CO

_34

N5

VC

CO

_34

M8

VC

CO

_34

L1V

CC

O_3

4K

4

VC

CO

_33

Y4

VC

CO

_33

W7

VC

CO

_33

U3

VC

CO

_33

AD

2V

CC

O_3

3A

C5

VC

CO

_33

AA

1

VC

CO

_16

F16

VC

CO

_16

E19

VC

CO

_16

D22

VC

CO

_16

C25

VC

CO

_16

B18

VC

CO

_16

A21

VC

CO

_15

M18

VC

CO

_15

K14

VC

CO

_15

J17

VC

CO

_15

H20

VC

CO

_15

G23

VC

CO

_15

F26

VC

CO

_14

R19

VC

CO

_14

P22

VC

CO

_14

N25

VC

CO

_14

N15

VC

CO

_14

L21

VC

CO

_14

K24

VC

CO

_13

Y24

VC

CO

_13

V20

VC

CO

_13

U23

VC

CO

_13

T26

VC

CO

_13

T16

VC

CO

_13

AC

25

VC

CO

_12

W17

VC

CO

_12

AF2

6V

CC

O_1

2A

E19

VC

CO

_12

AD

22V

CC

O_1

2A

B18

VC

CO

_12

AA

21

VC

CO

_0W

11V

CC

O_0

Y14

U10

J

XC

7A10

0T-3

FGG

676E

VC

CB

RA

MW

13

VC

CB

RA

MU

13V

CC

BR

AM

R13

VC

CB

RA

MN

13

VC

CA

UX

J9

VC

CA

UX

U9

VC

CA

UX

R9

VC

CA

UX

N9

VC

CA

UX

L9

VC

CIN

TV

12V

CC

INT

V10

VC

CIN

TU

11V

CC

INT

T12

VC

CIN

TT1

0V

CC

INT

P10

VC

CIN

TM

10V

CC

INT

L13

VC

CIN

TL1

1V

CC

INT

K12

VC

CIN

TK

10V

CC

INT

J13

VC

CIN

TJ1

1

VC

CA

DC

_0M

12V

CC

BA

TT_0

G14

U10

K

XC

7A10

0T-3

FGG

676E

GN

DV

13

GN

DY

19G

ND

Y13

GN

DY

10

GN

DY

11G

ND

W22

GN

DW

2

GN

DW

12

GN

DE1

5

GN

DV

5

GN

DV

25G

ND

V15

GN

DU

8

GN

DU

18G

ND

U12

GN

DU

10

GN

DT9

GN

DT2

1G

ND

T13

GN

DT1

1G

ND

T1

GN

DR

4

GN

DR

24G

ND

R10

GN

DP9

GN

DP7

GN

DP1

7G

ND

P13

GN

DN

20G

ND

N10

GN

DM

9G

ND

M3

GN

DM

23G

ND

M13

GN

DL6

GN

DL2

6G

ND

L16

GN

DL1

2G

ND

L10

GN

DK

9

GN

DK

19G

ND

K13

GN

DK

11G

ND

J22

GN

DJ2

GN

DJ1

2

GN

DH

5G

ND

H25

GN

DG

12

GN

DG

18

GN

DY

12

GN

DG

13

GN

DA

B9

GN

DG

11G

ND

G10

GN

DF9

GN

DF2

1G

ND

F14

GN

DF1

GN

DE9

GN

DE8

GN

DE7

GN

DE4

GN

DE2

4

GN

DE1

4G

ND

E12

GN

DE1

0

GN

DD

7

GN

DD

17G

ND

D15

GN

DC

9G

ND

C6

GN

DC

20G

ND

C16

GN

DC

13G

ND

C11

GN

DB

6G

ND

B3

GN

DB

23G

ND

B16

GN

DA

F8G

ND

AF6

GN

DA

F21

GN

DA

F16

GN

DA

F14

GN

DA

F12

GN

DA

F10

GN

DA

F1

GN

DA

E6G

ND

AE4

GN

DA

E24

GN

DA

D16

GN

DA

D9

GN

DA

D6

GN

DA

D13

GN

DA

D11

GN

DA

C7

GN

DA

C20

GN

DA

C15

GN

DA

B8

GN

DA

A9

GN

DA

B3

GN

DA

B23

GN

DA

B14

GN

DA

B12

GN

DA

B10

GN

DA

A6

GN

DA

A26

GN

DA

A16

GN

DA

A14

GN

DA

8G

ND

A6

GN

DA

26G

ND

A16

GN

DA

14G

ND

A12

GN

DA

10

GN

DB

15

GN

DA

E15

GN

DA

DC

_0M

11

U10

L

XC

7A10

0T-3

FGG

676E

NC

Y8

NC

Y7

NC

Y6

NC

Y5

NC

Y3

NC

Y2

NC

Y18

NC

Y17

NC

Y16

NC

Y15

NC

Y1

NC

W8

NC

W6

NC

W5

NC

W4

NC

W3

NC

W16

NC

W15

NC

W14

NC

W1

NC

V9

NC

V8

NC

V7

NC

V6

NC

V4

NC

V3

NC

V2

NC

V1

NC

U7

NC

AF5

NC

AF4

NC

AF3

NC

AF2

5

NC

AF2

4

NC

AF2

3

NC

AF2

2

NC

AF2

0

NC

AF2

NC

AF1

9

NC

AF1

8

NC

AF1

7

NC

AE5

NC

AE3

NC

AE2

6

NC

AE2

5

NC

AE2

3

NC

AE2

2

NC

AE2

1

NC

AE2

0

NC

AE2

NC

AE1

8

NC

AE1

7

NC

AE1

NC

AD

5N

CA

D4

NC

AD

3

NC

AD

26N

CA

D25

NC

AD

24N

CA

D23

NC

AD

21N

CA

D20

NC

AD

19N

CA

D18

NC

AD

17

NC

AD

1

NC

AC

6

NC

AC

4

NC

AC

3

NC

AC

23

NC

AC

22

NC

AC

21

NC

AC

2

NC

AC

19

NC

AC

18

NC

AC

17

NC

AC

16

NC

AC

1

NC

AB

6

NC

AB

5

NC

AB

4

NC

AB

22

NC

AB

21

NC

AB

20

NC

AB

2

NC

AB

19

NC

AB

17

NC

AB

16

NC

AB

1

NC

AA

8

NC

AA

7

NC

AA

5

NC

AA

4

NC

AA

3

NC

AA

20

NC

AA

2

NC

AA

19

NC

AA

18

NC

AA

17

NC

AA

15

U10

M

XC

7A10

0T-3

FGG

676E

EXTR

A_S

FP_1

1_FB

_PEX

TRA

_SFP

_11_

FB_N

EXTR

A_S

FP_1

1_FB

_PEX

TRA

_SFP

_11_

FB_N

TRIG

DEL

AY

ED_2

TOB

EDEL

AY

ED_2

LE_E

XT_

DEL

_8LE

_EX

T_D

EL_7

LE_E

XT_

DEL

_6

LE_E

XT_

DEL

_5LE

_EX

T_D

EL_4

LE_E

XT_

DEL

_3LE

_EX

T_D

EL_2

LE_E

XT_

DEL

TX_F

AU

LT_S

FP_1

1TX

_FA

ULT

_TO

BED

ELA

YED

TX_D

ISA

BLE

_TO

BED

ELA

YED

TX_D

ISA

BLE

_SFP

_11

LOS_

TRIG

DEL

AY

ED

LOS_

SFP_

11

TRIG

DEL

AY

ED_D

IF_P

TRIG

DEL

AY

ED_D

IF_N

TRIG

DEL

AY

ED_D

IF_P

TRIG

DEL

AY

ED_D

IF_NEX

TRA

_19_

PEX

TRA

_19_

NEX

TRA

_19_

PEX

TRA

_19_

N

EXTR

A_1

8_P

EXTR

A_1

8_N

EXTR

A_1

8_P

EXTR

A_1

8_N

EXTR

A_1

7_P

EXTR

A_1

7_N

EXTR

A_1

7_P

EXTR

A_1

7_N

EXTR

A_1

6_P

EXTR

A_1

6_N

EXTR

A_1

6_P

EXTR

A_1

6_N

EXTR

A_1

5_P

EXTR

A_1

5_N

EXTR

A_1

5_P

EXTR

A_1

5_N

EXTR

A_1

4_P

EXTR

A_1

4_N

EXTR

A_1

4_P

EXTR

A_1

4_N

EXTR

A_1

3_P

EXTR

A_1

3_N

EXTR

A_1

3_P

EXTR

A_1

3_N

EXTR

A_1

2_P

EXTR

A_1

2_N

EXTR

A_1

2_P

EXTR

A_1

2_N

EXTR

A_1

1_P

EXTR

A_1

1_N

EXTR

A_1

1_P

EXTR

A_1

1_N

EXTR

A_1

0_P

EXTR

A_1

0_N

EXTR

A_1

0_P

EXTR

A_1

0_N

EXTR

A_9

_PEX

TRA

_9_N

EXTR

A_9

_PEX

TRA

_9_N

EXTR

A_8

_PEX

TRA

_8_N

EXTR

A_8

_PEX

TRA

_8_N

EXTR

A_7

_PEX

TRA

_7_N

EXTR

A_7

_PEX

TRA

_7_N

EXTR

A_6

_PEX

TRA

_6_N

EXTR

A_6

_PEX

TRA

_6_N

EXTR

A_5

_PEX

TRA

_5_N

EXTR

A_5

_PEX

TRA

_5_N

EXTR

A_4

_PEX

TRA

_4_N

EXTR

A_4

_PEX

TRA

_4_N

EXTR

A_3

_PEX

TRA

_3_N

EXTR

A_3

_PEX

TRA

_3_N

EXTR

A_2

_PEX

TRA

_2_N

EXTR

A_2

_PEX

TRA

_2_N

EXTR

A_1

_PEX

TRA

_1_N

EXTR

A_1

_PEX

TRA

_1_N

EXTR

A_0

_PEX

TRA

_0_N

EXTR

A_0

_PEX

TRA

_0_N

TOB

EDEL

AY

ED_D

IF_P

TOB

EDEL

AY

ED_D

IF_N

TOB

EDEL

AY

ED_D

IF_P

TOB

EDEL

AY

ED_D

IF_N

GN

DG

ND

GN

D

GN

D

+2.5

V

+3.3

V

+1.8

V

GN

D

GN

D

100

R21

Res

3

100

R22

Res

3

GN

D

GN

D

4.7u

F

C51

Cap

Sem

i4.

7uF

C50

Cap

Sem

i

4.7u

F

C48

Cap

Sem

i

4.7u

F

C49

Cap

Sem

i

GN

DG

ND

GN

D

Luis

A. T

ejed

or

SPI_

MO

SI_D

IN

CA

BLE

_DET

ECT

TX_D

ISA

BLE

_0

CO

NFI

G_C

CLK

FD1

Fidu

cial

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

LOS_

0LO

S_1

LOS_

2LO

S_3

LOS_

4LO

S_5

LOS_

6

LOS_

7

LOS_

TRIG

DEL

AY

EDLO

S_C

ALI

BLO

S_SF

P_11

LOS_

PED

ESTA

L

TX_F

AU

LT_0

TX_F

AU

LT_1

TX_F

AU

LT_2

TX_F

AU

LT_3

TX_F

AU

LT_4

TX_F

AU

LT_5

TX_F

AU

LT_6

TX_F

AU

LT_7

TX_F

AU

LT_C

ALI

BTX

_FA

ULT

_PED

ESTA

LTX

_FA

ULT

_SFP

_11

TX_F

AU

LT_T

OB

EDEL

AY

ED

TX_D

ISA

BLE

_0TX

_DIS

AB

LE_1

TX_D

ISA

BLE

_2TX

_DIS

AB

LE_3

TX_D

ISA

BLE

_4

TX_D

ISA

BLE

_5TX

_DIS

AB

LE_6

TX_D

ISA

BLE

_SFP

_11

TX_D

ISA

BLE

_PED

ESTA

LTX

_DIS

AB

LE_C

ALI

BTX

_DIS

AB

LE_7

TX_D

ISA

BLE

_TO

BED

ELA

YED

VP_

0 an

d V

N_0

are

the

anal

og in

puts

to th

e X

AD

C.

Con

nect

to G

ND

whe

n no

t us

ed.

VR

EF_P

and

N a

re v

olta

ge

refe

renc

e in

puts.

C

onne

ct to

GN

D w

hen

an

exte

rnal

refe

renc

e is

not

pres

ent.

See

UG

480.

DX

P_0

and

DX

N_0

are

the

ports

of t

he te

mpe

ratu

re

sens

or

Inde

pend

ent p

ower

supp

lies

reco

mm

ende

d fo

r tra

nsce

iver

s.

Tran

scei

ver p

ads:

If re

fere

nce

cloc

k in

put i

s not

use

d,

leav

e th

e as

soci

ated

pin

pai

r un

conn

ecte

d.If

a tra

nsm

itter

is n

ot u

sed,

leav

e th

e as

soci

ated

pin

pai

r unc

onne

cted

. If

a re

ceiv

er is

not

use

d, c

onne

ct th

e as

soci

ated

pin

pai

r to

grou

nd.

If tra

nsce

iver

s are

not

in u

se a

t all:

MG

TAV

CC

-->

GN

DM

GTA

VTT

-->

GN

DM

GTR

REF

-->

GN

DSe

e ug

476_

7Ser

ies_

Tran

scei

vers

.pdf

or

ug

482_

7Ser

ies_

GTP

_tra

nsce

iver

s.pdf

fo

r mor

e in

form

atio

n.

PIC4801

PIC4802COC4

8

PIC490

1PIC4902COC4

9 PIC5

001

PIC5002COC5

0

PIC5101PIC5102CO

C51

COFD

1

PIR2101

PIR2

102

COR2

1

PIR2201

PIR2

202

COR2

2PIR2301 PIR2302CO

R23

PIR2401 PIR2402

COR24

PIR2501 PIR2502COR25

PIR2601 PIR2602COR2

6

PIU100AA22

PIU100AA23

PIU1

00AA

24

PIU100AA25

PIU100AB24

PIU100AB25

PIU1

00AB

26

PIU1

00AC

24

PIU100AC26

PIU100T14

PIU1

00T1

5PIU100T17

PIU100T18

PIU100T19

PIU100T20

PIU1

00U1

4

PIU1

00U1

5PIU100U16

PIU1

00U1

7

PIU1

00U1

9

PIU1

00U2

0

PIU100U21

PIU100U22

PIU100U24

PIU1

00U2

5PIU100U26

PIU100V14

PIU1

00V1

6PIU100V17

PIU100V18

PIU100V19

PIU1

00V2

1

PIU1

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8

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3

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5

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0

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1

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3

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5

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9

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7

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1PIU100N22

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6

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9

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6

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5

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7

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2

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3

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4

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6

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6

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4

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6

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1

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9

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0

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2

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1PIU100B22

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8

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9

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3

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4

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6

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6

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8

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PIU100L3

PIU100L4

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PIU100L7

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PIU100M2

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PIU100M6

PIU100M7

PIU100N1

PIU100N2

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PIU100N4

PIU100N6

PIU100N7

PIU100N8

PIU100P1

PIU100P3

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PIU100P6

PIU100P8

PIU100R1

PIU100R2

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PIU100R8

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PIU100T3

PIU100T4

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PIU100T7

PIU100T8

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PIU100U2

PIU100U4

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00C1

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00C3

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00C4

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PIU100D3

PIU100D4

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00D5

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00E1

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00E3

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00E6

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00F4

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00G2

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PIU100G5

PIU100G6

PIU100G7

PIU100G8

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PIU1

00H3

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00H4

PIU1

00H6

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00H7

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00H8

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00H9

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PIU100J5

PIU100J6

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00K6

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00K8

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COU1

0F

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7

PIU1

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15

PIU100AE16

PIU100H10

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00H1

1

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00H1

3

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0

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00N1

1

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2PIU100P11

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2

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00W9

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0

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PIU100A9

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1

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3

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PIU100AA13

PIU100AB11

PIU100AB13

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8

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PIU100AC14

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00AE

7

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9

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PIU100AE13

PIU100AF7

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3

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PIU100AC9

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PIU100AD7

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00B1

2PIU100B14

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7

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8

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3

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0

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4

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COU10J

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3PIU100K10

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2

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3

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PIU100A8

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00A1

2PIU100A14

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6PIU100A26

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6

PIU1

00AA

9PIU100AA14

PIU100AA16

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PIU1

00AB

3PIU100AB8

PIU1

00AB

9PIU100AB10

PIU100AB12

PIU100AB14

PIU100AB23

PIU100AC7

PIU100AC15

PIU100AC20

PIU1

00AD

6PIU100AD9

PIU100AD11

PIU100AD13

PIU100AD16

PIU100AE4

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6PIU100AE15

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PIU1

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6PIU100AF8

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PIU100AF14

PIU100AF16

PIU100AF21

PIU100B3

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00B1

5PIU100B16

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00B2

3PIU100C6

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0PIU100D7

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4

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8PIU100H5

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2PIU100U18

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5PIU100V25

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2

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4

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7

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PIU1

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2

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5

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PIU100AB16

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PIU100AC1

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2

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4

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PIU100AC18

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3

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5

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1

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2

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5

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5

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PIU100V1

PIU100V2

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PIU100V4

PIU100V6

PIU100V7

PIU100V8

PIU100V9

PIU100W1

PIU100W3

PIU100W4

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PIU100W6

PIU100W8

PIU100W14

PIU1

00W1

5

PIU100W16

PIU100Y1

PIU100Y2

PIU100Y3

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PIU1

00Y1

6

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7

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00L9

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3PIU100K10

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0

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0PIU100T12

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2

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3

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PIU1

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25

PIU1

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22PIU100AE19

PIU1

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26

PIU1

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8

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00C5

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00D2

2PIU100E19

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00F6

PIU1

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6

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PIU1

00J7

PIU1

00K4

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PIU1

00M8

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PIU1

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PIU1

00T1

6PIU100T26

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3

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0

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PIU100Y24

PIR2301

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7

PIU1

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15

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2

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3PIU100H20

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7PIU100K14

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4PIU100L21

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8

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5PIU100N25

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2PIU100R19

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PIU1

00W9

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PIU1

00Y4

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PIU1

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4

PIU100N4

NLAR

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NPOARRAYTRIG0N

PIU100P4

NLARRAYTRIG0PPOARRAYTRIG0P

PIU100U26

NLCALIB0FB0N

POCALIB0FB0N

PIU1

00U2

5NLCALIB0FB0P

POCALIB0FB0P

PIU1

00C4

NLCA

LIB0

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PIU100D4

NLCA

LIB0

PPOCALIB0P

PIU1

00V2

1NL

CLK0

10MH

Z0N

POCLK010MHZ0N

PIU100U21

NLCLK010MHZ0P

POCLK010MHZ0P

PIU100J3

NLEXTRA000N

POEXTRA000N

PIU100K3

NLEXTRA000P

POEXTRA000P

PIU100L4

NLEXTRA010N

POEXTRA010N

PIU100M4

NLEXTRA010P

POEXTRA010P

PIU100J1

NLEXTRA020N

POEXTRA020N

PIU100K1

NLEXTRA020P

POEXTRA020P

PIU100K2

NLEXTRA030N

POEXTRA030N

PIU100L3

NLEXTRA030P

POEXTRA030P

PIU100M1

NLEXTRA040N

POEXTRA040N

PIU100N1

NLEXTRA040P

POEXTRA040P

PIU100H1

NLEXTRA050N

POEXTRA050N

PIU100H2

NLEXTRA050P

POEXTRA050P

PIU100P1

NLEXTRA060N

POEXTRA060N

PIU100R1

NLEXTRA060P

POEXTRA060P

PIU100T3

NLEXTRA070N

POEXTRA070N

PIU100T4

NLEXTRA070P

POEXTRA070P

PIU100R2

NLEXTRA080N

POEXTRA080N

PIU100T2

NLEXTRA080P

POEXTRA080P

PIU100U1

NLEXTRA090N

POEXTRA090N

PIU100U2

NLEXTRA090P

POEXTRA090P

PIU1

00A2

0NLEXTRA0100N

POEXTRA0100N

PIU100B20

NLEX

TRA0

100P

POEXTRA0100P

PIU1

00B2

1NLEXTRA0110N

POEXTRA0110N

PIU100C21

NLEX

TRA0

110P

POEXTRA0110P

PIU1

00A2

2NLEXTRA0120N

POEXTRA0120N

PIU100B22

NLEX

TRA0

120P

POEXTRA0120P

PIU1

00D2

1NLEXTRA0130N

POEXTRA0130N

PIU100E21

NLEX

TRA0

130P

POEXTRA0130P

PIU100A25

NLEXTRA0140N

POEXTRA0140N

PIU100B25

NLEX

TRA0

140P

POEXTRA0140P

PIU100A24

NLEXTRA0150N

POEXTRA0150N

PIU1

00A2

3NL

EXTR

A015

0PPOEXTRA0150P

PIU100B26

NLEXTRA0160N

POEXTRA0160N

PIU1

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6NL

EXTR

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0PPOEXTRA0160P

PIU100B24

NLEXTRA0170N

POEXTRA0170N

PIU1

00C2

4NL

EXTR

A017

0PPOEXTRA0170P

PIU100D24

NLEXTRA0180N

POEXTRA0180N

PIU1

00D2

3NL

EXTR

A018

0PPOEXTRA0180P

PIU1

00A1

8NLEXTRA0190N

POEXTRA0190N

PIU100A17

NLEXTRA0190P

POEXTRA0190P

PIU100Y26

NLEX

TRA0

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110F

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PIU1

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5NLEXTRA0SFP0110FB0PPOEXTRA0SFP0110FB0P

PIU100AC26

NLEXTRA0SFP0110N

POEXTRA0SFP0110N

PIU1

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26NLEXTRA0SFP0110P

POEXTRA0SFP0110P

PIC4801

PIC4802

PIC490

1PIC4902

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001

PIC5002

PIC5101PIC5102

PIR2

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PIR2

202

PIU100A6

PIU100A8

PIU100A10

PIU1

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1

PIU1

00A1

2

PIU1

00A1

3

PIU100A14

PIU1

00A1

6PIU100A26

PIU1

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6

PIU1

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9

PIU100AA10

PIU100AA12

PIU100AA14

PIU100AA16

PIU100AA26

PIU1

00AB

3PIU100AB8

PIU1

00AB

9PIU100AB10

PIU100AB12

PIU100AB14

PIU100AB23

PIU100AC7

PIU100AC9

PIU100AC11

PIU100AC12

PIU100AC13

PIU100AC14

PIU100AC15

PIU100AC20

PIU1

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6

PIU100AD7

PIU100AD9

PIU100AD11

PIU100AD12

PIU100AD13

PIU100AD14

PIU100AD15

PIU100AD16

PIU100AE4

PIU1

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6

PIU100AE8

PIU100AE10

PIU100AE11

PIU100AE12

PIU100AE13

PIU100AE14

PIU100AE15

PIU100AE24

PIU100AF1

PIU1

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6PIU100AF8

PIU100AF10

PIU100AF11

PIU100AF12

PIU100AF13

PIU100AF14

PIU100AF16

PIU100AF21

PIU100B3

PIU100B6

PIU100B8

PIU100B10

PIU1

00B1

1

PIU1

00B1

2

PIU100B13

PIU100B14

PIU1

00B1

5PIU100B16

PIU1

00B2

3PIU100C6

PIU100C7

PIU100C9

PIU100C11

PIU1

00C1

2

PIU1

00C1

3

PIU1

00C1

4

PIU100C15

PIU100C16

PIU1

00C2

0PIU100D7

PIU100D9

PIU100D11

PIU100D12

PIU1

00D1

3

PIU100D14

PIU1

00D1

5PIU100D17

PIU100E4

PIU100E7

PIU100E8

PIU100E9

PIU1

00E1

0PIU100E12

PIU1

00E1

4

PIU1

00E1

5PIU100E24

PIU100F1

PIU100F9

PIU100F10

PIU100F12

PIU1

00F1

4PIU100F21

PIU1

00G1

0PIU100G11

PIU1

00G1

2PIU100G13

PIU100G14

PIU1

00G1

8PIU100H5

PIU1

00H2

5PIU100J2

PIU1

00J1

2PIU100J22

PIU100K9

PIU100K11

PIU1

00K1

3PIU100K19

PIU100L6

PIU100L10

PIU1

00L1

2PIU100L16

PIU1

00L2

6PIU100M3

PIU100M9

PIU100M11

PIU100M13

PIU100M23

PIU1

00N1

0

PIU1

00N1

1

PIU1

00N1

2

PIU100N20

PIU100P7

PIU100P9

PIU100P11

PIU100P12

PIU1

00P1

3

PIU100P15

PIU100P17

PIU100R4

PIU100R10

PIU100R11

PIU1

00R1

2

PIU1

00R2

4PIU100T1

PIU100T9

PIU100T11

PIU1

00T1

3PIU100T21

PIU100U8

PIU100U10

PIU1

00U1

2PIU100U18

PIU100V5

PIU100V13

PIU1

00V1

5PIU100V25

PIU100W2

PIU100W12

PIU1

00W2

2PIU100Y10

PIU1

00Y1

1PIU100Y12

PIU1

00Y1

3PIU100Y19

PIU1

00F5

NLIN

PUT0

00N

POINPUT000N

PIU100G5

NLIN

PUT0

00P

POINPUT000P

PIU1

00D5

NLIN

PUT0

10N

POINPUT010N

PIU100E5

NLIN

PUT0

10P

POINPUT010P

PIU1

00V2

2NL

INPU

T020

NPOINPUT020N

PIU100U22

NLINPUT020P

POINPUT020P

PIU1

00C1

8NL

INPU

T030

NPOINPUT030N

PIU100D18

NLIN

PUT0

30P

POINPUT030P

PIU100P3

NLIN

PUT0

40N

POINPUT040N

PIU100R3

NLIN

PUT0

40P

POINPUT040P

PIU1

00Y2

3NL

INPU

T050

NPOINPUT050N

PIU100Y22

NLINPUT050P

POINPUT050P

PIU100N2

NLIN

PUT0

60N

POINPUT060N

PIU100N3

NLIN

PUT0

60P

POINPUT060P

PIU1

00D2

0NL

INPU

T070

NPOINPUT070N

PIU100E20

NLIN

PUT0

70P

POINPUT070P

PIU1

00C1

9NL

INPU

T080

NPOINPUT080N

PIU100D19

NLIN

PUT0

80P

POINPUT080P

PIU100H26

NLLO

S00

POLOS00

PIU1

00G2

6NL

LOS0

1POLOS01

PIU100G25

NLLO

S02

POLOS02

PIU1

00F2

5NL

LOS0

3POLOS03

PIU100J25

NLLO

S04

POLOS04

PIU1

00J2

6NL

LOS0

5POLOS05

PIU100L19

NLLO

S06

POLOS06

PIU100H24

NLLO

S07

POLOS07

PIU100H19

NLLOS0CALIB

POLOS0CALIB

PIU1

00K1

8NLLOS0PEDESTAL

POLOS0PEDESTAL

PIU100L17

NLLO

S0SF

P011

POLOS0SFP011

PIU100J19

NLLOS0TRIGDELAYED

POLOS0TRIGDELAYED

PIR2101

PIU100AF15

PIR2201

PIU100A15

PIR2302PI

U100

H13

POCONFIG0CCLK

PIR2402PI

U100

W10

PODONE

PIR2502

PIU100AE16

POPROGRAM0B

PIR2602PIU100V11

POINIT0B

PIU100A7

PIU100A9

PIU1

00A1

9

PIU1

00AA

2

PIU100AA3

PIU1

00AA

4

PIU100AA5

PIU1

00AA

7

PIU100AA8

PIU100AA11

PIU100AA13

PIU100AA15

PIU100AA17

PIU100AA18

PIU100AA19

PIU100AA20

PIU100AA22

PIU100AA23

PIU100AB1

PIU1

00AB

2

PIU100AB4

PIU1

00AB

5

PIU100AB6

PIU100AB11

PIU100AB13

PIU100AB16

PIU100AB17

PIU100AB19

PIU100AB20

PIU100AB21

PIU100AB22

PIU100AC1

PIU1

00AC

2

PIU100AC3

PIU1

00AC

4

PIU100AC6

PIU1

00AC

8

PIU100AC10

PIU100AC16

PIU100AC17

PIU100AC18

PIU100AC19

PIU100AC21

PIU100AC22

PIU100AC23

PIU100AD1

PIU1

00AD

3

PIU100AD4

PIU1

00AD

5

PIU100AD8

PIU100AD10

PIU100AD17

PIU100AD18

PIU100AD19

PIU100AD20

PIU100AD21

PIU100AD23

PIU100AD24

PIU100AD25

PIU100AD26

PIU1

00AE

1

PIU1

00AE

2

PIU100AE3

PIU1

00AE

5

PIU1

00AE

7

PIU1

00AE

9

PIU100AE17

PIU100AE18

PIU100AE20

PIU100AE21

PIU100AE22

PIU100AE23

PIU100AE25

PIU100AE26

PIU100AF2

PIU1

00AF

3

PIU100AF4

PIU1

00AF

5

PIU100AF7

PIU100AF9

PIU100AF17

PIU100AF18

PIU100AF19

PIU100AF20

PIU100AF22

PIU100AF23

PIU100AF24

PIU100AF25

PIU1

00B2

PIU100B7

PIU100B9

PIU100B17

PIU100B19

PIU100C2

PIU100C8

PIU1

00C1

0

PIU100C17

PIU100C22

PIU1

00C2

3

PIU100D6

PIU100D8

PIU100D10

PIU1

00D1

6

PIU100D25

POLE0EXT0DEL07

PIU1

00D2

6POLE0EXT0DEL09

PIU1

00E6

PIU1

00E1

1

PIU1

00E1

3

PIU100E16

PIU1

00E2

2

PIU100E23

POLE0EXT0DEL02

PIU1

00E2

5POLE0EXT0DEL06

PIU100E26

POLE0EXT0DEL08

PIU100F11

PIU100F13

PIU100F15

PIU100F17

PIU1

00F1

8PIU100F19

PIU100F20

PIU100F22

POTOBEDELAYED02

PIU1

00F2

3POLE0EXT0DEL

PIU100F24

PIU100G1

PIU1

00G2

PIU100G6

PIU100G7

PIU100G8

PIU100G9

PIU1

00G1

5

PIU100G16

PIU1

00G1

7

PIU1

00G1

9

PIU1

00G2

0POMISO0EXT0DEL

PIU100G21

POMOSI0EXT0DEL

PIU1

00G2

2POTOBEDELAYED

PIU1

00G2

4POLE0EXT0DEL05

PIU1

00H3

PIU1

00H4

PIU1

00H6

PIU1

00H7

PIU1

00H8

PIU1

00H9

PIU100H10

POTDI

PIU1

00H1

1POTMS

PIU100H12

POTCK

PIU1

00H1

4PIU100H15

PIU1

00H1

6

PIU100H17

PIU1

00H2

1POI2C0SCLK

PIU100H22

POI2C0SDA

PIU100H23

POTRIGDELAYED02

PIU100J4

PIU100J5

PIU100J6

PIU100J8

PIU1

00J1

0POTDO

PIU100J14

PIU1

00J1

5

PIU1

00J1

6

PIU100J21

PIU1

00J2

3POTRIGDELAYED

PIU1

00J2

4POREF0EXT0DEL

PIU100K5

PIU1

00K6

PIU100K7

PIU1

00K8

PIU100K15

PIU100K16

PIU1

00K1

7

PIU1

00K2

1POCLK0EXT0DEL

PIU1

00K2

2POLE0EXT0DEL03

PIU100K23

POLE0EXT0DEL04

PIU100L5

PIU100L7

PIU100L8

PIU1

00L1

4

PIU1

00L1

5

PIU100L20

PIU1

00L2

2PORESET

PIU100L23

POCLK0TH

PIU1

00L2

4POP1015

PIU100L25

POP1013

PIU100M5

PIU100M6

PIU100M7

PIU100M14

PIU100M15

PIU100M16

PIU1

00M1

7

PIU1

00M1

9

PIU100M20

PIU1

00M2

1POUART0TX

PIU100M22

POUART0RX

PIU1

00M2

4POP1011

PIU100M25

POP107

PIU100N6

PIU100N7

PIU100N8

PIU1

00N1

4

PIU100N16

PIU1

00N1

7

PIU1

00N1

8

PIU1

00N2

1POSPI0CCLK

PIU100N22

POSPI0MISO

PIU1

00N2

3POIO0TH

PIU100N24

POCS0TH

PIU100P5

PIU100P6

PIU100P8

PIU100P14

PIU1

00P1

6

PIU100P18

PIU1

00P2

0POSPI0CS00

PIU100P21

POSPI0CS01

PIU100P25

PIU1

00P2

6POCABLE0DETECT

PIU100R5

PIU100R6

PIU100R7

PIU100R8

PIU100R14

PIU1

00R1

5POSPI0MOSI0DIN

PIU100R16

PIU1

00R1

7

PIU100T5

PIU100T7

PIU100T8

PIU100T14

PIU1

00T1

5PIU100T17

PIU100T18

PIU100T19

PIU100T20

PIU100U4

PIU100U5

PIU100U6

PIU100U7

PIU1

00U1

4

PIU1

00U1

5PIU100U16

PIU1

00U1

7

PIU1

00U1

9

PIU1

00U2

0

PIU100U24

PIU100V1

PIU100V2

PIU100V3

PIU100V4

PIU100V6

PIU100V7

PIU100V8

PIU100V9

PIU100V14

PIU1

00V1

6PIU100V17

PIU100V18

PIU100V19

PIU100W1

PIU100W3

PIU100W4

PIU100W5

PIU100W6

PIU100W8

PIU100W14

PIU1

00W1

5

PIU100W16

PIU1

00W1

8

PIU1

00W1

9

PIU100W20

PIU100Y1

PIU100Y2

PIU100Y3

PIU100Y5

PIU100Y6

PIU100Y7

PIU100Y8

PIU100Y15

PIU1

00Y1

6

PIU1

00Y1

7

PIU100Y18

PIU1

00Y2

0PI

U100

A5NLOUTPUT000N

POOUTPUT000N

PIU100B5

NLOU

TPUT

000P

POOUTPUT000P

PIU1

00A4

NLOUTPUT010N

POOUTPUT010N

PIU100B4

NLOU

TPUT

010P

POOUTPUT010P

PIU1

00C3

NLOUTPUT020N

POOUTPUT020N

PIU100D3

NLOU

TPUT

020P

POOUTPUT020P

PIU1

00E3

NLOUTPUT030N

POOUTPUT030N

PIU100F3

NLOU

TPUT

030P

POOUTPUT030P

PIU100A2

NLOUTPUT040N

POOUTPUT040N

PIU100A3

NLOU

TPUT

040P

POOUTPUT040P

PIU100B1

NLOUTPUT050N

POOUTPUT050N

PIU1

00C1

NLOU

TPUT

050P

POOUTPUT050P

PIU100E2

NLOUTPUT060N

POOUTPUT060N

PIU1

00F2

NLOU

TPUT

060P

POOUTPUT060P

PIU100D1

NLOUTPUT070N

POOUTPUT070N

PIU1

00E1

NLOU

TPUT

070P

POOUTPUT070P

PIU100W26

NLPEDESTAL0FB0N

POPE

DEST

AL0F

B0N

PIU1

00V2

6NLPEDESTAL0FB0P

POPEDESTAL0FB0P

PIU100L2

NLPEDESTAL0N

POPEDESTAL0N

PIU100M2

NLPEDESTAL0P

POPEDESTAL0P

PIU1

00W2

3NL

SPAR

E010

NPOSPARE010N

PIU100V23

NLSPARE010P

POSPARE010P

PIU1

00F4

NLSTEREO0CB0N

POSTEREO0CB0N

PIU100G4

NLSTEREO0CB0P

POSTEREO0CB0P

PIU1

00Y2

1NL

STER

EO0M

WR0N

POSTEREO0MWR0N

PIU100W21

NLSTEREO0MWR0P

POSTEREO0MWR0P

PIU100F7

NLTOBEDELAYED0DIF0NPO

TOBEDE

LAYE

D0DI

F0N

PIU1

00F8

NLTOBEDELAYED0DIF0P

POTOBEDELAYED0DIF0P

PIU100W24

NLTR

GTYP

E00C

B0N

POTRGTYPE00CB0N

PIU1

00V2

4NLTRGTYPE00CB0P

POTRGTYPE00CB0P

PIU100AA25

NLTRGTYPE00MWR0N

POTRGTYPE00MWR0N

PIU1

00Y2

5NLTRGTYPE00MWR0P

POTRGTYPE00MWR0P

PIU1

00AC

24NL

TRGT

YPE1

0CB0

NPOTRGTYPE10CB0N

PIU100AB24

NLTRGTYPE10CB0P

POTRGTYPE10CB0P

PIU100AB25

NLTRGTYPE10MWR0N

POTRGTYPE10MWR0N

PIU1

00AA

24NLTRGTYPE10MWR0P

POTRGTYPE10MWR0P

PIU1

00E1

8NLTRIGDELAYED0DIF0NPOTRIGDELAYED0DIF0N

PIU100E17

NLTRIGDELAYED0DIF0P

POTR

IGDE

LAYE

D0DI

F0P

PIU100T22NLTX0DISABLE00

POTX0DISABLE00

PIU1

00R2

2NLTX

0DIS

ABLE

01POTX0DISABLE01

PIU100T23NLTX0DISABLE02

POTX0DISABLE02

PIU1

00R2

3NLTX

0DIS

ABLE

03POTX0DISABLE03

PIU100R18NLTX0DISABLE04

POTX0DISABLE04

PIU100K25NL

TX0D

ISAB

LE05

POTX0DISABLE05

PIU100K26NLTX0DISABLE06POTX0DISABLE06

PIU100H18

NLTX0DISABLE07

POTX0DISABLE07

PIU1

00J1

8NLTX0DISABLE0CALIB

POTX0DISABLE0CALIB

PIU100J20

NLTX0DISABLE0PEDESTAL

POTX0DISABLE0PEDESTAL

PIU1

00K2

0NL

TX0D

ISAB

LE0S

FP01

1POTX0DISABLE0SFP011

PIU100L18

NLTX0DISABLE0TOBEDELAYEDPOTX0DISABLE0TOBEDELAYED

PIU1

00P1

9NLTX0FAULT00POTX0FAULT00

PIU100N19NLTX0FAULT01POTX0FAULT01

PIU1

00P2


PIU100P24NLTX0FAULT03POTX0FAULT03

PIU1

00R2


PIU100R21NLTX0FAULT05POTX0FAULT05

PIU1

00R2


PIU1

00N2

6NLTX0FAULT07

POTX0FAULT07

PIU100M26NLTX0FAULT0CALIB

POTX0FAULT0CALIB

PIU100T24NLTX0FAULT0PEDESTALPOTX0FAULT0PEDESTAL

PIU1

00T2

5NLTX

0FAU

LT0S

FP01

1PO

TX0F

AULT

0SFP

011

PIU100R26NLTX0FAULT0TOBEDELAYED

POTX0FAULT0TOBEDELAYED

POARRAYTRIG0N

POARRAYTRIG0P

POCABLE0DETECT

POCALIB0FB0N

POCALIB0FB0P

POCALIB0N

POCALIB0P

POCLK010MHZ0N

POCLK010MHZ0P

POCLK0EXT0DEL

POCLK0TH

POCONFIG0CCLK

POCS0TH

PODONE

POEXTRA000N

POEXTRA000P

POEXTRA010N

POEXTRA010P

POEXTRA020N

POEXTRA020P

POEXTRA030N

POEXTRA030P

POEXTRA040N

POEXTRA040P

POEXTRA050N

POEXTRA050P

POEXTRA060N

POEXTRA060P

POEXTRA070N

POEXTRA070P

POEXTRA080N

POEXTRA080P

POEXTRA090N

POEXTRA090P

POEXTRA0100N

POEXTRA0100P

POEXTRA0110N

POEXTRA0110P

POEXTRA0120N

POEXTRA0120P

POEXTRA0130N

POEXTRA0130P

POEXTRA0140N

POEXTRA0140P

POEXTRA0150N

POEXTRA0150P

POEXTRA0160N

POEXTRA0160P

POEXTRA0170N

POEXTRA0170P

POEXTRA0180N

POEXTRA0180P

POEXTRA0190N

POEXTRA0190P

POEXTRA0SFP0110FB0N

POEXTRA0SFP0110FB0P

POEXTRA0SFP0110N

POEXTRA0SFP0110P

POI2C0SCLK

POI2C0SDA

POINIT0B

POINPUT000N

POINPUT000P

POINPUT010N

POINPUT010P

POINPUT020N

POINPUT020P

POINPUT030N

POINPUT030P

POINPUT040N

POINPUT040P

POINPUT050N

POINPUT050P

POINPUT060N

POINPUT060P

POINPUT070N

POINPUT070P

POINPUT080N

POINPUT080P

POIO0TH

POLE0EXT0DEL

POLE0EXT0DEL02

POLE0EXT0DEL03

POLE0EXT0DEL04

POLE0EXT0DEL05

POLE0EXT0DEL06

POLE0EXT0DEL07

POLE0EXT0DEL08

POLE0EXT0DEL09

POLOS00

POLOS01

POLOS02

POLOS03

POLOS04

POLOS05

POLOS06

POLOS07

POLOS0CALIB

POLOS0PEDESTAL

POLOS0SFP011

POLOS0TRIGDELAYED

POMISO0EXT0DEL

POMOSI0EXT0DEL

POOUTPUT000N

POOUTPUT000P

POOUTPUT010N

POOUTPUT010P

POOUTPUT020N

POOUTPUT020P

POOUTPUT030N

POOUTPUT030P

POOUTPUT040N

POOUTPUT040P

POOUTPUT050N

POOUTPUT050P

POOUTPUT060N

POOUTPUT060P

POOUTPUT070N

POOUTPUT070P

POP107

POP1011

POP1013

POP1015

POPE

DEST

AL0F

B0N

POPEDESTAL0FB0P

POPEDESTAL0N

POPEDESTAL0P

POPROGRAM0B

POREF0EXT0DEL

PORESET

POSPARE010N

POSPARE010P

POSPI0CCLK

POSPI0CS00

POSPI0CS01

POSPI0MISO

POSPI0MOSI0DIN

POSTEREO0CB0N

POSTEREO0CB0P

POSTEREO0MWR0N

POSTEREO0MWR0P

POTCK

POTDI

POTDO

POTMS

POTOBEDELAYED

POTOBEDELAYED02

POTO

BEDE

LAYE

D0DI

F0N

POTOBEDELAYED0DIF0P

POTRGTYPE00CB0N

POTRGTYPE00CB0P

POTRGTYPE00MWR0N

POTRGTYPE00MWR0P

POTRGTYPE10CB0N

POTRGTYPE10CB0P

POTRGTYPE10MWR0N

POTRGTYPE10MWR0P

POTRIGDELAYED

POTRIGDELAYED02

POTRIGDELAYED0DIF0N

POTR

IGDE

LAYE

D0DI

F0P

POTX0DISABLE00

POTX0DISABLE01

POTX0DISABLE02

POTX0DISABLE03

POTX0DISABLE04

POTX0DISABLE05

POTX0DISABLE06

POTX0DISABLE07

POTX0DISABLE0CALIB


POTX0DISABLE0SFP011

POTX0DISABLE0TOBEDELAYED

POTX0FAULT00

POTX0FAULT01

POTX0FAULT02

POTX0FAULT03

POTX0FAULT04

POTX0FAULT05

POTX0FAULT06

POTX0FAULT07

POTX0FAULT0CALIB

POTX0FAULT0PEDESTAL

POTX

0FAU

LT0S

FP01

1POTX0FAULT0TOBEDELAYED

POUART0RX

POUART0TX

Figure A.14: TIB: FPGA pins

A. Schematics 225

11

22

33

44

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A4

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\FP

GA

_Pow

er.S

chD

ocD

raw

n B

y:

+1V

330u

F

C52

Cap

Pol

3

GN

D

4.7u

F

C53

Cap

Sem

i

GN

D

4.7u

F

C54

Cap

Sem

i

GN

D

4.7u

F

C55

Cap

Sem

i

GN

D

4.7u

F

C56

Cap

Sem

i

GN

D

4.7u

F

C57

Cap

Sem

i

GN

D

4.7u

F

C58

Cap

Sem

i

GN

D

4.7u

F

C59

Cap

Sem

i

GN

D

4.7u

F

C60

Cap

Sem

i

GN

D

4.7u

F

C61

Cap

Sem

i

GN

D

4.7u

F

C62

Cap

Sem

i

GN

D

4.7u

F

C63

Cap

Sem

i

GN

D+1

V

470n

F

C65

Cap

Sem

i

GN

D

470n

F

C66

Cap

Sem

i

GN

D

470n

F

C67

Cap

Sem

i

GN

D

470n

F

C68

Cap

Sem

i

GN

D

470n

F

C69

Cap

Sem

i

GN

D

470n

F

C70

Cap

Sem

i

GN

D

470n

F

C71

Cap

Sem

i

GN

D

470n

F

C72

Cap

Sem

i

GN

D

470n

F

C73

Cap

Sem

i

GN

D

470n

F

C74

Cap

Sem

i

GN

D

470n

F

C75

Cap

Sem

i

GN

D

470n

F

C76

Cap

Sem

i

GN

D

470n

F

C77

Cap

Sem

i

GN

D

470n

F

C78

Cap

Sem

i

GN

D

470n

F

C79

Cap

Sem

i

GN

D

470n

F

C80

Cap

Sem

i

GN

D

470n

F

C81

Cap

Sem

i

GN

D+1

V

100u

F

C82

Cap

Sem

i

GN

D

4.7u

F

C83

Cap

Sem

i

GN

D

4.7u

F

C84

Cap

Sem

i

GN

D

470n

F

C85

Cap

Sem

i

GN

D

470n

F

C86

Cap

Sem

i

GN

D

470n

F

C87

Cap

Sem

i

GN

D

+1.8

V 47uF

C88

Cap

Sem

i

GN

D

47uF

C89

Cap

Sem

i

GN

D

4.7u

F

C90

Cap

Sem

i

GN

D

4.7u

F

C91

Cap

Sem

i

GN

D

4.7u

F

C92

Cap

Sem

i

GN

D

470n

F

C93

Cap

Sem

i

GN

D

470n

F

C94

Cap

Sem

i

GN

D

470n

F

C95

Cap

Sem

i

GN

D

470n

F

C96

Cap

Sem

i

GN

D

470n

F

C97

Cap

Sem

i

GN

D

+3.3

V 47uF

C64

Cap

Sem

i

GN

D

+3.3

V

100u

F

C11

6C

ap S

emi

GN

D

4.7u

F

C11

7C

ap S

emi

GN

D

4.7u

F

C11

8C

ap S

emi

GN

D

4.7u

F

C11

9C

ap S

emi

GN

D

470n

F

C12

0C

ap S

emi

GN

D

470n

F

C12

1C

ap S

emi

GN

D

470n

F

C12

2C

ap S

emi

GN

D

470n

F

C12

3C

ap S

emi

GN

D

470n

F

C12

4C

ap S

emi

GN

D

+3.3

V

100u

F

C12

5C

ap S

emi

GN

D

4.7u

F

C12

6C

ap S

emi

GN

D

4.7u

F

C12

7C

ap S

emi

GN

D

4.7u

F

C12

8C

ap S

emi

GN

D

470n

F

C12

9C

ap S

emi

GN

D

470n

F

C13

0C

ap S

emi

GN

D

470n

F

C13

1C

ap S

emi

GN

D

470n

F

C13

2C

ap S

emi

GN

D

470n

F

C13

3C

ap S

emi

GN

D

+2.5

V

100u

F

C10

7C

ap S

emi

GN

D

4.7u

F

C10

8C

ap S

emi

GN

D

4.7u

F

C10

9C

ap S

emi

GN

D

4.7u

F

C11

0C

ap S

emi

GN

D

470n

F

C11

1C

ap S

emi

GN

D

470n

F

C11

2C

ap S

emi

GN

D

470n

F

C11

3C

ap S

emi

GN

D

470n

F

C11

4C

ap S

emi

GN

D

470n

F

C11

5C

ap S

emi

GN

D

+2.5

V

100u

F

C13

4C

ap S

emi

GN

D

4.7u

F

C13

5C

ap S

emi

GN

D

4.7u

F

C13

6C

ap S

emi

GN

D

4.7u

F

C13

7C

ap S

emi

GN

D

470n

F

C13

8C

ap S

emi

GN

D

470n

F

C13

9C

ap S

emi

GN

D

470n

F

C14

0C

ap S

emi

GN

D

470n

F

C14

1C

ap S

emi

GN

D

470n

F

C14

2C

ap S

emi

GN

D

+2.5

V

100u

F

C15

2C

ap S

emi

GN

D

4.7u

F

C15

3C

ap S

emi

GN

D

4.7u

F

C15

4C

ap S

emi

GN

D

4.7u

F

C15

5C

ap S

emi

GN

D

470n

F

C15

6C

ap S

emi

GN

D

470n

F

C15

7C

ap S

emi

GN

D

470n

F

C15

8C

ap S

emi

GN

D

470n

F

C15

9C

ap S

emi

GN

D

470n

F

C16

0C

ap S

emi

GN

D

+2.5

V

100u

F

C16

1C

ap S

emi

GN

D

4.7u

F

C16

2C

ap S

emi

GN

D

4.7u

F

C16

3C

ap S

emi

GN

D

4.7u

F

C16

4C

ap S

emi

GN

D

470n

F

C16

5C

ap S

emi

GN

D

470n

F

C16

6C

ap S

emi

GN

D

470n

F

C16

7C

ap S

emi

GN

D

470n

F

C16

8C

ap S

emi

GN

D

470n

F

C16

9C

ap S

emi

GN

D

Luis

A. T

ejed

or

Ster

eo T

rigge

r

1

+2.5

V

100u

F

C98

Cap

Sem

i

GN

D

4.7u

F

C99

Cap

Sem

i

GN

D

4.7u

F

C10

0C

ap S

emi

GN

D

4.7u

F

C10

1C

ap S

emi

GN

D

470n

F

C10

2C

ap S

emi

GN

D

470n

F

C10

3C

ap S

emi

GN

D

470n

F

C10

4C

ap S

emi

GN

D

470n

F

C10

5C

ap S

emi

GN

D

470n

F

C10

6C

ap S

emi

GN

D

+2.5

V

100u

F

C14

3C

ap S

emi

GN

D

4.7u

F

C14

4C

ap S

emi

GN

D

4.7u

F

C14

5C

ap S

emi

GN

D

4.7u

F

C14

6C

ap S

emi

GN

D

470n

F

C14

7C

ap S

emi

GN

D

470n

F

C14

8C

ap S

emi

GN

D

470n

F

C14

9C

ap S

emi

GN

D

470n

F

C15

0C

ap S

emi

GN

D

470n

F

C15

1C

ap S

emi

GN

D

VC

CB

RA

M

VC

CIN

T

VC

CIN

T

VC

CA

UX

Ban

k 0

Ban

k 14

Ban

k 15

Ban

k 13

Ban

k 16

Ban

k 35

Ban

k 34

Ban

k 12

Ban

k 33

PIC5201 PIC5202

COC5

2

PIC5301PIC5302CO

C53

PIC5401PIC5402CO

C54

PIC5501PIC5502COC55

PIC5601PIC5602COC56

PIC5701PIC5702COC57

PIC5801PIC5802COC58

PIC5901PIC5902COC59

PIC6001PIC6002COC60

PIC6101PIC6102COC61

PIC6201PIC6202COC62

PIC6301PIC6302COC63

PIC6401PIC6402CO

C64

PIC6501PIC6502CO

C65

PIC6601PIC6602CO

C66

PIC6701PIC6702CO

C67

PIC6801PIC6802CO

C68

PIC6901PIC6902COC69

PIC7001PIC7002COC70

PIC7101PIC7102COC71

PIC7201PIC7202COC72

PIC7301PIC7302COC73

PIC7401PIC7402COC74

PIC7501PIC7502COC75

PIC7601PIC7602COC76

PIC7701PIC7702COC77

PIC7801PIC7802COC78

PIC7901PIC7902CO

C79

PIC8001PIC8002CO

C80

PIC8101PIC8102CO

C81

PIC8201PIC8202CO

C82

PIC8301PIC8302CO

C83

PIC8401PIC8402CO

C84

PIC8501PIC8502CO

C85

PIC8601PIC8602COC86

PIC8701PIC8702COC87

PIC8801PIC8802COC88

PIC8901PIC8902COC89

PIC9001PIC9002COC90

PIC9101PIC9102COC91

PIC9201PIC9202CO

C92

PIC9301PIC9302CO

C93

PIC9401PIC9402CO

C94

PIC9501PIC9502CO

C95

PIC9601PIC9602CO

C96

PIC9701PIC9702CO

C97

PIC9801PIC9802CO

C98

PIC9901PIC9902CO

C99

PIC10001PIC10002CO

C100

PIC10101PIC10102CO

C101

PIC10201PIC10202COC102










PIC11201PIC11202CO

C112

PIC11301PIC11302CO

C113

PIC11401PIC11402CO

C114

PIC11501PIC11502CO

C115

PIC11601PIC11602CO

C116

PIC11701PIC11702CO

C117

PIC11801PIC11802CO

C118

PIC11901PIC11902CO

C119












PIC13101PIC13102CO

C131

PIC13201PIC13202CO

C132

PIC13301PIC13302CO

C133

PIC13401PIC13402CO

C134

PIC13501PIC13502CO

C135

PIC13601PIC13602CO

C136

PIC13701PIC13702CO

C137











PIC14801PIC14802CO

C148

PIC14901PIC14902CO

C149

PIC15001PIC15002CO

C150

PIC15101PIC15102CO

C151






PIC15701PIC15702CO

C157

PIC15801PIC15802CO

C158

PIC15901PIC15902CO

C159

PIC16001PIC16002CO

C160

PIC16101PIC16102CO

C161

PIC16201PIC16202CO

C162

PIC16301PIC16302CO

C163

PIC16401PIC16402CO

C164

PIC16501PIC16502CO

C165





PIC8802PIC8902

PIC9002PIC9102

PIC9202PIC9302

PIC9402PIC9502

PIC9602PIC9702

PIC5201PIC5302

PIC5402PIC5502

PIC5602PIC5702

PIC5802PIC5902

PIC6002PIC6102

PIC6202PIC6302

PIC6502PIC6602

PIC6702PIC6802

PIC6902PIC7002

PIC7102PIC7202

PIC7302PIC7402

PIC7502PIC7602

PIC7702PIC7802

PIC7902PIC8002

PIC8102

PIC8202PIC8302

PIC8402PIC8502

PIC8602PIC8702

PIC9802PIC9902

PIC10002PIC10102

PIC10202PIC10302

PIC10402PIC10502

PIC10602PIC10702

PIC10802PIC10902

PIC11002PIC11102

PIC11202PIC11302

PIC11402PIC11502

PIC13402PIC13502

PIC13602PIC13702

PIC13802PIC13902

PIC14002PIC14102

PIC14202PIC14302

PIC14402PIC14502

PIC14602PIC14702

PIC14802PIC14902

PIC15002PIC15102

PIC15202PIC15302

PIC15402PIC15502

PIC15602PIC15702

PIC15802PIC15902

PIC16002

PIC16102PIC16202

PIC16302PIC16402

PIC16502PIC16602

PIC16702PIC16802

PIC16902

PIC6402

PIC11602PIC11702

PIC11802PIC11902

PIC12002PIC12102

PIC12202PIC12302

PIC12402PIC12502

PIC12602PIC12702

PIC12802PIC12902

PIC13002PIC13102

PIC13202PIC13302

PIC5202PIC5301

PIC5401PIC5501

PIC5601PIC5701

PIC5801PIC5901

PIC6001PIC6101

PIC6201PIC6301

PIC6401

PIC6501PIC6601

PIC6701PIC6801

PIC6901PIC7001

PIC7101PIC7201

PIC7301PIC7401

PIC7501PIC7601

PIC7701PIC7801

PIC7901PIC8001

PIC8101

PIC8201PIC8301

PIC8401PIC8501

PIC8601PIC8701

PIC8801PIC8901

PIC9001PIC9101

PIC9201PIC9301

PIC9401PIC9501

PIC9601PIC9701

PIC9801PIC9901

PIC10001PIC10101

PIC10201PIC10301

PIC10401PIC10501

PIC10601PIC10701

PIC10801PIC10901

PIC11001PIC11101

PIC11201PIC11301

PIC11401PIC11501

PIC11601PIC11701

PIC11801PIC11901

PIC12001PIC12101

PIC12201PIC12301

PIC12401PIC12501

PIC12601PIC12701

PIC12801PIC12901

PIC13001PIC13101

PIC13201PIC13301

PIC13401PIC13501

PIC13601PIC13701

PIC13801PIC13901

PIC14001PIC14101

PIC14201PIC14301

PIC14401PIC14501

PIC14601PIC14701

PIC14801PIC14901

PIC15001PIC15101

PIC15201PIC15301

PIC15401PIC15501

PIC15601PIC15701

PIC15801PIC15901

PIC16001

PIC16101PIC16201

PIC16301PIC16401

PIC16501PIC16601

PIC16701PIC16801

PIC16901

Figure A.15: TIB: FPGA power filtering

226 A. Schematics

11

22

33

44

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A4

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\JT

AG

.Sch

Doc

Dra

wn

By:

+3.3

V

GN

D

TMS

TCK

TDI

TDO

Luis

A. T

ejed

or

Ster

eo T

rigge

r

1JT

AG

11

33

55

77

99

1111

1313

22

44

66

88

1010

1212

1414

J31

Mol

ex 8

7833

-142

0

J30

Sock

et

J29

Sock

et

J32

Sock

etJ3

3

Sock

et

TMS

TCK

TDO

TDI

PIJ2901COJ

29

PIJ3001COJ

30

PIJ3101

PIJ3102

PIJ3103

PIJ3104

PIJ3105

PIJ3106

PIJ3107

PIJ3108

PIJ3109

PIJ31010

PIJ31011

PIJ31012

PIJ31013

PIJ31014

COJ31

PIJ3201COJ

32

PIJ3301COJ

33

PIJ3102

PIJ3101

PIJ3103

PIJ3105

PIJ3107

PIJ3109

PIJ31011

PIJ31013

PIJ31012

PIJ31014

PIJ2901

PIJ3106NL

TCK

POTCK

PIJ31010

PIJ3201

NLTD

IPOTDI

PIJ3108

PIJ3301

NLTD

OPOTDO

PIJ3001

PIJ3104NL

TMS

POTMS

POTCK

POTDI

POTDO

POTMS

Figure A.16: TIB: JTAG connector

A. Schematics 227

11

22

33

44

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A4

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\R

aspb

erry

_Pi.S

chD

ocD

raw

n B

y:

+5V

GN

D

GN

D

GN

D

+3.3

V

GN

D

GN

D

+3.3

V

UA

RT_

RX

UA

RT_

TX

PRO

GR

AM

_B

INIT

_B

DO

NE

RES

ET

SPI_

CS_

0

SPI_

CS_

1

I2C

_SC

LK

I2C

_SD

A

P1_7

P1_1

1

P1_1

3

P1_1

5

SPI_

MO

SI_D

IN

SPI_

MIS

O

SPI_

CC

LK

Luis

A. T

ejed

or

Ster

eo T

rigge

r

1R

aspb

erry

Pi

CO

NFI

G_C

CLK

CLK

IN1

OE

2

1Y0

3

GN

D4

1Y3

8

1Y2

7

VD

D6

1Y1

5

U40

CD

CV

304

+3.3

V

GN

DRPi

_CC

LK

RPi

_CC

LK

+3.3

V

100p

F

C30

4C

ap S

emi

100n

F

C30

5C

ap S

emi

10uF

C30

6C

ap S

emi

GN

DG

ND

GN

D

100

R81

Res

3

100

R80

Res

3

GN

D

GN

D SPI_

CLK

_CO

PY1

SPI_

CLK

_CO

PY0

FD3

Fidu

cial

J78

Sock

et

J77

Sock

et

J79

Sock

et

J71

Sock

etJ7

4

Sock

et

J69

Sock

et

J66

Sock

et

J63

Sock

et

J67

Sock

et

J64

Sock

et

J61

Sock

et

J72

Sock

etJ7

5

Sock

etJ7

6

Sock

et

J68

Sock

et

J65

Sock

et

J62

Sock

et

J70

Sock

etJ7

3

Sock

et

GN

D

I2C

_SD

A3

5V0

4

I2C

_CLK

5G

ND

6

GPI

O_4

7U

AR

T_TX

8

GN

D9

UA

RT_

RX

10

GPI

O_1

711

GPI

O_1

812

GPI

O_2

713

GN

D14

GPI

O_2

215

GPI

O_2

316

3.3V

17G

PIO

_24

18

SPI_

MO

SI19

GN

D20

SPI_

MIS

O21

GPI

O_2

522

SPI_

CLK

23SP

I_C

S024

GN

D25

SPI_

CS1

26

GND 0

3.3V

15V

02

J85

Ras

pber

ry_P

i

I2C

_SD

A

I2C

_SC

LK

P1_7

P1_1

1

P1_1

3

P1_1

5

SPI_

MO

SI_D

IN

SPI_

MIS

O

UA

RT_

RX

UA

RT_

TX

PRO

GR

AM

_B

INIT

_B

DO

NE

RES

ET

SPI_

CS_

0

SPI_

CS_

1

SPI c

lock

mus

t be

repl

icat

ed

to fe

ed th

e cl

k pa

d us

ed

durin

g co

nfig

urat

ion

and

the

spi c

lk p

ad u

sed

for s

low

co

ntro

l.




COFD

3

PIJ6101

COJ61

PIJ6201COJ

62

PIJ6301

COJ63

PIJ6401

COJ64

PIJ6501COJ

65

PIJ6601

COJ66

PIJ6701

COJ67

PIJ6801COJ

68

PIJ6901

COJ69

PIJ7001COJ

70

PIJ7101

COJ71

PIJ7201COJ

72

PIJ7301COJ

73

PIJ7401

COJ74

PIJ7501COJ75

PIJ7601COJ

76

PIJ7701COJ

77

PIJ7801

COJ78

PIJ7901COJ

79

PIJ8500

PIJ8501

PIJ8502

PIJ8503

PIJ8504

PIJ8505

PIJ8506

PIJ8507

PIJ8508

PIJ8509

PIJ85010

PIJ8

5011

PIJ85012

PIJ8

5013

PIJ85014

PIJ8

5015

PIJ85016

PIJ8

5017

PIJ85018

PIJ8

5019

PIJ85020

PIJ8

5021

PIJ85022

PIJ8

5023

PIJ8

5024

PIJ8

5025

PIJ85026

COJ85

PIR8001PIR8002CO

R80

PIR8101PIR8102COR81

PIU4001

PIU4002

PIU4003

PIU4004

PIU4005

PIU4006

PIU4007

PIU4008

COU40

PIC30402PIC30502

PIC30602

PIJ8501

PIJ8

5017

PIU4002

PIU4006

PIJ8502

PIJ8504

PIJ7001

PIJ85018

NLDO

NEPODONE

PIC30401PIC30501

PIC30601

PIJ8500

PIJ8506

PIJ8509

PIJ85014

PIJ85020

PIJ8

5025

PIR8002

PIR8101

PIU4004

PIJ6401

PIJ8505

NLI2C0SCLK

POI2C0SCLK

PIJ6701

PIJ8503

NLI2C0SDA

POI2C0SDA

PIJ7301

PIJ85016

NLINIT0B

POINIT0B

PIJ7701

PIU4008

POSPI0CCLK

PIJ7901

PIU4005

POCONFIG0CCLK

PIJ6101

PIJ8507

NLP1

07POP107

PIJ6901

PIJ8

5011

NLP1011

POP1011

PIJ6601

PIJ8

5013

NLP1013

POP1013

PIJ6301

PIJ8

5015

NLP1015

POP1015

PIJ6201

PIJ85012

NLPROGRAM0B

POPROGRAM0B

PIJ7601

PIJ85022

NLRESET

PORESET

PIJ7801

PIJ8

5023

PIU4001

NLRP

i0CC

LK

PIR8102PIU4003

NLSPI0CLK0COPY0

PIR8001PIU4007

NLSPI0CLK0COPY1

PIJ7501

PIJ8

5024

NLSP

I0CS

00POSPI0CS00

PIJ7201

PIJ85026

NLSP

I0CS

01POSPI0CS01

PIJ7101

PIJ8

5021

NLSPI0MISO

POSPI0MISO

PIJ7401

PIJ8

5019

NLSP

I0MO

SI0D

INPOSPI0MOSI0DIN

PIJ6801

PIJ8508

NLUA

RT0R

XPOUART0RX

PIJ6501

PIJ85010

NLUA

RT0T

XPOUART0TX

POCONFIG0CCLK

PODONE

POI2C0SCLK

POI2C0SDA

POINIT0B

POP107

POP1011

POP1013

POP1015

POPROGRAM0B

PORESET

POSPI0CCLK

POSPI0CS00

POSPI0CS01

POSPI0MISO

POSPI0MOSI0DIN

POUART0RX

POUART0TX

Figure A.17: TIB: Raspberry Pi pins

228 A. Schematics

11

22

33

44

55

66

77

88

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A3

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\LV

DSt

oLV

PEC

L.Sc

hDocDra

wn

By:

100

R27

Res

3

OU

TPU

T_0_

P

OU

TPU

T_0_

N

100

R29

Res

3

OU

TPU

T_1_

P

OU

TPU

T_1_

N

100

R31

Res

3

OU

TPU

T_2_

P

OU

TPU

T_2_

N

100

R33

Res

3

OU

TPU

T_3_

P

OU

TPU

T_3_

N

100

R28

Res

3

OU

TPU

T_4_

P

OU

TPU

T_4_

N

100

R30

Res

3

OU

TPU

T_5_

P

OU

TPU

T_5_

N

100

R32

Res

3

OU

TPU

T_6_

P

OU

TPU

T_6_

N

100

R34

Res

3

OU

TPU

T_7_

P

OU

TPU

T_7_

N

LVPE

CL_

OU

TPU

T_0_

PLV

PEC

L_O

UTP

UT_

0_N

LVPE

CL_

OU

TPU

T_1_

PLV

PEC

L_O

UTP

UT_

1_N

LVPE

CL_

OU

TPU

T_2_

PLV

PEC

L_O

UTP

UT_

2_N

LVPE

CL_

OU

TPU

T_3_

PLV

PEC

L_O

UTP

UT_

3_N

LVPE

CL_

OU

TPU

T_4_

PLV

PEC

L_O

UTP

UT_

4_N

LVPE

CL_

OU

TPU

T_5_

PLV

PEC

L_O

UTP

UT_

5_N

LVPE

CL_

OU

TPU

T_6_

PLV

PEC

L_O

UTP

UT_

6_N

LVPE

CL_

OU

TPU

T_7_

PLV

PEC

L_O

UTP

UT_

7_N

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

PED

ESTA

L_FB

_P

PED

ESTA

L_FB

_N

LVPE

CL_

PED

ESTA

L_FB

_PLV

PEC

L_PE

DES

TAL_

FB_N

+3.3

V

GN

D

CA

LIB

_FB

_P

CA

LIB

_FB

_N

LVPE

CL_

CA

LIB

_FB

_PLV

PEC

L_C

ALI

B_F

B_N

+3.3

V

GN

D

100n

F

C17

2C

ap S

emi

100p

F

C17

1C

ap S

emi

10uF

C17

0C

ap S

emi+3

.3V

GN

D

100n

F

C17

8C

ap S

emi

100p

F

C17

7C

ap S

emi

10uF

C17

6C

ap S

emi+3

.3V

GN

D

100n

F

C18

4C

ap S

emi

100p

F

C18

3C

ap S

emi

10uF

C18

2C

ap S

emi+3

.3V

GN

D

100n

F

C19

0C

ap S

emi

100p

F

C18

9C

ap S

emi

10uF

C18

8C

ap S

emi+3

.3V

GN

D

100n

F

C19

6C

ap S

emi

100p

F

C19

5C

ap S

emi

10uF

C19

4C

ap S

emi+3

.3V

GN

D

100n

F

C17

5C

ap S

emi

100p

F

C17

4C

ap S

emi

10uF

C17

3C

ap S

emi+3

.3V

GN

D

100n

F

C18

1C

ap S

emi

100p

F

C18

0C

ap S

emi

10uF

C17

9C

ap S

emi+3

.3V

GN

D

100n

F

C18

7C

ap S

emi

100p

F

C18

6C

ap S

emi

10uF

C18

5C

ap S

emi+3

.3V

GN

D

100n

F

C19

3C

ap S

emi

100p

F

C19

2C

ap S

emi

10uF

C19

1C

ap S

emi+3

.3V

GN

D

100n

F

C19

9C

ap S

emi

100p

F

C19

8C

ap S

emi

10uF

C19

7C

ap S

emi+3

.3V

GN

D

Ster

eo T

rigge

r

LVD

S to

LV

PEC

L1

Luis

A. T

ejed

or

OU

TPU

T_4_

P

OU

TPU

T_4_

N

LVPE

CL_

OU

TPU

T_4_

PLV

PEC

L_O

UTP

UT_

4_N

OU

TPU

T_5_

P

OU

TPU

T_5_

N

LVPE

CL_

OU

TPU

T_5_

PLV

PEC

L_O

UTP

UT_

5_N

OU

TPU

T_6_

P

OU

TPU

T_6_

N

LVPE

CL_

OU

TPU

T_6_

PLV

PEC

L_O

UTP

UT_

6_N

OU

TPU

T_7_

P

OU

TPU

T_7_

N

LVPE

CL_

OU

TPU

T_7_

PLV

PEC

L_O

UTP

UT_

7_N

LVPE

CL_

CA

LIB

_FB

_PLV

PEC

L_C

ALI

B_F

B_N

100

R35

Res

3

CA

LIB

_FB

_P

CA

LIB

_FB

_N

LVPE

CL_

OU

TPU

T_0_

PLV

PEC

L_O

UTP

UT_

0_N

OU

TPU

T_0_

P

OU

TPU

T_0_

N

LVPE

CL_

OU

TPU

T_1_

PLV

PEC

L_O

UTP

UT_

1_N

OU

TPU

T_1_

P

OU

TPU

T_1_

N

OU

TPU

T_2_

P

OU

TPU

T_2_

N

LVPE

CL_

OU

TPU

T_2_

PLV

PEC

L_O

UTP

UT_

2_N

OU

TPU

T_3_

P

OU

TPU

T_3_

N

LVPE

CL_

OU

TPU

T_3_

PLV

PEC

L_O

UTP

UT_

3_N

LVPE

CL_

PED

ESTA

L_FB

_PLV

PEC

L_PE

DES

TAL_

FB_N

100

R36

Res

3

PED

ESTA

L_FB

_P

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U11

SN65

LVD

S101

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U13

SN65

LVD

S101

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U15

SN65

LVD

S101

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U17

SN65

LVD

S101

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U20

SN65

LVD

S101

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U12

SN65

LVD

S101

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U14

SN65

LVD

S101

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U16

SN65

LVD

S101

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U18

SN65

LVD

S101

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U19

SN65

LVD

S101

PED

ESTA

L_FB

_N

TOB

EDEL

AY

ED_D

IF_P

TOB

EDEL

AY

ED_D

IF_N

LVPE

CL_

TOB

EDEL

AY

ED_D

IF_P

LVPE

CL_

TOB

EDEL

AY

ED_D

IF_N

+3.3

V

GN

D

100n

F

C20

2C

ap S

emi

100p

F

C20

1C

ap S

emi

10uF

C20

0C

ap S

emi+3

.3V

GN

D

LVPE

CL_

TOB

EDEL

AY

ED_D

IF_P

LVPE

CL_

TOB

EDEL

AY

ED_D

IF_N

100

R37

Res

3

TOB

EDEL

AY

ED_D

IF_P

TOB

EDEL

AY

ED_D

IF_N

EXTR

A_S

FP_1

1_FB

_P

EXTR

A_S

FP_1

1_FB

_N

LVPE

CL_

EXTR

A_S

FP_1

1_FB

_PLV

PEC

L_EX

TRA

_SFP

_11_

FB_N

+3.3

V

GN

D

100n

F

C20

5C

ap S

emi

100p

F

C20

4C

ap S

emi

10uF

C20

3C

ap S

emi+3

.3V

GN

D

LVPE

CL_

EXTR

A_S

FP_1

1_FB

_PLV

PEC

L_EX

TRA

_SFP

_11_

FB_N

100

R38

Res

3

EXTR

A_S

FP_1

1_FB

_P

EXTR

A_S

FP_1

1_FB

_N

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U21

SN65

LVD

S101

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U22

SN65

LVD

S101

FD2

Fidu

cial

1 2

P9 Hea

der 2

1 2

P11

Hea

der 2

1 2

P13

Hea

der 2

1 2

P15

Hea

der 2

1 2

P18

Hea

der 2

1 2

P19

Hea

der 2

1 2

P20

Hea

der 2

1 2

P17

Hea

der 2

1 2

P16

Hea

der 2

1 2

P14

Hea

der 2

1 2

P12

Hea

der 2

1 2

P10

Hea

der 2

PIC17001PIC17002CO

C170

PIC17101PIC17102CO

C171

PIC17201PIC17202CO

C172

PIC17301PIC17302CO

C173

PIC17401PIC17402CO

C174

PIC17501PIC17502CO

C175

PIC17601PIC17602CO

C176

PIC17701PIC17702CO

C177

PIC17801PIC17802CO

C178

PIC17901PIC17902CO

C179

PIC18001PIC18002CO

C180

PIC18101PIC18102CO

C181

PIC18201PIC18202CO

C182

PIC18301PIC18302CO

C183

PIC18401PIC18402CO

C184

PIC18501PIC18502CO

C185

PIC18601PIC18602CO

C186

PIC18701PIC18702CO

C187

PIC18801PIC18802CO

C188

PIC18901PIC18902CO

C189

PIC19001PIC19002CO

C190

PIC19101PIC19102CO

C191

PIC19201PIC19202CO

C192

PIC19301PIC19302CO

C193

PIC19401PIC19402CO

C194

PIC19501PIC19502CO

C195

PIC19601PIC19602CO

C196

PIC19701PIC19702CO

C197

PIC19801PIC19802CO

C198

PIC19901PIC19902CO

C199

PIC20001PIC20002CO

C200

PIC20101PIC20102CO

C201

PIC20201PIC20202CO

C202

PIC20301PIC20302CO

C203

PIC20401PIC20402CO

C204

PIC20501PIC20502CO

C205

COFD

2

PIP901

PIP902

COP9

PIP1001

PIP1002

COP10

PIP1101

PIP1102

COP11

PIP1201

PIP1202

COP12

PIP1301

PIP1302

COP13

PIP1401

PIP1402

COP14

PIP1501

PIP1502

COP15

PIP1601

PIP1602

COP16

PIP1701

PIP1702

COP17

PIP1801

PIP1802

COP18

PIP1901

PIP1902

COP1

9PIP2001

PIP2002

COP20

PIR2701 PIR2702COR2

7PIR2801 PIR2802CO

R28

PIR2901 PIR2902COR2

9PIR3001 PIR3002CO

R30

PIR3101 PIR3102COR3

1PIR3201 PIR3202CO

R32

PIR3301 PIR3302COR3

3PIR3401 PIR3402CO

R34

PIR3501PIR3502 COR3

5

PIR3601PIR3602 COR3

6

PIR3701PIR3702COR37

PIR3801PIR3802COR38

PIU1101

PIU1102

PIU1103

PIU1104

PIU1105

PIU1106

PIU1107

PIU1108

COU1

1PIU1201

PIU1202

PIU1203

PIU1204

PIU1205

PIU1206

PIU1207

PIU1208

COU1

2

PIU1301

PIU1302

PIU1303

PIU1304

PIU1305

PIU1306

PIU1307

PIU1308

COU1

3

PIU1401

PIU1402

PIU1403

PIU1404

PIU1405

PIU1406

PIU1407

PIU1408

COU1

4

PIU1501

PIU1502

PIU1503

PIU1504

PIU1505

PIU1506

PIU1507

PIU1508

COU1

5

PIU1601

PIU1602

PIU1603

PIU1604

PIU1605

PIU1606

PIU1607

PIU1608

COU1

6

PIU1701

PIU1702

PIU1703

PIU1704

PIU1705

PIU1706

PIU1707

PIU1708

COU1

7

PIU1801

PIU1802

PIU1803

PIU1804

PIU1805

PIU1806

PIU1807

PIU1808

COU1

8

PIU1901

PIU1902

PIU1903

PIU1904

PIU1905

PIU1906

PIU1907

PIU1908

COU1

9

PIU2001

PIU2002

PIU2003

PIU2004

PIU2005

PIU2006

PIU2007

PIU2008

COU2

0 PIU2101

PIU2102

PIU2103

PIU2104

PIU2105

PIU2106

PIU2107

PIU2108

COU2

1

PIU2201

PIU2202

PIU2203

PIU2204

PIU2205

PIU2206

PIU2207

PIU2208

COU2

2

PIC17002PIC17102

PIC17202PIC17302

PIC17402PIC17502

PIC17602PIC17702

PIC17802PIC17902

PIC18002PIC18102

PIC18202PIC18302

PIC18402PIC18502

PIC18602PIC18702

PIC18802PIC18902

PIC19002PIC19102

PIC19202PIC19302

PIC19402PIC19502

PIC19602PIC19702

PIC19802PIC19902

PIC20002PIC20102

PIC20202PIC20302

PIC20402PIC20502

PIU1108

PIU1208

PIU1308

PIU1408

PIU1508

PIU1608

PIU1708

PIU1808

PIU1908

PIU2008

PIU2108

PIU2208

PIP1702

PIR3501PIU1903

NLCALIB0FB0N

POCALIB0FB0N

PIP1701

PIR3502PIU1902

NLCA

LIB0

FB0P

POCALIB0FB0P

PIP2002

PIR3801PIU2203

NLEXTRA0SFP0110FB0N

POEXTRA0SFP0110FB0N

PIP2001

PIR3802PIU2202

NLEXTRA0SFP0110FB0P

POEXTRA0SFP0110FB0P

PIC17001PIC17101

PIC17201PIC17301

PIC17401PIC17501

PIC17601PIC17701

PIC17801PIC17901

PIC18001PIC18101

PIC18201PIC18301

PIC18401PIC18501

PIC18601PIC18701

PIC18801PIC18901

PIC19001PIC19101

PIC19201PIC19301

PIC19401PIC19501

PIC19601PIC19701

PIC19801PIC19901

PIC20001PIC20101

PIC20201PIC20301

PIC20401PIC20501

PIU1105

PIU1205

PIU1305

PIU1405

PIU1505

PIU1605

PIU1705

PIU1805

PIU1905

PIU2005

PIU2105

PIU2205

PIU1906

NLLVPECL0CALIB0FB0N

POLVPECL0CALIB0FB0N

PIU1907

NLLV

PECL

0CAL

IB0F

B0P

POLVPECL0CALIB0FB0P

PIU2206

NLLV

PECL

0EXT

RA0S

FP01

10FB

0NPOLVPECL0EXTRA0SFP0110FB0N

PIU2207

NLLV

PECL

0EXT

RA0S

FP01

10FB

0PPOLVPECL0EXTRA0SFP0110FB0P

PIU1106

NLLV

PECL

0OUT

PUT0

00NPOLVPECL0OUTPUT000N

PIU1107

NLLVPECL0OUTPUT000P

POLVPECL0OUTPUT000P

PIU1306

NLLV

PECL

0OUT

PUT0


PIU1307

NLLVPECL0OUTPUT010P

POLVPECL0OUTPUT010P

PIU1506

NLLV

PECL

0OUT

PUT0


PIU1507

NLLVPECL0OUTPUT020P

POLVPECL0OUTPUT020P

PIU1706

NLLV

PECL

0OUT

PUT0


PIU1707

NLLVPECL0OUTPUT030P

POLVPECL0OUTPUT030P

PIU1206

NLLV

PECL

0OUT

PUT0


PIU1207

NLLVPECL0OUTPUT040P

POLVPECL0OUTPUT040P

PIU1406

NLLV

PECL

0OUT

PUT0


PIU1407

NLLVPECL0OUTPUT050P

POLVPECL0OUTPUT050P

PIU1606

NLLV

PECL

0OUT

PUT0


PIU1607

NLLVPECL0OUTPUT060P

POLVPECL0OUTPUT060P

PIU1806

NLLV

PECL

0OUT

PUT0


PIU1807

NLLVPECL0OUTPUT070P

POLVPECL0OUTPUT070P

PIU2006

NLLVPECL0PEDESTAL0FB0NPOLVPECL0PEDESTAL0FB0N

PIU2007

NLLV

PECL

0PED

ESTA

L0FB

0PPOLVPECL0PEDESTAL0FB0P

PIU2106

NLLVPECL0TOBEDELAYED0DIF0NPOLVPECL0TOBEDELAYED0DIF0N

PIU2107

NLLV

PECL

0TOB

EDEL

AYED

0DIF

0PPOLVPECL0TOBEDELAYED0DIF0P

PIU1101

PIU1104

PIU1201

PIU1204

PIU1301

PIU1304

PIU1401

PIU1404

PIU1501

PIU1504

PIU1601

PIU1604

PIU1701

PIU1704

PIU1801

PIU1804

PIU1901

PIU1904

PIU2001

PIU2004

PIU2101

PIU2104

PIU2201

PIU2204

PIP902

PIR2702PIU1103

NLOUTPUT000N

POOUTPUT000N

PIP901

PIR2701PIU1102

NLOUTPUT000P

POOUTPUT000P

PIP1102

PIR2902PIU1303

NLOUTPUT010N

POOUTPUT010N

PIP1101

PIR2901PIU1302

NLOUTPUT010P

POOUTPUT010P

PIP1302

PIR3102PIU1503

NLOUTPUT020N

POOUTPUT020N

PIP1301

PIR3101PIU1502

NLOUTPUT020P

POOUTPUT020P

PIP1502

PIR3302PIU1703

NLOUTPUT030N

POOUTPUT030N

PIP1501

PIR3301PIU1702

NLOUTPUT030P

POOUTPUT030P

PIP1002

PIR2802PIU1203

NLOUTPUT040N

POOUTPUT040N

PIP1001

PIR2801PIU1202

NLOUTPUT040P

POOUTPUT040P P

IP1202

PIR3002PIU1403

NLOUTPUT050N

POOUTPUT050N

PIP1201

PIR3001PIU1402

NLOUTPUT050P

POOUTPUT050P

PIP1402

PIR3202PIU1603

NLOUTPUT060N

POOUTPUT060N

PIP1401

PIR3201PIU1602

NLOUTPUT060P

POOUTPUT060P

PIP1602

PIR3402PIU1803

NLOUTPUT070N

POOUTPUT070N

PIP1601

PIR3401PIU1802

NLOUTPUT070P

POOUTPUT070P

PIP1802

PIR3601PIU2003

NLPEDESTAL0FB0N

POPEDESTAL0FB0NPIP1801

PIR3602PIU2002

NLPEDESTAL0FB0P

POPEDESTAL0FB0P

PIP1902

PIR3701PIU2103

NLTOBEDELAYED0DIF0N

POTOBEDELAYED0DIF0N

PIP1901

PIR3702PIU2102

NLTO

BEDE

LAYE

D0DI

F0P

POTOBEDELAYED0DIF0P

POCALIB0FB0N

POCALIB0FB0P

POEXTRA0SFP0110FB0N

POEXTRA0SFP0110FB0P

POLVPECL0CALIB0FB0N

POLVPECL0CALIB0FB0P

POLVPECL0EXTRA0SFP0110FB0N

POLVPECL0EXTRA0SFP0110FB0P

POLVPECL0OUTPUT000N

POLVPECL0OUTPUT000P

POLVPECL0OUTPUT010N

POLVPECL0OUTPUT010P

POLVPECL0OUTPUT020N

POLVPECL0OUTPUT020P

POLVPECL0OUTPUT030N

POLVPECL0OUTPUT030P

POLVPECL0OUTPUT040N

POLVPECL0OUTPUT040P

POLVPECL0OUTPUT050N

POLVPECL0OUTPUT050P

POLVPECL0OUTPUT060N

POLVPECL0OUTPUT060P

POLVPECL0OUTPUT070N

POLVPECL0OUTPUT070P

POLVPECL0PEDESTAL0FB0N

POLVPECL0PEDESTAL0FB0P

POLVPECL0TOBEDELAYED0DIF0N

POLVPECL0TOBEDELAYED0DIF0P

POOUTPUT000N

POOUTPUT000P

POOUTPUT010N

POOUTPUT010P

POOUTPUT020N

POOUTPUT020P

POOUTPUT030N

POOUTPUT030P

POOUTPUT040N

POOUTPUT040P

POOUTPUT050N

POOUTPUT050P

POOUTPUT060N

POOUTPUT060P

POOUTPUT070N

POOUTPUT070P

POPEDESTAL0FB0N

POPEDESTAL0FB0P

POTOBEDELAYED0DIF0N

POTOBEDELAYED0DIF0P

Figure A.18: TIB: LVDS to LVPECL translators

A. Schematics 229

11

22

33

44

55

66

77

88

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A3

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\LV

PEC

LtoL

VD

S.Sc

hDocDra

wn

By:

INPU

T_1_

PIN

PUT_

1_N

INPU

T_2_

PIN

PUT_

2_N

INPU

T_3_

PIN

PUT_

3_N

INPU

T_4_

PIN

PUT_

4_N

INPU

T_5_

PIN

PUT_

5_N

INPU

T_6_

PIN

PUT_

6_N

INPU

T_7_

PIN

PUT_

7_N

INPU

T_8_

PIN

PUT_

8_N

LVPE

CL_

INPU

T_1_

PLV

PEC

L_IN

PUT_

1_N

LVPE

CL_

INPU

T_2_

PLV

PEC

L_IN

PUT_

2_N

LVPE

CL_

INPU

T_3_

PLV

PEC

L_IN

PUT_

3_N

LVPE

CL_

INPU

T_4_

PLV

PEC

L_IN

PUT_

4_N

LVPE

CL_

INPU

T_5_

PLV

PEC

L_IN

PUT_

5_N

LVPE

CL_

INPU

T_6_

PLV

PEC

L_IN

PUT_

6_N

LVPE

CL_

INPU

T_7_

PLV

PEC

L_IN

PUT_

7_N

LVPE

CL_

INPU

T_8_

PLV

PEC

L_IN

PUT_

8_N

+3.3

V+3

.3V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

PED

ESTA

L_P

PED

ESTA

L_N

LVPE

CL_

PED

ESTA

L_P

LVPE

CL_

PED

ESTA

L_N

+3.3

V

GN

D

CA

LIB

_PC

ALI

B_N

LVPE

CL_

CA

LIB

_PLV

PEC

L_C

ALI

B_N

+3.3

V

GN

D

100n

F

C20

8C

ap S

emi

100p

F

C20

7C

ap S

emi

10uF

C20

6C

ap S

emi+3

.3V

GN

D

100n

F

C21

1C

ap S

emi

100p

F

C21

0C

ap S

emi

10uF

C20

9C

ap S

emi+3

.3V

GN

D

100n

F

C21

4C

ap S

emi

100p

F

C21

3C

ap S

emi

10uF

C21

2C

ap S

emi+3

.3V

GN

D

100n

F

C21

7C

ap S

emi

100p

F

C21

6C

ap S

emi

10uF

C21

5C

ap S

emi+3

.3V

GN

D

100n

F

C22

3C

ap S

emi

100p

F

C22

2C

ap S

emi

10uF

C22

1C

ap S

emi+3

.3V

GN

D

100n

F

C22

0C

ap S

emi

100p

F

C21

9C

ap S

emi

10uF

C21

8C

ap S

emi+3

.3V

GN

D

100n

F

C22

6C

ap S

emi

100p

F

C22

5C

ap S

emi

10uF

C22

4C

ap S

emi+3

.3V

GN

D

100n

F

C22

9C

ap S

emi

100p

F

C22

8C

ap S

emi

10uF

C22

7C

ap S

emi+3

.3V

GN

D

100n

F

C23

2C

ap S

emi

100p

F

C23

1C

ap S

emi

10uF

C23

0C

ap S

emi+3

.3V

GN

D

100n

F

C23

5C

ap S

emi

100p

F

C23

4C

ap S

emi

10uF

C23

3C

ap S

emi+3

.3V

GN

D

Ster

eo T

rigge

r

LVPE

CL

to L

VD

S1

Luis

A. T

ejed

or

LVPE

CL_

INPU

T_5_

PLV

PEC

L_IN

PUT_

5_N

INPU

T_5_

PIN

PUT_

5_N

LVPE

CL_

INPU

T_6_

PLV

PEC

L_IN

PUT_

6_N

INPU

T_6_

PIN

PUT_

6_N

LVPE

CL_

INPU

T_7_

PLV

PEC

L_IN

PUT_

7_N

INPU

T_7_

PIN

PUT_

7_N

LVPE

CL_

INPU

T_8_

PLV

PEC

L_IN

PUT_

8_N

INPU

T_8_

PIN

PUT_

8_N

LVPE

CL_

CA

LIB

_PLV

PEC

L_C

ALI

B_N

CA

LIB

_PC

ALI

B_N

LVPE

CL_

INPU

T_1_

PLV

PEC

L_IN

PUT_

1_N

INPU

T_1_

PIN

PUT_

1_N

LVPE

CL_

INPU

T_2_

PLV

PEC

L_IN

PUT_

2_N

INPU

T_2_

PIN

PUT_

2_N

LVPE

CL_

INPU

T_3_

PLV

PEC

L_IN

PUT_

3_N

INPU

T_3_

PIN

PUT_

3_N

LVPE

CL_

INPU

T_4_

PLV

PEC

L_IN

PUT_

4_N

INPU

T_4_

PIN

PUT_

4_N

LVPE

CL_

PED

ESTA

L_P

LVPE

CL_

PED

ESTA

L_N

PED

ESTA

L_P

PED

ESTA

L_N

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U24

SN65

LVD

S100

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U26

SN65

LVD

S100

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U28

SN65

LVD

S100

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U30

SN65

LVD

S100

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U31

SN65

LVD

S100

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U32

SN65

LVD

S100

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U29

SN65

LVD

S100

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U27

SN65

LVD

S100

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U25

SN65

LVD

S100

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U23

SN65

LVD

S100

TRIG

DEL

AY

ED_D

IF_P

TRIG

DEL

AY

ED_D

IF_N

LVPE

CL_

TRIG

DEL

AY

ED_D

IF_P

LVPE

CL_

TRIG

DEL

AY

ED_D

IF_N

+3.3

V

GN

D

100n

F

C24

1C

ap S

emi

100p

F

C24

0C

ap S

emi

10uF

C23

9C

ap S

emi+3

.3V

GN

D

LVPE

CL_

TRIG

DEL

AY

ED_D

IF_P

LVPE

CL_

TRIG

DEL

AY

ED_D

IF_N

TRIG

DEL

AY

ED_D

IF_P

TRIG

DEL

AY

ED_D

IF_N

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U34

SN65

LVD

S100

EXTR

A_S

FP_1

1_P

EXTR

A_S

FP_1

1_N

LVPE

CL_

EXTR

A_S

FP_1

1_P

LVPE

CL_

EXTR

A_S

FP_1

1_N

+3.3

V

GN

D

LVPE

CL_

EXTR

A_S

FP_1

1_P

LVPE

CL_

EXTR

A_S

FP_1

1_N

EXTR

A_S

FP_1

1_P

EXTR

A_S

FP_1

1_N

NC

1

A2

B3

Vbb

4

Vcc

8

Y7

Z6

GN

D5

U33

SN65

LVD

S100

100n

F

C23

8C

ap S

emi

100p

F

C23

7C

ap S

emi

10uF

C23

6C

ap S

emi+3

.3V

GN

D

1 2

P22

Hea

der 2

INPU

T_1_

PIN

PUT_

1_N

1 2

P24

Hea

der 2

INPU

T_2_

PIN

PUT_

2_N

1 2

P26

Hea

der 2

INPU

T_3_

PIN

PUT_

3_N

1 2

P28

Hea

der 2

INPU

T_4_

PIN

PUT_

4_N

1 2

P29

Hea

der 2

PED

ESTA

L_P

PED

ESTA

L_N

1 2

P21

Hea

der 2

INPU

T_5_

PIN

PUT_

5_N

1 2

P23

Hea

der 2

INPU

T_6_

PIN

PUT_

6_N

1 2

P25

Hea

der 2

INPU

T_7_

PIN

PUT_

7_N

1 2

P27

Hea

der 2

INPU

T_8_

PIN

PUT_

8_N

1 2

P30

Hea

der 2

CA

LIB

_PC

ALI

B_N

1 2

P31

Hea

der 2

EXTR

A_S

FP_1

1_P

EXTR

A_S

FP_1

1_N

1 2

P32

Hea

der 2

TRIG

DEL

AY

ED_D

IF_P

TRIG

DEL

AY

ED_D

IF_N





































PIP2101

PIP2102

COP2

1

PIP2201

PIP2202

COP2

2

PIP2301

PIP2302

COP2

3

PIP2401

PIP2402

COP24

PIP2501

PIP2502

COP2

5

PIP2601

PIP2602

COP2

6

PIP2701

PIP2702

COP2

7

PIP2801

PIP2802

COP2

8

PIP2901

PIP2902

COP2

9PIP3001

PIP3002

COP3

0 PIP3101

PIP3102

COP3

1

PIP3201

PIP3202

COP3

2

PIU2301

PIU2302

PIU2303

PIU2304

PIU2305

PIU2306

PIU2307

PIU2308

COU2

3

PIU2401

PIU2402

PIU2403

PIU2404

PIU2405

PIU2406

PIU2407

PIU2408

COU24

PIU2501

PIU2502

PIU2503

PIU2504

PIU2505

PIU2506

PIU2507

PIU2508

COU2

5

PIU2601

PIU2602

PIU2603

PIU2604

PIU2605

PIU2606

PIU2607

PIU2608

COU26

PIU2701

PIU2702

PIU2703

PIU2704

PIU2705

PIU2706

PIU2707

PIU2708

COU2

7

PIU2801

PIU2802

PIU2803

PIU2804

PIU2805

PIU2806

PIU2807

PIU2808

COU28

PIU2901

PIU2902

PIU2903

PIU2904

PIU2905

PIU2906

PIU2907

PIU2908

COU2

9

PIU3001

PIU3002

PIU3003

PIU3004

PIU3005

PIU3006

PIU3007

PIU3008

COU30

PIU3101

PIU3102

PIU3103

PIU3104

PIU3105

PIU3106

PIU3107

PIU3108

COU31

PIU3201

PIU3202

PIU3203

PIU3204

PIU3205

PIU3206

PIU3207

PIU3208

COU32

PIU3301

PIU3302

PIU3303

PIU3304

PIU3305

PIU3306

PIU3307

PIU3308

COU33

PIU3401

PIU3402

PIU3403

PIU3404

PIU3405

PIU3406

PIU3407

PIU3408

COU34

PIC20602PIC20702

PIC20802PIC20902

PIC21002PIC21102

PIC21202PIC21302

PIC21402PIC21502

PIC21602PIC21702

PIC21802PIC21902

PIC22002PIC22102

PIC22202PIC22302

PIC22402PIC22502

PIC22602PIC22702

PIC22802PIC22902

PIC23002PIC23102

PIC23202PIC23302

PIC23402PIC23502

PIC23602PIC23702

PIC23802

PIC23902PIC24002

PIC24102

PIU2308

PIU2408

PIU2508

PIU2608

PIU2708

PIU2808

PIU2908

PIU3008

PIU3108

PIU3208

PIU3308

PIU3408

PIP3002

PIU3206

NLCA

LIB0

N

POCALIB0N

PIP3001

PIU3207

NLCA

LIB0

P

POCALIB0P

PIP3102

PIU3306

NLEXTRA0SFP0110N

POEXTRA0SFP0110N

PIP3101

PIU3307

NLEXTRA0SFP0110P

POEXTRA0SFP0110P

PIC20601PIC20701

PIC20801PIC20901

PIC21001PIC21101

PIC21201PIC21301

PIC21401PIC21501

PIC21601PIC21701

PIC21801PIC21901

PIC22001PIC22101

PIC22201PIC22301

PIC22401PIC22501

PIC22601PIC22701

PIC22801PIC22901

PIC23001PIC23101

PIC23201PIC23301

PIC23401PIC23501

PIC23601PIC23701

PIC23801

PIC23901PIC24001

PIC24101

PIU2305

PIU2405

PIU2505

PIU2605

PIU2705

PIU2805

PIU2905

PIU3005

PIU3105

PIU3205

PIU3305

PIU3405

PIP2202

PIU2406

NLIN

PUT0

10N

POINPUT010N

PIP2201

PIU2407

NLIN

PUT0

10P

POINPUT010P

PIP2402

PIU2606

NLIN

PUT0

20N

POINPUT020N

PIP2401

PIU2607

NLIN

PUT0

20P

POINPUT020P

PIP2602

PIU2806

NLIN

PUT0

30N

POINPUT030N

PIP2601

PIU2807

NLIN

PUT0

30P

POINPUT030P

PIP2802

PIU3006

NLIN

PUT0

40N

POINPUT040N

PIP2801

PIU3007

NLIN

PUT0

40P

POINPUT040P

PIP2102

PIU2306

NLIN

PUT0

50N

POINPUT050N

PIP2101

PIU2307

NLIN

PUT0

50P

POINPUT050P

PIP2302

PIU2506

NLIN

PUT0

60N

POINPUT060N

PIP2301

PIU2507

NLIN

PUT0

60P

POINPUT060P

PIP2502

PIU2706

NLIN

PUT0

70N

POINPUT070N

PIP2501

PIU2707

NLIN

PUT0

70P

POINPUT070P

PIP2702

PIU2906

NLIN

PUT0

80N

POINPUT080N

PIP2701

PIU2907

NLIN

PUT0

80P

POINPUT080P

PIU3203

NLLVPECL0CALIB0N

POLVPECL0CALIB0N

PIU3202

NLLVPECL0CALIB0P

POLVPECL0CALIB0P

PIU3303

NLLV

PECL

0EXT

RA0S

FP01

10N

POLV

PECL

0EXT

RA0S

FP01

10N

PIU3302

NLLV

PECL

0EXT

RA0S

FP01

10P

POLVPECL0EXTRA0SFP0110P

PIU2403

NLLVPECL0INPUT010N

POLVPECL0INPUT010N

PIU2402

NLLVPECL0INPUT010P

POLVPECL0INPUT010P

PIU2603

NLLVPECL0INPUT020N

POLVPECL0INPUT020N

PIU2602

NLLVPECL0INPUT020P

POLVPECL0INPUT020P

PIU2803

NLLVPECL0INPUT030N

POLVPECL0INPUT030N

PIU2802

NLLVPECL0INPUT030P

POLVPECL0INPUT030P

PIU3003

NLLVPECL0INPUT040N

POLVPECL0INPUT040N

PIU3002

NLLVPECL0INPUT040P

POLV

PECL

0INP

UT04

0P

PIU2303

NLLVPECL0INPUT050N

POLVPECL0INPUT050N

PIU2302

NLLVPECL0INPUT050P

POLVPECL0INPUT050P

PIU2503

NLLVPECL0INPUT060N

POLVPECL0INPUT060N

PIU2502

NLLVPECL0INPUT060P

POLVPECL0INPUT060P

PIU2703

NLLVPECL0INPUT070N

POLVPECL0INPUT070N

PIU2702

NLLVPECL0INPUT070P

POLVPECL0INPUT070P

PIU2903

NLLVPECL0INPUT080N

POLV

PECL

0INP

UT08

0NPIU2902

NLLVPECL0INPUT080P

POLV

PECL

0INP

UT08

0P

PIU3103

NLLV

PECL

0PED

ESTA

L0N

POLVPECL0PEDESTAL0N

PIU3102

NLLV

PECL

0PED

ESTA

L0P

POLVPECL0PEDESTAL0P

PIU3403

NLLV

PECL

0TRI

GDEL

AYED

0DIF

0NPOLVPECL0TRIGDELAYED0DIF0N

PIU3402

NLLVPECL0TRIGDELAYED0DIF0P

POLVPECL0TRIGDELAYED0DIF0P

PIU2301

PIU2304

PIU2401

PIU2404

PIU2501

PIU2504

PIU2601

PIU2604

PIU2701

PIU2704

PIU2801

PIU2804

PIU2901

PIU2904

PIU3001

PIU3004

PIU3101

PIU3104

PIU3201

PIU3204

PIU3301

PIU3304

PIU3401

PIU3404

PIP2902

PIU3106

NLPEDESTAL0N

POPEDESTAL0N

PIP2901

PIU3107

NLPEDESTAL0P

POPEDESTAL0P

PIP3202

PIU3406

NLTR

IGDE

LAYE

D0DI

F0N

POTRIGDELAYED0DIF0N

PIP3201

PIU3407

NLTR

IGDE

LAYE

D0DI

F0P

POTRIGDELAYED0DIF0P

POCALIB0N

POCALIB0P

POEXTRA0SFP0110N

POEXTRA0SFP0110P

POINPUT010N

POINPUT010P

POINPUT020N

POINPUT020P

POINPUT030N

POINPUT030P

POINPUT040N

POINPUT040P

POINPUT050N

POINPUT050P

POINPUT060N

POINPUT060P

POINPUT070N

POINPUT070P

POINPUT080N

POINPUT080P

POLVPECL0CALIB0N

POLVPECL0CALIB0P

POLV

PECL

0EXT

RA0S

FP01

10N


POLVPECL0INPUT010N

POLVPECL0INPUT010P

POLVPECL0INPUT020N

POLVPECL0INPUT020P

POLVPECL0INPUT030N

POLVPECL0INPUT030P

POLVPECL0INPUT040N

POLV

PECL

0INP

UT04

0P

POLVPECL0INPUT050N

POLVPECL0INPUT050P

POLVPECL0INPUT060N

POLVPECL0INPUT060P

POLVPECL0INPUT070N

POLVPECL0INPUT070P

POLV

PECL

0INP

UT08

0NPO

LVPE

CL0I

NPUT

080P

POLVPECL0PEDESTAL0N

POLVPECL0PEDESTAL0P

POLVPECL0TRIGDELAYED0DIF0N


POPEDESTAL0N

POPEDESTAL0P

POTRIGDELAYED0DIF0N

POTRIGDELAYED0DIF0P

Figure A.19: TIB: LVPECL to LVDS translators

230 A. Schematics

11

22

33

44

55

66

77

88

DD

CC

BB

AA

Title

Num

ber

Rev

ision

Size A2

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\N

eigh

bour

s.Sch

Doc

Dra

wn

By:

TX_F

AU

LT_0

TX_D

ISA

BLE

_0

LOS_

0

GN

DG

ND

GN

DG

ND

LVPE

CL_

OU

TPU

T_0_

PLV

PEC

L_O

UTP

UT_

0_N

LVPE

CL_

INPU

T_1_

PLV

PEC

L_IN

PUT_

1_N

TX_F

AU

LT_1

TX_D

ISA

BLE

_1

LOS_

1

GN

D

GN

D

TX_F

AU

LT_2

TX_D

ISA

BLE

_2

LOS_

2

GN

D

GN

D

TX_F

AU

LT_3

TX_D

ISA

BLE

_3

LOS_

3

GN

D

GN

D

TX_F

AU

LT_4

TX_D

ISA

BLE

_4

LOS_

4

GN

D

GN

DTX

_FA

ULT

_5TX

_DIS

AB

LE_5

LOS_

5

GN

D

GN

D

TX_F

AU

LT_6

TX_D

ISA

BLE

_6

LOS_

6

GN

D

GN

DTX

_FA

ULT

_7TX

_DIS

AB

LE_7

LOS_

7

GN

D

GN

D

GN

D

GN

D

LVPE

CL_

OU

TPU

T_1_

PLV

PEC

L_O

UTP

UT_

1_N

LVPE

CL_

INPU

T_2_

PLV

PEC

L_IN

PUT_

2_N

GN

D

GN

D

LVPE

CL_

OU

TPU

T_2_

PLV

PEC

L_O

UTP

UT_

2_N

LVPE

CL_

INPU

T_3_

PLV

PEC

L_IN

PUT_

3_N

GN

D

GN

D

LVPE

CL_

OU

TPU

T_3_

PLV

PEC

L_O

UTP

UT_

3_N

LVPE

CL_

INPU

T_4_

PLV

PEC

L_IN

PUT_

4_N

GN

D

GN

D

LVPE

CL_

OU

TPU

T_7_

PLV

PEC

L_O

UTP

UT_

7_N

LVPE

CL_

INPU

T_8_

PLV

PEC

L_IN

PUT_

8_N

GN

D

GN

D

LVPE

CL_

OU

TPU

T_6_

PLV

PEC

L_O

UTP

UT_

6_N

LVPE

CL_

INPU

T_7_

PLV

PEC

L_IN

PUT_

7_N

GN

D

GN

D

LVPE

CL_

OU

TPU

T_5_

PLV

PEC

L_O

UTP

UT_

5_N

LVPE

CL_

INPU

T_6_

PLV

PEC

L_IN

PUT_

6_N

GN

D

GN

D

LVPE

CL_

OU

TPU

T_4_

PLV

PEC

L_O

UTP

UT_

4_N

LVPE

CL_

INPU

T_5_

PLV

PEC

L_IN

PUT_

5_N

100n

F

C24

2C

ap S

emi

100n

F

C24

4C

ap S

emi

1uH

L9In

duct

or

1uH

L11

Indu

ctor

10uF

C24

5C

ap S

emi

GN

D

GN

D GN

D

100n

F

C24

6C

ap S

emi

10uF

C24

7C

ap S

emi

GN

DG

ND

+3.3

V10

0nF

C24

3C

ap S

emi

100n

F

C24

8C

ap S

emi

1uH

L10

Indu

ctor

1uH

L12

Indu

ctor

10uF

C24

9C

ap S

emi

GN

D

GN

D

GN

D

100n

F

C25

0C

ap S

emi

10uFC

251

Cap

Sem

i

GN

DG

ND

+3.3

V

100n

F

C25

2C

ap S

emi

C25

4C

ap S

emi

1uH

L13

Indu

ctor

1uH

L14

Indu

ctor

10uF

C25

5C

ap S

emi

GN

D

GN

D

GN

D

100n

F

C25

6C

ap S

emi

10uF

C25

7C

ap S

emi

GN

DG

ND

+3.3

V

100n

F

C25

3C

ap S

emi

100n

F

C25

8C

ap S

emi

1uH

L15

Indu

ctor

1uH

L16

Indu

ctor

10uF

C25

9C

ap S

emi

GN

D

GN

D GN

D

100n

F

C26

0C

ap S

emi

10uF

C26

1C

ap S

emi

GN

DG

ND

+3.3

V

100n

F

C26

3C

ap S

emi

100n

F

C26

8C

ap S

emi

1uH

L18

Indu

ctor

1uH

L20

Indu

ctor

10uF

C26

9C

ap S

emi

GN

D

GN

D

GN

D

100n

F

C27

0C

ap S

emi

10uF

C27

1C

ap S

emi

GN

DG

ND

+3.3

V

100n

F

C26

2C

ap S

emi

100n

F

C26

4C

ap S

emi

1uH

L17

Indu

ctor

1uH

L19

Indu

ctor

10uF

C26

5C

ap S

emi

GN

D

GN

D

GN

D

100n

F

C26

6C

ap S

emi

10uF

C26

7C

ap S

emi

GN

DG

ND

+3.3

V

100n

F

C27

3C

ap S

emi

100n

F

C27

8C

ap S

emi

1uH

L22

Indu

ctor

1uH

L24

Indu

ctor

10uF

C27

9C

ap S

emi

GN

D

GN

D

GN

D

100n

F

C28

0C

ap S

emi

10uF

C28

1C

ap S

emi

GN

DG

ND

+3.3

V

100n

F

C27

2C

ap S

emi

100n

F

C27

4C

ap S

emi

1uH

L21

Indu

ctor

1uH

L23

Indu

ctor

10uF

C27

5C

ap S

emi

GN

D

GN

D

GN

D

100n

F

C27

6C

ap S

emi

10uF

C27

7C

ap S

emi

GN

DG

ND

+3.3

V

10K

R69

Res

3

10K

R77

Res

3

+3.3

V

+3.3

V

10K

R53

Res

3

+3.3

V 10K

R58

Res

3

+3.3

V

10K

R71

Res

3

+3.3

V

10K

R78

Res

3

+3.3

V10K

R49

Res

3

+3.3

V 10K

R57

Res

3

+3.3

V

10K

R59

Res

3

+3.3

V 10K

R67

Res

3

+3.3

V

10K

R40

Res

3

+3.3

V

10K

R48

Res

3

+3.3

V

10K

R68

Res

3

+3.3

V

10K

R60

Res

3

+3.3

V

10K

R39

Res

3

+3.3

V 10K

R47

Res

3

+3.3

V

Luis

A. T

ejed

or

Ster

eo T

rigge

r

1N

eigh

bour

s

Vee

T1A

Tx F

ault

2ATx

Disa

ble

3A

MO

D-D

EF2

4A

MO

D-D

EF1

5A

MO

D-D

EF0

6A

Rat

e Se

lect

ion

7A

LOS

8A

Vee

R9A

Vee

R10

AV

eeR

11A

RD

-12

AR

D+

13A

Vee

R14

AV

ccR

15A

Vcc

T16

AV

eeT

17A

TD+

18A

TD-

19A

Vee

T20

A

0 0

J38A

SFP-

1761

008-

1

Vee

T1C

Tx F

ault

2C

Tx D

isabl

e3C

MO

D-D

EF2

4C

MO

D-D

EF1

5CM

OD

-DEF

06C

Rat

e Se

lect

ion

7C

LOS

8C

Vee

R9C

Vee

R10

CV

eeR

11C

RD

-12

CR

D+

13C

Vee

R14

CV

ccR

15C

Vcc

T16

CV

eeT

17C

TD+

18C

TD-

19C

Vee

T20

CJ3

8C

SFP-

1761

008-

1

Vee

T1B

Tx F

ault

2BTx

Disa

ble

3B

MO

D-D

EF2

4B

MO

D-D

EF1

5B

MO

D-D

EF0

6B

Rat

e Se

lect

ion

7B

LOS

8B

Vee

R9B

Vee

R10

BV

eeR

11B

RD

-12

BR

D+

13B

Vee

R14

BV

ccR

15B

Vcc

T16

BV

eeT

17B

TD+

18B

TD-

19B

Vee

T20

BJ5

0B

SFP-

1761

008-

1

Vee

T1D

Tx F

ault

2DTx

Disa

ble

3D

MO

D-D

EF2

4D

MO

D-D

EF1

5D

MO

D-D

EF0

6D

Rat

e Se

lect

ion

7D

LOS

8D

Vee

R9D

Vee

R10

DV

eeR

11D

RD

-12

DR

D+

13D

Vee

R14

DV

ccR

15D

Vcc

T16

DV

eeT

17D

TD+

18D

TD-

19D

Vee

T20

DJ5

0D

SFP-

1761

008-

1Vee

T1B

Tx F

ault

2BTx

Disa

ble

3B

MO

D-D

EF2

4B

MO

D-D

EF1

5B

MO

D-D

EF0

6B

Rat

e Se

lect

ion

7B

LOS

8B

Vee

R9B

Vee

R10

BV

eeR

11B

RD

-12

BR

D+

13B

Vee

R14

BV

ccR

15B

Vcc

T16

BV

eeT

17B

TD+

18B

TD-

19B

Vee

T20

BJ3

8B

SFP-

1761

008-

1

Vee

T1D

Tx F

ault

2D

Tx D

isabl

e3D

MO

D-D

EF2

4D

MO

D-D

EF1

5D

MO

D-D

EF0

6D

Rat

e Se

lect

ion

7DLO

S8D

Vee

R9D

Vee

R10

DV

eeR

11D

RD

-12

DR

D+

13D

Vee

R14

DV

ccR

15D

Vcc

T16

DV

eeT

17D

TD+

18D

TD-

19D

Vee

T20

DJ3

8D

SFP-

1761

008-

1

Vee

T1A

Tx F

ault

2A

Tx D

isabl

e3A

MO

D-D

EF2

4A

MO

D-D

EF1

5A

MO

D-D

EF0

6A

Rat

e Se

lect

ion

7ALO

S8A

Vee

R9A

Vee

R10

AV

eeR

11A

RD

-12

AR

D+

13A

Vee

R14

AV

ccR

15A

Vcc

T16

AV

eeT

17A

TD+

18A

TD-

19A

Vee

T20

A

0 0

J50A

SFP-

1761

008-

1

Vee

T1C

Tx F

ault

2C

Tx D

isabl

e3C

MO

D-D

EF2

4C

MO

D-D

EF1

5C

MO

D-D

EF0

6CR

ate

Sele

ctio

n7C

LOS

8C

Vee

R9C

Vee

R10

CV

eeR

11C

RD

-12

CR

D+

13C

Vee

R14

CV

ccR

15C

Vcc

T16

CV

eeT

17C

TD+

18C

TD-

19C

Vee

T20

CJ5

0C

SFP-

1761

008-

1

LVPE

CL_

OU

TPU

T_0_

PLV

PEC

L_O

UTP

UT_

0_N

LVPE

CL_

INPU

T_1_

PLV

PEC

L_IN

PUT_

1_N

LVPE

CL_

OU

TPU

T_4_

PLV

PEC

L_O

UTP

UT_

4_N

LVPE

CL_

INPU

T_5_

PLV

PEC

L_IN

PUT_

5_N

LVPE

CL_

OU

TPU

T_1_

PLV

PEC

L_O

UTP

UT_

1_N

LVPE

CL_

INPU

T_2_

PLV

PEC

L_IN

PUT_

2_N

LVPE

CL_

OU

TPU

T_5_

PLV

PEC

L_O

UTP

UT_

5_N

LVPE

CL_

INPU

T_6_

PLV

PEC

L_IN

PUT_

6_N

LVPE

CL_

OU

TPU

T_2_

PLV

PEC

L_O

UTP

UT_

2_N

LVPE

CL_

INPU

T_3_

PLV

PEC

L_IN

PUT_

3_N

LVPE

CL_

OU

TPU

T_6_

PLV

PEC

L_O

UTP

UT_

6_N

LVPE

CL_

INPU

T_7_

PLV

PEC

L_IN

PUT_

7_N

LVPE

CL_

OU

TPU

T_3_

PLV

PEC

L_O

UTP

UT_

3_N

LVPE

CL_

INPU

T_4_

PLV

PEC

L_IN

PUT_

4_N

LVPE

CL_

OU

TPU

T_7_

PLV

PEC

L_O

UTP

UT_

7_N

LVPE

CL_

INPU

T_8_

PLV

PEC

L_IN

PUT_

8_N

10K

R41

Res

3

10K

R43

Res

3

10K

R45

Res

3

+3.3

V+3

.3V

+3.3

V

10K

R63

Res

3

10K

R65

Res

3

10K

R66

Res

3

+3.3

V+3

.3V

+3.3

V10

K

R61

Res

3

10K

R62

Res

3

10K

R64

Res

3

+3.3

V+3

.3V

+3.3

V

10K

R74

Res

3

10K

R75

Res

3

10K

R76

Res

3

+3.3

V+3

.3V

+3.3

V10

K

R70

Res

3

10K

R72

Res

3

10K

R73

Res

3

+3.3

V+3

.3V

+3.3

V

10K

R54

Res

3

10K

R55

Res

3

10K

R56

Res

3

+3.3

V+3

.3V

+3.3

V

10K

R50

Res

3

10K

R51

Res

3

10K

R52

Res

3

+3.3

V+3

.3V

+3.3

V

10K

R42

Res

3

10K

R44

Res

3

10K

R46

Res

3

+3.3

V+3

.3V

+3.3

V

VC

C_T

_0V

CC

_R_0

DEF

2_0

DEF

1_0

DEF

0_0

VC

C_T

_2V

CC

_R_2

DEF

2_2

DEF

1_2

DEF

0_2

VC

C_T

_1V

CC

_R_1

DEF

2_1

DEF

1_1

DEF

0_1

VC

C_T

_3V

CC

_R_3

DEF

2_3

DEF

1_3

DEF

0_3

VC

C_T

_4V

CC

_R_4

DEF

2_4

DEF

1_4

DEF

0_4

VC

C_T

_5V

CC

_R_5

DEF

2_5

DEF

1_5

DEF

0_5

VC

C_T

_6V

CC

_R_6

DEF

2_6

DEF

1_6

DEF

0_6

VC

C_T

_7V

CC

_R_7

DEF

2_7

DEF

1_7

DEF

0_7

1 2

P35

Hea

der 2

1 2

P36

Hea

der 2

LVPE

CL_

OU

TPU

T_0_

PLV

PEC

L_O

UTP

UT_

0_N

LVPE

CL_

INPU

T_1_

PLV

PEC

L_IN

PUT_

1_N

1 2

P33

Hea

der 2

1 2

P34

Hea

der 2

LVPE

CL_

OU

TPU

T_1_

PLV

PEC

L_O

UTP

UT_

1_N

LVPE

CL_

INPU

T_2_

PLV

PEC

L_IN

PUT_

2_N

1 2

P37

Hea

der 2

1 2

P38

Hea

der 2

LVPE

CL_

OU

TPU

T_2_

PLV

PEC

L_O

UTP

UT_

2_N

LVPE

CL_

INPU

T_3_

PLV

PEC

L_IN

PUT_

3_N

1 2

P39

Hea

der 2

1 2

P40

Hea

der 2

LVPE

CL_

OU

TPU

T_3_

PLV

PEC

L_O

UTP

UT_

3_N

LVPE

CL_

INPU

T_4_

PLV

PEC

L_IN

PUT_

4_N

1 2

P43

Hea

der 2

1 2

P44

Hea

der 2

LVPE

CL_

OU

TPU

T_4_

PLV

PEC

L_O

UTP

UT_

4_N

LVPE

CL_

INPU

T_5_

PLV

PEC

L_IN

PUT_

5_N

1 2

P41

Hea

der 2

1 2

P42

Hea

der 2

LVPE

CL_

OU

TPU

T_5_

PLV

PEC

L_O

UTP

UT_

5_N

LVPE

CL_

INPU

T_6_

PLV

PEC

L_IN

PUT_

6_N

1 2

P47

Hea

der 2

1 2

P48

Hea

der 2

LVPE

CL_

OU

TPU

T_6_

PLV

PEC

L_O

UTP

UT_

6_N

LVPE

CL_

INPU

T_7_

PLV

PEC

L_IN

PUT_

7_N

1 2

P45

Hea

der 2

1 2

P46

Hea

der 2

LVPE

CL_

OU

TPU

T_7_

PLV

PEC

L_O

UTP

UT_

7_N

LVPE

CL_

INPU

T_8_

PLV

PEC

L_IN

PUT_

8_N

J34

Sock

et J36

Sock

et

J39

Sock

et

J37

Sock

etJ35

Sock

et

J40

Sock

et

J42

Sock

etJ41

Sock

et

J45

Sock

et

J44

Sock

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Sock

et

J46

Sock

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J51

Sock

etJ48

Sock

et J53

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J49

Sock

etJ47

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et J52

Sock

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J57

Sock

etJ55

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et

J59

Sock

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J56

Sock

etJ54

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et J58

Sock

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GN

D

100u

F

C31

4

Cap

Sem

i

100n

F

C31

6

Cap

Sem

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100p

F

C31

5

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10uF

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DG

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100u

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DG

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PIC24201PIC24202CO

C242

PIC24301PIC24302CO

C243

PIC24401PIC24402CO

C244

PIC24501PIC24502CO

C245

PIC24601PIC24602CO

C246

PIC24701PIC24702CO

C247

PIC24801PIC24802CO

C248

PIC24901PIC24902CO

C249

PIC25001PIC25002CO

C250

PIC25101PIC25102CO

C251

PIC25201PIC25202CO

C252

PIC25301PIC25302CO

C253

PIC25401PIC25402CO

C254

PIC25501PIC25502CO

C255

PIC25601PIC25602CO

C256

PIC25701PIC25702CO

C257

PIC25801PIC25802CO

C258

PIC25901PIC25902CO

C259

PIC26001PIC26002CO

C260

PIC26101PIC26102CO

C261

PIC26201PIC26202CO

C262

PIC26301PIC26302CO

C263

PIC26401PIC26402CO

C264

PIC26501PIC26502CO

C265

PIC26601PIC26602CO

C266

PIC26701PIC26702CO

C267


PIC26901PIC26902CO

C269

PIC27001PIC27002CO

C270

PIC27101PIC27102CO

C271

PIC27201PIC27202CO

C272

PIC27301PIC27302CO

C273

PIC27401PIC27402CO

C274

PIC27501PIC27502CO

C275

PIC27601PIC27602CO

C276

PIC27701PIC27702CO

C277

PIC27801PIC27802CO

C278

PIC27901PIC27902CO

C279

PIC28001PIC28002CO

C280

PIC28101PIC28102CO

C281

PIC3

1401

PIC3

1402

COC3

14

PIC315

01PIC

31502

COC3

15

PIC3

1601

PIC3

1602

COC3

16

PIC3

1701

PIC3

1702

COC3

17

PIC3

1801

PIC3

1802

COC3

18

PIC319

01PIC

31902

COC3

19

PIC3

2001

PIC3

2002

COC3

20

PIC321

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32102

COC3

21

PIJ3

401

COJ34

PIJ3

501

COJ35

PIJ3601

COJ3

6PIJ3701

COJ3

7

PIJ3800

PIJ3801A

PIJ3802A

PIJ3803A

PIJ3804A

PIJ3805A

PIJ3806A

PIJ3807A

PIJ3808A

PIJ3809A

PIJ38010A

PIJ38011A

PIJ38012A

PIJ38013A

PIJ38014A

PIJ38015A

PIJ38016A

PIJ38017A

PIJ38018A

PIJ38019A

PIJ38020A

COJ3

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PIJ3802B

PIJ3803B

PIJ3804B

PIJ3805B

PIJ3806B

PIJ3807B

PIJ3

808B

PIJ3809B

PIJ38010B

PIJ38011B

PIJ38012B

PIJ38013B

PIJ38014B

PIJ38015B

PIJ38016B

PIJ38017B

PIJ38018B

PIJ38019B

PIJ38020B

COJ38B

PIJ3801C

PIJ3802C

PIJ3803C

PIJ3804C

PIJ3805C

PIJ3806C

PIJ3807C

PIJ3808C

PIJ3809C

PIJ38010C

PIJ38011C

PIJ38012C

PIJ38013C

PIJ38014C

PIJ38015C

PIJ38016C

PIJ38017C

PIJ38018C

PIJ38019C

PIJ38020C

COJ3

8C

PIJ3801D

PIJ3802D

PIJ3803D

PIJ3804D

PIJ3805D

PIJ3806D

PIJ3807D

PIJ3808D

PIJ3809D

PIJ38010D

PIJ38011D

PIJ38012D

PIJ38013D

PIJ38014D

PIJ38015D

PIJ38016D

PIJ38017D

PIJ38018D

PIJ38019D

PIJ38020D

COJ3

8D

PIJ3901

COJ39

PIJ4001

COJ4

0

PIJ4101

COJ41

PIJ4201

COJ42

PIJ4301

COJ43

PIJ4401

COJ44

PIJ4501

COJ45

PIJ4601

COJ4

6 PIJ4701

COJ47

PIJ4801

COJ48

PIJ4901

COJ49

PIJ5000

PIJ5001A

PIJ5002A

PIJ5003A

PIJ5004A

PIJ5

005A

PIJ5006A

PIJ5007A

PIJ5008A

PIJ5009A

PIJ50010A

PIJ50011A

PIJ50012A

PIJ50013A

PIJ50014A

PIJ50015A

PIJ50016A

PIJ50017A

PIJ50018A

PIJ50019A

PIJ50020A

COJ5

0APIJ5001B

PIJ5002B

PIJ5003B

PIJ5004B

PIJ5005B

PIJ5006B

PIJ5

007B

PIJ5008B

PIJ5009B

PIJ50010B

PIJ50011B

PIJ50012B

PIJ50013B

PIJ50014B

PIJ50015B

PIJ50016B

PIJ50017B

PIJ50018B

PIJ50019B

PIJ50020B

COJ5

0B

PIJ5001C

PIJ5002C

PIJ5003C

PIJ5004C

PIJ5005C

PIJ5006C

PIJ5007C

PIJ5008C

PIJ5009C

PIJ50010C

PIJ50011C

PIJ50012C

PIJ50013C

PIJ50014C

PIJ50015C

PIJ50016C

PIJ50017C

PIJ50018C

PIJ50019C

PIJ50020C

COJ50C

PIJ5001D

PIJ5002D

PIJ5

003D

PIJ5004D

PIJ5005D

PIJ5006D

PIJ5007D

PIJ5008D

PIJ5009D

PIJ50010D

PIJ50011D

PIJ50012D

PIJ50013D

PIJ50014D

PIJ50015D

PIJ50016D

PIJ50017D

PIJ50018D

PIJ50019D

PIJ50020D

COJ5

0D

PIJ5101

COJ51

PIJ5201

COJ52

PIJ5301

COJ53

PIJ5401

COJ54

PIJ5501

COJ55

PIJ5601

COJ56

PIJ5701

COJ57

PIJ5801

COJ58

PIJ5901

COJ59

PIL901

PIL902COL

9PI

L100

1PI

L100

2COL10

PIL1

101

PIL1

102 COL

11

PIL1

201

PIL1

202 COL

12

PIL1

301

PIL1

302COL1

3

PIL140

1PIL

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14PI

L150

1PI

L150

2COL15

PIL1

601

PIL1

602 COL

16

PIL1

701

PIL1

702COL1

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PIL180

1PIL

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L18

PIL190

1PIL

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19PI

L200

1PI

L200

2 COL20

PIL2

101

PIL2

102COL

21

PIL2

201

PIL2

202CO

L22

PIL2

301

PIL2

302 COL

23

PIL2

401

PIL2

402 COL

24

PIL2

801

PIL2

802

COL28

PIL2

901

PIL2

902

COL29

PIP3301

PIP3302COP

33

PIP3

401

PIP3402

COP34

PIP3501

PIP3502COP

35

PIP3601

PIP3602COP

36

PIP3701

PIP3702

COP37

PIP3801

PIP3802COP

38

PIP3901

PIP3902

COP39

PIP4001

PIP4002COP

40

PIP4101

PIP4102

COP4

1

PIP4201

PIP4202CO

P42

PIP4301

PIP4302

COP43

PIP4401

PIP4402COP

44

PIP4501

PIP4502COP

45

PIP4

601

PIP4602

COP46

PIP4701

PIP4702

COP4

7

PIP4801

PIP4802CO

P48

PIR3901PIR3902COR

39

PIR4001PIR4002 COR4

0

PIR4101PIR4102 COR4

1

PIR4201PIR4202 COR42

PIR4301PIR4302COR

43

PIR4401PIR4402 COR4

4

PIR4501PIR4502CO

R45

PIR4601PIR4602 COR4

6

PIR4701 PIR4702

COR4

7PIR4801 PIR4802

COR4

8

PIR4901PIR4902COR

49

PIR5001PIR5002COR

50

PIR5101PIR5102 COR5

1

PIR5201PIR5202 COR5

2

PIR5301PIR5302CO

R53

PIR5401PIR5402 COR5

4

PIR5501PIR5502CO

R55

PIR5601PIR5602COR

56PIR5701 PIR5702

COR57

PIR5801 PIR5802

COR58

PIR5901PIR5902COR

59

PIR6001PIR6002COR

60

PIR6101PIR6102COR

61

PIR6201PIR6202 COR6

2

PIR6301PIR6302COR

63

PIR6401PIR6402 COR6

4

PIR6501PIR6502 COR6

5

PIR6601PIR6602 COR6

6

PIR6701 PIR6702

COR67

PIR6801 PIR6802COR6

8

PIR6901PIR6902 COR6

9

PIR7001PIR7002 COR7

0

PIR7101PIR7102COR

71

PIR7201PIR7202COR

72

PIR7301PIR7302CO

R73

PIR7401PIR7402COR

74

PIR7501PIR7502 COR7

5

PIR7601PIR7602 COR7

6

PIR7701PIR7702 COR7

7

PIR7801 PIR7802

COR78

PIC24602PIC24702

PIC25002PIC25102

PIC25602PIC25702

PIC26002PIC26102

PIC26602PIC26702

PIC27002PIC27102

PIC27602PIC27702

PIC28002PIC28102

PIL901

PIL1

001

PIL1

101

PIL1

201

PIL1

301

PIL140

1

PIL1

501

PIL1

601

PIL1

701

PIL180

1PIL

1901

PIL2

001

PIL2

101

PIL2

201

PIL2

301

PIL2

401

PIR3902PIR4002

PIR4102PIR4202

PIR4302PIR4402

PIR4502PIR4602

PIR4702PIR4802

PIR4902

PIR5002PIR5102

PIR5202PIR5302

PIR5402PIR5502

PIR5602

PIR5702

PIR5802 PIR5902

PIR6002PIR6102

PIR6202PIR6302

PIR6402PIR6502

PIR6602

PIR6702

PIR6802

PIR6902

PIR7002PIR7102

PIR7202PIR7302

PIR7402PIR7502

PIR7602

PIR7701

PIR7802

PIJ3806A

PIR4501NLDEF000

PIJ3806B

PIR4601NLDEF001

PIJ3806C

PIR5201NLDEF002

PIJ3806D

PIR5601NLDEF003

PIJ5006A

PIR6601NLDEF004

PIJ5006B

PIR6401NLDEF005

PIJ5006C

PIR7601NLDEF006

PIJ5006D

PIR7301NLDEF007

PIJ3805A

PIR4301NLDEF100

PIJ3805B

PIR4401NLDEF101

PIJ3805C

PIR5101NLDEF102

PIJ3805D

PIR5501NLDEF103

PIJ5

005A

PIR6501NLDEF104

PIJ5005B

PIR6201NLDEF105

PIJ5005C

PIR7501NLDEF106

PIJ5005D

PIR7201NLDEF107

PIJ3804A

PIR4101NLDEF200

PIJ3804B

PIR4201NLDEF201

PIJ3804C

PIR5001NLDEF202

PIJ3804D

PIR5401NLDEF203

PIJ5004A

PIR6301NLDEF204

PIJ5004B

PIR6101NLDEF205

PIJ5004C

PIR7401NLDEF206

PIJ5004D

PIR7001NLDEF207

PIC24202PIC24302

PIC24401PIC24501

PIC24601PIC24701

PIC24801PIC24901

PIC25001PIC25101

PIC25202

PIC25302

PIC25401PIC25501

PIC25601PIC25701

PIC25801PIC25901

PIC26001PIC26101

PIC26202

PIC26302

PIC26401PIC26501

PIC26601PIC26701

PIC26801PIC26901

PIC27001PIC27101

PIC27202

PIC27302

PIC27401PIC27501

PIC27601PIC27701

PIC27801PIC27901

PIC28001PIC28101

PIC3

1402

PIC315

01

PIC3

1602

PIC3

1701

PIC3

1802

PIC319

01

PIC3

2002

PIC321

01

PIJ3801A

PIJ3801B

PIJ3801C

PIJ3801D

PIJ3809A

PIJ3809B

PIJ3809C

PIJ3809D

PIJ38010A

PIJ38010B

PIJ38010C

PIJ38010D

PIJ38011A

PIJ38011B

PIJ38011C

PIJ38011D

PIJ38014A

PIJ38014B

PIJ38014C

PIJ38014D

PIJ38017A

PIJ38017B

PIJ38017C

PIJ38017D

PIJ38020A

PIJ38020B

PIJ38020C

PIJ38020D

PIJ5001A

PIJ5001B

PIJ5001C

PIJ5001D

PIJ5009A

PIJ5009B

PIJ5009C

PIJ5009D

PIJ50010A

PIJ50010B

PIJ50010C

PIJ50010D

PIJ50011A

PIJ50011B

PIJ50011C

PIJ50011D

PIJ50014A

PIJ50014B

PIJ50014C

PIJ50014D

PIJ50017A

PIJ50017B

PIJ50017C

PIJ50017D

PIJ50020A

PIJ50020B

PIJ50020C

PIJ50020D

PIL2

802

PIL2

902

PIJ38012A

PIP3602

NLLVPECL0INPUT010N

POLVPECL0INPUT010N

PIJ38013A

PIP3601

NLLVPECL0INPUT010P

POLVPECL0INPUT010P

PIJ38012B

PIP3402

NLLVPECL0INPUT020N

POLVPECL0INPUT020N

PIJ38013B

PIP3

401

NLLVPECL0INPUT020P

POLVPECL0INPUT020P

PIJ38012C

PIP3802

NLLV

PECL

0INP

UT03

0N

POLVPECL0INPUT030N

PIJ38013C

PIP3801

NLLVPECL0INPUT030P

POLVPECL0INPUT030P

PIJ38012D

PIP4002

NLLV

PECL

0INP

UT04

0N

POLVPECL0INPUT040N

PIJ38013D

PIP4001

NLLVPECL0INPUT040P

POLVPECL0INPUT040P

PIJ50012A

PIP4402

NLLV

PECL

0INP

UT05

0N

POLVPECL0INPUT050N

PIJ50013A

PIP4401

NLLVPECL0INPUT050P

POLVPECL0INPUT050P

PIJ50012B

PIP4202

NLLVPECL0INPUT060N

POLVPECL0INPUT060N

PIJ50013B

PIP4201

NLLV

PECL

0INP

UT06

0P

POLVPECL0INPUT060P

PIJ50012C

PIP4802

NLLVPECL0INPUT070N

POLVPECL0INPUT070N

PIJ50013C

PIP4801

NLLV

PECL

0INP

UT07

0P

POLVPECL0INPUT070P

PIJ50012D

PIP4602

NLLVPECL0INPUT080N

POLVPECL0INPUT080N

PIJ50013D

PIP4

601

NLLVPECL0INPUT080P

POLVPECL0INPUT080P

PIJ38018A

PIP3502

NLLVPECL0OUTPUT000N

POLVPECL0OUTPUT000N

PIJ38019A

PIP3501

NLLVPECL0OUTPUT000P

POLVPECL0OUTPUT000P

PIJ38018B

PIP3302

NLLV

PECL

0OUT

PUT0


PIJ38019B

PIP3301

NLLV

PECL

0OUT

PUT0

10P

POLV

PECL

0OUT

PUT0

10P

PIJ38018C

PIP3702

NLLVPECL0OUTPUT020NPOLVPECL0OUTPUT020N

PIJ38019C

PIP3701

NLLV

PECL

0OUT

PUT0

20P

POLVPECL0OUTPUT020P

PIJ38018D

PIP3902

NLLVPECL0OUTPUT030N

POLVPECL0OUTPUT030N

PIJ38019D

PIP3901

NLLV

PECL

0OUT

PUT0

30P

POLVPECL0OUTPUT030P

PIJ50018A

PIP4302

NLLVPECL0OUTPUT040N

POLVPECL0OUTPUT040N

PIJ50019A

PIP4301

NLLVPECL0OUTPUT040P

POLV

PECL

0OUT

PUT0

40P

PIJ50018B

PIP4102

NLLVPECL0OUTPUT050N

POLVPECL0OUTPUT050N

PIJ50019B

PIP4101

NLLV

PECL

0OUT

PUT0

50P

POLVPECL0OUTPUT050P

PIJ50018C

PIP4702

NLLVPECL0OUTPUT060N

POLVPECL0OUTPUT060N

PIJ50019C

PIP4701

NLLVPECL0OUTPUT060P

POLVPECL0OUTPUT060P

PIJ50018D

PIP4502

NLLVPE

CL0OUT

PUT0

70N

POLVPECL0OUTPUT070N

PIJ50019D

PIP4501

NLLV

PECL

0OUT

PUT0

70P

POLVPECL0OUTPUT070P

PIC3

1401

PIC315

02

PIC3

1601

PIC3

1702

PIJ3800 PIL2

801

PIC3

1801

PIC319

02

PIC3

2001

PIC321

02

PIJ5000 PIL2

901

PIJ3

401

PIJ3803A

POTX0DISABLE00

PIJ3

501

PIJ3803B

POTX0DISABLE01

PIJ3601

PIJ3802A

PIR3901POTX0FAULT00

PIJ3701

PIJ3802B

PIR4001POTX0FAULT01

PIJ3802C

PIJ4201

PIR4901POTX0FAULT02

PIJ3802D

PIJ4401

PIR5301POTX0FAULT03

PIJ3803C

PIJ4101

POTX0DISABLE02

PIJ3803D

PIJ4301

POTX0DISABLE03

PIJ3807A

PIJ3807B

PIJ3807C

PIJ3807D

PIJ3808A

PIJ3901

PIR4701POLOS00

PIJ3

808B

PIJ4001

PIR4801POLOS01

PIJ3808C

PIJ4501

PIR5701POLOS02

PIJ3808D

PIJ4601

PIR5801POLOS03

PIJ4701

PIJ5003B

POTX0DISABLE05

PIJ4801

PIJ5003A

POTX0DISABLE04

PIJ4901

PIJ5002B

PIR5901POTX0FAULT05

PIJ5002A

PIJ5101

PIR6001POTX0FAULT04

PIJ5002C

PIJ5701

PIR7101POTX0FAULT06

PIJ5002D

PIJ5601

PIR6901POTX0FAULT07

PIJ5003C

PIJ5501

POTX0DISABLE06

PIJ5

003D

PIJ5401

POTX0DISABLE07

PIJ5007A

PIJ5

007B

PIJ5007C

PIJ5007D

PIJ5008A

PIJ5301

PIR6801POLOS04

PIJ5008B

PIJ5201

PIR6701POLOS05

PIJ5008C

PIJ5901

PIR7801POLOS06

PIJ5008D

PIJ5801

PIR7702POLOS07

PIC24402PIC24502

PIJ38015A

PIL1

102

NLVCC0R00

PIC24802PIC24902

PIJ38015B

PIL1

202

NLVCC0R01

PIC25402PIC25502

PIJ38015C

PIL140

2

NLVCC0R02

PIC25802PIC25902

PIJ38015D

PIL1

602

NLVCC0R03

PIC26802PIC26902

PIJ50015A

PIL2

002

NLVCC0R04

PIC26402PIC26502

PIJ50015B

PIL190

2

NLVCC0R05

PIC27802PIC27902

PIJ50015C

PIL2

402

NLVCC0R06

PIC27402PIC27502

PIJ50015D

PIL2

302

NLVCC0R07

PIC24201PIJ38016A

PIL902

NLVCC0T00

PIC24301PIJ38016B

PIL1

002

NLVCC0T01

PIC25201PIJ38016C

PIL1

302

NLVCC0T02

PIC25301PIJ38016D

PIL1

502

NLVCC0T03

PIC26301PIJ50016A

PIL180

2NLVCC0T04

PIC26201PIJ50016B

PIL1

702

NLVCC0T05

PIC27301PIJ50016C

PIL2

202

NLVCC0T06

PIC27201PIJ50016D

PIL2

102

NLVCC0T07

POLOS00

POLOS01

POLOS02

POLOS03

POLOS04

POLOS05

POLOS06

POLOS07

POLVPECL0INPUT010N

POLVPECL0INPUT010P

POLVPECL0INPUT020N

POLVPECL0INPUT020P

POLVPECL0INPUT030N

POLVPECL0INPUT030P

POLVPECL0INPUT040N

POLVPECL0INPUT040P

POLVPECL0INPUT050N

POLVPECL0INPUT050P

POLVPECL0INPUT060N

POLVPECL0INPUT060P

POLVPECL0INPUT070N

POLVPECL0INPUT070P

POLVPECL0INPUT080N

POLVPECL0INPUT080P

POLVPECL0OUTPUT000N

POLVPECL0OUTPUT000P

POLVPECL0OUTPUT010N

POLV

PECL

0OUT

PUT0

10P

POLVPECL0OUTPUT020N

POLVPECL0OUTPUT020P

POLVPECL0OUTPUT030N

POLVPECL0OUTPUT030P

POLVPECL0OUTPUT040N

POLV

PECL

0OUT

PUT0

40P

POLVPECL0OUTPUT050N

POLVPECL0OUTPUT050P

POLVPECL0OUTPUT060N

POLVPECL0OUTPUT060P

POLVPECL0OUTPUT070N

POLVPECL0OUTPUT070P

POTX0DISABLE00

POTX0DISABLE01

POTX0DISABLE02

POTX0DISABLE03

POTX0DISABLE04

POTX0DISABLE05

POTX0DISABLE06

POTX0DISABLE07

POTX0FAULT00

POTX0FAULT01

POTX0FAULT02

POTX0FAULT03

POTX0FAULT04

POTX0FAULT05

POTX0FAULT06

POTX0FAULT07

Figure A.20: TIB: Optical transceivers to/from neighbours

A. Schematics 231

11

22

33

44

55

66

77

88

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A3

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\SF

P_ca

lib_a

nd_D

elay

.Sch

Doc

Dra

wn

By:

TX_F

AU

LT_C

ALI

BTX

_DIS

AB

LE_C

ALI

B

LOS_

CA

LIB

GN

DG

ND

GN

DG

ND

LVPE

CL_

CA

LIB

_FB

_PLV

PEC

L_C

ALI

B_F

B_N

LVPE

CL_

CA

LIB

_PLV

PEC

L_C

ALI

B_N

100n

F

C1

Cap

Sem

i

100n

F

C2

Cap

Sem

i

1uH

L1In

duct

or

1uH

L2In

duct

or

10uF

C3

Cap

Sem

i

GN

D

GN

D GN

D

100n

F

C4

Cap

Sem

i10

uF

C5

Cap

Sem

i

GN

DG

ND

+3.3

V

10K

R1

Res

3

+3.3

V 10K

R5

Res

3

+3.3

V

TX_F

AU

LT_P

EDES

TAL

TX_D

ISA

BLE

_PED

ESTA

L

LOS_

PED

ESTA

L

GN

DG

ND

GN

DG

ND

LVPE

CL_

PED

ESTA

L_FB

_PLV

PEC

L_PE

DES

TAL_

FB_N

LVPE

CL_

PED

ESTA

L_P

LVPE

CL_

PED

ESTA

L_N

100n

F

C6

Cap

Sem

i

100n

F

C7

Cap

Sem

i

1uH

L3In

duct

or

1uH

L4In

duct

or

10uF

C8

Cap

Sem

i

GN

D

GN

D GN

D

100n

F

C9

Cap

Sem

i10

uF

C10

Cap

Sem

i

GN

DG

ND

+3.3

V

10K

R6

Res

3

+3.3

V 10K

R10

Res

3

+3.3

V

Luis

A. T

ejed

or

Ster

eo T

rigge

r

1

SFP_

calib

_and

_Del

ay

LVPE

CL_

CA

LIB

_FB

_PLV

PEC

L_C

ALI

B_F

B_N

LVPE

CL_

CA

LIB

_PLV

PEC

L_C

ALI

B_N

LVPE

CL_

PED

ESTA

L_FB

_PLV

PEC

L_PE

DES

TAL_

FB_N

LVPE

CL_

PED

ESTA

L_P

LVPE

CL_

PED

ESTA

L_N

10K

R2

Res

3

10K

R3

Res

3

10K

R4

Res

3

+3.3

V+3

.3V

+3.3

V

10K

R7

Res

3

10K

R8

Res

3

10K

R9

Res

3

+3.3

V+3

.3V

+3.3

V

Vee

T1A

Tx F

ault

2A

Tx D

isab

le3A

MO

D-D

EF2

4A

MO

D-D

EF1

5A

MO

D-D

EF0

6A

Rat

e Se

lect

ion

7A

LOS

8A

Vee

R9A

Vee

R10

AV

eeR

11A

RD

-12

AR

D+

13A

Vee

R14

AV

ccR

15A

Vcc

T16

AV

eeT

17A

TD+

18A

TD-

19A

Vee

T20

A

0 0

J3A

SFP-

1761

008-

1 Vee

T1B

Tx F

ault

2B

Tx D

isab

le3B

MO

D-D

EF2

4B

MO

D-D

EF1

5B

MO

D-D

EF0

6B

Rat

e Se

lect

ion

7B

LOS

8B

Vee

R9B

Vee

R10

BV

eeR

11B

RD

-12

BR

D+

13B

Vee

R14

BV

ccR

15B

Vcc

T16

BV

eeT

17B

TD+

18B

TD-

19B

Vee

T20

BJ3

B

SFP-

1761

008-

1

Vee

T1C

Tx F

ault

2C

Tx D

isab

le3C

MO

D-D

EF2

4C

MO

D-D

EF1

5C

MO

D-D

EF0

6C

Rat

e Se

lect

ion

7C

LOS

8C

Vee

R9C

Vee

R10

CV

eeR

11C

RD

-12

CR

D+

13C

Vee

R14

CV

ccR

15C

Vcc

T16

CV

eeT

17C

TD+

18C

TD-

19C

Vee

T20

CJ3

C

SFP-

1761

008-

1

Vee

T1D

Tx F

ault

2D

Tx D

isab

le3D

MO

D-D

EF2

4D

MO

D-D

EF1

5D

MO

D-D

EF0

6D

Rat

e Se

lect

ion

7D

LOS

8D

Vee

R9D

Vee

R10

DV

eeR

11D

RD

-12

DR

D+

13D

Vee

R14

DV

ccR

15D

Vcc

T16

DV

eeT

17D

TD+

18D

TD-

19D

Vee

T20

DJ3

D

SFP-

1761

008-

1

TX_F

AU

LT_T

OB

EDEL

AY

EDTX

_DIS

AB

LE_T

OB

EDEL

AY

ED

LOS_

TRIG

DEL

AY

ED

GN

D

GN

D

10K

R11

Res

3

+3.3

V 10K

R15

Res

3

+3.3

V

10K

R12

Res

3

10K

R13

Res

3

10K

R14

Res

3

+3.3

V+3

.3V

+3.3

V

GN

D

GN

D

LVPE

CL_

TOB

EDEL

AY

ED_D

IF_P

LVPE

CL_

TOB

EDEL

AY

ED_D

IF_N

LVPE

CL_

TRIG

DEL

AY

ED_D

IF_P

LVPE

CL_

TRIG

DEL

AY

ED_D

IF_N

100n

F

C11

Cap

Sem

i

100n

F

C12

Cap

Sem

i

1uH

L5In

duct

or

1uH

L6In

duct

or

10uF

C13

Cap

Sem

i

GN

D

GN

D GN

D

100n

F

C14

Cap

Sem

i10

uF

C15

Cap

Sem

i

GN

DG

ND

+3.3

V

LVPE

CL_

TOB

EDEL

AY

ED_D

IF_P

LVPE

CL_

TOB

EDEL

AY

ED_D

IF_N

LVPE

CL_

TRIG

DEL

AY

ED_D

IF_P

LVPE

CL_

TRIG

DEL

AY

ED_D

IF_N

TX_F

AU

LT_S

FP_1

1TX

_DIS

AB

LE_S

FP_1

1

LOS_

SFP_

11

GN

D

GN

D

10K

R16

Res

3

+3.3

V 10K

R20

Res

3

+3.3

V

10K

R17

Res

3

10K

R18

Res

3

10K

R19

Res

3

+3.3

V+3

.3V

+3.3

V

GN

D

GN

D

LVPE

CL_

EXTR

A_S

FP_1

1_FB

_PLV

PEC

L_EX

TRA

_SFP

_11_

FB_N

LVPE

CL_

EXTR

A_S

FP_1

1_P

LVPE

CL_

EXTR

A_S

FP_1

1_N

100n

F

C16

Cap

Sem

i

100n

F

C17

Cap

Sem

i

1uH

L7In

duct

or

1uH

L8In

duct

or

10uF

C18

Cap

Sem

i

GN

D

GN

D GN

D

100n

F

C19

Cap

Sem

i10

uF

C20

Cap

Sem

i

GN

DG

ND

+3.3

V

LVPE

CL_

EXTR

A_S

FP_1

1_FB

_PLV

PEC

L_EX

TRA

_SFP

_11_

FB_N

LVPE

CL_

EXTR

A_S

FP_1

1_P

LVPE

CL_

EXTR

A_S

FP_1

1_N

VC

C_T

_8V

CC

_R_8

DEF

2_8

DEF

1_8

DEF

0_8

VC

C_T

_9V

CC

_R_9

DEF

2_9

DEF

1_9

DEF

0_9

VC

C_T

_10

VC

C_R

_10

DEF

2_10

DEF

1_10

DEF

0_10

VC

C_T

_11

VC

C_R

_11

DEF

2_11

DEF

1_11

DEF

0_11

1 2

P1 Hea

der 2

1 2

P2 Hea

der 2

LVPE

CL_

CA

LIB

_FB

_PLV

PEC

L_C

ALI

B_F

B_N

LVPE

CL_

CA

LIB

_PLV

PEC

L_C

ALI

B_N

1 2

P3 Hea

der 2

1 2

P4 Hea

der 2

LVPE

CL_

PED

ESTA

L_FB

_PLV

PEC

L_PE

DES

TAL_

FB_N

LVPE

CL_

PED

ESTA

L_P

LVPE

CL_

PED

ESTA

L_N

1 2

P5 Hea

der 2

1 2

P6 Hea

der 2

LVPE

CL_

TOB

EDEL

AY

ED_D

IF_P

LVPE

CL_

TOB

EDEL

AY

ED_D

IF_N

LVPE

CL_

TRIG

DEL

AY

ED_D

IF_P

LVPE

CL_

TRIG

DEL

AY

ED_D

IF_N

1 2

P7 Hea

der 2

1 2

P8 Hea

der 2

LVPE

CL_

EXTR

A_S

FP_1

1_FB

_PLV

PEC

L_EX

TRA

_SFP

_11_

FB_N

LVPE

CL_

EXTR

A_S

FP_1

1_P

LVPE

CL_

EXTR

A_S

FP_1

1_N

J2 Sock

et

J1 Sock

et

J4 Sock

et

J6 Sock

et

J5 Sock

et

J7 Sock

et

J9 Sock

et

J8 Sock

et J10

Sock

et

J12

Sock

et

J11

Sock

et

J13

Sock

et

GN

D

100u

F

C31

0

Cap

Sem

i

100n

F

C31

2

Cap

Sem

i

100p

F

C31

1

Cap

Sem

i

10uF

C31

3

Cap

Sem

i

1uH

L27

Indu

ctor

GN

D

GN

DG

ND

GN

D

PIC101PIC102COC

1

PIC201PIC202COC

2PIC301PIC302

COC3

PIC401PIC402CO

C4PIC501PIC502

COC5

PIC601PIC602COC

6

PIC701PIC702CO

C7PIC801PIC802

COC8

PIC901PIC902COC

9PIC1001PIC1002

COC1

0

PIC1101PIC1102COC11

PIC1201PIC1202COC12

PIC1301PIC1302CO

C13

PIC1401PIC1402CO

C14

PIC1501PIC1502CO

C15

PIC1601PIC1602CO

C16

PIC1701PIC1702COC17

PIC1801PIC1802CO

C18

PIC1901PIC1902COC19

PIC2001PIC2002CO

C20

PIC31001

PIC3

1002

COC3

10

PIC31101

PIC31102

COC3

11

PIC31201

PIC3

1202

COC3

12

PIC31301

PIC31302

COC3

13

PIJ101

COJ1 PIJ201

COJ2

PIJ300

PIJ301A

PIJ302A

PIJ303A

PIJ304A

PIJ305A

PIJ306A

PIJ307A

PIJ308A

PIJ309A

PIJ3010A

PIJ3011A

PIJ3012A

PIJ3013A

PIJ3014A

PIJ3015A

PIJ3016A

PIJ3017A

PIJ3018A

PIJ3019A

PIJ3020A

COJ3A

PIJ301B

PIJ302B

PIJ303B

PIJ304B

PIJ305B

PIJ306B

PIJ307B

PIJ308B

PIJ309B

PIJ3010B

PIJ3011B

PIJ3012B

PIJ3013B

PIJ3014B

PIJ3015B

PIJ3016B

PIJ3017B

PIJ3018B

PIJ3019B

PIJ3020B

COJ3B

PIJ301C

PIJ302C

PIJ303C

PIJ304C

PIJ305C

PIJ306C

PIJ307C

PIJ308C

PIJ309C

PIJ3010C

PIJ3011C

PIJ3012C

PIJ3013C

PIJ3014C

PIJ3015C

PIJ3016C

PIJ3017C

PIJ3018C

PIJ3019C

PIJ3020C

COJ3C

PIJ301D

PIJ302D

PIJ303D

PIJ304D

PIJ305D

PIJ306D

PIJ307D

PIJ308D

PIJ309D

PIJ3010D

PIJ3011D

PIJ3012D

PIJ3013D

PIJ3014D

PIJ3015D

PIJ3016D

PIJ3017D

PIJ3018D

PIJ3019D

PIJ3020D

COJ3D

PIJ401

COJ4

PIJ501

COJ5 P

IJ601

COJ6 P

IJ701

COJ7

PIJ801

COJ8 P

IJ901

COJ9

PIJ1001

COJ10

PIJ1101

COJ11 PIJ1201

COJ12

PIJ1301

COJ13

PIL1

01PI

L102COL

1

PIL2

01PI

L202 COL

2

PIL3

01PI

L302COL

3

PIL4

01PI

L402 COL

4

PIL5

01PI

L502COL

5

PIL6

01PI

L602 COL

6 PIL7

01PIL702COL

7

PIL8

01PIL802

COL8

PIL2

701

PIL2

702

COL2

7

PIP101

PIP102COP

1

PIP201

PIP202COP

2

PIP301

PIP302COP

3

PIP401

PIP402COP

4

PIP501

PIP502COP

5

PIP601

PIP602COP

6

PIP701

PIP702COP

7

PIP801

PIP802COP

8

PIR101PIR102 COR1

PIR201PIR202 COR2

PIR301PIR302 COR3

PIR401PIR402 COR4

PIR501 PIR502COR5

PIR601PIR602 COR6

PIR701PIR702COR

7

PIR801PIR802 COR8

PIR901PIR902 COR9

PIR1001 PIR1002COR1

0 PIR1101PIR1102 COR11

PIR1201PIR1202COR12

PIR1301PIR1302 COR1

3

PIR1401PIR1402 COR1

4

PIR1501 PIR1502

COR15

PIR1601PIR1602 COR1

6

PIR1701PIR1702COR17

PIR1801PIR1802 COR1

8

PIR1901PIR1902 COR1

9

PIR2001 PIR2002COR2

0

PIC402PIC502

PIC902PIC1002

PIC1402PIC1502

PIC1902PIC2002

PIL1

01

PIL2

01

PIL3

01

PIL4

01

PIL5

01

PIL6

01

PIL7

01

PIL8

01

PIR102

PIR202PIR302

PIR402

PIR502

PIR602

PIR702PIR802

PIR902

PIR1002

PIR1102PIR1202

PIR1302PIR1402

PIR1502

PIR1602

PIR1702PIR1802

PIR1902

PIR2002PIJ306A

PIR401NL

DEF0

08

PIJ306B

PIR901NL

DEF0

09

PIJ306C

PIR1401NL

DEF0

010

PIJ306D

PIR1901NL

DEF0

011

PIJ305A

PIR301NL

DEF1

08

PIJ305B

PIR801NL

DEF1

09

PIJ305C

PIR1301NL

DEF1

010

PIJ305D

PIR1801NL

DEF1

011

PIJ304A

PIR201NLDEF208

PIJ304B

PIR701NLDEF209

PIJ304C

PIR1201NL

DEF2

010

PIJ304D

PIR1701NL

DEF2

011

PIC102

PIC201PIC301

PIC401PIC501

PIC602

PIC701PIC801

PIC901PIC1001

PIC1102

PIC1201PIC1301

PIC1401PIC1501

PIC1602

PIC1701PIC1801

PIC1901PIC2001

PIC3

1002

PIC31101

PIC3

1202

PIC31301

PIJ301A

PIJ301B

PIJ301C

PIJ301D

PIJ309A

PIJ309B

PIJ309C

PIJ309D

PIJ3010A

PIJ3010B

PIJ3010C

PIJ3010D

PIJ3011A

PIJ3011B

PIJ3011C

PIJ3011D

PIJ3014A

PIJ3014B

PIJ3014C

PIJ3014D

PIJ3017A

PIJ3017B

PIJ3017C

PIJ3017D

PIJ3020A

PIJ3020B

PIJ3020C

PIJ3020D

PIL2

702

PIJ3018A

PIP102

NLLVPECL0CALIB0FB0N

POLVPECL0CALIB0FB0N

PIJ3019A

PIP101

NLLV

PECL

0CAL

IB0F

B0P

POLVPECL0CALIB0FB0P

PIJ3012A

PIP202

NLLVPECL0CALIB0N

POLVPECL0CALIB0N

PIJ3013A

PIP201

NLLVPECL0CALIB0P

POLVPECL0CALIB0P

PIJ3018D

PIP702

NLLV

PECL

0EXT

RA0S

FP01

10FB

0NPOLVPECL0EXTRA0SFP0110FB0N

PIJ3019D

PIP701

NLLV

PECL

0EXT

RA0S

FP01

10FB

0PPOLVPECL0EXTRA0SFP0110FB0P

PIJ3012D

PIP802

NLLVPECL0EXTRA0SFP0110N

POLVPECL0EXTRA0SFP0110N

PIJ3013D

PIP801

NLLVPECL0EXTRA0SFP0110P


PIJ3018B

PIP302

NLLVPECL0PEDESTAL0FB0N


PIJ3019B

PIP301

NLLV

PECL

0PED

ESTA

L0FB

0P


PIJ3012B

PIP402

NLLV

PECL

0PED

ESTA

L0N

POLVPECL0PEDESTAL0N

PIJ3013B

PIP401

NLLVPECL0PEDESTAL0P

POLVPECL0PEDESTAL0P

PIJ3018C

PIP502

NLLV

PECL

0TOB

EDEL

AYED

0DIF

0N


PIJ3019C

PIP501

NLLV

PECL

0TOB

EDEL

AYED

0DIF

0P


PIJ3012C

PIP602

NLLV

PECL

0TRI

GDEL

AYED

0DIF

0N


PIJ3013C

PIP601

NLLV

PECL

0TRI

GDEL

AYED

0DIF

0P


PIC31001

PIC31102

PIC31201

PIC31302

PIJ300

PIL2

701

PIJ101

PIJ303A

POTX0DISABLE0CALIB

PIJ201

PIJ302A

PIR101POTX0FAULT0CALIB

PIJ302B

PIJ601

PIR601POTX0FAULT0PEDESTAL

PIJ302C

PIJ901

PIR1101POTX0FAULT0TOBEDELAYED

PIJ302D

PIJ1201

PIR1601POTX0FAULT0SFP011

PIJ303B

PIJ501


PIJ303C

PIJ801


PIJ303D

PIJ1101

POTX0DISABLE0SFP011

PIJ307A

PIJ307B

PIJ307C

PIJ307D

PIJ308A

PIJ401

PIR501POLOS0CALIB

PIJ308B

PIJ701

PIR1001POLOS0PEDESTAL

PIJ308C

PIJ1001

PIR1501POLOS0TRIGDELAYED

PIJ308D

PIJ1301

PIR2001POLOS0SFP011

PIC202PIC302

PIJ3015A

PIL2

02

NLVCC0R08

PIC702PIC802

PIJ3015B

PIL4

02

NLVCC0R09

PIC1202PIC1302

PIJ3015C

PIL6

02

NLVC

C0R0

10

PIC1702PIC1802

PIJ3015D

PIL802

NLVC

C0R0

11

PIC101PIJ3016A

PIL1

02NLVCC0T08

PIC601PIJ3016B

PIL3

02NLVCC0T09

PIC1101PIJ3016C

PIL5

02NL

VCC0

T010

PIC1601PIJ3016D

PIL702

NLVC

C0T0

11

POLOS0CALIB

POLOS0PEDESTAL

POLOS0SFP011

POLOS0TRIGDELAYED

POLVPECL0CALIB0FB0N

POLVPECL0CALIB0FB0P

POLVPECL0CALIB0N

POLVPECL0CALIB0P

POLVPECL0EXTRA0SFP0110FB0N

POLVPECL0EXTRA0SFP0110FB0P

POLVPECL0EXTRA0SFP0110N




POLVPECL0PEDESTAL0N

POLVPECL0PEDESTAL0P





POTX0DISABLE0CALIB


POTX0DISABLE0SFP011


POTX0FAULT0CALIB

POTX0FAULT0PEDESTAL

POTX0FAULT0SFP011

POTX0FAULT0TOBEDELAYED

Figure A.21: TIB: Optical transceivers to/from calibration box

232 A. Schematics

11

22

33

44

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A4

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\R

J45s

.Sch

Doc

Dra

wn

By:

STER

EO_M

WR

_PST

EREO

_MW

R_N

TRG

TYPE

0_M

WR

_PTR

GTY

PE0_

MW

R_N

TRG

TYPE

1_M

WR

_P

TRG

TYPE

1_M

WR

_N

CLK

_10M

HZ_

PC

LK_1

0MH

Z_N

AR

RA

YTR

IG_P

AR

RA

YTR

IG_N

SPA

RE_

1_P

SPA

RE_

1_N

CA

BLE

_DET

ECT

STER

EO_C

B_P

STER

EO_C

B_N

INPU

T_0_

PIN

PUT_

0_N

TRG

TYPE

0_C

B_P

TRG

TYPE

0_C

B_N

TRG

TYPE

1_C

B_P

TRG

TYPE

1_C

B_N

EXTR

A_0

_PEX

TRA

_0_N

EXTR

A_1

_PEX

TRA

_1_N

EXTR

A_2

_P

EXTR

A_2

_N

EXTR

A_3

_PEX

TRA

_3_N

Luis

A. T

ejed

or

Ster

eo T

rigge

r

1R

J 45s

TRG

TYPE

1_M

WR

_PTR

GTY

PE0_

MW

R_P

STER

EO_M

WR

_NST

EREO

_MW

R_P

TRG

TYPE

1_M

WR

_NTR

GTY

PE0_

MW

R_N

CLK

_10M

HZ_

PC

LK_1

0MH

Z_N

AR

RA

YTR

IG_P

SPA

RE_

1_P

SPA

RE_

1_N

AR

RA

YTR

IG_N

INPU

T_0_

PIN

PUT_

0_N

STER

EO_C

B_P

TRG

TYPE

0_C

B_P

TRG

TYPE

0_C

B_N

STER

EO_C

B_N

TRG

TYPE

1_C

B_P

TRG

TYPE

1_C

B_N

EXTR

A_0

_P

EXTR

A_1

_PEX

TRA

_0_N

EXTR

A_2

_P

EXTR

A_2

_NEX

TRA

_1_N

EXTR

A_3

_PEX

TRA

_3_N

1A1A

2A2A

3A3A

4A4A

5A5A

6A6A

7A7A

8A8A

0 0

J80A

TE 5

5692

62-1

1B1B

2B2B

3B3B

4B4B

5B5B

6B6B

7B7B

8B8B

J80B

TE 5

5692

62-1

1C1C

2C2C

3C3C

4C4C

5C5C

6C6C

7C7C

8C8C

J80C

TE 5

5692

62-1

1D1D

2D2D

3D3D

4D4D

5D5D

6D6D

7D7D

8D8D

J80D

TE 5

5692

62-1

1E1E

2E2E

3E3E

4E4E

5E5E

6E6E

7E7E

8E8E

J80E

TE 5

5692

62-1

1F1F

2F2F

3F3F

4F4F

5F5F

6F6F

7F7F

8F8F

J80F

TE 5

5692

62-1

1G1G

2G2G

3G3G

4G4G

5G5G

6G6G

7G7G

8G8G

J80G

TE 5

5692

62-1

1H1H

2H2H

3H3H

4H4H

5H5H

6H6H

7H7H

8H8H

J80H

TE 5

5692

62-1

EXTR

A_4

_PEX

TRA

_4_N

EXTR

A_5

_PEX

TRA

_6_P

EXTR

A_4

_P

EXTR

A_5

_PEX

TRA

_4_N

EXTR

A_6

_P

EXTR

A_1

2_P

EXTR

A_1

2_N

EXTR

A_1

3_P

EXTR

A_1

4_P

EXTR

A_1

2_P

EXTR

A_1

3_P

EXTR

A_1

2_N

EXTR

A_1

4_P

EXTR

A_8

_PEX

TRA

_8_N

EXTR

A_9

_PEX

TRA

_10_

P

EXTR

A_8

_P

EXTR

A_9

_PEX

TRA

_8_N

EXTR

A_1

0_P

EXTR

A_1

6_P

EXTR

A_1

6_N

EXTR

A_1

7_P

EXTR

A_1

8_P

EXTR

A_1

6_P

EXTR

A_1

7_P

EXTR

A_1

6_N

EXTR

A_1

8_P

EXTR

A_5

_NEX

TRA

_6_N

EXTR

A_7

_PEX

TRA

_7_N

EXTR

A_6

_NEX

TRA

_5_N

EXTR

A_7

_PEX

TRA

_7_N

EXTR

A_1

3_N

EXTR

A_1

4_N

EXTR

A_1

5_P

EXTR

A_1

5_N

EXTR

A_1

4_N

EXTR

A_1

3_N

EXTR

A_1

5_P

EXTR

A_1

5_N

EXTR

A_9

_NEX

TRA

_10_

N

EXTR

A_1

1_P

EXTR

A_1

1_N

EXTR

A_1

0_N

EXTR

A_9

_NEX

TRA

_11_

PEX

TRA

_11_

N

EXTR

A_1

7_N

EXTR

A_1

8_N

EXTR

A_1

9_P

EXTR

A_1

9_N

EXTR

A_1

8_N

EXTR

A_1

7_N

EXTR

A_1

9_P

EXTR

A_1

9_N

+5V

GN

D

22

11

J81

Jum

per

GN

D

FD4

Fidu

cial

1 2

P50

Hea

der 2

1 2

P51

Hea

der 2

1 2

P52

Hea

der 2

1 2

P53

Hea

der 2

INPU

T_0_

PIN

PUT_

0_N

STER

EO_C

B_P

STER

EO_C

B_N

TRG

TYPE

0_C

B_P

TRG

TYPE

0_C

B_N

TRG

TYPE

1_C

B_P

TRG

TYPE

1_C

B_N

1 2

P54

Hea

der 2

STER

EO_M

WR

_PST

EREO

_MW

R_N

1 2

P55

Hea

der 2

TRG

TYPE

0_M

WR

_PTR

GTY

PE0_

MW

R_N

1 2

P56

Hea

der 2

TRG

TYPE

1_M

WR

_PTR

GTY

PE1_

MW

R_N

1 2

P57

Hea

der 2

CLK

_10M

HZ_

PC

LK_1

0MH

Z_N

1 2

P58

Hea

der 2

AR

RA

YTR

IG_P

AR

RA

YTR

IG_N

1 2

P63

Hea

der 2

SPA

RE_

1_P

SPA

RE_

1_N

1 2P6

4H

eade

r 2

CA

BLE

_DET

ECT

CA

BLE

_DET

ECT

GN

D_O

UT

GN

D_O

UT

1 2

P59

Hea

der 2

EXTR

A_0

_PEX

TRA

_0_N

1 2

P60

Hea

der 2

EXTR

A_1

_PEX

TRA

_1_N

1 2

P61

Hea

der 2

EXTR

A_2

_PEX

TRA

_2_N

1 2

P62

Hea

der 2

EXTR

A_3

_PEX

TRA

_3_N

1 2

P65

Hea

der 2

EXTR

A_4

_PEX

TRA

_4_N

1 2

P66

Hea

der 2

EXTR

A_5

_PEX

TRA

_5_N

1 2

P67

Hea

der 2

EXTR

A_6

_PEX

TRA

_6_N

1 2

P68

Hea

der 2

EXTR

A_7

_PEX

TRA

_7_N

1 2

P69

Hea

der 2

EXTR

A_8

_PEX

TRA

_8_N

1 2

P70

Hea

der 2

EXTR

A_9

_PEX

TRA

_9_N

1 2

P71

Hea

der 2

EXTR

A_1

0_P

EXTR

A_1

0_N

1 2

P72

Hea

der 2

EXTR

A_1

1_P

EXTR

A_1

1_N

1 2

P77

Hea

der 2

EXTR

A_1

2_P

EXTR

A_1

2_N

1 2

P78

Hea

der 2

EXTR

A_1

3_P

EXTR

A_1

3_N

1 2

P79

Hea

der 2

EXTR

A_1

4_P

EXTR

A_1

4_N

1 2

P80

Hea

der 2

EXTR

A_1

5_P

EXTR

A_1

5_N

1 2

P73

Hea

der 2

EXTR

A_1

6_P

EXTR

A_1

6_N

1 2

P74

Hea

der 2

EXTR

A_1

7_P

EXTR

A_1

7_N

1 2

P75

Hea

der 2

EXTR

A_1

8_P

EXTR

A_1

8_N

1 2

P76

Hea

der 2

EXTR

A_1

9_P

EXTR

A_1

9_N

GN

D

100u

F

C32

3C

ap S

emi

100n

F

C32

4C

ap S

emi

100p

F

C32

5

Cap

Sem

i

10uF

C32

2C

ap S

emi

1uH

L30

Indu

ctor

GN

DG

ND

GN

D

GN

D

To M

UTI

N /

Whi

te R

abbi

t

From

MU

TIN

/ W

hite

Rab

bit

Cen

tral B

ackp

lane

RJ4

5-3

RJ4

5-4

RJ4

5-5

RJ4

5-6

RJ4

5-7

PIC32201PIC32202CO

C322



PIC325

01PIC

32502

COC3

25

COFD

4

PIJ8000

PIJ8001A

PIJ8002A

PIJ8003A

PIJ8004A

PIJ8005A

PIJ8006A

PIJ8007A

PIJ8008A

COJ80A

PIJ8001B

PIJ8002B

PIJ8003B

PIJ8004B

PIJ8005B

PIJ8006B

PIJ8007B

PIJ8008B

COJ8

0B

PIJ8001C

PIJ8002C

PIJ8003C

PIJ8004C

PIJ8005C

PIJ8006C

PIJ8007C

PIJ8008C

COJ8

0C

PIJ8001D

PIJ8002D

PIJ8003D

PIJ8004D

PIJ8005D

PIJ8006D

PIJ8007D

PIJ8008D

COJ8

0D

PIJ8001E

PIJ8002E

PIJ8003E

PIJ8004E

PIJ8005E

PIJ8006E

PIJ8007E

PIJ8008E

COJ8

0E

PIJ8001F

PIJ8002F

PIJ8003F

PIJ8004F

PIJ8005F

PIJ8006F

PIJ8007F

PIJ8008F

COJ8

0F

PIJ8001G

PIJ8002G

PIJ8003G

PIJ8004G

PIJ8005G

PIJ8006G

PIJ8007G

PIJ8008G

COJ80G

PIJ8001H

PIJ8002H

PIJ8003H

PIJ8004H

PIJ8005H

PIJ8006H

PIJ8007H

PIJ8008H

COJ8

0H

PIJ8101

PIJ8102

COJ81

PIL3001 PIL3002

COL3

0

PIP5001

PIP5002CO

P50

PIP5101

PIP5102CO

P51

PIP5201

PIP5202CO

P52

PIP5301

PIP5302CO

P53

PIP5401

PIP5402CO

P54

PIP5501

PIP5502COP

55

PIP5601

PIP560

2COP56

PIP5701

PIP5702CO

P57

PIP5801

PIP5802CO

P58

PIP5901

PIP5902CO

P59

PIP6001

PIP6002COP

60

PIP6101

PIP6102COP

61

PIP6201

PIP6202CO

P62

PIP6301

PIP6302

COP6

3PIP6401

PIP6402

COP6

4

PIP6501

PIP6502CO

P65

PIP6601

PIP6602CO

P66

PIP6701

PIP6702CO

P67

PIP6801

PIP6802CO

P68

PIP6901

PIP6902CO

P69

PIP7001

PIP7002COP

70

PIP7

101

PIP7102COP

71

PIP720

1PIP7202CO

P72

PIP7301

PIP7302CO

P73

PIP7401

PIP7402COP

74

PIP7501

PIP7502COP

75

PIP7601

PIP7602CO

P76

PIP7701

PIP7702CO

P77

PIP7801

PIP7802CO

P78

PIP7901

PIP7902CO

P79

PIP8001

PIP8002CO

P80

PIJ8007B

PIJ8006C

PIP5802

NLAR

RAYT

RIG0

NPOARRAYTRIG0N

PIJ8003C

PIP5801

NLAR

RAYT

RIG0

PPOARRAYTRIG0P

PIJ8007C

PIP6401

NLCABLE0DETECT

POCABLE0DETECT

PIJ8002C

PIP5702

NLCL

K010

MHZ0

NPOCLK010MHZ0N

PIJ8001C

PIP5701

NLCLK010MHZ0P

POCLK010MHZ0P

PIJ8002D

PIP5902

NLEXTRA000N

POEXTRA000N

PIJ8001D

PIP5901

NLEXTRA0

00P

POEXTRA000P

PIJ8006D

PIP6002

NLEXTRA010N

POEXTRA010N

PIJ8003D

PIP6001

NLEXTRA0

10P

POEXTRA010P

PIJ8005D

PIP6102

NLEXTRA020N

POEXTRA020N

PIJ8004D

PIP6101

NLEXTRA0

20P

POEXTRA020P

PIJ8008D

PIP6202

NLEXTRA030N

POEXTRA030N

PIJ8007D

PIP6201

NLEX

TRA0

30P

POEXTRA030P

PIJ8002E

PIP6502

NLEXTRA040N

POEXTRA040N

PIJ8001E

PIP6501

NLEX

TRA0

40P

POEXTRA040P

PIJ8006E

PIP6602

NLEXTRA050N

POEXTRA050N

PIJ8003E

PIP6601

NLEX

TRA0

50P

POEXTRA050P

PIJ8005E

PIP6702

NLEXTRA060N

POEXTRA060N

PIJ8004E

PIP6701

NLEX

TRA0

60P

POEXTRA060P

PIJ8008E

PIP6802

NLEXTRA070N

POEXTRA070N

PIJ8007E

PIP6801

NLEX

TRA0

70P

POEXTRA070P

PIJ8002F

PIP6902

NLEXTRA080N

POEXTRA080N

PIJ8001F

PIP6901

NLEXTRA0

80P

POEXTRA080P

PIJ8006F

PIP7002

NLEXTRA090N

POEXTRA090N

PIJ8003F

PIP7001

NLEXTRA0

90P

POEXTRA090P

PIJ8005F

PIP7102

NLEX

TRA0

100N

POEXTRA0100N

PIJ8004F

PIP7

101

NLEX

TRA0

100P

POEXTRA0100P

PIJ8008F

PIP7202

NLEX

TRA0

110N

POEXTRA0110N

PIJ8007F

PIP720

1NL

EXTR

A011

0P

POEXTRA0110P

PIJ8002G

PIP7702

NLEXTRA0120N

POEXTRA0120N

PIJ8001G

PIP7701

NLEX

TRA0

120P

POEXTRA0120P

PIJ8006G

PIP7802

NLEX

TRA0

130N

POEXTRA0130N

PIJ8003G

PIP7801

NLEX

TRA0

130P

POEXTRA0130P

PIJ8005G

PIP7902

NLEX

TRA0

140N

POEXTRA0140N

PIJ8004G

PIP7901

NLEX

TRA0

140P

POEXTRA0140P

PIJ8008G

PIP8002

NLEX

TRA0

150N

POEXTRA0150N

PIJ8007G

PIP8001

NLEX

TRA0

150P

POEXTRA0150P

PIJ8002H

PIP7302

NLEX

TRA0

160N

POEXTRA0160N

PIJ8001H

PIP7301

NLEX

TRA0

160P

POEXTRA0160P

PIJ8006H

PIP7402

NLEX

TRA0

170N

POEXTRA0170N

PIJ8003H

PIP7401

NLEX

TRA0

170P

POEXTRA0170P

PIJ8005H

PIP7502

NLEX

TRA0

180N

POEXTRA0180N

PIJ8004H

PIP7501

NLEX

TRA0

180P

POEXTRA0180P

PIJ8008H

PIP7602

NLEX

TRA0

190N

POEXTRA0190N

PIJ8007H

PIP7601

NLEX

TRA0

190P

POEXTRA0190P

PIC32201PIC32301

PIC32401PIC

32501

PIJ8008B

PIJ8102

PIL3002

PIJ8008C

PIJ8101

PIP6402

NLGND0OUT

PIJ8002A

PIP5002

NLIN

PUT0

00N

POINPUT000N

PIJ8001A

PIP5001

NLIN

PUT0

00P

POINPUT000P

PIC32202PIC32302

PIC32402

PIC325

02

PIJ8000PIL3001

PIJ8005C

PIP6302

NLSP

ARE0

10N

POSPARE010N

PIJ8004C

PIP6301

NLSP

ARE0

10P

POSPARE010P

PIJ8006A

PIP5102

NLSTEREO0CB0N

POSTEREO0CB0N

PIJ8003A

PIP5101

NLST

EREO

0CB0

PPOSTEREO0CB0P

PIJ8002B

PIP5402

NLST

EREO

0MWR

0NPOSTEREO0MWR0N

PIJ8001B

PIP5401

NLST

EREO

0MWR

0PPOSTEREO0MWR0P

PIJ8005A

PIP5202

NLTRGTYPE00CB0N

POTRGTYPE00CB0N

PIJ8004A

PIP5201

NLTRGTYPE00CB0P

POTRGTYPE00CB0P

PIJ8006B

PIP5502

NLTR

GTYP

E00M

WR0NPOTRGTYPE00MWR0N

PIJ8003B

PIP5501

NLTR

GTYP

E00M

WR0P

POTRGTYPE00MWR0P

PIJ8008A

PIP5302

NLTRGTYPE10CB0N

POTRGTYPE10CB0N

PIJ8007A

PIP5301

NLTRGTYPE10CB0P

POTRGTYPE10CB0P

PIJ8005B

PIP560

2NL

TRGT

YPE1

0MWR

0N

POTRGTYPE10MWR0N

PIJ8004B

PIP5601

NLTR

GTYP

E10M

WR0P

POTRGTYPE10MWR0P

POARRAYTRIG0N

POARRAYTRIG0P

POCABLE0DETECT

POCLK010MHZ0N

POCLK010MHZ0P

POEXTRA000N

POEXTRA000P

POEXTRA010N

POEXTRA010P

POEXTRA020N

POEXTRA020P

POEXTRA030N

POEXTRA030P

POEXTRA040N

POEXTRA040P

POEXTRA050N

POEXTRA050P

POEXTRA060N

POEXTRA060P

POEXTRA070N

POEXTRA070P

POEXTRA080N

POEXTRA080P

POEXTRA090N

POEXTRA090P

POEXTRA0100N

POEXTRA0100P

POEXTRA0110N

POEXTRA0110P

POEXTRA0120N

POEXTRA0120P

POEXTRA0130N

POEXTRA0130P

POEXTRA0140N

POEXTRA0140P

POEXTRA0150N

POEXTRA0150P

POEXTRA0160N

POEXTRA0160P

POEXTRA0170N

POEXTRA0170P

POEXTRA0180N

POEXTRA0180P

POEXTRA0190N

POEXTRA0190P

POINPUT000N

POINPUT000P

POSPARE010N

POSPARE010P

POSTEREO0CB0N

POSTEREO0CB0P

POSTEREO0MWR0N

POSTEREO0MWR0P

POTRGTYPE00CB0N

POTRGTYPE00CB0P

POTRGTYPE00MWR0N

POTRGTYPE00MWR0P

POTRGTYPE10CB0N

POTRGTYPE10CB0P

POTRGTYPE10MWR0N

POTRGTYPE10MWR0P

Figure A.22: TIB: RJ45 connectors

A. Schematics 233

11

22

33

44

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A4

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\Ex

tern

alD

elay

.Sch

Doc

Dra

wn

By:

IN1

LE2

P0/Q

3

P1/C

LK4

P2/D

5

P36

P47

GN

D8

REF

/PW

M9

P510

MS

11

P612

P713

P*/S

14

OU

T/O

UT*

15

Vcc

16

U1

DS1

123L

LE_E

XT_

DEL

TOB

EDEL

AY

ED

TRIG

DEL

AY

ED

GN

D

CLK

_EX

T_D

EL

+3.3

V

+3.3

V

MIS

O_E

XT_

DEL

MO

SI_E

XT_

DEL

GN

D

+3.3

V

100n

F

C23

Cap

Sem

i10

0pF

C22

Cap

Sem

i10

uF

C21

Cap

Sem

i

GN

D

REF

_EX

T_D

EL

Luis

A. T

ejed

or

Ster

eo T

rigge

r

1Ex

tern

al D

elay

IN1

LE2

P0/Q

3

P1/C

LK4

P2/D

5

P36

P47

GN

D8

REF

/PW

M9

P510

MS

11

P612

P713

P*/S

14

OU

T/O

UT*

15

Vcc

16

U2

DS1

123L

IN1

LE2

P0/Q

3

P1/C

LK4

P2/D

5

P36

P47

GN

D8

REF

/PW

M9

P510

MS

11

P612

P713

P*/S

14

OU

T/O

UT*

15

Vcc

16

U3

DS1

123L

IN1

LE2

P0/Q

3

P1/C

LK4

P2/D

5

P36

P47

GN

D8

REF

/PW

M9

P510

MS

11

P612

P713

P*/S

14

OU

T/O

UT*

15

Vcc

16

U4

DS1

123L

IN1

LE2

P0/Q

3

P1/C

LK4

P2/D

5

P36

P47

GN

D8

REF

/PW

M9

P510

MS

11

P612

P713

P*/S

14

OU

T/O

UT*

15

Vcc

16

U5

DS1

123L

IN1

LE2

P0/Q

3

P1/C

LK4

P2/D

5

P36

P47

GN

D8

REF

/PW

M9

P510

MS

11

P612

P713

P*/S

14

OU

T/O

UT*

15

Vcc

16

U8

DS1

123L

IN1

LE2

P0/Q

3

P1/C

LK4

P2/D

5

P36

P47

GN

D8

REF

/PW

M9

P510

MS

11

P612

P713

P*/S

14

OU

T/O

UT*

15

Vcc

16

U6

DS1

123L

IN1

LE2

P0/Q

3

P1/C

LK4

P2/D

5

P36

P47

GN

D8

REF

/PW

M9

P510

MS

11

P612

P713

P*/S

14

OU

T/O

UT*

15

Vcc

16

U7

DS1

123L

IN1

LE2

P0/Q

3

P1/C

LK4

P2/D

5

P36

P47

GN

D8

REF

/PW

M9

P510

MS

11

P612

P713

P*/S

14

OU

T/O

UT*

15

Vcc

16

U9

DS1

123L

LE_E

XT_

DEL

_2TO

BED

ELA

YED

_2

GN

D+3

.3V

+3.3

V

GN

DLE

_EX

T_D

EL_3

GN

D+3

.3V

+3.3

V

GN

DLE

_EX

T_D

EL_4

GN

D+3

.3V

100n

F

C32

Cap

Sem

i10

0pF

C31

Cap

Sem

i10

uF

C30

Cap

Sem

i

GN

D

+3.3

V

100n

F

C35

Cap

Sem

i10

0pF

C34

Cap

Sem

i10

uF

C33

Cap

Sem

i

GN

D

+3.3

V

+3.3

V

GN

D

+3.3

V

100n

F

C38

Cap

Sem

i10

0pF

C37

Cap

Sem

i10

uF

C36

Cap

Sem

i

GN

D

LE_E

XT_

DEL

_5

GN

D+3

.3V

+3.3

V

GN

DLE

_EX

T_D

EL_6

GN

D+3

.3V

+3.3

V

GN

DLE

_EX

T_D

EL_7

GN

D+3

.3V

100n

F

C41

Cap

Sem

i10

0pF

C40

Cap

Sem

i10

uF

C39

Cap

Sem

i

GN

D

+3.3

V

100n

F

C44

Cap

Sem

i10

0pF

C43

Cap

Sem

i10

uF

C42

Cap

Sem

i

GN

D

+3.3

V

100n

F

C47

Cap

Sem

i10

0pF

C46

Cap

Sem

i10

uF

C45

Cap

Sem

i

GN

D

+3.3

V

+3.3

V

GN

D

LE_E

XT_

DEL

_8

GN

D+3

.3V

+3.3

V

GN

D

+3.3

V

+3.3

V

GN

DLE

_EX

T_D

EL_9

GN

D

TRIG

DEL

AY

ED_2

+3.3

V

100n

F

C26

Cap

Sem

i10

0pF

C25

Cap

Sem

i10

uF

C24

Cap

Sem

i

GN

D

+3.3

V

100n

F

C29

Cap

Sem

i10

0pF

C28

Cap

Sem

i10

uF

C27

Cap

Sem

i

GN

D

DEL

AY

_CH

AIN

_1D

ELA

Y_C

HA

IN_2

DEL

AY

_CH

AIN

_3

DEL

AY

_CH

AIN

_4D

ELA

Y_C

HA

IN_5

DEL

AY

_CH

AIN

_6

DEL

AY

_CH

AIN

_7

CLK

_EX

T_D

EL

CLK

_EX

T_D

ELC

LK_E

XT_

DEL

CLK

_EX

T_D

EL

CLK

_EX

T_D

ELC

LK_E

XT_

DEL

CLK

_EX

T_D

EL

CLK

_EX

T_D

ELC

LK_E

XT_

DEL

MIS

O_E

XT_

DEL

MO

SI_E

XT_

DEL

MIS

O_E

XT_

DEL

MO

SI_E

XT_

DEL

MIS

O_E

XT_

DEL

MO

SI_E

XT_

DEL

MIS

O_E

XT_

DEL

MO

SI_E

XT_

DEL

MIS

O_E

XT_

DEL

MO

SI_E

XT_

DEL

MIS

O_E

XT_

DEL

MO

SI_E

XT_

DEL

MIS

O_E

XT_

DEL

MO

SI_E

XT_

DEL

MIS

O_E

XT_

DEL

MO

SI_E

XT_

DEL

MIS

O_E

XT_

DEL

MO

SI_E

XT_

DEL

J20

Sock

et

J18

Sock

et

J19

Sock

et

J21

Sock

et

J22

Sock

et

J23

Sock

et

J28

Sock

et

J27

Sock

et

J15 So

cket

J17

Sock

et

J14

Sock

et

J16

Sock

et

J24

Sock

etJ2

5

Sock

et

J26

Sock

et

MIS

O_E

XT_

DEL

CLK

_EX

T_D

EL

MO

SI_E

XT_

DEL

TOB

EDEL

AY

EDLE

_EX

T_D

EL

TRIG

DEL

AY

ED

REF

_EX

T_D

EL

TBD

2LE

2LE

3LE

4

LE5

LE6

LE7

LE8

LE9

TRIG

DEL

AY

ED_2

PIC2101PIC2102CO

C21

PIC2201PIC2202CO

C22

PIC2301PIC2302CO

C23

PIC2401PIC2402CO

C24

PIC2501PIC2502CO

C25

PIC2601PIC2602CO

C26

PIC2701PIC2702CO

C27

PIC2801PIC2802CO

C28

PIC2901PIC2902CO

C29

PIC3001PIC3002CO

C30

PIC3101PIC3102CO

C31

PIC3201PIC3202CO

C32

PIC3301PIC3302CO

C33

PIC3401PIC3402CO

C34

PIC3501PIC3502CO

C35

PIC3601PIC3602CO

C36

PIC3701PIC3702CO

C37

PIC3801PIC3802CO

C38

PIC3901PIC3902CO

C39

PIC4001PIC4002CO

C40

PIC4101PIC4102CO

C41

PIC4201PIC4202CO

C42

PIC4301PIC4302CO

C43

PIC4401PIC4402CO

C44

PIC4501PIC4502CO

C45

PIC4601PIC4602CO

C46

PIC4701PIC4702CO

C47

PIJ1401

COJ14

PIJ1501

COJ15

PIJ1601

COJ16

PIJ1701

COJ17

PIJ1801COJ

18

PIJ1901COJ

19

PIJ2001COJ

20

PIJ2101COJ

21

PIJ2201COJ

22

PIJ2301COJ

23

PIJ2401COJ

24

PIJ2501COJ

25

PIJ2601COJ

26

PIJ2701COJ

27

PIJ2801COJ

28

PIU101

PIU102

PIU103

PIU104

PIU105

PIU106

PIU107

PIU108

PIU109

PIU1010

PIU1011

PIU1012

PIU1013

PIU1014

PIU1015

PIU1016

COU1

PIU201

PIU202

PIU203

PIU204

PIU205

PIU206

PIU207

PIU208

PIU209

PIU2010

PIU2011

PIU2012

PIU2013

PIU2014

PIU2015

PIU2016

COU2

PIU301

PIU302

PIU303

PIU304

PIU305

PIU306

PIU307

PIU308

PIU309

PIU3010

PIU3011

PIU3012

PIU3013

PIU3014

PIU3015

PIU3016

COU3

PIU401

PIU402

PIU403

PIU404

PIU405

PIU406

PIU407

PIU408

PIU409

PIU4010

PIU4011

PIU4012

PIU4013

PIU4014

PIU4015

PIU4016

COU4

PIU501

PIU502

PIU503

PIU504

PIU505

PIU506

PIU507

PIU508

PIU509

PIU5010

PIU5011

PIU5012

PIU5013

PIU5014

PIU5015

PIU5016

COU5

PIU601

PIU602

PIU603

PIU604

PIU605

PIU606

PIU607

PIU608

PIU609

PIU6010

PIU6011

PIU6012

PIU6013

PIU6014

PIU6015

PIU6016

COU6

PIU701

PIU702

PIU703

PIU704

PIU705

PIU706

PIU707

PIU708

PIU709

PIU7010

PIU7011

PIU7012

PIU7013

PIU7014

PIU7015

PIU7016

COU7

PIU801

PIU802

PIU803

PIU804

PIU805

PIU806

PIU807

PIU808

PIU809

PIU8010

PIU8011

PIU8012

PIU8013

PIU8014

PIU8015

PIU8016

COU8

PIU901

PIU902

PIU903

PIU904

PIU905

PIU906

PIU907

PIU908

PIU909

PIU9010

PIU9011

PIU9012

PIU9013

PIU9014

PIU9015

PIU9016

COU9

PIC2102PIC2202

PIC2302PIC2402

PIC2502PIC2602

PIC2702PIC2802

PIC2902

PIC3002PIC3102

PIC3202PIC3302

PIC3402PIC3502

PIC3602PIC3702

PIC3802

PIC3902PIC4002

PIC4102PIC4202

PIC4302PIC4402

PIC4502PIC4602

PIC4702

PIU1014

PIU1016

PIU2014

PIU2016

PIU3014

PIU3016

PIU4014

PIU4016

PIU5014

PIU5016

PIU6014

PIU6016

PIU7014

PIU7016

PIU8014

PIU8016

PIU9014

PIU9016

PIJ2501

PIU104

PIU204

PIU304

PIU404

PIU504

PIU604

PIU704

PIU804

PIU904

NLCL

K0EX

T0DE

L

POCLK0EXT0DEL

PIJ1801

PIU2015

PIU301

NLDELAY0CHAIN01

PIJ1901

PIU3015

PIU401

NLDELAY0CHAIN02

PIJ2001

PIU4015

PIU501

NLDELAY0CHAIN03

PIJ2101

PIU5015

PIU601

NLDELAY0CHAIN04

PIJ2201

PIU6015

PIU701

NLDELAY0CHAIN05

PIJ2301

PIU7015

PIU801

NLDELAY0CHAIN06

PIJ2801

PIU8015

PIU901

NLDELAY0CHAIN07

PIC2101PIC2201

PIC2301PIC2401

PIC2501PIC2601

PIC2701PIC2801

PIC2901

PIC3001PIC3101

PIC3201PIC3301

PIC3401PIC3501

PIC3601PIC3701

PIC3801

PIC3901PIC4001

PIC4101PIC4201

PIC4301PIC4401

PIC4501PIC4601

PIC4701

PIU106

PIU107

PIU108

PIU1010

PIU1011

PIU1012

PIU1013

PIU206

PIU207

PIU208

PIU2010

PIU2011

PIU2012

PIU2013

PIU306

PIU307

PIU308

PIU3010

PIU3011

PIU3012

PIU3013

PIU406

PIU407

PIU408

PIU4010

PIU4011

PIU4012

PIU4013

PIU506

PIU507

PIU508

PIU5010

PIU5011

PIU5012

PIU5013

PIU606

PIU607

PIU608

PIU6010

PIU6011

PIU6012

PIU6013

PIU706

PIU707

PIU708

PIU7010

PIU7011

PIU7012

PIU7013

PIU806

PIU807

PIU808

PIU8010

PIU8011

PIU8012

PIU8013

PIU906

PIU907

PIU908

PIU9010

PIU9011

PIU9012

PIU9013

PIU202

NLLE

2POLE0EXT0DEL02

PIU302

NLLE

3POLE0EXT0DEL03

PIU402

NLLE

4POLE0EXT0DEL04

PIU502

NLLE

5POLE0EXT0DEL05

PIU602

NLLE

6POLE0EXT0DEL06

PIU702

NLLE

7POLE0EXT0DEL07

PIU802

NLLE

8POLE0EXT0DEL08

PIU902

NLLE

9POLE0EXT0DEL09

PIU102

NLLE0EXT0DEL

POLE0EXT0DEL

PIJ2401

PIU103

PIU203

PIU303

PIU403

PIU503

PIU603

PIU703

PIU803

PIU903

NLMISO0EXT0DEL

POMISO0EXT0DEL

PIJ2601

PIU105

PIU205

PIU305

PIU405

PIU505

PIU605

PIU705

PIU805

PIU905

NLMOSI0EXT0DEL

POMOSI0EXT0DEL

PIU209

PIU309

PIU409

PIU509

PIU609

PIU709

PIU809

PIU909

PIJ1401

PIU109NLR

EF0E

XT0D

ELPOREF0EXT0DEL

PIJ1601

PIU201

NLTB

D2POTOBEDELAYED02

PIJ1501

PIU101

NLTO

BEDE

LAYE

DPOTOBEDELAYED

PIJ1701

PIU1015NLT

RIGD

ELAY

EDPOTRIGDELAYED

PIJ2701

PIU9015NLTRIGDELAYED02POTRIGDELAYED02

POCLK0EXT0DEL

POLE0EXT0DEL

POLE0EXT0DEL02

POLE0EXT0DEL03

POLE0EXT0DEL04

POLE0EXT0DEL05

POLE0EXT0DEL06

POLE0EXT0DEL07

POLE0EXT0DEL08

POLE0EXT0DEL09

POMISO0EXT0DEL

POMOSI0EXT0DEL

POREF0EXT0DEL

POTOBEDELAYED

POTOBEDELAYED02

POTRIGDELAYED

POTRIGDELAYED02

Figure A.23: TIB: External delays

234 A. Schematics

11

22

33

44

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A4

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\Th

erm

omet

er.S

chD

ocD

raw

n B

y:

VSS

2

SI/O

4

CS

1

VD

D5

SCK

3

U41

TC77

-3.3

MC

TTR

CLK

_TH

CS_

TH

GN

D

IO_T

H

+3.3

V

100n

F

C30

9C

ap S

emi

100p

F

C30

8C

ap S

emi G

ND

GN

D

10uF

C30

7C

ap S

emi

GN

D

Luis

A. T

ejed

or

Ster

eo T

rigge

r

1Th

erm

omet

er

J84

Sock

et

J83

Sock

et

J82

Sock

et

CS_

TH

CLK

_TH

IO_T

H




PIJ8201

COJ82 PIJ8301

COJ83 PIJ8401

COJ84

PIU4101

PIU4102

PIU4103

PIU4104

PIU4105CO

U41

PIC30702PIC30802

PIC30902PIU4105

PIJ8301

PIU4103

NLCL

K0TH

POCLK0TH

PIJ8201

PIU4101

NLCS0TH

POCS0TH

PIC30701PIC30801

PIC30901

PIU4102

PIJ8401

PIU4104

NLIO

0TH

POIO0TH

POCLK0TH

POCS0TH

POIO0TH

Figure A.24: TIB: Thermometer

A. Schematics 235

11

22

33

44

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A4

Dat

e:30

/12/

2013

Shee

t o

fFi

le:

C:\G

oogl

e D

rive\

..\Po

wer

Supp

ly.S

chD

ocD

raw

n B

y:

+24V

4.7u

F

C28

5C

ap S

emi

100n

F

C28

6C

ap S

emi

GN

DG

ND

15nF

C28

7C

ap S

emi

GN

D

GN

D

2.2u

F

C29

1C

ap S

emi

GN

D

GN

D

470n

F

C28

4

Cap

Sem

i

GN

D

+3.3

V

1uF

C28

2C

ap S

emi

GN

D

+3.3

V

1uF

C28

3C

ap S

emi

GN

D

GN

D

+2.5

V

IN3

OU

T1

4

GN

D

U37

LP38

691D

T-1.

8/N

OPB

1uF

C28

9C

ap S

emi

GN

D

1uF

C29

0C

ap S

emi

GN

DG

ND

+3.3

V+1

.8V

IN4

AD

J6

GN

D3

NC

7

SD8

DA

P9

OU

T5

BY

P1

NC

2

U38

LP38

78SD

-AD

J/N

OPB

4.7u

F

C29

2C

ap S

emi

10nF

C29

4C

ap S

emi10

uF

C29

3C

ap S

emi

GN

D

+3.3

V+1

V

Ster

eo T

rigge

r

Pow

er S

uppl

y1

Luis

A. T

ejed

or

8.2u

H

L25

Indu

ctor

+24V

GN

D

220u

F

C30

0C

ap P

ol3

100p

F

C30

3C

ap S

emi

100n

F

C30

2C

ap S

emi

10uF

C30

1C

ap S

emi

F4 2.5A

F1 1.5A

F2 0.5A

F3 1.5A

BO

OT

1

SS2

RT/

SYN

C3

FB4

EN5

GN

D6

VIN

7

SW8

DA

P9

U39

LM22

672M

R-5

.0/N

OPB

4.7u

F

C29

5C

ap S

emi

1uF

C29

6C

ap S

emi

39nF

C29

8C

ap S

emi

61.9

K

R79

Res

3

GN

D

GN

D

+24V

GN

D

10nF

C29

7C

ap S

emi

GN

D

22uH

L26

Indu

ctor

180u

F

C29

9C

ap P

ol3

GN

DG

ND

+5V

D1

BA

S240

A-1

3-F

IN3

OU

T1

4

GN

D

U35

LP38

690D

T-2.

5/N

OPB

VC

C1

VIN

2

EN3

FB4

SGN

D5

SS6

NC

7

NC

8

SGN

D9

SW10

HG

11

BST

12

LG13

PGN

D14

DA

P15

U36

LM31

51M

H-3

.3/N

OPB

180u

F

C28

8C

ap P

ol3

4

5 1Q1

CSD

1853

4Q5A

4

5 1Q2

CSD

1853

4Q5A

3_3_

SS

3_3_

BST

3_3_

HG 3_

3_LG3_

3_SW

3_3_

VC

C

5_SS5_

RT

5_B

OO

T

5_SW

1_IN

1_B

YP

1_8_

IN

2_5_

IN

11

22

J60

IPL1

-102

-01-

L-S-

RA

-K

GN

D

PIC28201 PIC28202COC282

PIC28301 PIC28302CO

C283

PIC284

01PIC

28402

COC284

PIC28501PIC28502CO

C285

PIC28601PIC28602CO

C286

PIC28701PIC28702CO

C287

PIC28801 PIC28802COC288

PIC28901 PIC28902CO

C289

PIC29001 PIC29002CO

C290

PIC29101PIC29102CO

C291


PIC29301 PIC29302CO

C293

PIC29401PIC29402CO

C294

PIC29501PIC29502CO

C295

PIC29601PIC29602CO

C296

PIC29701 PIC29702COC297

PIC29801PIC29802CO

C298

PIC29901 PIC29902

COC299

PIC30001 PIC30002COC300

PIC30101 PIC30102COC301

PIC30201 PIC30202COC302

PIC30301 PIC30302COC303

PID101 PID102CO

D1

PIF101

PIF102

COF1

PIF201

PIF202

COF2

PIF301

PIF302

COF3

PIF401

PIF402

COF4

PIJ6001

PIJ6002COJ

60

PIL2501

PIL2502

COL2

5

PIL2601

PIL2602

COL2

6

PIQ101

PIQ104

PIQ105 COQ1 PIQ201

PIQ204

PIQ205 COQ2

PIR7901PIR7902 COR7

9

PIU3501

PIU3503

PIU3504

COU3

5

PIU3601

PIU3602

PIU3603

PIU3604

PIU3605

PIU3606

PIU3607

PIU3608

PIU3609

PIU3

6010

PIU36011

PIU3

6012

PIU3

6013

PIU36014

PIU3

6015

COU3

6

PIU370

1PIU370

3

PIU3704

COU3

7

PIU3

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PIU380

2

PIU3

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PIU3804

PIU3805

PIU3806

PIU3807

PIU3808

PIU380

9COU3

8

PIU3901

PIU3902

PIU3903

PIU3904

PIU3905

PIU3906

PIU3907

PIU3908

PIU3909

COU3

9

PIC29001PIU370

1

PIC29301PIU3805

PIU3806

PIC28301PIU3501

PIC28801

PIF101

PIF201

PIF301

PIL2502

PIU3604

PIC29901

PIL2602

PIU3904

PIC28502PIC28602

PIC29502PIC29602

PIC30001PIC30101

PIC30201PIC30301

PIF401

PIQ105

PIU3602

PIU3907

PIC28901PIF202

PIU370

3NL1080IN

PIC29402PIU3

801

NL10BYP

PIC29202PIF302

PIU3804

PIU3808

NL10

IN

PIC28201PIF102

PIU3503

NL2050IN

PIC284

01PI

U360

12NL

3030

BST

PIQ104

PIU36011

NL3030HG

PIQ204

PIU3

6013

NL30

30LG

PIC28702PIU3606

NL30

30SS

PIC284

02

PIL2501

PIQ101 PIQ205

PIU3

6010

NL3030SW

PIC29102PIU3601

NL30

30VC

C

PIC29701PIU3901

NL50

BOOT

PIR7902PIU3903

NL50

RT

PIC29802PIU3902

NL50SS

PIC29702 PID101PIL2601

PIU3908

NL50

SW

PIC28202PIC28302

PIC28501PIC28601

PIC28701

PIC28802PIC28902

PIC29002

PIC29101

PIC29201PIC29302

PIC29401

PIC29501PIC29601

PIC29801PIC29902

PIC30002PIC30102

PIC30202PIC30302

PID102

PIJ6002

PIQ201

PIR7901

PIU3504

PIU3605

PIU3609

PIU36014

PIU3

6015

PIU3704

PIU3

803

PIU380

9

PIU3906

PIU3909

PIF402PIJ6001

PIU3603

PIU3607

PIU3608

PIU380

2

PIU3807

PIU3905

Figure A.25: TIB: Power supplies

236 A. Schematics

11

22

33

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BB

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Title

Num

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D6

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+5V

+3.3

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+1V

2.4K

R82

Res

350

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R83

Res

333

0

R84

Res

324

9

R85

Res

310

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R86

Res

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GN

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GN

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GN

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S2 M3

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S3 M3

grou

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S4 M3

grou

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S5 M3

grou

nded

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S6 M3

grou

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S7 M3

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GN

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boa

rd.

PID201PID202CO

D2

PID301PID302CO

D3

PID401PID402COD

4

PID501PID502COD

5

PID601PID602COD

6

COFD5

COFD

6

PIR8201PIR8202CO

R82

PIR8301PIR8302CO

R83

PIR8401PIR8402CO

R84

PIR8501PIR8502CO

R85

PIR8601PIR8602CO

R86

PIS100COS

1

PIS200COS

2

PIS300COS

3

PIS400COS

4

PIS500COS

5

PIS600COS

6

PIS700COS

7

PID602PID502

PID402PID302

PID202 PIR8201PIR8301

PIR8401PIR8501

PIR8601

PIS100

PIS200

PIS300

PIS400

PIS500

PIS600

PIS700

PID201 PIR8202

PID301 PIR8302

PID401 PIR8402

PID501 PIR8502

PID601 PIR8602

Figure A.26: TIB: Power monitor LEDs, mechanical holes and grounding

Appendix B

Bill of materials

B.1 Bill of materials of Level 1

The following table shows the cost of the different devices which are part of the Level 1 triggersubsystem:

Functionality Reference ManufacturerCost/unit(AC)

QuantityTotal cost(AC)

min max min max

Differential AD8003 Analog Devices 2.92 3.44 2 5.84 6.88to Resistors Various 0.01 0.02 36 0.36 0.72

single-ended Capacitors Various 0.02 0.05 12 0.24 0.60

Inductors Tyco Electronics 0.10 0.15 6 0.60 0.90Splitter 3 Resistors Various 0.01 0.02 8 0.08 0.16

Capacitors Various 0.02 0.05 10 0.20 0.50

Inductors Tyco Electronics 0.10 0.15 4 0.20 0.40Splitter 2 Resistors Various 0.01 0.02 4 0.04 0.08


Attenuator Resistors Various 0.01 0.02 4 0.04 0.08

Switching ADG901 Analog Devices 0.98 1.02 8 7.84 8.16Network Capacitors Various 0.02 0.05 16 0.32 0.80

Matching and Resistors Various 0.01 0.02 19 0.19 0.38decoupling Capacitors Various 0.02 0.05 22 0.44 1.10

Slow Control 74HC00 NXP 0.10 0.15 1 0.10 0.15Logic SN74LVC1G32 Texas Inst. 0.12 0.14 1 0.12 0.14


AD8003 Analog Devices 2.92 3.44 1 2.92 3.44Adder Resistors Various 0.01 0.02 27 0.27 0.54


Comparator ADCMP604 Analog Devices 2.18 2.78 3 6.54 8.34Capacitors Various 0.02 0.05 9 0.18 0.45

Comparator ADCMP604 Analog Devices 2.18 2.78 3 6.54 8.34Colibri Capacitors Various 0.02 0.05 9 0.18 0.45

238 B. Bill of materials

HSMS2855 Avago Tech. 0.67 0.72 3 2.01 2.16LVDS ADCMP604 Analog Devices 2.18 2.78 1 2.18 2.78

OR gate Resistors Various 0.01 0.02 6 0.06 0.12Capacitors Various 0.02 0.05 3 0.06 0.15

LVDS HSMS2855 Avago Tech. 0.67 0.72 3 2.01 2.16OR gate ADCMP604 Analog Devices 2.18 2.78 1 2.18 2.78Colibri Resistors Various 0.01 0.02 6 0.06 0.12


LVDS HSMS2855 Avago Tech. 0.67 0.72 2 1.34 1.44AND gate ADCMP604 Analog Devices 2.18 2.78 1 2.18 2.78

Delay Resistors Various 0.01 0.02 4 0.04 0.08Calibration Capacitors Various 0.02 0.05 3 0.06 0.15

Width to HSMS2855 Avago Tech. 0.67 0.72 1 0.67 0.72Amplitude OPA2830 Texas Inst. 0.76 1.00 1 0.76 1.00

Delay Resistors Various 0.01 0.02 6 0.06 0.12Calibration Capacitors Various 0.02 0.05 6 0.12 0.30

Read ADCMP600 Analog Devices 1.25 1.45 1 1.25 1.45Pulse ADG801 Analog Devices 0.65 0.75 1 0.65 0.75

Amplitude AD7478A Analog Devices 0.65 0.75 1 0.65 0.75Delay Resistors Various 0.01 0.02 3 0.03 0.06

Calibration Capacitors Various 0.02 0.05 14 0.28 0.70

Output switch ADG936 Analog Devices 1.10 1.20 1 1.10 1.20Delay Calib. Capacitors Various 0.02 0.05 3 0.06 0.15

Power Supply AP2141 Diodes Zetex 0.30 0.35 1 0.30 0.35Delay Resistors Various 0.01 0.02 1 0.01 0.02

Calibration Capacitors Various 0.02 0.05 7 0.14 0.35

DAC AD5663R Analog Devices 3.10 3.50 1 3.10 3.50Capacitors Various 0.02 0.05 12 0.24 0.60

Total Components 319 55.26 70.40

Table B.1: Level 1 bill of materials per cluster: Componentcosts in AC

Table B.1 comprise the costs of the components, which correspond to the final cost of the Level 1once it will be integrated in the front-end boards. However, the cost of the mezzanines used for thefirst prototypes was somewhat more expensive. Table B.2 gathers the additional costs of each newmanufactured mezzanine, while table B.3 shows the fixed costs of a PCB production, to be sharedamong all the manufactured boards.

B. Bill of materials 239

ConceptManufacturer

Unit price(AC)Quantity

Total cost(AC)min max min max

Connector Samtec 5.00 6.65 1 5.00 6.65QMSS-016-06.75-L-D-DP-A

Connector Samtec 7.00 7.99 1 7.00 7.99QMSS-016-06.75-L-D-DP-PC4

Capacitors for Various 0.02 0.05 6 0.12 0.30power filtering

FR4 multilayer Lab Circuits 3.32 8.56 1 3.32 8.56PCB manufacturing

Board SETI 19.94 30.40 1 19.94 30.40assembly Electronica

Additional mezzanine cost (AC) 35.38 53.90

Table B.2: Level 1 bill of materials per cluster: Mezzanine manufacturing costs in AC

Concept ManufacturerUnit price(AC)


min max min max

PCB manufacturingLab Circuits 597.00 1056.00 1 597.00 1056.00

fixed costs

Silk Screen SETI Electronica 150.00 150.00 2 300.00 300.00

SMD Pick & Place program SETI Electronica 120.00 120.00 1 120.00 120.00

Board batch production fixed cost (AC) 1017.00 1476.00

Table B.3: Level 1 mezzanine production fixed costs in AC


B.2 Bill of materials of the trigger interface board

Table B.4 contains all the costs required to manufacture one trigger interface board module.Unlike in the case of Level 1, the TIB is an independent module, so the costs of manufacturing thePCB and assembling the components must be always taken into account. Additionally, there willbe also some fixed costs gathered in table B.5 to be shared between all the manufactured boards1. The total number of TIBs will quite smaller, so from the manufacturer point of view all of theboards will be considered as prototypes, which means more expensive prices.

Component ValueUnit price (AC)

QuantityCost (AC)

min max min max

LP38690DT-2.5 0.79 0.91 1 0.79 0.91

LM22672MR-5.0 2.00 2.72 1 2.00 2.72

CDCV304PWRG4 1.63 2.08 1 1.63 2.08

DS1123L-200 11.51 11.51 9 103.59 103.59

SFP box x4 24.93 27.61 3 74.79 82.83

LP38691DT-1.8 0.62 0.826 1 0.82 0.83

CSD18534Q5A 0.76 1.89 2 1.52 3.78

Artix-7 FPGA 203.50 203.50 1 203.50 203.50

B240A-13-F 0.057 0.079 1 0.06 0.08

JTAG connector 0.836 1.41 1 0.84 1.41

Jumper 2 vias 0.062 0.072 1 0.062 0.072

SN65LVDS101 2.68 4.19 12 32.16 50.28

LP3878SD-ADJ 0.92 1.87 1 0.92 1.87

SN65LVDS100 2.60 4.19 12 31.20 50.28

Raspberry Pi3.03 10.13 1 3.03 10.13

connector

RJ45 connector 15.79 17.74 1 15.79 17.74

Power connector 0.68 1.23 1 0.68 1.23

LM3151MHE-3.3 3.16 3.84 1 3.16 3.84

TC77 0.61 0.67 1 0.61 0.67

Green LED SMD 0.038 0.053 5 0.19 0.27

Fuse 0.5 A 0.775 1.141 1 0.78 1.14

Capacitor 0603 10V 1 µF 0.003 0.009 4 0.01 0.04

Capacitor 0603 50V 1 µF 0.032 0.1 1 0.03 0.1

Inductor 0805 1 µH 0.055 0.092 24 1.32 2.21

Inductor 0603 1 µH 0.044 0.11 4 0.18 0.44

Fuse 1.5 A 0.674 1.063 2 1.35 2.13

Capacitor 0805 2.2 µF 0.077 0.168 1 0.08 0.17

Resistor 0603 2.4 kΩ 0.009 0.016 1 0.01 0.02

Fuse 2.5 A 0.594 0.874 1 0.59 0.87

Resistor 0603 4.7 kΩ 0.004 0.008 3 0.01 0.02

Capacitor 0805 4.7 µF 0.183 0.51 2 0.37 1.02

1Considering LSTs and MSTs, in North and South observatories, around 50 operating TIBs are expected. Somemore TIBs must be produced as spares

B. Bill of materials 241

Capacitor 0603 4.7 µF 0.015 0.026 1 0.02 0.03

Capacitor 0402 4.7 µF 0.099 0.198 44 4.36 8.71

Inductor XAL1010 8.3 µH 2.55 2.78 1 2.55 2.78

Resistor 0603 10 kΩ 0.006 0.011 60 0.36 0.66

Capacitor 0603 10 nF 0.008 0.014 2 0.02 0.03

Capacitor 0805 10V 10 µF 0.011 0.02 64 0.70 1.28

Capacitor 0805 25V 10 µF 0.083 0.143 1 0.08 0.14

Capacitor 0805 15 nF 0.008 0.013 1 0.01 0.01

Inductor XAL5050 22 µH 0.86 0.95 1 0.86 0.95

Capacitor 0603 39 nF 0.005 0.009 1 0.01 0.01

Capacitor 1812 47 µF 0.77 1.71 3 2.31 5.13

Resistor 0603 61.9 kΩ 0.017 0.027 1 0.02 0.03

Resistor 0402 100 Ω 0.006 0.01 2 0.01 0.02

Resistor 0603 100 Ω 0.006 0.01 15 0.09 0.15

Capacitor 0603 25V 100 nF 0.007 0.012 75 0.53 0.90

Capacitor 0805 100 nF 0.011 0.024 1 0.01 0.02

Capacitor 0603 50V 100 nF 0.011 0.014 1 0.01 0.01

Capacitor 0603 100 pF 0.009 0.012 36 0.32 0.42

Capacitor 0402 100 pF 0.005 0.009 4 0.02 0.04

Capacitor 1206 100 µF 0.11 0.235 4 0.44 0.94

Capacitor 1210 100 µF 0.69 1.29 9 6.21 11.61

Al capacitor 180 µF 1.00 1.75 2 2.00 3.50

Al capacitor 220 µF 0.165 0.228 1 0.17 0.23

Resistor 0603 249 Ω 0.006 0.011 1 0.01 0.01

Resistor 0603 330 Ω 0.007 0.011 2 0.01 0.02

Ta Capacitor 330 µF 1.47 3.83 1 1.47 3.83

Capacitor 0603 470 nF 0.017 0.033 1 0.02 0.03

Capacitor 0402 470 nF 0.017 0.022 65 1.11 1.43

Resistor 0603 500 Ω 0.009 0.016 1 0.01 0.02

Screw M2.5 plane 12 mm 0.0177 0.0213 11 0.19 0.23

Nut M2.5 plane 2 mm 0.0136 0.0163 9 0.12 0.15

Spacer M2.5 5 mm 0.092 0.152 9 0.83 1.37

Washer M2.5 0.023 0.028 9 0.21 0.25

Spacer M2.5 12.7 mm 0.041 0.0803 2 0.08 0.16

Raspberry Pi 39.00 39.00 1 39.00 39.00

SFP transceiver40.38 41.91 12 484.56 502.92

Avago AFBR5715ALZ

SFP connector 4.03 4.24 12 48.36 50.88

Al Rack box 1U 220 mm 30.80 32.75 1 30.80 32.75

Closed cover plate 220 mm 10.16 11.54 1 10.16 11.54

Ventilated cover plate 220 mm 17.20 19.57 1 17.20 19.57

PCB 411.17 411.17 1 411.17 411.17

Component assembly 1

Total components 570 1548.24 1548.24


Table B.4: Bill of materials of 1 Trigger Interface Board

Concept ManufacturerUnit price(AC)


min max min max

PCB manufacturingLab Circuits 1468.00 1468.00 1 1468.00 1468.00

fixed costs

Silk Screen SETI Electronica 2

SMD Pick & Place program SETI Electronica 1

Board batch production fixed cost (AC) 1468.00 1468.00

Table B.5: Fixed costs of the Trigger Interface Board

The costs of table B.4 correspond to the first TIB prototype. The costs of the final version whichwill be installed in the telescopes cameras will be slightly different. For instance, one of the mostexpensive components are the optical transceivers (c.a. 40 ACeach), of which there are 12 units inthe prototype. In the real case, it is very unlikely to have more than 4 LSTs in each observatory,so there would be only 3 neighbours in the case of LSTs and 0 neighbours in the case of MSTs.Additionally, other optical link is an spare and other is reserved to check the performance of theoptical delay of the signals. So in fact, only 5 from the 12 optical transceivers are strictly requiredfor LSTs and 2 for MSTs, which involves saving up to 280 ACin the boards installed in LSTs and 400ACin the ones placed in MST cameras. As was explained in section 7.4.2.2, all the TIBs will have thehousing for the 12 transceivers mounted, but only the required transceivers will be installed. In thesame way, another significant costs are the delay chips, which need to be tested before deciding touse them in the final version.

Appendix C

Reliability

In a large project as CTA, it is very important to estimate the reliability of the different systemsproperly in order to foresee the number of spares required, the human resources which should bededicated to reparations, and in sum the budget required for maintenance. With this aim, all thesubsystems must provide to the system engineers with their reliability estimations. This appendixcontains the reliability estimations for the Level 1 (table C.1) and the Trigger Interface Board (tableC.2). For this estimations, the Middle Time Between Failures (MTBF) or the Failure In Time(FIT) information provided by the manufacturers of the different active components has been used.However, for the pasive components this information is sometimes difficult to find, and due to thehigh number of elements and the different manufactures which can produce equivalent components,getting the MTBF or the FIT from the manufacturers would be and endless task. For this reason, thereliability of the passive components have been estimated with the generic prediction models includedin the FIDES guide[172], instead of with their specific data. A free software tool implementing theseprediction models have been used [173], as shown in figure C.1.

Figure C.1: Free MTBF calculator, from ALD [173]

244 C. Reliability

Component Value Unit MTBF (hours) Quantity FIT (in 1 hour)

Capacitor 0603 100 nF 1.82 · 1010 33 1.81 · 10−9

Capacitor 0805 10 µF 1.82 · 1010 31 1.70 · 10−9

Capacitor 0603 10 µF 1.82 · 1010 23 1.26 · 10−9

Capacitor 0603 100 pF 1.82 · 1010 32 1.76 · 10−9

Capacitor 0603 1 nF 1.82 · 1010 8 4.39 · 10−10

Capacitor 0603 4 pF 1.82 · 1010 2 1.10 · 10−10

Capacitor 0603 2 pF 1.82 · 1010 10 5.49 · 10−10

Capacitor 0603 5.6 pF 1.82 · 1010 2 1.10 · 10−10

Capacitor 0603 1 pF 1.82 · 1010 2 1.10 · 10−10

Capacitor 1206 Ta 68 µF 1.58 · 109 1 6.33 · 10−10

Capacitor 0603 10 nF 1.82 · 1010 2 1.10 · 10−10

Capacitor 0805 33 µF 1.82 · 1010 1 5.49 · 10−11

Capacitor 0603 120 pF 1.82 · 1010 2 1.10 · 10−10

Capacitor 0603 68 pF 1.82 · 1010 1 5.49 · 10−11

Capacitor 0603 47 pF 1.82 · 1010 1 5.49 · 10−11

Capacitor 1206 Ta 100 µF 1.58 · 109 1 6.33 · 10−10

Capacitor 1206 1 µF 1.82 · 1010 1 5.49 · 10−11

Inductor 0402 15 nH 4.34 · 109 4 9.22 · 10−10

Inductor 0402 20 nH 4.34 · 109 6 1.38 · 10−9

Resistor 0603 100 Ω 3.28 · 1010 10 3.05 · 10−10

Resistor 0603 200 Ω 3.28 · 1010 18 5.49 · 10−10

Resistor 0603 49.9 Ω 3.28 · 1010 23 7.01 · 10−10

Resistor 0603 62 Ω 3.28 · 1010 2 6.10 · 10−11

Resistor 0603 261 Ω 3.28 · 1010 4 1.22 · 10−10

Resistor 0603 56 Ω 3.28 · 1010 8 2.44 · 10−10

Resistor 0603 60.4 Ω 3.28 · 1010 4 1.22 · 10−10

Resistor 0603 360 Ω 3.28 · 1010 8 2.44 · 10−10

Resistor 0603 470 Ω 3.28 · 1010 8 2.44 · 10−10

Resistor 0603 330 Ω 3.28 · 1010 4 1.22 · 10−10

Resistor 0603 191 Ω 3.28 · 1010 2 6.10 · 10−11

Resistor 0603 620 Ω 3.28 · 1010 3 9.15 · 10−11

Resistor 0603 1 kΩ 3.28 · 1010 2 6.10 · 10−11

Resistor 0603 0 Ω 3.28 · 1010 1 3.05 · 10−11

Resistor 0603 100 kΩ 3.28 · 1010 1 3.05 · 10−11

Resistor 0603 10 kΩ 3.28 · 1010 4 1.22 · 10−10

Resistor 0603 1.8 kΩ 3.28 · 1010 4 1.22 · 10−10

Resistor 0603 1 MΩ 3.28 · 1010 4 1.22 · 10−10

Resistor 0603 390 kΩ 3.28 · 1010 1 3.05 · 10−11

Resistor 0603 1.5 kΩ 3.28 · 1010 1 3.05 · 10−11

Resistor 0603 3.3 kΩ 3.28 · 1010 12 3.66 · 10−10

Diode HSMS2855 1.50 · 1011 9 6.00 · 1011

74HC00 logic gate 1.51 · 108 1 6.62 · 10−9

ADG901 RF switch 8.88 · 108 8 9.01 · 10−9

C. Reliability 245

AP2141 power switch 1.00 · 109 1 1.00 · 10−9

SN74LVC1G32 logic 9.66 · 108 1 1.04 · 10−9

AD5663R DAC 3.67 · 109 1 2.73 · 10−10

AD8003 Op.Amp. 5.73 · 109 3 5.23 · 10−10

ADCMP604 comparator 5.73 · 109 9 1.57 · 10−9

ADG936 RF switch 8.88 · 108 1 1.13 · 10−9

OPA2830 Op.Amp. 9.84 · 107 1 1.02 · 10−8

ADCMP600 comparator 5.73 · 109 1 1.74 · 10−10

ADG801 switch 3.67 · 109 1 2.73 · 10−10

AD7478A ADC 3.67 · 109 1 2.73 · 10−10

System FIT 4.77 · 10−8

System MTBF (hours) 2.09 · 107

System MTBF (years) 2391

Table C.1: Reliability estimation for the Level 1, only com-ponents

According with table C.1, An average of only 1 failure in each 2391 years is expected. Thisnumber is very high, because it corresponds to a relatively small subsystem. Considering that therewill be 265 Level 1 modules in each camera, every camera will suffer one Level 1 failure in 9 years asan average. Additionally, it is important to notice that the estimation of table C.1 corresponds onlyto the components, considering that the Level 1 is integrated in the front-end board. If the Level 1is installed as a mezzanine, the failure rate of the connectors must be taken into account. Accordingto FIDES model, for a 52 contacts SMD connector, a MTBF of 1.13 ·108 is expected. Once includedin the estimation, an MTBF of 1.53 · 107 hours (1745 years) is obtained for the Level 1 mezzanine.

Component Value Unit MTBF (hours) Quantity FIT (in 1 hour)

LP38690DT-2.5 1.81 · 109 1 5.51 · 10−10

LM22672MR-5.0 4.62 · 108 1 2.17 · 10−9

CDCV304PWRG4 3.41 · 108 1 2.93 · 10−9

DS1123L-200 7.13 · 108 9 1.26 · 10−8

SFP box x4 9.14 · 107 3 3.28 · 10−8

LP38691DT-1.8 1.81 · 109 1 5.51 · 10−10

CSD18534Q5A 3.45 · 108 2 5.80 · 10−9

Artix-7 FPGA 1.43 · 108 1 7.00 · 10−9

B240A-13-F 4.34 · 108 1 2.30 · 10−9

JTAG connector 3.64 · 108 1 2.75 · 10−9

Jumper 2 vias 9.64 · 108 1 1.04 · 10−9

SN65LVDS101 2.88 · 108 12 4.17 · 10−8

LP3878SD-ADJ 1.99 · 108 1 5.02 · 10−9

SN65LVDS100 2.88 · 108 12 4.17 · 10−8

Raspberry Pi2.67 · 108 1 3.74 · 10−9

connector

RJ45 connector 1.70 · 108 1 5.87 · 10−9

Power connector 9.64 · 108 1 1.04 · 10−9

246 C. Reliability

LM3151MHE-3.3 4.62 · 108 1 2.17 · 10−9

TC77 2.99 · 108 1 3.34 · 10−9

Green LED SMD 5.39 · 108 5 9.28 · 10−9

Fuse 0.5 A 2.04 · 108 1 4.90 · 10−9

Capacitor 0603 10V 1 µF 1.82 · 1010 4 2.20 · 10−10

Capacitor 0603 50V 1 µF 1.82 · 109 1 5.49 · 10−11

Inductor 0805 1 µH 4.34 · 109 24 5.53 · 10−9

Inductor 0603 1 µH 4.34 · 109 4 9.22 · 10−10

Fuse 1.5 A 2.06 · 108 2 9.69 · 10−9

Capacitor 0805 2.2 µF 1.82 · 1010 1 5.49 · 10−11

Resistor 0603 2.4 kΩ 3.28 · 1010 1 3.05 · 10−11

Fuse 2.5 A 2.05 · 108 1 4.88 · 10−9

Resistor 0603 4.7 kΩ 3.28 · 1010 3 9.15 · 10−11

Capacitor 0805 4.7 µF 1.82 · 1010 2 1.10 · 10−10

Capacitor 0603 4.7 µF 1.82 · 1010 1 5.49 · 10−11

Capacitor 0402 4.7 µF 1.82 · 1010 44 2.42 · 10−9

Inductor XAL1010 8.3 µH 2.63 · 107 1 3.80 · 10−8

Resistor 0603 10 kΩ 3.28 · 1010 60 1.83 · 10−9

Capacitor 0603 10 nF 1.82 · 1010 2 1.10 · 10−10

Capacitor 0805 10V 10 µF 1.82 · 1010 64 3.51 · 10−9

Capacitor 0805 25V 10 µF 1.82 · 1010 1 5.49 · 10−11

Capacitor 0805 15 nF 1.82 · 1010 1 5.49 · 10−11

Inductor XAL5050 22 µH 2.63 · 107 1 3.80 · 10−8

Capacitor 0603 39 nF 1.82 · 1010 1 5.49 · 10−11

Capacitor 1812 47 µF 1.82 · 1010 3 1.65 · 10−10

Resistor 0603 61.9 kΩ 3.28 · 1010 1 3.05 · 10−11

Resistor 0402 100 Ω 3.28 · 1010 2 6.10 · 10−11

Resistor 0603 100 Ω 3.28 · 1010 15 4.57 · 10−10

Capacitor 0603 25V 100 nF 1.82 · 1010 75 4.12 · 10−9

Capacitor 0805 100 nF 1.82 · 1010 1 5.49 · 10−11

Capacitor 0603 50V 100 nF 1.82 · 1010 1 5.49 · 10−11

Capacitor 0603 100 pF 1.82 · 1010 36 1.98 · 10−9

Capacitor 0402 100 pF 1.82 · 1010 4 2.20 · 10−10

Capacitor 1206 100 µF 1.82 · 1010 4 2.20 · 10−10

Capacitor 1210 100 µF 1.82 · 1010 9 4.94 · 10−10

Al capacitor 180 µF 1.82 · 109 2 1.10 · 10−9

Al capacitor 220 µF 1.82 · 109 1 5.48 · 10−10

Resistor 0603 249 Ω 3.28 · 1010 1 3.05 · 10−11

Resistor 0603 330 Ω 3.28 · 1010 2 6.10 · 10−11

Ta Capacitor 330 µF 1.58 · 109 1 6.34 · 10−10

Capacitor 0603 470 nF 1.82 · 1010 1 5.49 · 10−11

Capacitor 0402 470 nF 1.82 · 1010 65 3.57 · 10−9

Resistor 0603 500 Ω 3.28 · 1010 1 3.05 · 10−11

Raspberry Pi 2.00 · 106 1 5.00 · 10−7

C. Reliability 247

SFP transceiver3.49 · 107 12 3.44 · 107

Avago AFBR5715ALZ

System FIT 1.15 · 10−6

System MTBF (hours) 8.68 · 105

System MTBF (years) 99

Table C.2: Reliability estimation for the Trigger InterfaceBoard

In the case of the Trigger Interface Board, a MTBF of 8.65 · 105 hours (99 years) is obtained.This is much smaller than the MTBF of the Level 1 because the system has more components andbecause there are two components specially critical: the SFP transceivers and the Raspberry Pi.

It is difficult to find reliability information about the Raspberry Pi, but it is known that itsreliability is limited by the MTBF of the SD card used as hard disk drive (to store the operatingsystem, the slow control software, etc.). The best SD cards have an MTBF of around 2 millionhours. Nevertheless, this estimation considers that the SD card is read and write quite often, as inthe case of using it in a photograph camera, reaching the maximum number of times that the cardcan be written. In the case of the Raspberry Pi used in the TIB, the SD card contains the softwarerunning in the computer, but it is not used to store data, so it will be written only for softwareupdating. Therefore, a longer lifetime for the SD card could be possible.

Regarding the SFP transceivers, there is not much to do to enlarge their lifetime, apart fromavoiding to work at high temperatures. Anyway, as there is only one Trigger Interface Board percamera, 99 years of MTBF is acceptable.

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Firmado: Luis Angel Tejedor Alvarez.

Doctor Ingeniero de Telecomunicacion.

Madrid, 15 de Julio de 2014

7.2 Hardware stereo trigger - Archivo Digital UPM

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