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Eindhoven University of Technology

MASTER

Frequency control in an optical polarization diversity transceiver

Janssen, A.W.L.

Award date:1996

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Eindhoven tLi) University of Technology

Faculty of Electrical EngineeringTelecommunications division

Frequency Control in an OpticalPolarization Diversity Transceiver

by

A.W.L. Janssen

Graduation report

Period:

Mentors:

Supervisors:

April 1993 - December 1993

ir. H.P.A. van den Boom

ir. E.J.E. van der Put

ing. P.K. van Bennekom

prof. ir. G.D. Khoe

dr. ir. w.e. van Etten

The faculty of Electrical Engineering of the Eindhoven University of

Technology does not accept any liability for the contents of student

and graduation reports

Summary

The Telecommunications division of the Eindhoven University of Technology is

developing an optical polarization diversity transceiver. The transceiver contains two

lasers: a transmitting laser an a local oscillator (LO) laser. For coherent detection, the LO

laser must be frequency locked to the received signal. When there is a frequency lock, the

Intermediate Frequency (IF) of the detected baseband signal will be 465 MHz. To prevent

interference between the up and down stream waves, their optical frequencies are

separated by 3 GHz.

A frequency controller has been developed to control the LO laser. The controller

consists of two parts: an analog part to detect the Intermediate Frequency (IF) and a

digital part to control the laser's frequency, on the basis of the detected IF.

The analog detection circuit is a modified version of the delay and multiply demodulator

which is used in the system. To deal with the varying state of polarization, the received

optical signal is split up into two orthogonal components which are detected separately.

Two discriminators have been implemented to process both components. The total

detection circuit produces a dc-signal that is proportional to the IF. After the

modification, the dynamic range of the discriminator amounts to approximately 900 MHz.

The digital part is build up around a micro controller that receives the discriminator's

signal after an analog to digital conversion. The control algorithm controls the LO

frequency by controlling the laser current and laser temperature. The algorithm consists

of two parts: a start up sequence to obtain frequency lock and a tracking loop to maintain

frequency lock. Theoretically, the tracking range of the controller amounts to 64 GHz.

The controller has been tested by using a test signal generator because the lasers were not

yet operative when the controller was ready for testing. The controller was able to lock

the test signal at 465 MHz and easily regain frequency lock after a forced frequency shift

(step) of 50 MHz. The broadening of the spectrum due to phase modulation by the

controller is approximately 150 kHz.

Contents

Acronyms and Abbreviations 1

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2

2. Frequency Control , 4

2.1 Necessity for Frequency Control . 4

2.2 Methods for Frequency Detection 4

3. The Delay and Multiply Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6

3.1 Theoretical Analysis . . . . . . . . . 6

3.2 Matlab Simulations . . . . . . . . . 8

3.2.1 Operation under optimal conditions . . . . . . . . . . . . . . . . . .. 8

3.2.2 Influence of shifting the spectrum 11

3.3 Measurements 12

3.3. 1 Static transfer characteristic 13

3.3.2 Shifting of the CPFSK-spectrum . 15

3.3.3 Transfer function of the variable gain amplifier 17

4. Influence of Saturation in the Mixer . 18

4.1 Polarization Diversity . . . . . . . . . . . . . . . . . . . . . 19

4.2 Mathematical Approximation of the Saturation Process 20

4.3 Frequency Dependence 22

4.4 Influence of Power Distribution on Baseband Signal 24

5. Automatic Gain Control 27

5.1 Principle of Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2 De~ection of Ai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3 Realization of the AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.4 Measurements 30

5.4.1 Tuning of the loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.4.2 Static transfer function with AGC operative 31

6. Micro Control Board 33

6.1 Structure of the Control Board 33

6.1.1 Choice of the micro controller 33

6.1.2 Block diagram 33

6. 1.3 Memory structure 34

6.1.4 Analog part 34

6.1.5 External communication 35

6.2 Peripheral Equipment 35

6.2.1 EPROM emulator 35

6.2.2 PC LED display 36

6.3 Test Software 36

6.3.1 Alive.pas 36

6.3.2 Dactest.pas 37

6.3.3 Display.pas 37

6.3.4 Adctest.pas 38

6.3.5 Standard procedures 39

7. Frequency Control System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... 40

7.1 Control Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2 Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.2.1 Start up sequence 42

7.2.2 Tracking loop 42

7.3 Implementation in Software 43

7.3.1 Start up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.3.2 Tracking loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.4 Measurements 44

7.4.1 Measurement set-up 44

7.4.2 Step response 46

7.4.3 Phase noise introduced by the controller . . . . . . . . . . . . . . . . 47

8. Conclusions and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

References 49

Appendix A: Matlab Programs and Functions 53

Appendix B: Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Appendix C: Schematic Diagrams 65

Appendix D: Printed Circuit Board Designs 68

Appendix E: Pascal Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Appendix F: CPFSK Test Signal Generator 72

Acronyms and Abbreviations

ADC Analog to Digital Converter

AFC Automatic Frequency Control(ler)

AGC Automatic Gain Control(ler)

ALE Address Latch Enable

BER Bit Error Rate

CPFSK Continuous Phase Frequency Shift Keying

D&M Demodulator Delay and Multiply Demodulator

DAC Digital to Analog Converter

DFB Laser Distributed FeedBack Laser

EPROM Erasable Programmable Read Only Memory

EUT Eindhoven University of Technology

IC Integrated Circuit

IF Intermediate Frequency

lOP Innovatief Onderzoek Programma

lSI Inter Symbol Interference

LD Laser Diode

LO Local Oscillator

LP(F) Low Pass (Filter)

NTC Resistor Negative Temperature Coefficient Resistor

PBS Polarization Beam Splitter

PCB Printed Circuit Board

PI Compensation Proportional Integral Compensation

PRBS Pseudo Random Binary Sequence

RAM Random Access Memory

ROM Read Only Memory

SCL Serial CLock

SDA Serial DAta

TL Transmitting Laser

VCO Voltage Controlled Oscillator

CHAPTER 1

Introduction

The Telecommunications division of the Eindhoven University of Technology (EUT) is

developing a Coherent Polarization Diversity Transceiver within the framework of the

innovatief onderzoek programma (lOP) EO cluster A project. Figure 1.1 shows a

schematic diagram of the transceiver; it consists of a receiving and a transmitting part. In

order to prevent interference, the optical frequencies of the received and transmitted

signal are separated by 3 GHz; the modulation format of both signals is Continuous Phase

Frequency Shift Keying (CPFSK).

TRANSMIlIliR

PD RECliLYER

~~~ataout

AFC = Automatic Frequency ControllerDEC - DecoderDEMOD - DemodulatorENC = EncoderFC = Frequency ControllerLa - Local OscillatorOpt in/out = Optical input/outputPBS = Polarization Beam SplitterPC - Polarization ControllerPD - Photo DiodePLL = Phase Locked LoopSW = SwitchTL - Transmitting Laser

Figure 1.1: Schematic diagram of the Optical Polarization Diversity Transceiver

The transceiver is build up according to the polarization diversity principle [4]. This

principle is used to eliminate the negative effects caused by the randomly varying state of

polarization of the received signal. If there is a mismatch between the states of

polarization of the received signal and the light of the Local Oscillator (LO) laser, the

mixing of both signals will not be optimal due to lack of interference.

To overcome this problem, the received optical signal as well as the LO light are split up

into two orthogonal components (x and y-component) by the polarization beam splitters

2

(PBS); subsequently, the corresponding components are mixed.

For coherent detection, the LO laser must be locked onto the frequency of the received

signal in order to obtain a stable Intermediate Frequency (IF). This task is carried out by

the Frequency Controller (FC, see Figure 1.1).

In order to maintain a separation of 3 GHz between the received and transmitted signal, a

second frequency control unit is required. The Automatic Frequency Controller (AFC,

see Figure 1.1) tunes the Transmitting Laser (TL) to a frequency which differs 3 GHz

from the LO laser.

When two transceivers (e.g. central office and subscriber) are communicating there are 4

lasers which are locked onto each other; with one reference laser, a total of 3 FCs is

needed to maintain stable operation. This means that in such a system, one of the four

FCs can be omitted. The locking procedure is more complex if both transceivers try to

lock onto the received signal frequency at the same time. It is therefore easier to equip

both transceivers with a 3 GHz controller which obtains frequency lock before there is a

connection and one transceiver with a controller for the TL which starts locking during

the connection procedure.

The laser frequencies of both Distributed FeedBack (DFB) lasers not only depend on the

laser currents (=:: 500 MHz/rnA), but also on the laser temperatures (10 - 20 GHz/K).

Temperature variations can be compensated by adjusting the laser current. However, the

current range is limited to approximately 1 rnA which corresponds to a frequency

variation of approximately 0.5 GHz; the maximum temperature variation which can be

compensated by the laser current is only (+/-)0.25 GHz/lO GHz/K = 0.025 K.

This range is insufficient for long term stable operation. Therefore, the frequency

controllers must have control over the laser current as well as the laser temperature.

The CPFSK demodulator has already been developed; the realization of the two frequency

controllers is the next step towards a digital, full duplex, optical polarization diversity

communication system.

3

CHAPTER 2

Frequency Control

For optimal performance, the CPFSK demodulator requires a signal spectrum stabilized at

an IF of 465 MHz [1].

2.1 Necessity for Frequency Control

The CPFSK signal is obtained by mixing the received optical signal with the optical

signal of the LO laser. The semiconductor lasers used to generate these optical signals

suffer from a phase noise which spectral density has two main components: 1) a high

frequency flat or white component which has the effect of broadening the spectral

linewidth of the emitted field, and 2) a low-frequency flicker component (mainly caused

by temperature variations) which causes a slow drift of the spectrum itself [5]. The effect

of this last component must be eliminated in order to stabilize the received CPFSK signal

spectrum.

2.2 Methods for Frequency Detection

To be able to control the IF of the signal, it has to be detected in a certain way. Several

methods have been reported in literature.

In [2,3] the use of a counter is mentioned; a micro controller simply counts the number of

zero crossings within a specified time interval. As a result of the high frequencies

involved, prescalers are needed to lower the IF before the counting can take place. Due to

the varying state of polarization, the signal amplitude in the different branches can vary

substantially; prescalers are very susceptible to amplitude variations and therefore this

method is not appropriate for a polarization diversity system.

In [10] the use of a bank of band pass filters is mentioned. The central frequencies of 8

band pass filters are distributed over a frequency width of approximately 1 GHz. Square

4

law detectors with Analog to Digital Convertors (ADCs) are used to detect the energy

concentrated in each filter. The information is clocked into a micro controller, which

calculates the distribution of the signal spectrum. This method is very complex and should

be implemented twice for a polarization diversity system (one for each branch); therefore,

this method will not be used for the FC.

The use of a Delay and Multiply (D&M) frequency discriminator is an attractive

alternative compared to the methods described above. The realization is relatively simple

and a polarization diversity D&M demodulator has already been developed for the project

[1].

2.3 Frequency Control by Laser Current and Temperature

As stated in the introduction, the optical frequency of DFB lasers is a function of both

laser current and temperature. If these two quantities can be controlled, the frequency can

be controlled.

The current control is rather simple; it consists of a variable current source, which directs

a stabilized current through the Laser Diode (LD). It is very important that the FC does

not vary the current too much, because not only the frequency depends on the current,

but also the output power of the laser. This could cause a considerable temperature

variation which in its turn causes a frequency shift which could be much larger than the

shift intended by changing the current. To keep these temperature variations acceptable,

the current variation should be limited to approximately 1 rnA.

The laser temperature can be controlled by a Peltier thermo-electric heat pump which can

cool or heat the laser chip; a temperature sensor (e.g. an NTC resistor) is used to detect

the temperature of the laser. These two devices are combined in a control loop which can

be used by the FC. In contrast to the current, the temperature can only be changed

slowly; the FC must take this into account by adjusting the temperature amply before the

current control falls out of range.

5

CHAPTER 3

The Delay and Multiply Demodulator

In order to gain more insight into the D&M demodulator, a brief theoretical analysis as

well as a computer simulation of this device will be described in this chapter.

Measurements to verify some of the simulations have also been performed.

3.1 Theoretical Analysis

The D&M demodulator (see Figure 3.1) can be analyzed more easily in the time domain

rather than in the frequency domain due to the multiplier which introduces a non-linear

operation.

IF filter Multiplier LP filter

Input ~~ (X)I---I \ L?u~ut

o~~-A I r'~ lillie y ~

Figure 3.1 : Block diagram D&M demodulator.

The CPFSK input signal is filtered by an IF filter to remove out of band noise. The

remaining signal is delayed by a time interval Td and multiplied by the undelayed signal

which results in an output signal containing two components: a baseband term (Vbb) and a

double frequency term (Vdj). If the input signal is denoted by x(t) =Aisin(wift+ q,) , the

signal at the output of the multiplier: y(t) = Cmt(t) 'x(t-Td) is denoted by:

(3.1)

(the term Cm is a constant [V-I] which depends on the multiplier type). The double

frequency term is cancelled out by a Low Pass (LP) filter (see Figure 3.1). The baseband

term remains after filtering and represents the demodulated signal.

6

The data bits are Manchester coded which doubles the line bit rate in comparison with the

data bit rate. The line bits are CPFSK modulated by the frequencies fo and h: the

signalling waveforms for both logical symbols "0" and "1" are depicted in Figure 3.2.

"0" "1"data bits < > ( >

<"0" "1"

> <"1" "0"

line bits )( )( >

waveforms

fo f 1 f 1 fo

Figure 3.2:

line bit time 'E--(------')Tb

Signalling waveforms of line and data bits for logical "0" and "1".

The frequency difference between the two frequencies is prescribed by the line bit rate

'b = Tb-1 and de modulation index h:

(3.2)

The delay time Td as well as the central frequency Ie = 1/2(j1 +fo) must be optimized in

order to obtain maximum performance. The maximum difference in the baseband term

occurs if the following applies to the two input frequencies (see Equation (3.1)):

i'T = 11mJo d /\ J;Td

= 1/2(n+I), for n =0, I ,2,3 ,... (3.3)

From this the following relations can be derived:

1; -10 = 81 = 1/2 Td-1 and 1; +10 = 2fc = (n+V2)T/. (3.4)

One of the system's design criteria is the modulation index which is set at 1. Another

criterion is the 155.52 Mbit/s data bit rate; the frequency difference of, is therefore

prescribed at 311.04 MHz (Equation (3.2)). According to the specifications, n = 1 in

Equation (3.4); this results in the following values:

Td = 1/20r1 = 1.61 ns,

Ie = 3f4Td-1 = 465.56 MHz,

fo = 1/2T/ = 311.04 MHz and f1 = T/ = 622.08 MHz.

The relation between the input frequency and Vbb is plotted in Figure 3.3; the frequencies

7

'hCmA2~-----------------;~,------------,

[V]

.; 0 +----+------+------t-------\---~

-Y.CmA2

775 [MHz] 930310 465 620

Input frequency155

-V2CmA2-'-----~-------'~---+------+-------,-----'>-jo

Figure 3.3: Relation between the input frequency and the baseband signal level of the D&Mdemodulator.

fe,Io and II have been rounded off to respectively 465 MHz, 310 MHz and 620 MHz.

These rounding offs will also be made in the simulations. In the figure it is clear that the

baseband term has the maximum difference of Cnr42 for the frequencies 10 and II'

3.2 Matlab Simulations

In the simulation, signals and their frequency power spectra will be described at 4

different reference planes: A,B,C and D; Figure 3.4 shows the definition of these planes.

The influence of noise will not be taken into account so that the IF filter can be omitted

in the simulation. Reference plane A therefore coincides with the input plane of the

demodulator.

Inputo

IF fllter Multiplier LP filter :

I~ 6<)1--------'---1 \ I:....:.: vOuu:!tput

f\, i Qel~:mi tY ~A B C D

Figure 3.4: Definition of reference planes in the D&M demodulator.

3.2.1 Operation under optimal conditions

In the MATLAB simulation denm.m (see Appendix A), a Pseudo Random Binary

8

Sequence (PRBS) of 10,000 symbols is generated. This sequence is Manchester coded and

CPFSK modulated at frequenciesfo=310 MHz andfl=620 MHz with a sample rate of

31 GHz. Figure 3.5 shows the signals at the four reference planes; for clarity reasons,

only the first 10 bits (Manchester coded) are shown: 1001100100.

n=RTlf[flJ{Sl£~dalasi~l

Mixed signal (ref C)

~(~~;io 10 20 30 40 50 60 [ns] 70

Time

Figure 3.5: Time domain signals at the various reference planes in the D&M demodulator.

The power spectra have been calculated and are depicted in Figures 3.6 to 3.8.

50

40

>-..........CI.l 305

'"0~Q)

~ 200~

10

00 0.2 0.4 0.6 0.8 1.0 1.2 [GHz] 1.5

Figure 3.6:

Frequency

Power spectrum Manchester coded CPFSK-signal (ref. A and B).

Figure 3.6 shows the typical CPFSK Manchester coded power spectrum. If the

9

attenuation of the delay-line is negligible, the power spectrum at reference plane B is

equal to this power spectrum.

The high frequency components at reference plane C which are introduced by the mixer

can also be recognized in the power spectrum beyond 310 MHz (Figure 3.7).

50

40

>.........5 30

'e....(I)

~ 20p.,

10

0.2 0.4 0.6 0.8 1.0 1.2 [GHz] 1.5

Figure 3.7:

FrequencyPower spectrum at the output of the mixer (ref. C).

The low pass filter (4th order Cauer filter, see [1]) successfully removes these

components; this can be seen in both the time domain picture (Figure 3.5) as the

frequency power spectrum (Figure 3.8) at reference plane D.

50

40

~....305

'e

~~ 200

p.,

10

0.2 0.4 0.6 0.8 1.0 1.2 [GHz] 1.5

Figure 3.8:

FrequencyPower spectrum at the output of the demodulator (ref. D).

10

3.2.2 Influence of shifting the spectrum

In order to determine whether the existing demodulator can be used by the frequency

controller, its response to a shift of the CPFSK signal spectrum has been simulated. The

average baseband output level has been calculated as a function of the frequency shift I::.f.

This calculation (deltaf.m see Appendix A) has been repeated for a three times smaller

delay time: with this delay time the demodulator also has a zero crossing at

f=fc=465 MHz and the frequency difference of at which the maximum difference in

baseband output level occurs, is multiplied by three. Figure 3.9 shows the two transfer

characteristics with the CPFSK signal power spectrum and the definition of

I::.f = IFcPFsKfc'

o

requency

Figure 3.9:

1_ Td-1.61 ns .--- Td-0.53 ns ICPFSK-signal spectrum shifted by I1f with respect to the transfer characteristicof the D&M demodulator.

The results of these calculations are plotted in Figure 3.10; it is clear, that for frequency

control applications, the demodulator with Td =O.53 ns has a much more attractive

characteristic than the one with Td= 1.61 ns: the range is larger because the derivative

does not change sign across the entire interval and the slope is larger which increases

sensitivity.

The difference between the two curves can be explained by the fact that the derivative of

11

the transfer characteristic for Td =0.53 ns does not change sign in the interval 0-

930 MHz, whereas the characteristic with Td=1.61 ns changes sign 3 times in the same

interval. If a delay time of 0.53 ns is used and the CPFSK spectrum is shifted by 1:::.1, as

in Figure 3.9, the contributions to the average output level of all frequency components

decrease. If a delay time of 1.61 ns is used, the contributions to the average output level

of the frequency components at the edges of the spectrum (including the delta peaks)

cancel each other out, even when the spectrum is shifted with an arbitrary I:::.f. This means

that only the frequency components in the central lobe can influence the average output

level. This explains not only the limited sensitivity, but also the limited range: when the

central lobe passes the maximum/minimum of the transfer characteristic (1:::.1> Ih-fc I), the

contributions of the frequency components in the central lobe cause the average output

level to drift back towards its initial value.

0.4 -,-------------,---------------,

200 [MHz] 300-100 0 100

Frequency deviation Llf

-200-0.4 +-----,-----,-----+-------.-----.----1

-300

F3-1.61ns- Td-0.53 oS]

Figure 3.10: Normalized average output level as a function of the frequency shift, for twodifferent delay times.

3.3 ~easureunents

Measurements have been carried out, in order to check if the simulation results coincide

with the characteristics of a real D&M demodulator. This demodulator has been

developed by E.E. Vrolijks [1].

12

3.3.1 Static transfer characteristic

The first measurement which has been carried out is the measurement of the static

transfer characteristic. The output level has been recorded as a function of the input

frequency for two different delay times: 1.61 ns and 0.53 ns. The schematic diagram of

the D&M demodulator can be found in the following figure.

50n coax delay-line mixer

multiplier

amplifier

output

!AM 81018

Figure 3.11 : Schedule of the existing D&M demodulator.

Data sheets of the active components can be found in Appendix B. The control voltage

Vgc of the Variable Gain Amplifier (VGA) was set to 4.7 V, resulting in a gain of

approximately -5 dB. With an input power (Pin) of -6 dBm (-3 dBm), this amounts to a

signal power of -11 dBm (-8 dBm) at the input of the mixer. The results of this

measurement are plotted in Figure 3.12.

250

[mY]

125

Q)>

.£S 0fr;::l

0

-125

'\\

\VV'V,,

V,VV

' ..... ,\ /.1, I

'l.. .I\. .1\'. :Iv. :1\", :1

"" ,:/\", :,\ " ,'I\ .... /

..... ~,

//-"/ \

/!" ....\1/ " \

I," '\I: . \

I. ".\L' ".\, \

I ,I \

\\

\\V,V',V'V 'V '" ,,'', ..... /-:.:.:.:.~/

800 [MHz] 1000600400200

-250 +--------,,---------,------,------,-------1

o

Frequency

""" Pin=-6 <IBm --- Pin=-3 <IBmIFigure 3.12: Static transfer characteristic D&M demodulator for two input powers: -6 dBm

and -3 dBm.

The demodulator does not have a negative power supply, therefore, the output signal is

superimposed on a dc-level of approximately 3.43 V. This dc-level will be discarded in

13

all figures.

From Figure 3.12 it is clear that at least one of the two active components is operating in

saturation: the input power is doubled whereas the amplitude of the transfer characteristic

only increases slightly instead of doubling. Another indication is that the characteristic is

smoother for Pin=-6 dBm than for Pin =-3 dBm.

After reducing the delay time to 0.53 ns, the static transfer characteristic was recorded

again. The characteristic has been measured for five different values of Vgc : 3.5 V, 3.3 V,

3.1 V, 2.9 V and 2.7 V; for these values, the power gain sweeps from -5 dB to +20 dB.

The input power amounted to -25 dBm. Figure 3.13 shows the results of these

measurements; from this figure it can be seen that the characteristic is not yet optimal:

the minimum value occurs at 820 MHz in stead of the desired 930 MHz.

600 -,---------------------------,

[mV]

400

.-< 200

j~ 0

<5 -200

-400

Soo [MHz] woo400 600

Frequency

200

-600 +---__,---------,----------.-----,------1

o

1- Vgc ·3.5 V --_. Vgc·3.3 V . .. Vgc ·3.1 V······ Vgc ·2.9 V ._. Vgc ·2.7 V IFigure 3.13: Static transfer characteristics of D&M demodulator with delay time of 0.53 ns.

After the measurement the coax delay-line has been replaced by another one which length

was optimized using a trial and error method. The transfer characteristic of the

demodulator with this delay-line is plotted in Figure 3.14; the gain control voltage Vgc

amounted to 2.7 V. The "dips" which occur around 750 MHz in Figure 3.13 have

disappeared; they were probably caused by bad soldering of the previous delay-line.

14

600

[mV]

400

'0 200>~......!j 00..!j0 -200

-400

-6000 200 400 600 800 [MHz] 1000

FrequencyFigure 3.14: Static transfer characteristic of demodulator with optimized delay time of

0.53 ns.

3.3.2 Shifting of the CPFSK-spectrum

One of the most important measurements is the measurement of the average output level

as a function of the spectrum shift fif, for this quality determines whether a D&M

demodulator is useful for the frequency controller. This measurement has also been

carried out for two different delay-lines: 1.61 ns (32.2 cm coax) and 0.53 ns (10.7 cm

coax). The set-up which generates the CPFSK test signal is described in Appendix F.

The first measurement concerned the demodulator with the 1.61 ns delay-line. The

frequency shift extended from -300 MHz to +300 MHz with steps of 10 MHz. The

measurement has been carried out for three different values of Vgc: 4.7 V, 3.5 V and

3.25 V. The results are plotted in Figure 3.15. If these results are compared with the

results of the simulations (Figure 3.10), it appears that for negative fif, there is a

resemblance between the two curves. For positive fif, this resemblance is much less. This

is probably caused by low pass filters in the CPFSK signal generator; for high frequency

shifts (> 100 MHz) these filters cancel out the high frequency components of the CPFSK

spectrum so that their influence on the average output level is eliminated. This prevents

the curve to return to 0 mV after fif exceeds 155 MHz.

The measurement with the delay-line of 0.53 ns (see Figure 3.16) has been carried out for

two amplitudes of the input signal: Ai = 10 mV and Ai =20 mY. The results are more

promising than the previous results. Not only the range and amplitude of the curve are

15

15 ,-----------,-------------,

[mY]

10

200 [MHz] 300100o-100-200

-15 +-----,------.------+------,---.---------j-300

Frequency shift Ll f

1---- 'lgc=3,25 V -- 'lgc=3,5 V --- Vgc =4,7 V

Figure 3.15: Average output level as a function of the frequency shift l:J.f of the CPFSKspectrum (Td =1.61 ns).

larger for Td =0.53 ns (as could be expected from the simulations), but also the course

becomes smoother and the derivative does not change sign between -300 MHz and

+200 MHz. In this figure the effect of the low pass filter also emerges: for

t1j> 200 MHz, the curve starts to round off due to the absence of the contributions of the

higher frequency components of the CPFSK-spectrum.

0+-----------+-'_-----------1

-100

] 300

~ 200B<6 100Cl)

bIl

j

500 ,---------------,--------------,[mY]400

-200

200 [MHz] 300100o-100-200-300 +-----,----,-----+------.-------,------1

-300

Frequency shift Llf

Figure 3.16: Average output level as a function of the frequency shift l:J.f of the CPFSKspectrum (Td =O.53 ns).

The fact that the curves for Td =0.53 ns are smoother than for Td= 1.61 ns is probably

caused by incomplete cancelling out of contributions of frequency components at the

16

edges of the spectrum as described before for the latter delay time. For different

frequency shifts, the cancelling out could result in different values for the output level.

The difference of 40 mV between the levels at b.f=O MHz is too large to have been

caused by drift in the mixer; more measurements will have to be carried out to reveal the

real cause.

3.3.3 Transfer function of the variable gain amplifier

For measurements concerning the properties of the mixer, the influence of the VGA must

be known, because test signals can not be transferred to the mixer directly, without

passing the VGA. Most of the properties are mentioned in the data sheets (Appendix B),

but an important one must be measured because it can differ considerably from the typical

values. This property is the relation between the gain G and the gain control voltage Vge

The amplitude Ao' of the output signal was measured as a function of Vge; the input signal

had an amplitude Ai of 8 mV (-30 dBm at 50 0) and a frequency of 50 MHz. The gain G

results from the quotient of both amplitudes: G(Vge)=Ao(VgJ/Ai; the results (in dB) can be

found in Figure 3.17.

35[dB]

30

25

.S20

<Ilt.:)

15

10

5

00 2 3 4 [V] 5

Gain control voltage vgc

Figure 3.17: Transfer function variable gain amplifier.

There is an important difference between this curve and the one in the data sheets: in this

curve the gain is always greater than 0 dB whereas the data sheets show a minimum gain

of -5 dB. This explains the saturation which emerges in Figure 3.12; the input power is

5 dB higher than expected.

17

CHAPTER 4

Influence of Saturation in the Mixer

The mathematical operation y(t) = C~(t)-x(t-TrJ is carried out by an active double

balanced mixer (type IAM-81018). The data sheets (see Appendix B) describe the typical

operating conditions of this mixer: linear operation takes place for an La input power

approximately between -15 dBm and -10 dBm. These typical conditions include an RF

input power of -20 dBm; this is at least 5 dB less than the La input power. This means

that the mixer is not operating under typical conditions in the D&M demodulator, because

the RF and La input powers are equal.

According to Equation (3.1), the baseband term (Vbb) of the mixer output is proportional

to the square of the input amplitude:

(4.1)

However, this only holds if the mixer is operating linearly; when the mixer enters

saturation for large Ai' the output is no longer proportional to Al. This means that the

relation between Vbb and Ai (wi=constant) is not a parabola for large Ai' Figure 4.1 shows

the relation between Vbb and Ai (1=50 MHz). It appears that for small Ai the mixer indeed

acts as a squarer; but for larger Ai (> 35 mY) saturation takes place resulting in a more

linear relation. If Ai is increased even more (> 125 mY), the saturation becomes

complete: Vbb hardly increases when Ai increases. The figure indicates that the relation

between Vbb and Ai is of the kind:

v = 1/2 C A f(A i)

hh 111 1 '

(4.2)

with f(Ai) some function of Ai which starts off at 2 for small values of Ai to converge to 0

for large values of Ai'

18

Figure 4.1:

300

[mV]

250

200

.J:l150..:'

100

50

00 50 100 150 200 250 [mV] 300

Amplitude input signal Ai

Saturation curve of the mixer.

4.1 Polarization Diversity

In a polarization diversity system, there are two separate demodulators: one for each of

the two orthogonal signal components (x and y). The amplitudes of the input signals of

these demodulators depend on the power distribution between both components; from

Figure 4.2 it is clear that the amplitudes of these components can be described by:

A . = A ,cos(1/;) and A . = A sine1/;).a ~ 1

(4.3)

y

xFigure 4.2: Signal amplitudes orthogonal components.

The output signals of both demodulators are added; if the double frequency terms are

omitted, the sum Vs of both signals is:

V, 1/2Cm(A pose1/;»2cos(W7) +1hCn,CAisin(1/;»2cos(wI'd)

1hCmA/cos(w7d)'

The simplification which eliminates the 1/;-term is only valid if the mixers are not in

19

(4.4)

saturation. The powers at which the terms AiCOS(~) and Aisin(~) are raised, depend on the

magnitude of these terms (see Equation (4.2»; if one or both powers differ from 2, the

simplification does not hold any more so that ~ also becomes a function of ~. This

means that there is no longer a direct relation between ~ and wi['

4.2 Mathematical Approximation of the Saturation Process

To reduce the influence of the noise as much as possible, the input power needs to be

maximized. On the other hand, the input power should be limited due to the influence of

~ which increases with increasing input power. To predict ~(Ai' ~), a mathematical model

of the saturation process is needed.

In Equation (4.2) the function f(A;) needs to be approximated. To view the course of

f(A;) , the following operation must be performed on the data of Figure 4.1:

log(2V IC )V = 1/2C Af(A,) ~ f(A) = hh 11/

hh 11/ I I 10g(A)(4.5)

In Figure 4.3 the results of this operation can be found, together with two approximations

of f(A i): a linear and an exponential.

2.1 -,--------------------------,

[mY]

2.0

1.9

1.7

1.6

100 150 200 250 [mY] 300


50

1.5 +-----.--------.-------,.-------r--------.-----jo

o Measurement - f(Ai)=a-bAi ---- f(Aj)=a+b exp(-cAi)

Figure 4.3: Measurement and approximation of f(A;l.

20

300

[mY]

250

200

~

150~

100

50

00

The exponential fitting of f(A) = a+bexp(-cA) has been carried out by using MATLABTM

which resulted in: a = 1.350, b = 0.722 and c = 0.00380.

The linear fitting of f(A) = a-bAi has been carried out by hand and resulted in a = 2.025

and b = 0.00175. The linear fitting concentrated on the data from Ai = 0 to 175 mV

because the curve starts to round off for values of Ai higher than approximately 175mV;

taking these values into account would result in larger deviations for the lower values of

Ai'

Using these functions, the saturation curve can be approximated; Figure 4.4 shows these

approximations.

50 100 150 200 250 [mY] 300


CJ Measurement - f(Aj)=a-bA; ---- f(Aj)=a+b exp(-eAj)

Figure 4.4: Saturation curve with linear and exponential approximation of f(A).

To compare both approximations, their deviation with respect to the actual curve has been

calculated. The deviation is defined as:

Deviation(V -V )

hh ,,,,eas hh,appr'l 00%V

hh1meus

(4.6)

The results of the calculation can be found in Figure 4.5. This figure shows that for

values of Ai < 175 mV the linear approximation is slightly better than the exponential;

clearly for values of Ai> 175mV the exponential approximation is better than the linear.

The measured values of Vbb for low values of Ai are very small and due to the resolution

of the volt meter, not very accurate; this means that for these values the outcome of

21

Equation (4.6) is also inaccurate. The large deviations for the low values of Ai should

therefore not be taken too seriously.

35[%]

30

25

d200

'.;:lCIl......> 15eu

Cl10

5

00

'", \, \, \I \I \I \I \I -,

I " \\\

\"

50 100 150 200

Amplitude input signal Ai250 [mV] 300

Figure 4.5:

1- f(Aj)~a-bAj _n_ f(Aj)=a+b exp(-cAi) IDeviation of approximations as a function of the input amplitude.

4.3 Frequency Dependence

The mathematical model is based on a measurement at a frequency of 50 MHz. The

measurement has been repeated for frequencies from 100 MHz to 900 MHz, in order to

investigate the frequency dependence. The results of these measurements can be found in

Figure 4.6.

300 ,-------------------,

[mY]

2S0

200

.} ISO

100

SO

0+---"====-=-,...--~-~--,___-~-----1

o SO 100 ISO 200 2S0 [mY] 300

Amplitude input signal Aj

0[mY]

-SO

-100

-ISO.0.0

>-200

-250

-300

-3S00 SO 100 ISO 200 2S0 [mY] 300


@ MHz-600 MHz-700 MHz -800 MHz -900 MHz I

Figure 4.6: Saturation curve for frequencies from 10 MHz to 900 MHz.

22

In Equation (4.1) the frequency dependence consist of the tenn cOS(WifTd); if this tenn is

eliminated by dividing all data by this tenn, the curves should all coincide. This operation

has been perfonned and the results can be found in Figure 4.7. Only the curves for 400

and 500 MHz clearly differ from the others. The figure also shows that for higher

amplitudes the mutual differences start to increase. This all means that the frequency

dependence can not be described by the tenn COS(WifI'd) alone. The "extra" frequency

dependence becomes substantial for Ai > 100 mV; this means that the mixer should

operate outside of this domain. In the previous paragraph it was stated that for values of

Ai < 175mV the linear approximation of f(A) was sufficient; therefore this approximation

will be used to describe the saturation process of the mixer.

350 ,---------------------------,

[mV]

~ 300>~

§ 250

,D~ 200VJ<tI

,D

"0 150~

.~1100

Z 50

0+--"'---------,-------,--------,---,-------,------------1

o 50 100 150 200 250 [mV] 300Input amplitude Ai

Figure 4.7:

I~ 10 MHz ~ 100 MHz - 200 MHz - 300 MHz - 400 MHz I~ 500 MHz - 600 MHz - 700 MHz - 800 MHz ~ 900 MHz

Saturation curve for different frequencies after elimination of COS(WifTd)-term.

Assumed that the frequency dependence is restricted to the cos(wifT~ tenn for

a<Ai < 100 mV, the saturation curves can be approximated by the linear version of f(A):

(4.7)

In Figure 4.8 all curves are approximated by this equation.

The results of the linear approximations of f(A) are satisfactory and will be used to

predict the If-dependence of ~.

23

-200

I 0 SOO MHz • 600 MHz • 700 MHz • 800 MHz • 900 MHz I

-2S0 +--~-,____~-,____~-,____~-,____---jo 20 40 60 80 100 120 140 160(mY]180


~O":"::'" . '" ~ '1

• 0

" ~o 0

z"",~'

o,---~=====_-----------,(mY]

-so

-100.c

;>"-ISO

so

o +---""i'==-.=----~-~~-,____~-,____----jo 20 40 60 80 100 120 140 160 [mY] 180


I 010 MHz ·looMHz ·2ooMHz ·3OOMHz .400 MHz I

ISO

2S0,-------------------,

[mY]

200

.r>;>"

100

Figure 4.8: Approximation of saturation curves for frequencies from 10 MHz to 900 MHz.

4.4 Influence of Power Distribution on Baseband Signal

With the results of the previous paragraphs, the total influence of the saturation process

on the baseband signal can be approximated.

As stated in Equation (4.4), the output signal ~ is the sum of two orthogonal

components: Vbbx and Vbby ' With the mathematical description of the saturation process,

~(A;, tf,wif) can be approximated as follows:

(4.8)

In Figure 4.9 this approximation (with cOS(WifTd) set to 1) can be found for A;=5, 10, 15,

20,40,60,80 and 100 mY.

%n (00] 'hn

14,---------------_(mY]

12

10

o t=====;::::=====;=====:::;:::=====:jo

I-A,-s mV --·A,-IO mV .. ·--AI-IS mV--A,-20 mvi

2S0

[mY]

200

ISO .. '

';>~

100

SO

00 'A,n ~ll'l"t {rad] lh:1l:

Figure 4.9: Sum signal Vs as a function of IIJ for various input amplitudes Ai'

It is clear that for small Ai the influence of tf is negligible, but for larger values it

24

becomes substantial. When Vs is used as a measure for wif' the accuracy of wif is

determined by the variation of Vs as a function of If;. ~ has a maximum for

If; = IA7I" ± 1/2k7l" and a minimum for If; = 0 ± 1/2k7l", with kEN (see Figure 4.9). From

Equation (4.8), wif can be determined as a function of ~, Ai and If; (see Equation (4.9)).

As stated before, the accuracy of wif is related to the variation of g(Ai,If;); if Ai is constant,

the following applies to wif:

2nf, = T/arccos [ 2V, ]mill C (A,O)mg l' [

2V ]< < -I s_- Wi[ - Td arccos - 2nf .

1 C g(A" IA n) rna"III 1

(4.10)

This means that for a certain Vp wif can be determined with an accuracy which depends

on Ai and Vs itself. The maximum and minimum values fmax and fmin (according to

Equation (4.10)) as a function of ~ are plotted in Figure 4.10 for two values of Ai (30

and 100 mY). The maximum deviation from the average (df= V2(jmax-fmin)) can also be

found in this figure.

100

I [MHz]

r 80

60.~"'>/f "'<:!

40 ~

120

::E

" I 0150 [mY] 200

,100

Ys

500 ,--- ----,

[MHz]-

__---,30

[MHz]

:..-. 2.5!

I;' 20 €

I .~

/ '>/ 15..g

~JIO~

• 5\\\

\ 0

25 [mY] 302010

500 I[MHz] I

o

g 300 I~ i

1 200 jI

I100 I

o j .---------

[min -- [max -df I [min --- {max --df IFigure 4.10: Maximum and minimum frequencies with maximum deviation as a function of Vs

for A j = 30 mV (left) and 100 mV (right).

From the figure it becomes clear that when the IF is close to the desired 465 MHz, the

measurement is very accurate regardless of the input amplitude Ai' Only when the

receiver is far out of lock, there is a clear difference between the accuracy of the

frequency measurement for different Ai: for larger Ai' the measurement becomes less

25

accurate. On the other hand the sensitivity increases for larger Ai: 50 MHz/mV for

Ai=lO mV and 1.8 MHz/mV for Ai =100 mY. These values apply to the linear part of the

curves.

From these results it can be concluded that in spite of the decreasing accuracy of the

frequency measurement, the input amplitude has its optimal value when it is maximized.

It is very important that Vs is as stable as possible in the region of operation; the influence

of noise is minimal if the sensitivity is maximized.

26

CHAPTER 5

Automatic Gain Control

In the previous chapter the importance of a stable amplitude at the input of the mixer was

stated. To compensate for variations of the input amplitude, an Automatic Gain Control

(AGC) unit is required.

5.1 Principle of Automatic Gain Control

The AGC unit is a feedback control system which controls an error signal to a minimum.

This error signal represents the difference between the actual and desired value of the

amplitude; the AGC converts this error signal to a control signal which is fed back to a

Variable Gain Amplifier (VGA). The loop gain determines the maximum value of the

error signal; if this loop gain is large enough, the amplitude variations are negligible in

the region of operation.

Due to variations in the polarization (variations of 1/;), the input powers of both

demodulators can vary even when the power of the received signal remains the same.

This effect may not influence the AGC unit. To avoid this effect, the detection of the

amplitude must take place after adding the x and y-component. Equation (4.4) showed that

the addition of both baseband components results in elimination of the 1/;-term; this not

only applies to the baseband term, but also for the double frequency term:

Vd/ = 112 Cm(A pos(1/;)?cos(2w jt- IJ2 Td)+2c/» + 1/2 Cm(A ;sin(1/;)?cos(2w jt- 1/2 Td) + 2c/»

= 1/2CmA;2COs(2wjt-IJ2Td)+2c/».

(5.1)

This term is, in contrast to the baseband term, not dependent on cOS(WifTd)' This means

that in the absence of a data signal (cos(wifTrJ=O) this term can still be used to detect Ai

or Ai2

•

27

5.2 Detection of Ai

The AGe unit which was developed for the demodulator by E. E. Vrolijks [1], used an

envelope detector for the detection of Ai' A Shottky diode followed by a low pass filter

was used to rectify the waveform. In this set-up two amplifiers were needed to generate

the required signal power and to compensate for losses in the adding circuit.

An attractive alternative for an envelope detector is a square law detector which squares

the signal as in the D&M demodulator. This results in the following expression for the

output signal ~l:

V" = [1/2 CiliA /COS(Wl'd) -1/2CmA;2Cos(2wjt-lh Td)+21» r14C},A ;4[coS2(Wl'd)-2COS(Wl'd)COS(2wjt-1/2 Td)+21» +cos2(2wjt-1/2Td)+21»]

1faC,~ ;4[2 +cos(2wifTd)-COS(4wjt-1/2Td)+41» -2cos(2w/+21» -2cos(2wjt-Td)+21»].(5.2)

A simple low pass filter can easily remove the double and quadruple frequency terms

without affecting the dc-term which is proportional to A/.

5.3 Realization of the AGe

The block diagram of the control loop can be found in Figure 5.1. The output signals of

both demodulators are added, squared, filtered, compared and finally amplified to obtain

the correct loop gain.

x-component

y-component

D&M Demodulator I

D&M Demodulator 2

Square law detector

Figure 5.1: Block diagram automatic gain control loop.

28

The electrical schedule of the realized AGC can be found in Figure 5.2. The AGC can be

split up into 3 parts: the adder, the mixer and the amplifiers. The two input buffers/

amplifiers (lC3 and IC4, type MSA 385) have two functions: 1) decoupling before adding

and 2) compensation of losses in the adding and impedance matching circuits. The actual

addition of both components is carried out in the resistor network (R3, R4 and R5) which

is a 50 n matched network with an attenuation of 6 dB.

The squaring is carried out by a double balanced mixer (type lAM 81008); both inputs

are connected and matched to the resistor network via R6/C6 and R7/C7 (C6 and C7 are

for decoupling). The output has a decoupled 50 n load resistor (R8/ClO) followed by the

first order low pass filter R9/Cll (3 dB attenuation at 10 kHz).

Figure 5.2: Electrical schedule automatic gain control loop.

Because the transfer functions of the VGAs can differ considerably, a separate differential

amplifier is needed for each VGA. The control voltage Vgc may not exceed 5 V; the use

of the LM324 opamp makes a special protection circuit redundant because it can operate

on a supply voltage of 5 V. Two opamps (lC2A and IC2B) are used as high impedance

buffers, whereas the other two opamps (IC2C and IC2D) are used as differential

amplifiers. The setpoints of both VGAs can be adjusted by the variable resistors PI and

P3; the variable resistors P2 and P4 can be used to tune the loop gain for both branches.

Surface Mounted Devices (SMDs) have been used to keep the connections short in the

high frequency part (left of the broken line). The Printed Circuit Board (PCB) design can

be found in Appendix D.

29

5.4 Measurements

Because only one demodulator was available, the measurements could only be carried out

with one input of the AGC unit; the other input needed to be loaded by a 50 0 resistor.

5.4.1 Tuning of the loop gain

Before the control loop could be tested, the correct loop gain had to be established. The

loop gain depends on the transfer function of the square law detector and the limits

imposed on the error signal.

Before the PCB was designed, an experimental set-up was used to measure the dc-part

(Vdc) of Y:.l as a function of the input power Pi of the mixer in the demodulator. The gain

of the VGA was set to 2 dB C~c=3.6 V), so that Pi = Pin,VGA [dBm] + 2 dB. This

measurement was carried out for 5 frequencies and the results are plotted in Figure 5.3.

3.6 -,-----------------------,

[V]

3.5

3.4 I~=-

3.2

3.1

( 2 dBm >-4 [dBm] -2-6-10-12

3+----.----;-------,--;------,---,-------,--------1-14

Figure 5.3:

[--<>-100 MHz ----310 MHz -...-465 MHz __ 620 MHz --930 MHz IAverage output signal square law detector as a function of Pi'

In the previous chapter it was stated that Ai should be stabilized around 100 mV (-10 dBm

over 50 0). VdC Has a range of approximately 60 mV, if a variation of ± 1 dB is tolerated

(see Figure 5.3). The dynamic range of the VGA is approximately 32 dB and the active

region of Vgc reaches from approximately 2.5 V to 4 V (see Figure 3.17). This results in

a loop gain of approximately: (4 V-2.5 V)/60 mV=25. The setpoint should be adjusted

to approximately 3.3 V to establish an average input power of -10 dBm. With these

30

specifications, the control loop is operative.

5.4.2 Static transfer function with AGe operative

If the AGC control loop operates properly, the static transfer characteristic should be

constant for several input powers. To check this, the characteristic was recorded for three

different input powers: -40 dBm, -30 dBm and -20 dBm. The result of these

measurements can be found in Figure 5.4 together with the gain control voltage VgC'

800 [MHz] 1000200 400 600

Frequency800 [MHz] 1000 0

50

ISO ,-------------------,[mY]

lool;;::;:~~~_

:1 I:: -s:+------------"'~_-- >~ 3 :~:~::====~

~1 . ~I ~IIo 200 400 600

Frequency

I------Pin--40 dBm ---Pin'"'-30 dBm --Pin=-20 dBm I

Figure 5.4: Static transfer characteristic with AGe operational for three input powers.

The figure shows that for frequencies below 465 MHz, the AGC works very well; for

higher frequencies the performance decreases: the amplitude increases and the three

curves diverge more. This can be explained by the frequency dependence of the square

law detector which emerges from Figure 5.3. Vdc Is larger for high frequencies which

results in a higher gain of the VGA.

In a dynamical situation, Vgc can not vary as in Figure 5.4 due to the control loop

bandwidth which is smaller than the modulation frequency. In this situation, the control

loop will come to a state of equilibrium with Vgc stable for the entire frequency interval.

31

CHAPTER 6

Micro Control Board

In Chapter 2 it was stated that the laser frequency can be controlled by controlling the

laser's temperature and current. This means that the frequency control loop must control

two quantities. The design of an analog circuit for this task is fairly complex; a digital

circuit on the other hand is more flexible and easier to implement. A great advantage of

digital control is that the start-up and control algorithm can be combined in the same

program which prevents manual interference during the start-up sequence and the

regaining of frequency lock in case of a disturbance.

6.1 Structure of the Control Board

Digital control of processes is carried out by micro controllers: single chip computers

especially designed for control applications.

6.1.1 Choice of the micro controller

Philips developed a family of low cost 8 bit micro controllers based on Intel's 80C51.

One member of this family is the 80C552; this chip offers next to all the features of the

80C51 an extra set of useful tools. For signal processing, this controller is equipped with

a build in Analog to Digital Converter (ADC) and two build in Digital to Analog

Converters (DACs). For communication with the outside world, an PC-bus has been

integrated; this is a two line bus which offers bidirectional communication.

This micro controller offers the possibilities needed for the control task, and has therefore

been chosen.

6.1.2 Block diagram

The design of the micro control board was based on the data sheets of the processor [16],

application notes of Philips [17] and [5]. The block diagram can be found in Figure 6.1.

32

MICRO CONTROLLER

80C552Analog in A8..AI2 ~========::;:==---~~~;rn--I

PSENf------------"

RAMEPROM

PC BUS

ALE

ADO.. 1/~----oT----'\1 15AD7 j

DATA BUS

Figure 6.1 : Architecture of micro control board.

Due to the build in features of the micro controller, the architecture is quite simple (only

5 integrated circuits including the 80C552).

6.1.3 Memory structure

In order to reduce the number of pins on the processor, the memory structure is based on

bus multiplexing of the data and address bus. Port 0 of the processor is an 8 bit I/O port,

which also serves as a combined data and address port (ADO..AD7). In a read or write

cycle, port 0 first contains the lower order of the address (AO..A7) which is clocked into

a latch; when the address is valid on the output of the latch, port 0 switches over to data

transport so that a read or write operation can be carried out.

The memory consists of two chips: an Erasable Programmable Read Only Memory

(EPROM) which contains the machine code program and a Random Access Memory

(RAM) which can be used for storage of variable data. The address bus consists of 13

bits so that 213 = 8 kB of memory can be addressed. The control signals of the EPROM

and RAM chip are implemented separately, which results in a total memory range of

2*8 kB = 16 kB.

6.1.4 Analog part

The analog part of the circuit consists of the left part of the block diagram of Figure 6.1.

33

The build in DACs use Pulse Width Modulation (PWM) to generate their output signal.

The LP filters are needed to convert these signals to useful dc-levels. The 10 bit ADC

uses successive approximation and must therefore be supplied with a stable reference

voltage (Vrej). The last analog part is a buffer/amplifier to protect the ADC and to adapt

the input signal level to its range.

To reduce A/D errors as much as possible, the digital and analog supplies have been

realized separately and large earth planes have been applied to the PCB. The analog and

digital grounds have been connected in a single point to link them to the same potential.

6.1.5 External communication

The PC bus is a two line serial bus developed by Philips; the processor is connected to it

by two tri state ports: Serial CLock (SCL) and Serial DAta (SDA). This bus can easily be

used for (bidirectional) communication with peripheral equipment.

The complete electrical schedule of the micro control board can be found in Appendix C;

the PCB design can be found in Appendix D.

6.2 Peripheral Equipment

To facilitate the development of the micro program, two special circuits were build: an

EPROM emulator and a 4 digit LED display.

6.2.1 EPROM emulator

EPROMs are Read Only Memory (ROM) chips which can be programmed and also be

erased for re-use. The erasing process can take up to half an hour, which makes design of

(test) software difficult. Small alterations to the program can not be tested rapidly so that

the debugging process becomes time-consuming. A solution can be the use of an EPROM

emulator. This is a special circuit which acts like an EPROM, but uses a RAM chip to

store the data. The data can be erased by simply switching of the (battery) power. The

design in [14] was used to realize such a circuit. The electrical schedule can also be found

in Appendix C.

34

6.2.2 PC LED display

During the debugging process, it is very useful to have a display connected to the

processor. In this way the micro program can display (temporary) results which can then

be checked on correctness. The same display can also be used when the frequency

controller is operative; the program can show the status of the controller, the IF, the

laser temperature, etc..

In [15] the design of such a display is described. This circuit utilizes the previously

mentioned FC bus which makes it a very suitable design. The circuit consists of a single

Integrated Circuit (IC) which drives four 7 segment LED displays and communicates via

an FC port. All segments on the display can be controlled independently so that many

different symbols can be displayed. The electrical schedule can be found in Appendix C.

6.3 Test Software

Before the actual control algorithm could be written, the individual features of the

processor were tested by some programs. All the procedures are described in the data

sheets, but no useful example programs are given. Some example programs are mentioned

in the application notes, but they are specifically written for other members of the 80C51

family.

A specific Pascal cross assembler for the 80C552 has been used to develop all programs.

This cross assembler makes direct manipulation of special function registers possible.

6.3.1 Alive.pas

The very first micro program which was executed was alive.pas. This program was used

to check if the processor could find the program in the EPROM and execute it. The

program is listed in Listing 6.1. The program is very simple: pin 1.7 (pin 7 of port 1) is

switched between the logical levels "0" and" 1" in an infinite loop. While the processor

executed this program, pin 1.7 was monitored by an oscilloscope. After switching the

power on, the level at pin 1.7 started switching between 0 and 5 V with a frequency of

approximately 1/2 Hz. This positive result proved that the micro controller was indeed

'alive' .

35

program alive;

varn:integer;

beginrepeatpl.7:=true;for n:=l to 30000 dopl.7:=false;for n:=l to 30000 do

until false;end.

start infinite loop}pin 7 of port 1 is set to logic "l"}wait some time}pin 7 of port 1 is set to logic "O"}wait some time}

Listing 6.1: Alive.pas.

6.3.2 Dactest.pas

Once it appeared that the micro control board was operative, the Input/Output (I/O) ports

could be tested. The first ports under consideration were the two DACs. There are two

special registers which contain the data byte of both DACs: PWMO and PWMI. The

output level VDAC is determined by the contents of these registers:

V PWMx * 5 V . hOIlJACx = 255 ,WIt x=, . (6.1)

Both DACs were tested by the program dactest.pas (see Listing 6.2). The program

generates two saw-shaped signals with different amplitudes. Again the signals were

monitored by an oscilloscope during execution and indeed two saw-shaped signals with

different amplitudes were detected.

program dactest;

var n:byteim: integer i

beginrepeatfor n:=$OO to $7F do begin

PWMO:=n;PWM1:=2*n;

end; {for n}until false;

end.

!start infinite loop}n takes on values from 0 to 127}DACO=n}DACl becomes twice the value of DACO}

Listing 6.2: Dactest.pas.

6.3.3 Display.pas

The communication with the display is carried out via the PC bus. The PC bus format

36

for the write mode is depicted in Figure 6.2. First the slave address is send, followed by

the instruction byte; this byte indicates which register is addressed first. The next byte is

the control byte which determines the settings of the display (dynamic/static mode, power

consumption, etc.). The data bytes of the displays are the last bytes which are send in a

write cycle. After each byte, an acknowledge bit (A) is returned by the slave (display).

The 80C552 has three special registers for FC operations: SICON, SIDAT and SISTA.

The first register is the control register, the SIDAT is the data register and SISTA is the

status register. The program display.pas (Listing 6.3) was used to test the display; the

comments explain the working of the program. After execution the display shows "0000".

~O 1 1 1 0 Al AO O~O 0 000 SC sa SA~X C6 C5 C4 C3 C2 CI co0slave adress instruction byte control byte

ID17 DlO~ D27 D20~ D37... D30~1 D47 D40~

data digit 1 data digit 2 data digit 3 data digit 4

PC bus fonnat; WRITE mode.

S = start conditionP = stop conditionA = acknowledgeX = don't care

Al,AO = programmable address bitsSC SB SA = subaddress bitsC6 to CO = control bits

Figure 6.2: 12 C bus format for write operations to display.

6.3.4 Adctest.pas

The last test which was carried out was the test of the ADC. The ADC is controlled by a

special register: ADCON. Another register, ADCH, contains the 8 most significant bits

of the sample after conversion. The two least significant bits are stored in the ADCON

register. A conversion is preceded by selecting one of the eight multiplexed input ports.

When the start condition is given, the conversion process begins. The conversion process

is ended when the data valid flag in ADCON is set by hardware. The program adctest.pas

was used to test the ADC. This program can be found in Listing 6.4. The program

samples data at input channel 0 and reflects the value via one of the DACs. The

comments explain the meaning of the instructions.

37

program display;

beginSlCON:=$40;STA: =true;while not (SlSTA=$08) doSlDAT:=$72;STO:=false;SI:=false;while not (SlSTA=$18) doSlDAT:=$OO;STA:=false;STO:=false;SI:=false;while not (SlSTA=$28) do ;SlDAT:=$37;STA:=false;STO:=falseiSI:=false;while not (SlSTA=$28) do iSlDAT:=$ 3F iSTA:=falseiSTO:=falseiSI:=falseiwhile not (SlSTA=$28) do iSlDAT:=$3F;STA: =false i •••••••....•••••••.

STA:=falseiSTO:=true;SI:=falseiend.

initialize as master transmitter}start bus}wait until bus is ready}load slave address and write bit}send slave address and write bit}wait for acknowledge}load instruction byte}send instruction byte}wait for acknowledge}load control byte}send control byte}wait for acknowledge}load information for "O"}send information for display 1}wait for acknowledge}

{repeat this for the}{other 3 displays}

{stop bUs}

Listing 6.3: Display.pas.

program adctest;

vareoc : bytei

beginrepeat

ADCON:=$OO;ADCON:=$08irepeat

eoc:=ADCON AND $10;until eoc=$lO;PWMO:=ADCHi

until falseiend.

!start infinite loop}reset ADC and select channel O}start conversion}

{wait until end of conversion}

{reflect sampled data via DAC}

Listing 6.4: Adctest.pas.

6.3.5 Standard procedures

These test programs have been used to create standard procedures which can be used in

the main program. With just one instruction the display and the ADC can be controlled.

These procedures with comments are listed in Appendix E.

38

CHAPTER 7

Frequency Control System

When all components described in the previous chapters are combined, a complete

frequency control system results. The following block diagram shows the connection of

the different components.

currentcontrol

temperaturecontrol

Figure 7.1: Block diagram frequency control system.

At the time that the frequency controller was ready for testing, the lasers which should be

controlled, were not yet available. This meant that only tests could be carried out by

using a set-up which produces a CPFSK test signal (see Appendix F).

7.1 Control Task

The received optical signal is combined with the LO light via couplers (see Figure 1.1).

The combined signal is detected by photo diodes (PDs) which generate an electrical

current which contains the difference frequency of the two combined optical frequencies

[4]:

(7.1)

If the optical frequencies of both signals are nearly equal, the difference frequency

becomes small enough for electrical processing. The controller's task is to control the LO

laser to a frequency in such a way that the difference (intermediate) frequency W/F

39

(= IWw-WS/G I) is locked at 465 MHz. This can be accomplished in two cases: 1)

Ww > WS1G' and 2) Ww < WS/G' In the first case, an increase of Ww results in an increase of

W/F (aw/Flaww >0), whereas in the second case, an increase of Ww results in a decrease of

W/F (aWI~aWW< 0).

The controller uses the baseband term at the output of the D&M demodulator, Vbb to

detect W1F; Figure 7.2 shows the relation between V bb and W/F' The control loop tries to

lock on the zero crossing at 465 MHz. If Vbb is too high, the controller increases ww; if

Vbb is too low, the controller decreases Ww' This method only works in case 1

(ww > WS1G); in case 2 (ww < wS/G), the controller will not lock on the zero crossing at

465 MHz but on a zero crossing with an opposite aVbiaw/F (1395 MHz). In this case, a

decrease of W/F results in a decrease of V bb ; the controller responds with a decrease of Ww

for it 'thinks' that W/F is too high. Due to this decrease of Ww, W/F increases again and V bb

will converge to 0 V. The control algorithm must prevent that this situation occurs.

Passing zone input filter

\or>~ 0 ~--------\-----------j----;-----

465 MHz 1395 MHz.

o 250 500 750 1000 1250 1500 1750 [MHz] 2000

Intennediate Frequency

Figure 7.2: Transfer characteristic demodulator.

7.2 Control Algorithm

The control algorithm can roughly be split up into two parts: a start up sequence and a

tracking loop. The start up sequence must tune the LO laser to a frequency in such a way

that the CPFSK signal spectrum can be detected within the frequency range of the input

filter. The tracking loop then locks the CPFSK spectrum at an IF of 465 MHz .

40

7.2.1 Start up sequence

The start up sequence is a search algorithm which varies the LO frequency through a

wide range by varying the laser temperature. This process ends as soon as the CPFSK

signal spectrum is detected within locking range of the frequency controller. The locking

range is determined by the frequency range of the demodulator and the input filter which

filters the signal after mixing of the two optical components. This (LP) filter removes

frequency components above 1500 MHz; therefor, the spectrum must be (partially) in the

passing zone of this filter to be detected.

At the starting-point, it must be known whether the local oscillator frequency is higher or

lower than the transmitting laser in the other transceiver (see Paragraph 7.1). The

temperature is increased (or decreased; this depends on the starting point) until the

spectrum enters the passing zone of the input filter. The LP filter allows two zero

crossings of the demodulator in its passing zone (see Figure 7.2). To lock on the correct

zero crossing, the spectrum first has to pass the minimum of the transfer characteristic.

On the moment this minimum is passed, the locking procedure can be started up.

The search speed depends on the speed at which the temperature can be varied. This is

determined by the heat capacity of the laser with its heatsink and the maximum power

transfer of the Peltier element; from these parameters the time constant of the heating and

cooling process follows.

7.2.2 Tracking loop

The tracking loop locks the IF of the CPFSK signal spectrum at the desired 465 MHz.

The algorithm is an improved version of the algorithm used in [2,3]. The IF is detected

by the demodulator which produces a signal which is proportional to the IF. After

filtering of the high frequency by-products, the signal is sampled by the ADC and

compared with the value that corresponds to an IF of 465 MHz. From this comparison,

an error signal is derived; the control voltage is then updated by a value proportional to

the error signal (proportional compensation). The algorithm used in [2,3] does not use the

magnitude of the error signal but only the sign to update the laser's control voltage.

41

The current control is used for fine tuning and has a range of approximately 500 MHz.

The micro controller controls the current by an 8-bit DAC; one step of this DAC

therefore results in a frequency shift of approximately 500 MHz128 levels:::::: 2 MHz. The

temperature control is used for coarse tuning and is adjusted when the current control

threatens to fall out of that range. The temperature is also controlled by an 8-bit DAC;

one step of this DAC should take the current control from the edge of its range back to

its central position. This means that one step of the temperature DAC results in a

frequency shift of approximately 250 MHz. The total tracking range of the controller is

then 250 MHz/level * 256 levels = 64 GHz.

7.3 Implementation in Software

The control algorithm has been translated into a Pascal computer program. The start up

sequence is not part of this program but is only a concept expressed in a flow diagram;

the actual program should be written when the lasers are operative and more is known

about the time constants of the system and the behavior of the lasers.

7.3.1 Start up sequence

The flow diagram of Figure 7.3 is a reflection of Paragraph 7.2.1. The program starts by

setting the temperature to To; at this temperature, the LO frequency is definitely higher

(or lower) than the signal frequency. From this point the temperature is updated until the

Figure 7.3: Flow diagram start up sequence.

Minimum no

Reached1

42

CPFSK signal spectrum is detected. After detection, the current control is enabled so that

fine tuning is possible. Then the minimum of the transfer characteristic is searched by

controlling the current of the the local oscillator. When the minimum is found, the

CPFSK spectrum is within locking range and the locking procedure can be invoked.

7.3.2 Tracking loop

The tracking loop is invoked as soon as the start up sequence is ended. At this point, the

CPFSK signal spectrum is amply within the passing zone of the input filter. The tracking

loop then locks the intermediate frequency at 465 MHz. The procedure track is listed in

Listing 7.1. The IF is first detected (via Vbb) and compared with the constant IF_OK

which contains the value that coincides with an IF of 465 MHz. The variable error

contains the difference between both values and is multiplied by K to generate delta with

which the DAC for controlling the laser current is updated. If the current control

threatens to fall out of range, the temperature DAC is updated (the boundaries at which

the temperature is updated are the same as used in the algorithm in [2,3]). After the

update, the temperature control is disabled for a short period (the delay depends on the

variable xx). This is done to give the temperature controller some time to heat or cool the

laser chip to the desired temperature. During this period the current control is still

operative and will drift back to its central position.

7.4 Measurements

Some measurements have been carried out to test the frequency controller with the control

algorithm.

7.4.1 Measurement set-up

Appendix F describes the CPFSK test signal generator. The Voltage Controlled Oscillator

(VCO) can be controlled by a control voltage between 0 and 30 V. Within this range W/F

can be controlled between 1 GHz (0 V) and 186 MHz (30 V); however, the relation

between the control voltage and W 1F is not linear.

The frequency controller can only generate control signals between 0 and 5 V. A simple

differential amplifier was used to adapt the controller to the VCO. The circuit is depicted

43

procedure track;

vartemp timerenable_temp

integer;boolean;

begintemp timer:=xx;enable temp:=true;repeat start infinite loop}detect (sample) ; detect IF}if sample>IF OK then begin is detected IF too large ?}error:=sample-IF OK; derive error signal}delta:=K*error; - calculate update}if delta«$FF-PWMO) then PWMO:=PWMO+delta else PWMO:=$FF; {update}

end {if} lDAC & check range overflow}else begin detected IF is too lOw}error:=IF OK-sample; derive error signal}delta:=error div 16; calculate update}if delta<PWMO then PWMO:=PWMO-delta else PWMO:=$OO; {update DAC &}

end; {else} {check range overflow}if PWMO<$10 and enable_temp then begin {if current DAC nearly out}

PWM1:=PWM1-$Ol; lOf range and temperature}enable_temp:=false; control is enabled, update}

end; {if} temperature DAC}if PWMO>$FO and enable temp then begin

PWM1:=PWM1+$Olj -enable temp:=falsej

endj {if}if not (enable temp) then begin {update timer}

temp timer:=temp timer-1;if temp timer=O then beginenable=temp:=truejtemp timer:=xxj

endj Tif}end; {if}

until falsejend; {track}

Listing 7.1 : Tracking algorithm.

in Figure 7.4. The circuit has 3 input signals: current control, temperature control and an

input to disturb the control signal. The temperature control has a range of 12k12k * 5 V

= 30 V which covers the complete range of the Yeo. The current control range is

smaller (fine tuning) than the temperature control range and covers 12k/10k * 5 V =

6 V. To test the ability of the controller to compensate for disturbances, a third input was

added to the adapter. Signals at this input are attenuated by 12k/30k = 0.4.

The control range is adapted to the test set-up which range is limited compared to the

range of the DFB lasers which will be used; they do not coincide with the ranges

described in Paragraph 7.2.2.

44

R4

12k

Curr ctrlR1

10k

30V

Tern ctrl

Disturbance

30V

IC1A

L.M324

lovec

100k P1 20k

Figure 7.4: Circuit to adapt the frequency controller to the VCO.

7.4.2 Step response

An interesting test to characterize the controller is the step response. This test also gives

the opportunity to compare several control algorithms.

The step is invoked by a frequency generator which produces a square wave with an

amplitude of 5 V. This signal is coupled to the veo via the disturbance input of the

adapter (see Figure 7.4) and causes the IF to jump from 465 MHz to 515 MHz when the

signal is high and from 465 MHz to 440 MHz when the signal is low.

For three different control algorithms the controller's step response was recorded. The

first algorithm tested was the algorithm used in [2,3]. The second and third algorithm

both used proportional compensation; the second is underdamped (K= 1/16) and the third

is overdamped (K=1/32). Figure 7.5 shows the control signal of the veo (output signal

of the adaption circuit). From this figure it can be concluded that the proportional

compensation produces a faster recovery of the frequency lock than the algorithm used in

[2,3].

The value of K can be optimized as soon as the time constants of the laser circuits are

known. If necessary, an integrating action could be added to create a controller with

Proportional Integral (PI) compensation. However, this will decrease the speed of the

algorithm due to extra machine cycles.

45

-10.000 ns 100.000 IDS 200.000 IDS

------- '-- ----------- 1=-----....

- >.'.- - '.

/ ~

';J•...• ----f--' -... '"'~"'-',-

// VMain

Memory 1Memory 2Memory 3Memory 4

Timebase Delay/Pos Reference20.0 ms/div -10.000 ns Left

sensitivity Offset Probe Coupling5.00 V/div 0.00000 V MemSweep 20.0 ms/div2.48 V/div 12.0000 V MemSweep 20.0 ms/div2.48 V/div 12.0000 V MemSweep 20.0 ms/div2.48 V/div 12.0000 V MemSweep 20.0 ms/div

Figure 7.5: Step response for 3 different control algorithms.

7.4.3 Phase noise introduced by the controller

The controller continuously changes the control voltage of the YeO, resulting in phase

modulation. The delta peak at 311 MHz was detected under two different circumstances:

1) the controller was disabled and a power supply was used to generate the control signal

of the Yeo, and 2) the controller controlled the veo of the test set-up. Figure 7.6 shows

the results of these measurements. It can be seen that the broadening of the delta peak is

approximately 150 kHz which is acceptable compared to the linewidth of the lasers

(::=: 1 MHz).

- -

UK>:!309. 80 ~ Hz-100 oce Bm

I \.. IA" '" ~'L

CENTER 310.000 MHz

-

MKR310 P40 ~Hz

-4!: .27 Bm

r-

~ oj I.. ~

CENTER 310.000 MHz

A blank B view

SPAN 2.000 MHz

ATI 10 dB

RBW10 kHz

VBW10 kHz

SWP5s

REF -20.0 dBm10dB/

A blank B view

SPAN 2.000 MHz

ATI 10dB

RBW10 kHz

VBW10 kHz

SWP5s

REF -20.0 dBm10dB/

Figure 7.6: Broadening of the spectrum due to phase modulation by the controller.

46

CHAPTER 8

Conclusions and Recommendations

First it can be concluded that a working prototype of the frequency controller has been

developed. This prototype functions well in the test set-up. As soon as the lasers are

operative, the controller will be implemented in the complete communication system.

Assuming that the current range amounts to 500 MHz, the tracking range will be

approximately 64 GHz (:::::0.5 nm, at A=1540 nm).

The start up sequence should be implemented in the control algorithm as soon as the

system parameters of the lasers with their control circuits are known.

Measurements concerning the influence of noise will be necessary to determine the

sensitivity to noise.

The controller in combination with a prescaler can serve as a 3 GHz controller. This

controller will control local signals which states of polarization are controlled and

matched. Therefore, one of the two demodulators can be omitted which simplifies the

circuit.

47

References

[1] Vrolijks, E.E.

Een CPFSK demodulator m.b. v. de delay & multiply methode.

Graduation report.

Telecommunications Division, Faculty of Electrical Engineering, Eindhoven

University of Technology.

October 1992.

[2] Smets, R.C.J.

Frequentieregeling voor het middenfrequent van een phase diversity systeem.

Student report.



July 1992.

[3] VandenBoom, H.P.A.

A Frequency locked loop for a phase diversity optical homodyne receiver.

In: Proceedings of the 16th European Conference on Optical Communication,

Amsterdam, 16-20 September 1990.

Vol. 1.

Amersfoort: PTT Telecom (Long Lines and Radio Communication), 1990.

P. 377-380.

[4] VanEtten, W. and J. VanderPlaats

Fundamentals of optical fiber communications.

Hertfortshire: Prentice Hall, 1991.

[5] Kemper, J.P. and M.P.J. Stevens

Microcomputer systeemarchitectuur II

Hoogezand: Stuberg, 5th edition, 1986.

48

[6] Bononi, A. et al.

Analysis of the automatic frequency control in heterodyne optical receivers.

Journal of lightwave technology, vol. Lt-lO (1992), no. 6, p. 794-803.

[7] Kikuchi, K.

Frequency and phase control of light in coherent optical communication systems.

Electronics and communications in Japan, part 2, vol. 74 (1991), no. 9, p.l-lO.

Translation of: Denshi Joho Tsushin Gakkai Ronbunshi (Japan), vol. 73-C-I

(1990), no. 5, p. 199-206.

[8] Hardcastle, I. et al.

A practical high peiformance 140 Mbit/s FSK coherent system.



Vol. 1.


P. 415-418.

[9] Tsushima, H. et al.

A novel delay-line demodulation method for AMI-CPFSK heterodyne transmission

systems.



Vol. 1.


P. 343-346.

[10] Kikuchi, K. et al.

Design theory of electrically frequency-controlled narrow-linewidth semiconductor

lasers for coherent optical communication systems.

Journal of lightwave technology vol. Lt-5 (1987), no. 9, p. 1273-1276.

49

[11] Lowney, S.D. et al.

Frequency acquisition and tracking for optical heterodyne communication systems.

Journal of lightwave technology vol. Lt-5 (1987), no. 4, p. 538-550.

[12] Tsushima, H. et al.

1.244-Gb/s 32-channel transmission using a shelf-mounted continuous-phase FSK

optical heterodyne system.

Journal of lightwave technology vol. Lt-lO (1992), no. 7, p. 947-956.

[13] McKay, R.G.

Probability of error for narrow deviation coherent optical CPFSK-DD with noise

correlation and laser phase noise.

IEEE Photonics technology letters, vol. 4 (1992), no. 11, p. 1310-1312.

[14] Anon.

2764 EPROM emulator.

Elektuur, 1991, no. 7/8, p. 149-151.

[15] Anon.

PC led display.

Elektuur, 1992, no. 4, p. 76-79.

[16] Anon.

80C51-based microcontrollers.

Eindhoven, The Netherlands, Philips Semiconductors, 1993.

[17] Anon.

Application notes for 80C51-based 8-bit microcontrollers.

Eindhoven, The Netherlands, Philips Semiconductors, 1993.

50

[18] Kuipers, L.L.J.

Een frequentiedeier voor een bit error rate tester en een computerprogramma voor

dataconversie van pseudo random binary sequences.

Student report.



June 1993.

51

Appendix A: Matlab Programs and Functions

% denm.m%% delay and multiply simulation%echo offclear;fO=310E+06;f1=620E+06;ts=0:3.225E-11:3.225E-09;t=0:3.225E-11:6.45E-07;as=length(ts)-l;phi=O;for symbol=0:99

if rand>=0.5,wa=2*pi*fO;wb=2*pi*f1;

elsewa=2*pi*f1;wb=2*pi*fO;

% "O"-frequency% "l"-frequency% local time vector

% initialize phase

% choose randomly "01" or "10"

end% generate first part of symbol

vector=(1:length(ts))+2*symbol*as;signal (vector)=sin(phi+wa.*ts) ;phi=phi+wa*ts(as+1) ;

% generate second part of symbolvector=(1:length(ts))+(2*symbol+1)*as;signal (vector) =sin(phi+wb. *ts) ;phi=phi+wb*ts(as+1) ;

endf=(1/3.225E-ll) .*(0:16383)/16384;spec1=fft(signal,16384) ;SIGNAL2=spectrum(signal,16384) ;SIGNAL2=SIGNAL2/max(SIGNAL2) ;SIGNAL=spec1.*conj (spec1);SIGNAL=SIGNAL/max(SIGNAL) ;plot(f(1:600) ,SIGNAL(1:600) ,f(1:600) ,SIGNAL2(1:600));pause;% generate delayed signaltau=50;delayed=zeros(signal) i

delayed(l+tau:length(delayed))=signal(l: (length(signal)-tau));% generate multiplied signalmultiply=signal.*delayedispec2=fft(multiply) ;MULTIPLY=spec2.*conj (spec2);plot(f(1:1000) ,MULTIPLY(1:1000));plot(t(1:2000) ,signal(1:2000) ,t(1:2000) ,delayed(1:2000) ,t(1:2000) ,multiply(1:2000));j =sqrt (-1) ;% divide 4th order lowpass filter into two 2nd order filters% and filter the multiplied signal%% first filter:num1=1;p1=2*pi*(-0.816327544850+j*0.569381397319) ;p2=2*pi*(-0.816327544850-j*0.569381397319) ;polen1=2E+08*[p1 p2];den1=poly(polen1) ;den1=den1./den1(length(den1)) ;%% calculate output signal first filteroutput1=lsim(num1,den1,multiply,t) ;

52

%% second filter:% zeros:n1=2*pi*j*1.616068841673in2=- n1 inullen2=2E+08*[n1 n2] inum2=poly(nullen2) inum2=num2./num2(length(num2)) i%% poles:p3=2*pi*(-0.198700703604+j*1.114985370506) ip4=2*pi*(-0.198700703604-j*1.114985370506) ipolen2=2E+08*[p3 p4] iden2=poly(polen2) iden2=den2./den2(length(den2)) ioutput2=lsim(num2,den2,output1,t) ;plot(t(1:2000) ,signal(1:2000) ,t(1:2000) ,delayed(1:2000) ,t(1:2000) ,multiply(1:2000) ,t(1:2000) ,output2(1:2000));spec3=fft(output2) ;OUTPUT=spec3.*conj (spec3);plot(f(1:1000) ,OUTPUT(1:1000));end;

53

%- deltaf.m

%- simulate the influence of a frequency shift

echo offclear;df=-300E+06:10E+06:300E+06for q=l:length(df}

disp(q} ;fO=310E+06+df(q} ;f1=620E+06+df(q} ;ts=0:3.225E-11:3.225E-09;t=0:3.225E-11:6.45E-07;as=length(ts}-l;phi=O;for symbol=0:99

if rand>=0.5,wa=2*pi*fO;wb=2*pi*f1;

elsewa=2*pi*f1;wb=2*pi*fO;

%- "O"-frequency%- "l"-frequency%- local time vector

%- initialize phase

%- choose randomly "01" or "10"

end%- generate first part of symbol

vector=(1:length(ts}}+2*symbol*as;signal (vector}=sin(phi+wa.*ts) ;phi=phi+wa*ts(as+1} ;

%- generate second part of symbolvector=(1:length(ts}}+(2*symbol+1}*as;signal (vector}=sin(phi+wb.*ts) ;phi=phi+wb*ts(as+1} ;

end%- implement IF filter:

% generate delayed signaltau=17;delayed=zeros(signal} ;delayed(l+tau:length(delayed}}=signal(l: (length(signal}-tau});

%- generate multiplied signalmultiply=signal.*delayed;

plot(t(1:2000} ,signal(1:2000} ,t(1:2000} ,delayed(1:2000} ,t(1:2000},multiply(1:2000}} ;j=sqrt(-l} ;%- divide 4th order lowpass filter into two 2nd order filters% and filter the multiplied signal

%- first filter:num4=1;p4=2*pi*(-0.816327544850+j*0.569381397319} ;p5=2*pi*(-0.816327544850-j*0.569381397319} ;polen4=2E+08*[p4 p5];den4=poly(polen4} ;den4=den4.jden4(length(den4}} ;%-%- calculate output signal first filteroutput4=lsim(num4,den4,multiply,t} ;%% second filter:%- zeros:n4=2*pi*j*1.616068841673;n5=-n4;nullen5=2E+08*[n4 n5];num5=poly(nullen5} ;num5=num5.jnum5(length(num5}} ;%-

54

% poles:p6=2*pi*(-O.198700703604+j*1.114985370506) ;p7=2*pi*(-O.198700703604-j*1.114985370506) ;polen5=2E+08*[p6 p7];den5=poly(polen5) ;den5=den5./den5(length(den5)) ;output5=lsim(num5,den5,output4,t) ;dclevel(q)=sum(output5)/length(output5) ;plot(t(1:2000) ,signal(1:2000) ,t(1:2000) ,delayed(1:2000) ,t(1:2000),multiply(1:2000) ,t(1:2000) ,output5(1:2000));

endplot (df,dclevel) ;

55

Appendix B: Data Sheets

IVA-05118

Silicon Bipolar MMIC1.5 GHz Variable Gain Amplifier

The following pages contain the data sheets of the most important active components used

in the analog circuits.

0AVANTEK

Features Avantek 180 mil Package

'.0

0.006.127

-.LT

7

Noles:(unless otherwise specified)

1. Dimensions ere ~r;.,2. Tol.ranees

in .xxx = :!:.005mm .xx =:!:.13

0.5 1.0 2..0

RF Fr_. Gliz

Vee ACGROUND

0.2

TYPICAL VARIABLE GAIN ... FREQUENCYT",=25"'C,Ycc=5V,V.. :zOV

.......... Vge c2.5V

""3.7 V

" '.OV

"'- S.OV

20

30

-20

-300.'

-'0

-+ -+0.030-:76

0.40010.16

~:'';'~0.18050 -..

t· 4.5750

0.058 r=1.47 =.

i 10

8- 0

Ii: 2 D~r T- 4 .: ~~~5

~---o.:===~~T

FJIN DESCRIPTION

, IF OulpUl 18 RF 0"",," (opl"'oaQ2 V., AC Ground 7 Vee

3 V", AC Ground 6 LO Ground (optional)4 RF Input 5 LO Input

BouOf't 01 FJackaoe 15 V " (AC Ground}

Electrical Specifications', TA =25°C

Description

Avantek's IVA-05118 is a variable gain amplifier housed in aminiature glass·metal hermetic surface mount package. It is de·signed for narrow or wide bandwidth commercial. industrial andmilitary applications that require high gain and wide gain controlrange. The amplifier can be used in a single·ended or differentialoutput configuration. For low frequency applications «50 MHz)a bypass capacitor and series resistor are connected to pin 4,the AC Input Ground lead.

Typical applications include variable gain amplification for fiberoptic systems at data rates in excess of the 1.24 Gb/s SONETstandard, mobile radio and satellite receivers, millimeter wavereceiver IF ampl~iers and communications receivers.

The IVA series of variable gain amplifiers is fabricated usingAvantek's 10 GHz h. 25 GHz fM"" ISOSAfTM·1 silicon bipolarprocess. This process uses nitride se~·alignment. submicrometer lithography, trench isolation, ion implantation, goldmetallization and polyimide inter-metal dielectric and scratchprotection to achieve excellent performance, uniformity and reliability.

D~ferential input option is available. Contact factory for furtherdetails.

• 50 MHz to 1.5 GHz Bandwidth

• Data Rates up to 2.0 Gbltls

• High Gain: 26 dB typical

• Wide Gain Control Range: 30 dB typical

• Differential Output Capability

• Bias Vee·V•• =5 V

• 5 V TTL Compatible Vge Control Voltage, Ige < 3 rnA

• Hermetic Glass-Metal Surface Mount Package

Symbol Parameters and Test Conditions" Vee =5 V, Vee =0 V, Vge =0 V, Zo =50 Q Units Min. Typ. Max.

Gp Power Gain /5211' f = 0.5 GHz dB 20 26t.Gp Gain Flatness 1= 0.05 to 1.0 GHz dB ±<l.3

13dB 3 dB Bandwidth' GHz 1.0 1.5

GCR Gain Control Range f = 0.5 GHz, Vge = ato 5 V dB 25 30

ISO Reverse Isolation (lS,2I') 1= 0.5 GHz, Vge = 0 \0 5 V dB 45

InputVSWR f = 0.05 to \.5 GHz, Vge = 0 to 5 V 1.7:1VSWR

Output VSWR f = 0.05 to 1.5 GHz, Vge = a to 5 V 1.5:1

NF 50 Q Noise Figure 1= 0.5 GHz dB 9

P, dB Output Power @ 1 dB Compression ,= 0.5 GHz dBrn -2

IP3 Output Third Order Intercept Point 1= 0.5 GHz dBrn B

to Group Delay 1= 0.5 GHz psec 400

Icc Supply Current rnA 25 35 45

NOles. 1. The recommended operatmg """tage range for thiS deVice IS 4 to 6 V. TYPical porlon11ance as a funenon of voltage IS on lhe lollowlng page.2. As measured using Input Pin 1 and Output Pin 6: wilh Output Pin 7terminated into 50 ohms,3. Referenced Irom 50 MHz Gain.

Avantek. Inc. .. 3175 Bowera Ave.• San\a Clara. CA 95054 • Phone (408) 727·0100 • FAX: (408) 727-0539 • TWX: 310-371-8717 or 310-371·8478 • TELEX:34-6337 564-20

IVA-05118 Silicon Bipolar MMIC1.5 GHz Variable Gain Amplifier

Absolute Maximum Ratings

ParameterAbsoluteMaximum'

Device Voltage avPower Dissipation2,' 600mWInput Power +14dBmvgc-vee 7VJunction Temperature 200°CStorage Temperature ~5°C to 200°C

I Thermal Reslstance2,': 9jc = 50°CIW

Notes:1, Permanent damage may occur if any of these limits are exceeded,2, TCASE = 25°C

3, Derate at 20 mW;oC forTc >170°C,4, See MEASUREMENTS section ·Thermal Resistance" for more

information,

Typical Blasing Conflgura,tlonand Functional Block Diagram

.------t-o vgo

L-1nvertingr--I-O"""'""i r.:-:':' Output

Cblock

1-+-0--1~ Outpu,

Typical Performance, TA = 25°C,Vee =5 V, V•• =0 V(unless otherwise noted)

POWER GAIN and P, dB at 0,5 GHzand lee VI. BIAS VOLTAGE with Vgc =0 V

I--Pld~

~ ~

/'?'-GP ./

Icc --.

I

30

25+'25+25 +35

TemperalW'e. '"C

I_Gp- Ic~ ...... -I--..-- --1-0.....-- ~PldB

POWER GAIN and P, dB at 0,5 GHzand Icc ..... CASE TEMPERATURE with Vgc :a 0 V

, 45

->l-55 -25

E 0III

"at -1

"rr -224

30

28III

"~ 26

"

40

35~

30 S

45

25

2075

Vee' V

-'03

28

30

!II 26

8- 24

22

20

-Gp \.\ ,.,'"

~ ..!' dB......., """"-

.- --r-'QO- '-

Gp. 15-25 dB

1 IGp=5dB

I IGp:-6dB

4,00,2 0,5 1,0 2.0Frequency, GHz

NOISE RGURE Ya, FREQUENCY

I IGp:a 10dB -

I IGP=ti -

Gp=25dB5

0.'

,0

20

25

III

~ 15z

4,0

P1 dB ... FREQUENCY

0.2 0.5 '.0 2.0Frequency. GHz

-25D.,

.l! -6'U -10

~ -15rr

-20

2 g,3~

o5.1

POWER GAIN and Pl dB at 0.5 GHzand Igo'" GAIN CONTROl. VOLTAGE

-20o

30

20.Ii

~ 'U 10

8- ~ 0rr -'0

INPUT and OUTPUT VSWR ya, FREQUENCYVgc·O-SV

4,00.2 0,5 1.0 2.0Frequency, GHz

I I IGp=-5dB Gp :25dB.

t, .JI

GP=5r~ 'I\r"!i

""3000.1

GROUP DELAY Y" FREOUENCY

500

~400Q

4.110.5 '.0 2.0Frequency, GHz

0.2

INPUT

.'- I '\OUTr

"'10.1

~ 1,5

A....nlilk. Inc. • 3175 Bower. Ave.• Santa Oara. Ca 95054 • Phone (408) n7.(J700 • FAX: (408) n7.(J539 • 1WX: 310-371-8717 or 310-371·8478 • TELEX: 34-6337

4-21

57

OAVANTEK IAM-81018Silicon Bipolar MMIC 5 GHzActive Do~ble Balanced Mixer/IF Amp

'05.0

8

0.006-:127

=....LT

Nol••:(unless olherwl.8 spech

1. Dimensions arl ~~2. Tolerance.

In .XXX::I t.OOSmm.xx ct.13

0.5 1,0 2.0

RF F......ncy. GHz

V.. ACGROUND

0.2

Avantek 180 mil Package

..0.030:;&

TYPICAL RF '" IF CONVERSION GAIN va. RF FREQUENCYT. - 25"C (Low SIde LO)-

I IIF.7DMHz I""l

IF~ 1 GHZ-.........~

'0

o

-50.'

..P~N DESCRIPTION

1 IF~ : 18 RF G',,"n. toptoonoQ2 VH • ACGrcund 7 Voc.

3 V... Ae Ground 6 LO Ground (optional)4 AF Input 5 LO Input

aOUom of PaCkage. V ee (AC Ground)


Features

• 8 dB RF-IF Converslon.Galn From 0.05·5 GHz• IF Output From DC to 1 GHz• Low Power Dissipation: 60 mW at Vee =5 V typo• Single Polarity Bias Supply: Vee =4 to 8 V• Load·lnsensltlve Performance• Conversion Gain Flat Over Temperature

Low LO Power Requirements: ·5 dBm typical• Low RF to IF Feedthrough, Low LO Leakage• Hermetic Glass-Metal Surface Mount Package

DescriptionAvantek's lAM-a101 a is a complete low-power-consumptiondouble-balanced active mixer housed in a miniature glassmetal hermetic surface mount package. It is designed lornarrow or wide bandwidth commercial, industrial and militaryapplications having RF inputs up to 5 GHz and IF outputsfrom DC to 1 GHz. Operation at RF and LO frequencies lessthan 50 MHz can be achieved using optional external capacitors to ground. The IAM-a1 01 a is particularly well suitedfor applications that require load-insensitive conversion gainand good spurious signal suppression with minimum LO andbias power consumption. Typical applications include frequency down conversion. modulation, demodulation andphase detection for fiber-optic, GPS satellite navigation, mobile radio, and battery powered communications receivers.

The lAM series of Gilbert mu~iplier-based frequency converters is fabricated using Avantek's 10 GHz h. 25 GHz flAAJ(ISOSA-pM_I silicon bipolar process.This process uses nitridesell-alignment, submicrometer lithography. trench isolation.ion implantation. gold metallization and polyimide intermetal dielectric and scratch protection to achieve excellentperformance. uniformity and reliability.

Symbol Parameters and Test Conditions: Vee =5 V, Zo =50 Q, LO =-5 dBm, RF =·20 dBm Units Min. Typ. Max.

Gc Conversion Gain RF : 2 GHz. LO: 1.75 GHz dB 7.0 8.5 10

13d8RF RF Bandwidth (GC 3 dB Down) IF: 250 MHz GHz 4.5

13dBIF IF Bandwidth (GC 3 dB Down) LO: 2 GHz GHz 0.6

P, dB IF Output Power at 1 dB Gain Compression RF : 2 GHz, LO : 1.75 GHz dBm ~

IP3 IF Output Third Order Intercept Point RF : 2 GHz, LO: 1.75 GHz dBm 3

NF SSB Noise Figure RF = 2 GHz, LO: 1.75 GHz dB 15

RF PortVSWR I : 0.05 to 5 GHz 1.5:1

VSWR LOPortVSWR 1= 0.05 to 5 GHz 1.5:1

IFPortVSWR 1< 1 GHz 1.5:1

RFil RF Feedthrough at IF Port RF = 2 GHz, LO: 1.75 GHz dBc -25

LOil LO Leakage at IF Port LO: 1.75 GHz dBm -25

LOri LO Leakage at RF Port LO: 1.75 GHz dBm -35

Icc Supply Current rnA 10 12.5 16

Note: 1. The recommended ope,afing voltage range lor thiS deVice " 4 to 8 V. Typical performance as a luncfion 01 vol1llge " on the folloWing page.

Avan,"- Inc. • 3175 Bowefl AYe.. Santa Clara. CA 95054 • Phone (408) 727·CT700 • FAX: (408) 727-0539 • TWX: 310-371-8717 or 310-371·8478 • TELEX: :M-6337

4~

58

IAM-81018 Silicon Bipolar MMIC 5 GHzActive Double Balanced Mixer/IF Amp


ParometerAbooluteMaximum'

Dovice Voltago 10VPower Dissipation'.' 300mWRF Input Power +14 dBmLO Input Power +14 dBmJunction TemperabJre 200·CStorage TemperabJre -<55·C 10 200·C

I Thermal Resistance"'; ejc = SO·CIW

Notes:1. Permanent damago may occur if any of these limits are exceeded.

2. TCASE =25·C3. Derate at 20 mWI"C for Tc >185·C

4. See MEASUREMENTS section "Thermal Resistance" for moreinformation.

Typical Biasing Configurationand Functional Block Diagram

C blodr. C "'odt Optlonll

IFOu1pu' o-j r-------1-1 r-o----111~. 17II~ r----o Vce =5V

Voe=OV~ H~II~ 1""""1 11~ I I ~OptiontllRF Input~ , La Input

C~Odr.L_--r---!Jc.,.oclc.

Vee =o~_ rv

Nole: No elternll BALUNe are requited.

Typical Performance, TA =25°C, Vee =5 VRF: -20 dBm at 2 GHz, LO: ·5 dBm at 1.75 GHz(unless otherwise noted)

CONVERSiON GAIN, IF P, dO oncl Icc CURRENTva. Vee BIAS VOLTAGE •

+125+25 +85Temperatwe. ·C

15t--Gc Icc--"- .-- .- -I-:- -

r-- _ '0

I- ]--P'dO5-10

-55 -:l5

CONVERSION GAIN. IF P, dO oncl Icc CURRENTva. CASE lEMP£RAnJRE

"

1 .. 10..Ii u

"0

20

30

10

o45878910

Vee. V

ICC~L.

l- Gc

~ e:: V

~

/V 1/ 1" P;dO

-'0 o

E!ll 0

cia...rL-a!!,

".. '0..u"

-10 -5

1.O Power, dBrn

"'"V

RF to IF CONVERSION GAIN v.. La POWER

o-15

10

101.0

Frequency, GKz:

RF, La oncl IF PORT VSWR v.. FREQUENCY

0.1

RF--La--

I IF ----1

-' .., I\..1:

4:1

0: 3,

~>

2:

RF to IF CONVERSION GAIN ... IF FREQUENCY

ItGHSlCE Lao LOWSIOELO

-2 .'=0""1....L............."'"'~0!-:.1:-........L.JL.LL

IF F.-q..-cy (RF-LO), GHz

10

.. 8\=:::tU~~..U 4 I--t-+-HI+I~~-l-±'~

"

RF FEEOTHROUGH RELATlVE to IF CARRIER,dBm LO \0 RF and IF LEAKAGE ,e. FREQUENCY

RFtolF -LO to IF --LOtoRF--

;:::...",

~~r,1.0

F<oquency, GHz10

.~ ,g 2~

l~ ,4

HARMONIC INTERIIODULAnON SUPPRESSION(dO OELOW DESIRED OUTPUll

- RF o' I GHz, LO 010.752 GHz, IF o' 0 248 GHz

- 21 15 .75 .75 .70

12 0 48 48 .75 .75

13 41 39 71 .75 .75

38 :ra 53 57 .75 .7'

27 49 49 72 .75 .7'

45 15 63 82 .75 .75

2 3H.rmonic: RF OrderXmn z PI'.p(m.....-n'o)

AYurtek, Inc. • 3175 Bowers AW., Santa Clara, Ca 95054 • Phone (~) 727-0700 • FAX: (408) 727-0539 • TWX: 310.371-871701" 310-371--8478 • TELEX: 34·m7

4-7

_5_9'--- _

0AVANTEK IAM·81 008MaglCTM Silicon Bipolar MMIC 5 GHzActive Double Balanced Mixer/lF AmpJuly, 1990

Typical RF to IF Conversion Gain vs.RF Frequency TA = 25°C (Low Side LO)

10 .---.,.........~T"T"TT"TTT-...,.__,...,......"T'TTI

Notes:(unless otherwise specl1)ed)

1. Dimensions are J!L2. Tolerances mm

In .xxx =±.005mm .xx =±.13

IF =70 MHz

.069/.053

1.75/1.35 11- .2051.181 -I5.2014.60.030/.025

.009/.004 .771.64 l L-'--;--r--__,

~fQ;fl;J~ }Lf.; I L I l;; ~

050 I .0101.0071.27 TYP -I .25/.18

_ I..- .018/.014.48/.35

Avantek SO-8 Package

*- .197/.188 --1I 5.0014.78 .

PIN~CJ---------'-tr.158/.150 .2441.228

~.80 6.201f80

PIN1~

l'CD 51--+-++I-tI-Ht--+-+--PIl'-H'ttl.., !E.:.1GHz.:; ...

Cl 0 I--t-+--H-tt-ttt---+---l-'-f+t+ttt1\

PIN DESCRIPTION

1 IF Output 18 AF Ground (optional)2 Vte. AC Ground 7 Vee3 Vee. AC Ground 6 LO Ground (optional)4 RF Input 5 LO Input

• RF·IF Conversion Gain From 0.05 - 5 GHz• IF Conversion Gain From DC to 1 GHz• Low Power Dissipation: 65 mW at Vee =5 V typo• Single Polarity Bias Supply: Vee =4 to 8 V• Load-insensitive Performance• Conversion Gain Flat Over Temperature• Low LO Power Requirements: ·5 dBm typical• Low Cost Plastic Surface Mount Package

Features

Description

Avantek's IAM-81008 is a complete low power-consumptiondouble-balanced active mixer housed in a miniature low costplastic surface mount package. It is designed for narrow orwide bandwidth commercial and industrial applications havingRF inputs up to 5 GHz. Operation at RF and LO frequenciesless than 50 MHz can be achieved using optional externalcapacitors to ground. The IAM-81 008 is particularly well suitedfor applications that require load-insensitive conversion andgood spurious signal suppression with minimum LO and biaspower consumption. Typical applications include frequencydown conversion, modulation, demodulation and phase detection. Markets include fiber-optics, GPS satellite navigation,mobile radio, and battery powered communications receivers.

The lAM series of Gilbert multiplier-based frequency converters is fabricated using Avantek's 10 GHz fT. 25 GHz fMAxISOSATTM-I silicon bipolar process.This process uses nitrideself-alignment, submicrometer lithography, trench isolation,ion implantation, gold metallization and polyimide inter-metaldielectric and scratch protection to achieve excellent performance, uniformity and reliability.

Electrical Specifications1, TA =25°C

-5 L-_L-~LLLL-'-'-'--_",,---'--.J....1...L.LllJ

0.1 0.2 0.5 1.0 2.0 5.0 10RF Frequency, GHz

Symbol Parameters and Test Conditions: Vcc = 5 V, Zo = 50 n, La" -5 dBm, RF = -20 dBm

Gc Conversion Gain RF = 2 GHz, LO : 1.75 GHz

la dBRF RF Bandwidth (Gc 3 dB Down) IF = 250 MHz

fa dBIF IF Bandwidth (Gc 3 dB Down) LO = 2 GHz

P'dB IF Output Power all dB Gain Compression RF = 2 GHz, LO = 1.75 GHz

IPa IF Output Third Order Intercept Poinl RF = 2 GHz, LO = 1.75 GHz

NF SSB Noise Figure RF = 2 GHz, LO = 1.75 GHz

Units Min.

dB 6.0

GHz

GHz

dBm

dBm

dB

Typ. Max.

8.5 10

3.5

0.6

-6

3

17

RF Port VSWR 1= 0.05 to 3.5 GHz 1.5:1VSWR LO Port VSWR 1= 0.05 to 3.5 GHz 2.0:1

IF Port VSWR 1< 1 GHz 1.5:1

RFif RF Feedthrough at IF Port RF = 2 GHz, LO = 1.75 GHz dBc -25

LO Leakage aliF Port LO = 1.75 GHz dBm -25

LO~ LO Leakage al RF Port LO = 1.75 GHz dBm -30

ICC Supply Current rnA 10 13 16NOTES 1. The recommended operating VOltage range for this deVIce is 410 eV. Typical performance 8S a 'unction 01 vonage is on the following page.

104

60

IAM-81 008, Silicon Bipolar MMIC 5 GHzActive Double Balanced Mixer/IF Amp


Parameter Absolute Maximum'

Device Voltage 10VPower Dissipation2. 3 300mWRF Input Power +14 dBmLO Input Power +14 dBmJunction Temperatu re 150°CStorage Temperature -6510 150°C

Thermal Reslstance2 : Sjc: 225'CIW

Notes:1. Permanent damage may occur it any of these limits are exceeded.2. TCASE: 25°C.3. Derate at 4.4 mWrC for Te > 82°C.

Typical Biasing Configurationand Functional Block Diagram

Optional LowFrequencies

Cbloek

1* ., Cbloell

RF Ground

IFOUIPUI~ 1 ?1~11III 26 ~Vee:5V

V.. :OV I T-III 3{> ¥-I~II

----J 4' 15 ~OPlional LowRF Input~ LO Ground

CbIoek I----r --- Cblock

Vee=O~'"'"' LO Inpul

Note: No external baluns are required.

Typical Performance, TA :: 25°C, Vee:: 5 V,RF: -20 dBm at 2 GHz, LO: -5 dBm at 1.75 GHz(Unless otherwise noted)

Part Number Ordering Information

Part Number Devices Per Reel Reel Size

IAM-81 008-TR 1 1000 7"IAM-81008-TR2 4000 13"

20

15 '"E

"10 _u

+85+25

Temperature. °C

Conversion Gain, IF P1 dB and IccCurrent vs. Case Temperature

'tc

> <:..:.:.. _Icc

io""""'" -- -P11111

-10-55 -25

E....15

.. 10.."o 5

20 '"E

"o -"

Icc - I:;.-

Gee- 7 '";;..- ......

",II

V1

I ....- p, ..

Conversion Gain, IF P1 dB and Icc CurrentY5. Vee Bias voltage

5 ~

-10 0 1 2 3 4 5 6 7 6 9 10°

Vcc.V

E....15

o 5

.. 10..

r:- lO=2GHz

"-High Skte LO \.Lo,: sld8,L?III iI - I

RF to IF Conversion Gain YS.IF Frequency

1:1.1

10

-2.01 0.1 1.0 2.0

4:1

II: 3:13C

'"> 2:1

RF. LO and IF PortVSWR Y5. Frequency

RF-LOIF --

--- ~

1.0 10

RF to IF ConversionGain VS. LO Power

10,----,,---,---,----,

....,j 41---1---+---+----1

o-~15:----;'=-0----5':---':--~

IF Frequency (RF-LO), GHz Frequency, GHz LO Power, dBm

RF 10 IF --LQ 10 IF --LOtoRF--

Yl.--

--

RF FeedThrough Relative to IF Carrier,dBm LO 10 RF and IF Leakage Y5. Frequency

E 0..~~ -10..-~~i -20s ...t:~ -30

o-'-.01 2.0 0.3 0.40.5 1.0 2.0 3.04.05.0 10

Frequency, GHz

Harmonic Intermodulation Suppression(dB Below Desired Oulpul)

RF al1 GH2, LO al 0.752 GHz, IF al 0.248 GHz

- 21 35 74 >75 >75

18 0 45 48 >75 >75

16 35 42 72 >75 >75

42 20 44 59 >75 >75

29 44 52 64 >75 >75

45 36 57 64 >75 >75

Harmonic RF OrderXmn = PIf-P(m"rfoon"lo)

105

61

QAVANTEK MSA-0385MODAMpTM Cascadable Silicon BipolarMonolithic Microwave IntegratedCircuit Amplifiers

Avantek 85 Plastic Package

-j ~ .~~OGROUND 4

3

RFOUTPUTAND BIAS

NOlos:(unless otherwise specified)

1. Dimensions .re~

GRO~UND. 2~2' i:'~in~: .005mm .xx = ± .13

.0852.15

RF INPUT

.060 ±.010

1.52 ±-:8" ~ .00S±.002

J-.L-I---~=====:::J·J.·05n 1_._ .500±.030 jt

.020 iTI ±:76."T1"

DescriptionAvantek's MSA-0385 is a high performance silicon bipolarMonolithic Microwave Integrated Circuit (MMIC) housed in alow cost plastic package. This MODAMPTM MMIC is designed for use as a general purpose 50 n gain block. Typical applications include narrow and broad band IF and RFamplifiers in commercial and industrial applications.

The MODAMP MSA-series is fabricated using a 10 GHz fr,25 GHz fM.,. silicon bipolar MMIC process which utilizes nitride se~·alignment. ion implantation and gold metallizationto achieve excellent unfformity. performance. and reliability.The use of an external bias resistor for temperature and current stability also allows bias flexibility.

Features

o Cascadable 50 n Gain Blocko 3 dB Bandwidth: DC to 2.5 GHzo 12.0 dB typical Gain at 1.0 GHzo 10.0 dBm typical PI dB at 1.0 GHzo Unconditionally Stable (k>1)o Low Cost Plastic Package

TYPICAL POWER GAIN YO. FREQUENCY

Tit =2S-C,ld1l.35 mATypical Biasing Configuration

....................

1\

G.ln AI' to D.C.

ftoquonc:y,Gftz

'4

'2

'0

CD...Ii.

" I

0.1 0.3 0.5 1.0. 3.0

Rbi••.-"#.,....--0 Vee> 7 V

IN


Symbol Parameters and Test Conditions: Id =35 mA, 20 =50 n Units Min. Typ. Max.

Gp Power Gain (152,1') f = 0.1 GHz dB 12.5f = 1.0 GHz 10.0 12.0

~Gp Gain Flatness 1= 0.1 to 1.6 GHz dB ±O.7

f3dB 3 dB Bandwidth GHz 2.5

VSWRInputVSWR 1= 0.1 to 3.0 GHz 1.5:1

OutputVSWR f = 0.1 to 3.0 GHz 1.7:1

P, dB Output Power @ 1 dB Gain Compression f = 1.0 GHz dBm 10.0

NF 50 n Noise Figure f = 1.0 GHz dB 6.0

IP3 Third Order Intercept Point f = 1.0 GHz dBm 23.0

II) Group Delay f = 1.0 GHz psee. 125

Vd Device Voltage V 4.0 5.0 6.0

dV/dT Device Voltape Temperature Coefficient mVI"C -8.0Note: 1. The recommended operating QJrrent range lor thIS deVIce 1$ 20 mA to 50 mA. TYpical performance as a function 0' current IS on the follOWing page.

AvantBk. Inc. • 3175 Bowe., Ave.. Santa Clara, CA 95054 • Phone (408) 727·0700 • FAX; (408) 727-0539 •• TWX: 310.371-8717 or 310-371-8478 • TELEX: 34·6337

4---56

62

MSA-0385 MODAMpTM Cascadable Silicon Bipolar

Monolithic Microwave Integrated Circuit Amplifiers

oo

DEVICE CURRENT YL VOLTAGE

Typical Performance, TA = 25°C(unless othelWise noted)


Parameter AbsoluteMaxlmum'

Device Current 70mAPower Dissipation:!.' 400mWRF Input Power +20dBmJunction Temperature 150"CStorage Temperature --<i5"C to 150"C

I Thermal ReSistance'·': 9jc = 105"CIW

Notes:1. Permanent damage may occur if any of these limits are exceeded.

2. TCASE = 25"C

3. Derate at 9.5 mWrC for Tc > 108"C.4. See MEASUREMENTS section -Thermal Resistance" for more

information.

80

50

40

~ 30

20

10

I I I / I_ Tc·.a5"C- --Tc a +25"'C_ I :/ I_ Tc=-25"'C---

I iI / !

I!-J Ij-

POWER GAIN VL CURRENT

OUTPlJT POWER @ 1 dB GAIN COMPRESSIONNOISE FIGURE AND POWER GAlN YL CASE TiOMPERATURE

f= 1.0 GHz, Id =35 mA

-=~..:..=0.1 GHz0.5 GHz

~~,.... 1.0GHz

-- z.oGHz

~-:

Gp

P, dB-- I

NF-

-~-

14

12

!g 10

Ii.

"

410 20 30 40 50

.. 13..,~ 12

" 11

.. 7..,

.: .z

-25 .25 .55

•OUTPlJT POWER@ 1dB GAIN COMPRESSION

YL FREQUENCY NOISE RGURE vo. FREQUENCY

id:""so;;;;;t-- -r-.-........

ld= 35 mA ,~

'",..... '- f-f-. -- - -~Id= 20 mA5.0

0.1

.-' :::::~

Id:50mA_...--- -::: .... ".,,-

15

12

o0.1 0.2 0.3 0.5 1.0

Frequency, GHz

2.0 ...0

7.0

....,~ 8.0

5.5

0.2 0.3 0.5 1.0Frequency, GHz

2.0

Typical Scattering Parameters: Zo =50 n TA = 25°C, Id =35 mA511 521 5,2 S>2

Freq.Mag Ang dB Mag Ang dB Mag Ang Mag AngGHz

0.1 .09 178 12.6 4.26 175 -18.1 .124 2 .13 -100.2 .09 171 12.5 4.24 170 -18.4 .120 3 .13 -200.4 .08 166 12.4 .4.17 161 -18.4 .121 6 .14 -410.6 .07 160 12.3 4.10 151 -18.0 .126 8 .15 -570.8 .07 155 12.1 4.01 142 -17.9 .127 12 .16 -711.0 .06 152 11.9 3.92 133 -17.6 .132 12 .18 -841.5 .05 -169 11.2 3.63 112 -16.5 .149 18 .21 -1122.0 .08 -174 10.4 3.29 92 -15.6 .167 19 .23 -1362.5 .12 -173 9.5 2.98 79 -14.6 .186 22 .25 -1503.0 .20 178 8.4 2.64 63 -14.1 .198 20 .26 -1663.5 .25 '." 170 7.5 2.36 47 -13.5 .211 17 .25 -1744.0 .28 160 6.5 2.12 33 -13.0 .224 13 .24 -1805.0 .42 134 4.7 1.71 7 -12.2 .247 4 .20 1686.0 .50 99 2:7 1.37 -18 -12.0 .252 -7 .23 133

Amodel for thi. device i. available in the DEVICE MODELS .ecbon.

Anmek.lnc. . 3175 Bowers Ave.. Santa Clara. CA 95054 . Phone (4081 727~700 . FAX: (408) 727~539 . TWX: 310-37HI717 or 310-371·8478 . TELEX: 34-6337

4-57

63

Appendix C: Schematic Diagrams

The following pages show the schematic diagrams of all designed and used circuits.

L.:.II,--F..::.in,---~)

11-l----I.:::....-.._-o ...sVolt

IVA-05118C27

10nFII.

----« Uout

Figure C.1: Schematic diagram delay and multiply demodulator.

64

'~5Vj~~VDf:-~~~~~~~~~+Tvss ~AVSS

P3.OIRXOP3.1fTXO

P3.2/IN'i'i5""""P3~~:;;'~ ~~--+---P3.8(TlP3.8I'NRP37/AD~~~~

f=~r---'AD'DA"ESSIDA"'T'A'IllJ'S'().!Ni~~D";oe~R);;;;;;;;;;~:::-I~----------PO.a/ADO

:::::;;:g~~PO.31AD3

PO......AOoI qE::f,~;:JPO.51ADS ~

:~:~:~ ~t::1liEjP1.OICTOLPl.'fCT1LPl.21CT2LPl.31CT3L

P1.4/T2P1.51AT2Pl.8,ISCLPl.7/SDA

vOO

C410uF

P5.OIAOCOPS,1/ADC1P5.2/ADC2PS.3/ADC3PS.""ADC4P!U5/ADC8pS.!lr/AOCeP5.7/AOC7

::-'_OfCMSRO4.1!'CMSR1

::121CMSFl2....3/CMSFl3N <ll/CMSFl4P4.5/CMSFU5

P4:~:::~~

ASTEw

AVDDUl("):TCD3~n'a.Qi'ceQi33n'o(")o:J....ocoQl

0..

."cO'cCDn

'"

Q')U1

RS RS 82aSk 3Sk

Figure C.3:

VDDA2 02 AS'OOE 1N41 330E

A11

• C2 A4 R' A12u2 S60k 560 22

Schematic diagram EPROM emulator.

R12,. T2B

6264

A1.

BATes

co CO CI CO .2 CO CO a2 CO CO- - - -:I I :I I :I Ib2 •

:I Ic1 7 c1 7 c2 7 c2 7

d1 . - 1 .:I- - :I-:I I ., . I :I I .2 • I

f1 -. f1 -. 12 2 -. '2 2 -.d. d.

2 ,d.

2 ,d.

R''0'

pppppppp,,",1 1 1 1 1 1 1 0 x

l>- -f-_-"S"O"A -i:=]-_--''''--t :~ 4 3 2 1 0 2

VDO

co,oan

22.

Figure C.4: Schematic diagram 12C display.

66

Appendix 0: Printed Circuit Board Designs

PCB-design Automatic Gain Control unit

Component layout Bottom layer

... ... J

Figure 0.1: Printed circuit board design automatic gain control unit.

67

•

CRLJ.~ @[:!J@ •@~®·w ..w

•

~.•

~• •

c

~~~8l•." (J)

L

'" Ito •'"o "...., Il m.0'" ...

>--m !; ~ C;U •• ~ ~

-.JU •:on.~ •.~ • • •

~D~"I

•

.,,8>L

'" '"0".0'"f-m

5~

Figure D.2: Printed circuit board design micro control board.

68

Appendix E: Pascal Procedures

beginwhile not (SlSTA=status) do

end; {wait}

procedure wait (status byte) ; lthis procedure waits until the}status register SlSTA equals the}variable 'status'}

bit}bit}

bus is ready}address and Waddress and Wacknowledge}

this procedure generates a start}condition for the I2C bus and sends}the slave address of the display}initialize master transmitter mode}start bus}wait untilload slavesend slavewait until

beginSlCON:=$40;STA:=true;wait ($08);SlDAT:=$72;STO:=false;SI:=false;wait($18) ;

end; {start_bus}

procedure start_bus;

beginSlDAT:=data byte;STA:=false;STO:=false;SI:=false;wait($28) ;

end; {send_byte}

procedure send_byte(data_byte byte) ; {this procedure is used to}send 'data_byte' across the I2C bus}and wait for the acknowledge}load data into data register}start transmission}wait for acknowledge}

procedure stop bus;begin -

STA:=false;STO:=true;SI:=false;

end; {stop_bus}

{this procedure is used to shut down}{the 12 C bus}

procedure display(d1,d2,d3,d4

beginstart bus;send byte($OO);send-byte ($37) ;send-byte (d1) ;send-byte (d2) ;send-byte (d3) ;send-byte (d4) ;stop-bus;

end; Tdisplay}

byte) ; {this procedure is used to}{send the display information d1 .. d4}{to the display}

start 12C bUs}send instruction byte}send control byte}send data display 11send data display 2send data display 3send data display 4stop 12C bus}

procedure convert(input_int

begincase

o1234

input int ofoutput_byte:=$3F;output byte:=$06;output-byte:=$5B;output-byte:=$4F;output=byte:=$66;

integer; var output_byte : byte);

this procedure converts an integer}between 0 and 9 to a byte that will}light up the segments on the dis~lay}that correspond with the integer}concerned}

69

5 output byte:=$6D;6 output-byte:=$7D;7 output-byte: =$07;8 output-byte:=$7F;9 output-byte:=$6F;

end; {case}end; {convert}

procedure detect (var adc data

vareoc : byte;

beginADCON:=$OO;ADCON:=$08;repeat

eoc:=ADCON AND $10;until (eoc=$10);adc data:=ADCH;

end;-{detect}

byte) ; {this procedure starts the ADC}{and returns the sampled value in the}{variable 'adc_data/}

{reset ADC and select channel O}{start AD conversion}

{wait until end of conversion}

{return sample via adc_data}

70

Appendix F: CPFSK Test Signal Generator

At the moment of the development of the frequency controller, the lasers were not yet

operative. Tests of the various components had to be carried out by using a test set-up.

This set-up has been designed for tests of the demodulator developed by E.E. Vrolijks

[1]. The signal is simulated by a bit pattern in stead of switching an oscillator between the

two modulation frequencies. Figure F.1 shows how the bit pattern is coded.

Coding

No coding

"1"

Wavefonns

"0"

Manchester coding

Manchester &

CPFSK coding

le--: : : : :.. .· .. .· . . . . .. . . . .· . . . . .· . . . . .

: : : : ; :· . . . . .· . . . . .· . . . . .· . . .. . . . .

-UUU iLJlfLFigure F.1: Bit pattern simulation of CPFSK signal.

Each data bit in a Pseudo Random Bit Sequence (PRBS) is converted to 8 bits according

to Figure F.1; the 8 bit word simulates the waveforms as in Figure 3.2 by square waves.

The CPFSK test signal generator is build up around a Bit Error Rate Tester / Bit Pattern

Generator. Figure F.2 shows the block diagram of this set-up. The bit pattern generator

produces a PRBS which is converted to a Manchester/CPFSK coded sequence that is 8

times longer. This signal is low pass filtered to remove the higher harmonics of the

square waves.

To be able to shift the signal spectrum by /11, the signal is first mixed with its own clock

signal (1244.16 MHz); this causes the spectrum to move up by 1244.16 MHz. The image

frequency spectrum below 1250 MHz is removed by a High Pass Filter (HPF). After

filtering, the signal is mixed with a signal generated by a Voltage Controlled Oscillator

71

Bit Error Rate Tester IPatem Generator

Data Clock

LPF

\1900 MHz

HPF

1250 MHz

Control Voltage Vvco

LPF\rCPFSK=t900 MHz

Figure F.2: Block diagram CPFSK test signal generator.

(VCO). If the frequency of this VCO is 1244.16 MHz, the spectrum returns to its initial

position (the image frequency spectrum is removed by the last LPF). A deviation 111 of

the VCO frequency from 1244.16 MHz will cause the CPFSK spectrum to shift in the

opposite direction by the same !if with respect to 465 MHz. The VCO can therefore be

used to shift the CPFSK signal spectrum. Figure F.3 shows the position of the CPFSK

spectrum after mixing with the described signals .

465 MHz

779 MHz

1709 MHz - f veo

• 1244 MHz

First mixing process

1709 MHz + f veo

Figure F.3: Position of CPFSK spectrum as a result of the mixing processes.

More details about the CPFSK test signal generator can be found in [18].

72

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