Microprocessor & interfacing...Quiz 1 (Review) Ubahlah bilangan berikut menjadi format bilangan yang...
Transcript of Microprocessor & interfacing...Quiz 1 (Review) Ubahlah bilangan berikut menjadi format bilangan yang...
Microprocessor & interfacing
Lecture 2
Quiz 1 (Review)
Ubahlah bilangan berikut menjadi format bilangan yang lain :
Desimal Binary 8-bit Hexa BCD Packed BCD Unpacked
62
CF
00000010 00000101 00000011
01100011
01010110
OUTLINE
• Microprocessor Architectures – Basic Architecture
– Register Organization
– CISC vs RISC
– X86 Architecture
– ARM Architecture
• Memory Addressing
Microprocessor Architectures
Basic Machine Cycle
• Fetch Instruction processor reads instruction from memory • Interpret Instruction decode instruction to determine what
action is required • Fetch Data reads data from memory or I/O for execution • Process Data execution such as arithmetic or logic function • Write Data write data to memory or I/O
Fetch Decode Execute
Basic Computer System
Microprocessor
Memory I/O
Data Bus
Address Bus
Control Bus
ALU?
• Arithmetic Operations (+ - x / )
• Logic Operations (and, or, not, etc)
• There’s an Accumulator!
A B
n n
+ - x / logic
Accumulator
Arithmetic Logic Operation
• Subtract is addition using 2’s complement
• Multiply is addition and shift left
• Divide is addition and shift right
ALU consists of FA and HA plus Shift Register (Remember Logic Circuit!)
Flags
• An effect of operation
• To give an information for the next execution
Zero activate when operation result is zero.
1 1 0 0 1 1 0 0
1 1 0 0 1 1 0 0 xor
0 0 0 0 0 0 0 0
Carry If bits from addition process result become larger than register capacity
1 1 1 1
1 1 0 0 1 1 0 0
1 1 0 0 1 1 0 0 +
1 0 0 1 1 0 0 0
FE
FE +
1 FC
Carry bit
Overflow to validate sign number after arithmetic process
1 1 1
+76 0 1 0 0 1 1 0 0
+68 0 1 0 0 0 1 0 0 +
+144 1 0 0 1 0 0 0 0
I8086/8088 Microprocessor Architecture
ES
CS
SS
DS
4
3
2
1
CONTROL
SYSTEM
AH AL
BH BL
CH CL
DH DL
SP
BP
SI
DI
OPERAND
FLAGS
C-BUS
IP
ALU
INSTRUCTIONSTREAM
BYTEQUEUE
A- BUS
BIU
EU
Register Organization
User-Visible Registers
• Enable the machine- or assembly language programmer to minimize
main memory references by optimizing use of registers.
Control and Status Registers
• Used by the control unit to control the operation of the processor
and by privileged, operating system programs to control the
execution of programs.
User-Visible Register
• General Purpose – can be assigned to a variety of functions by the
programmer • Data
– may be used only to hold data and cannot be employed in the calculation of an operand address
• Address – may themselves be somewhat general purpose, or they
may be devoted to a particular addressing mode – Segment Pointer, Index Register, Stack Pointer
• Condition – Flags
Control and Status Register
• There are a variety of processor registers that are employed to control the operation of the processor.
Program counter (PC): Contains the address of an instruction to be fetched
Instruction register (IR): Contains the instruction most recently fetched
Memory address register (MAR): Contains the address of a location in memory
Memory buffer register (MBR): Contains a word of data to be written to memory or the word most recently read
Example
Data Flow
X86 Architecture
X86 Architecture
X86 Architecture
CISC vs RISC
CISC (Complex Instruction Set Computing)
Hardware optimized
Complex instruction
Greater machine cycle per instruction e.g. 12 clocks
Hardware circuitry more complex
Draws greater power consumption
CISC vs RISC
RISC (Reduce Instruction Set Computing)
• An instruction per cycle
• Operation between register
• Simple addressing mode
• Simple and Fix instruction format
• Need reliable compiler
ARM Architecture
• A moderate array of uniform registers, more than are found on some CISC systems but fewer than are found on many RISC systems.
• A load/store model of data processing, in which operations only perform on operands in registers and not directly in memory. All data must be loaded into registers before an operation can be performed; the result can then be used for further processing or stored into memory.
• A uniform fixed-length instruction of 32 bits for the standard set and 16 bits for the Thumb instruction set.
• To make each data processing instruction more flexible, either a shift or rotation can preprocess one of the source registers. To efficiently support this feature, there are separate arithmetic logic unit (ALU) and shifter units.
ARM Architecture
• A small number of addressing modes with all load/store addressees determined from registers and instruction fields. Indirect or indexed addressing involving values in memory are not used.
• Auto-increment and auto-decrement addressing modes are used to improve the operation of program loops.
• Conditional execution of instructions minimizes the need for conditional branch instructions, thereby improving pipeline efficiency, because pipeline flushing is reduced.