1100 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 6, NOVEMBER 2012

Optimized Design of a 32-nm CNFET-BasedLow-Power Ultrawideband CCII

Ale Imran, Member, IEEE, Mohd. Hasan, Member, IEEE, Aminul Islam, Member, IEEE,and Shuja Ahmad Abbasi, Senior Member, IEEE

Abstract—CMOS technology faces significant challenges liketunneling effect, random dopant fluctuation, and line edge rough-ness at channel lengths below 45 nm. Carbon nanotube-based elec-tronics seems to be a better prospect for extending the saturatingMoore’s law because of its higher mobility, scalability, and betterchannel electrostatics. This paper presents an optimum design ofa wide bandwidth, high-performance carbon nanotube field-effecttransistor (CNFET) realization of a dual-output second-generationcurrent conveyor (CCII±) at a 32-nm technology node. The per-formance of the CCII module has been thoroughly investigatedin terms of number of carbon nanotubes (CNTs), the diameter ofCNT and inter-CNT pitch. The parameters of individual CNFETare then modified to further improve the performance. The per-formance of the optimum CNFET (ITOPT)-based CCII is thencompared with CMOS at different supply voltages. It has beenfound that CNFET-based CCII provides excellent high-frequencyresponse and also consumes lower power at scaled supply voltagecompared with its CMOS counterpart.

Index Terms—Carbon nanotube (CNT), carbon nanotube field-effect transistor (CNFET), current conveyor, current mode circuits,nanoelectronics.

I. INTRODUCTION

THE last decade has witnessed tremendous growth in thefield of current-mode (CM) analog-signal processing. In

CM operation, the circuit response is described in terms of cur-rent rather than voltage. The use of current, rather than voltageas the active variable in the whole circuit (or in part), offers anelegant solution for various circuit- and system-based problems.Generally, CM circuits exhibit better high-frequency response,have simpler architecture, provide better dynamic range, andoperate at lower voltages than their voltage-mode counterparts.Another important reason for the fast development in CM cir-cuits is the recent availability of attractive integrated devices like

Manuscript received September 29, 2011; accepted July 12, 2012. Date ofpublication August 8, 2012; date of current version November 16, 2012. Thiswork was supported by the Comprehensive National Plan for Science, Technol-ogy and Innovation, King Saud University, Riyadh, Saudi Arabia, under Grant09-ELE854-0. The review of this paper was arranged by Associate Editor S. D.Cotofana.

A. Imran and M. Hasan are with the Department of Electronics Engi-neering, Aligarh Muslim University, Aligarh 202002, India (e-mail: aleimran.amu@gmail.com; mohd.hasan@amu.ac.in).

A. Islam is with the Department of Electronics and Communication Engi-neering, Birla Institute of Technology, Mesra, Ranchi 835215, India (e-mail:aminulislam@bitmesra.ac.in).

S. A. Abbasi is with the Department of Electrical Engineering, King SaudUniversity, Riyadh 11421, Saudi Arabia (e-mail: abbasi@ksu.edu.sa).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNANO.2012.2212248

current feedback amplifier (CFA), current differencing bufferedamplifier (CDBA), current differencing transconductance am-plifier (CDTA) for an analog circuit design. However, among allCM devices, a dual-output second-generation current conveyor(CCII±) by far is the most popular one. A current conveyor isbasically a CM device that conveys (transfers) current with unitygain from an input port to an output port. It is widely consideredas the op amp equivalent in CM analog signal processing andfinds wide range of applications in realizing amplifiers, differ-entiators, impedance converters, integrators, filters, oscillators,etc. [1]–[4]. The performance of the current conveyor is charac-terized by its voltage and current following behaviors.

In the past many decades, CMOS technology has played aninstrumental role in driving the world economics and scalingdown of size has been the fundamental strategy for improvingthe performance of the device. However, ITRS suggests that by2016, the gate length of the MOSFET will be less than 10 nmand at these nanoscale regimes both the fundamental limits andthe technological challenges are going to be encountered [5]. Inaddition to that problems like process variations, extreme short-channel effects, leakage current, high field effect, lithographiclimits and quantum confinement effect will have significant im-pact on the MOSFET’s functioning. Therefore, it is extremelyimperative to find new, molecular-scale devices that could com-plement the existing silicon platform by providing it with newcapabilities or that might even replace existing silicon CMOStechnology and allow device scaling to continue to the atomicscale [6].

It is a well-known fact that the last few years have witnessedsignificant increase in nanoelectronics research, where manypossibilities are appearing in the form of various device struc-tures such as multigate field-effect transistor (FET), FinFET,nanowire FET, etc., to name a few. However, among all these,carbon nanotubes (CNTs) is generally considered to be the mostpromising nanostructured material for realizing nanoelectronictransistors because of its ballistic transport capability, very nar-row diameter of the order of few nm, possible engineering ofelectronic properties and high current carrying capacity [7].

A carbon nanotube field-effect transistor (CNFET) is a three-terminal device which consists of a semiconducting nanotubebridging two contacts (source and drain) and acting as a carrierchannel, which is turned ON or OFF electrostatically via thethird contact, i.e., gate. It was first fabricated in 1998 and sincethen it has come a long way.

A CNFET has the potential of taking over in the post siliconera due to its exceptional electrical and structural characteristics,such as quasi 1-D (ballistic) transport of electrons (and equally

1536-125X/$31.00 © 2012 IEEE

IMRAN et al.: OPTIMIZED DESIGN OF A 32-nm CNFET-BASED LOW-POWER ULTRAWIDEBAND CCII 1101

likely for holes), higher drive current (three to four times thanMOSFETs), large transconductance (four times), low intrinsiccapacitance, near ideal subthreshold slope, high temperatureresilience and strong covalent bonding [8]. Moreover, the devicestructure and the operating principle of CNFET are quite similarto the existing CMOS and it can also be fabricated by utilizingthe existing CMOS infrastructure.

Significant research work has already been carried out inthe digital domain using the emerging CNFET technology.Full adders, multiplexers, memory (SRAM), LUTs, etc., imple-mented using CNFET, are available in the literature [9]–[12].However, the design of analog modules like OTA, current con-veyor, etc. in CNFET technology still remains an unexploredterritory. This paper presents the design of a high-performancedual-output current conveyor module and investigates its designmetrics at 32-nm technology node. It is to be noted that to thebest of our knowledge, no previous work has been reported inthe literature on the performance of a CNFET-based currentconveyor. This paper makes the following contributions.

1) In view of the aforesaid requirement of circuits operat-ing in an ultrawideband range of frequencies, a CCII±module is designed to achieve high performance (in termsof current, voltage bandwidth and the input/output resis-tances) using a CNFET optimized in terms of number ofCNTs, inter-CNT pitch and the diameter of CNT. The per-formance of the optimized CNFET-based CCII is furtherimproved by altering parameters of an individual CNFET(ITOPT).

2) The performance of ITOPT CCII is then compared withCMOS at different supply voltages.

The rest of the paper is organized as follows. A brief introduc-tion of CCII± is given in Section II, followed by an overviewof CNFET design parameters and equations in Section III.Section IV and V discuss in detail the design and performanceanalysis of CNFET-based CCII. In Section VI, the parametersof individual CNFET are altered to further improve the per-formance of CNFET-based CCII, and then, its performance iscompared with the existing bulk CMOS-based CCII. It is thenfollowed by conclusion in Section VII.

II. CURRENT CONVEYOR

The first-generation current conveyor (CCI) was introducedway back in 1968 by Sedra and Smith [13]. In 1970, the sameduo modified the architecture of CCI and came up with a noveltype of current conveyor, which is now known as the second-generation current conveyor (CCII) [14]. It is an attractive build-ing block for voltage and CM circuits with great functionalversatility. It is widely used for implementing various functionsin analog signal processing, such as amplifiers, integrators, dif-ferentiators, oscillators, filters, etc.

CCII is basically a CM device, which conveys current, withunity gain, from the input port to the output port. It has reliablefrequency response and is popularly used for high frequencyapplications. The block diagram representation of CCII± andits internal transistor implementation are shown in Figs. 1 and 2respectively [15]. Using the standard notation, the characteristic

Fig. 1. General structure of CCII±.

Fig. 2. CCII± implementation using a translinear loop.

equations of the dual output current conveyor can be representedas follows:

IY = 0 (1)

VX = VY (2)

IZ = ±IX (3)

where VX and VY are the voltages at ports X and Y, respectively.IX and IY are the currents entering ports X and Y. Moreover,IZ+ is the positive-type output current and IZ− is the negative-type output current. Ideally, a current conveyor should satisfythe following attributes.

1) Infinite input impedance (RIN ) at port Y.2) Zero input impedance (RX ) at port X for current inputs.3) Infinite output impedance (ROUT ) at port Z.4) Unity current transfer gain between ports X and Z.5) Unity voltage transfer gain between ports Y and X.6) Infinite bandwidth.Current and voltage bandwidths along with the input and

output port resistances of the CCII have been chosen as the pa-rameters for the assessment of its performance using the emerg-ing CNFET technology at a 32-nm technology node. However,various configurations of CCII± based on silicon CMOS andbipolar technologies exist in the literature.

However, the one chosen in this paper for carrying out thedesign and performance optimization with CNFET technologyexhibits excellent high-frequency response.

1102 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 6, NOVEMBER 2012

Fig. 3. Top view of a CNFET.

III. CARBON NANOTUBE FET

As silicon CMOS technology reaches its scaling limit, thedevelopment of alternative technologies that could improvethe performance of the device/circuit is of utmost importance.Nanotechnology-based fabrication is expected to offer the ex-tra density and potential performance to take electronic circuitsto the next level. Among all the nanoscale electronic devicesinvestigated till date, CNT FET seems to have the brightestprospect due to its excellent electronic properties [16]. Most ofthe traditional fundamental problems like extreme short channeleffects, leakage currents, high field effects, lithographic limits,and quantum confinement effect associated with silicon CMOSare overcome in a CNFET [17]. A CNFET can be scaled down to10-nm channel length and 4-nm channel width, thus enhancingthroughput in terms of speed. Besides that a majority of issuesrelated to the fabrication process of CNFET has been solved andthe future looks promising [18]–[21].

A CNFET is obtained by replacing the channel of a conven-tional MOSFET by an array of semiconducting CNTs as shownin Fig. 3. CNTs are long, thin allotropic cylinders of carbon,discovered by Ijima [22]. They are composed of a single shellnamely single-walled CNT (SWCNT). SWCNTs are quasi—1-D molecular structures and can be formed by folding graphitelayers into a cylinder. It is because of this—1-D structure ofSWCNT that CNFETs provide better electrostatic control overthe channel as compared to 2-D (e.g., silicon on insulator) and3-D (bulk CMOS) devices [23]. The properties of SWCNT de-pend on the chirality (n1 , n2). The SWCNT is considered to bemetallic if n1 = n2 or (n1–n2) is a multiple of “3,” otherwiseit is a semiconductor. The diameter of the CNT (DCNT ) andits threshold voltage (Vth ) is calculated with the assistance ofchirality vector as follows:

DCNT =a(n2

1 + n22 + n1n2)1/2

π(4)

Vth =aVπ√

3 qDCNT(5)

where q = electronic charge, a = 2.49 A is the lattice constantand Vπ = 3.033 eV is the carbon π–π bond energy [24], [25].

The operating principle of CNFET is similar to a traditionalMOSFET. As in other FETs, the CNFET too relies on one of itsthree terminals, i.e., the gate, to modulate the carrier concentra-

tion in the device channel by applying a field perpendicular tothe charge flow between the two other contacts, i.e., source anddrain. The number of semiconducting SWCNTs required in thechannel region depends on the current drive requirement. Thecarrier transport between the n+ /p+ source and drain regionstakes place through these narrow CNTs and utilizes its ballistictransport property. Ballistic transport means that the mean freepath for a charge carrier is longer than the device dimensions.Thus, the charge carriers do not collide, reducing resistance tonegligible levels, resulting in higher mobility as compared to thebulk MOSFETs [26]. On the basis of device operation mecha-nism, the CNFET can be categorized into Schottky-barrier con-trolled FET (SB-CNFET) or MOSFET-like FET. In this work,MOSFET-like FETs are employed which exhibits unipolar be-havior by suppressing either the electron (pFET) or hole (nFET)transport with heavily doped source/drain.

Generally, while designing a circuit in the conventional sil-icon CMOS technology, a PMOS/NMOS ratio of 2–4 is used,in order to match the p- and n-type devices. However, no suchconstraint exists in CNFET technology. In a CNFET, a ratio of“1” could easily be used for PCNFET/NCNFET because both“p” and “n” types of a CNFET have similar current-drivingcapabilities with the same transistor geometries.

Moreover, unlike CMOS, where the widths and lengths ofthe transistor are adjusted to change the PMOS/NMOS ratio,a CNFET-based current conveyor is designed in terms of thefollowing optimal structural parameters.

1) Number of CNTs (N): It is important to determine thenumber of CNTs to be used in an array in order to en-sure sufficient current supply for driving fixed capacitiveloads as a single-nanotube-based transistor does not pro-vide competitive performance over CMOS.

2) Inter-CNT Pitch (S): It is defined as the distance betweenthe center of two adjacent lying CNTs in the channel.It is denoted by “S” and is one of the important factorsaffecting the performance of the CNFET.

3) Diameter of CNT (DCNT ): It should be chosen very care-fully because it directly affects the threshold voltage ofthe device.

The design equations relating to the diameter of the CNT(DCNT ), number of CNTs in the channel (N) and inter-CNTpitch (S) with the width of the CNFET (W) and the energy gap(∑

g ) are given as follows:

W = (N − 1) ∗ S + DCNT (6)∑

g

= 0.84 eV/DCNT . (7)

For carrying out simulation of CNFET-based CCII± at a32-nm technology node, we have used the Stanford CNFETmodel [24]. This model has been experimentally validated anddesigned for the unipolar MOSFET-like CNFET and takes intoconsideration the device parasitics and non-idealities includingchannel length dependence of current drive, source–drain seriesresistance, source–drain contact resistance, effect of the source–drain extension region, inter-CNT charge screening effect,etc. along with accurate predictions of dynamic and transient

IMRAN et al.: OPTIMIZED DESIGN OF A 32-nm CNFET-BASED LOW-POWER ULTRAWIDEBAND CCII 1103

TABLE ITECHNOLOGY PARAMETERS OF A CNFET

performance with more than 90% accuracy [27], [28]. Someof the important device and technology parameters related to aCNFET are given in Table I.

IV. CNFET-BASED CURRENT CONVEYOR

A second-generation current conveyor is designed using aCNFET, optimized in terms of uniformly spaced and perfectlyaligned CNTs, inter-CNT pitch, and the diameter of CNT. Atypical CNFET fabricated with Pd source/drain contacts and Algate contact is used in the simulation [29]. Intrinsic device ca-pacitance (∼2–5 aF/nanotube), overlap, and fringe capacitances(∼0.1 fF/nanotube) along with a capacitive load of 1fF are con-sidered for a 32-nm CNFET device. To begin with, the circuitis properly biased with power supply being kept constant at±0.9 V and the value of current source Io , set to 10 μA in orderto establish a current in the circuit. The performance evaluationis carried out on the basis of five key characteristics of a CCIInamely current bandwidth, voltage bandwidth, input port resis-tance X, input port resistance Y, and output port resistance Z.The next sections investigate the effect of key parameters of theCNFET on the performance of CCII.

A. Optimum Number of CNTs (N)

It is important to ascertain the number of CNTs to be usedin the channel so that sufficient current could be supplied fordriving load, as a single-CNT-based transistor cannot provide anedge in performance over traditional CMOS [30]. The variationof the performance parameters of CCII± with the number ofCNTs is shown in Figs. 4–6. It can be deduced from Fig. 4 thatwith the increase in number of CNTs, the bandwidth increasessomewhat linearly, which allows for the use of larger number oftubes to get best performance as expected. This is due to the factthat parallel CNTs improve the driving capability of the device,thus resulting in a significant increase in the transconductance[31].

The small signal analysis of the port resistances of the deviceis performed in order to seek their dependence on the transistorgeometries. The small signal analysis at input port X of theproposed circuit is depicted in Fig. 7. We can deduce from thesethat the theoretical expression of RX is given by [32]

RX =1

gm2 + gm4(8)

where gm 2 and gm 4 are the transconductances of transistors M2and M4, respectively. The variation of input port resistance X

Fig. 4. Number of CNTs versus 3-dB bandwidth.

Fig. 5. Number of CNTs versus resistance at port X.

Fig. 6. Number of CNT versus port resistance.

(RX ) with the number of CNTs is depicted in Fig. 5. It can easilybe inferred that as the number of CNTs is increased, the value ofRX gradually decreases. This happens because with the increasein the number of CNTs, the value of transconductance increasesand as per (8), RX decreases. Thus, increasing the number ofCNTs is a good option for reducing RX . The same approach isfollowed for input port resistance Y and output port resistanceZ. The small signal analysis of the port resistances, i.e., RY andRZ yields the following results:

RY =g−1

m1 + ro9

g−1m3 + ro11

(9)

1104 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 6, NOVEMBER 2012

Fig. 7. Small signal analysis at port X.

RZ =r06(1 − gm6/4αI0.5

o β0.5)r07(1 − gm7/4αI0.5

o β0.5)(10)

where gmn and ron represent the transconductance and outputresistance of the nth transistor. Io is the value of the currentsource that has been kept constant throughout the analysis at10 μm, in order to establish a current in the circuit, and α andβ represent the values of current and voltage gain. The resultsincorporating the variations in input port resistance Y (RY ) andoutput port resistance Z (RZ ) with increasing number of CNTsis shown in Fig. 6. It is to be noted that “Z” is an output currentport, and for proper cascading of the device, it is preferableto have high output resistance. However, it has been observedthat as the number CNTs in an array increases, and the valueof output port resistance Z (RZ ) decreases, thus presenting atradeoff with other parameters involved. Moreover, the powerdissipation goes up with the number of CNTs in the channel ofthe device, thus putting an upper limit on the number of CNTs tobe incorporated in the channel. Hence, the number of CNTs to beused is determined by the tradeoff involved between bandwidth,input port resistances on one side and power and output portresistances on the other. Nevertheless, looking at the overallperformance merits obtained sufficient number of tubes mustbe chosen. Based on the simulation results, the optimum valueof number of tubes comes out to be 9, which has been used forfurther simulation purposes.

B. Optimum Inter-CNT Pitch (S)

The effect of varying the inter-CNT pitch on the performanceof CCII is now investigated. It is worth noting that the CNFETmodel used for simulation purposes assumes that because of thescreening phenomenon, the CNTs lying at the corner, conductsin a better fashion compared to the CNTs lying in-between.Analytical results indicate that both the 3-dB current and voltagebandwidths improve slightly with the increase in inter-CNTpitch as shown in Fig. 8. The observed variations is due to thefact that the capacitance from the gate to each CNT channel(Cgc) decreases, as the CNTs are brought closer because everynanotube can mirror a small amount of charge [33]. Hence, the

Fig. 8. Inter-CNT pitch versus 3-dB bandwidth.

Fig. 9. Inter-CNT pitch versus resistance at port X.

Fig. 10. Inter-CNT pitch versus port resistance.

current per tube ITUBE gets reduced for lower pitch because ofthe inter-CNT screening effect. Furthermore, it is observed thatresistances at Ports X, Y, and Z decrease in a similar manneron increasing the inter-CNT pitch. Hence, compact packing ofCNTs deteriorates the overall performance. From the plots ofFigs. 8–10, we conclude that the optimum choice of inter-CNTpitch comes out to be 16 nm.

C. Optimum Diameter of CNT (DCNT )

The diameter of an SWCNT is a measure of its electronicproperties. An SWCNT is obtained by selective axial folding of

IMRAN et al.: OPTIMIZED DESIGN OF A 32-nm CNFET-BASED LOW-POWER ULTRAWIDEBAND CCII 1105

Fig. 11. CNT diameter versus 3-dB bandwidth.

Fig. 12. CNT diameter versus resistance at port X.

a single layer of graphite called graphene. The diameter of CNT(DCNT ), its bandgap energy Eg and the threshold voltage of thedevice (Vth ) are closely related as given by

Eg =0.84 eVDCNT

(11)

Vth =Eg

2e(12)

where “e” is the electronic charge. The diameter of a CNT is infact one of the most important design parameters because it notonly affect the source/drain series resistance but also the thresh-old voltage of CNFET. For optimum values of “N” and “S”, wenext consider the effect of variation in the CNT diameter on thecircuit performance. Analytical results suggest that with the in-crease in the diameter of the nanotube as shown in Figs. 11–13,there is a significant improvement in the frequency response ofa CNFET-based current conveyor. The trend could be well jus-tified because on increasing the diameter, the gate–to-channelcapacitance along with the fringe capacitance decrease appre-ciably on account of enhanced screening between the adjacentCNT channels [34]. Moreover, the transconductance also goesup with the reduction in the threshold voltage with the increasein diameter of the CNT.

The variation in input and output port resistances with theCNT diameter is depicted in Figs. 12 and 13, respectively. Re-sults indicate that the resistance at port X decreases, moving

Fig. 13. CNT diameter versus port resistance.

towards its ideal value of zero, as the diameter is increased.This happens because the bang gap decreases with the increasein diameter. As a result, a large number of charge carriers areable to overcome the energy barrier, thus strengthening the cur-rent flow, resulting in a higher value of transconductance. Asclearly indicated by (8), the expression of resistance at port Xis inversely proportional to the transconductance. However, itis to be noted that for larger values of CNT diameter, the cur-rent tends to saturate because of large screening and scatteringeffect.

Finally, Fig. 13 shows that deterioration is observed in re-sistances at ports Y and Z as the CNT diameter is increased.Therefore, opting for a suitable value of diameter is extremelydifficult; rather a compromise between conflicting requirementsand a tradeoff is involved between the 3-dB bandwidth and theport resistances. The optimum diameter value is hence chosen tobe 1.5 nm corresponding to chiral vector (19, 0). The simulationresults of CNFET-based CCII± obtained by using the optimizedCNFET transistor parameters are discussed in the next section.

V. PERFORMANCE OF CNFET-BASED CCII±We begin with the evaluation of static and dynamic charac-

teristics of the current conveyor. The dc input–output currentcharacteristics of the current conveyor between terminals X andZ+ and X and Z– are plotted in Fig. 14. The input current appliedto the X terminal, i.e., IIN , is swept from 100 to –100 μA, andthe characteristics obtained, follows the linear curve, in accor-dance with the theory satisfying the basic equations, i.e., IZ =IX and IZ = –IX . The voltage transfer characteristic betweenports Y and X is illustrated in Fig. 15. Now, as expected, an ex-cellent voltage following action can be seen over a wide rangein accordance with the theory of a current conveyor satisfyingthe relation VX = VY . Next, the frequency characterization ofthe current conveyor is presented. Fig. 16 shows the frequencyresponse of voltage gain between terminals Y and X of the cur-rent conveyor. It is to be noted that the static voltage gain closeto unity is obtained.

In addition to that a CNFET-based module provides ahigh voltage cut-off frequency. A voltage bandwidth exceed-ing 20 GHz is obtained by using optimum values of CNFET

1106 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 6, NOVEMBER 2012

Fig. 14. Current input–output characteristics at 32 nm.

Fig. 15. Voltage transfer characteristics at 32 nm.

Fig. 16. Frequency response of voltage gain at 32 nm.

parameters. Fig. 17 shows the small signal current gain char-acteristics between terminals Z± and X. The CNFET module,besides giving a high voltage cut-off frequency, also providesremarkably high 3-dB current bandwidth. It should be notedthat current bandwidth exceeding 25 GHz is obtained, keepingthe static current gain close to unity.

Finally, the resistances involved at the input and output portsof the device are investigated. The resistance at port X (RX )is plotted for a control current of 10 uA against the frequencyas shown in Fig. 18 with port Y grounded. It is observed thatRX has a value of 1.45 kΩ for frequencies below 4 GHz and itdecreases at high frequencies. The resistance at port Y (RY ) isplotted under the same condition in Fig. 19. Ideally, the resis-tance expected at port Y is infinite, since it draws no current,i.e., IY = 0. However, the value obtained through the HSPICEsimulation is 153.4 kΩ, which though not very high, but is satis-factory. The variation of resistance RZ with frequency is shown

Fig. 17. Frequency response of current gain at 32 nm.

Fig. 18. Resistance RX against frequency at 32 nm.

Fig. 19. Resistance RY against frequency at 32 nm.

in Fig. 20 and it shows a value of approximately 362 kΩ, whichdecreases at higher frequencies. The optimized design param-eters and the corresponding performance characteristics of theCNFET-based current conveyor is summarized in Table II.

VI. OPTIMIZED CNFET-BASED CCII± (ITOPT)

Simulation results obtained after several iterations clearlyindicate that a CNFET-based current conveyor is an excel-lent prospect for designing high-performance analog circuits.Various analog modules like multifunctional filters, amplifiers,multiphase oscillators, etc., now could easily be designed forultrawideband range of frequencies by using a CNFET-basedCCII± module. However, in this section, an attempt is made

IMRAN et al.: OPTIMIZED DESIGN OF A 32-nm CNFET-BASED LOW-POWER ULTRAWIDEBAND CCII 1107

Fig. 20. Resistance RZ against frequency at 32 nm.

TABLE IIDESIGN PARAMETERS AND PERFORMANCE CHARACTERISTICS

to explore the possibility of further improving the performanceby optimizing parameters of individual transistors of currentconveyors (ITOPT-individual transistor optimization).

The designed module, shown in Fig. 2, uses a mixed translin-ear loop (transistors M1–M4) as the input cell. Two currentmirrors (transistors M9, M10 and M11, M13) allow the mixedloop to be dc biased by the current Io . The input cell presents ahigh input impedance at the input port Y and a low impedanceat port X. This cell acts as a voltage follower. The output Zthat copies the current flowing through port X is realized in theconventional manner using two complementary mirrors.

Now, as already discussed in the previous sections, the num-ber of CNTs along with the pitch and diameter plays a prominentrole in designing of a CNFET-based circuit. However, amongthese, the changes in diameter are crucial because even minorchanges can lead to much improved current drive and higherpower dissipations. Since the designed CNFET CCII± modulehas not so high port Y resistance values, the diameters of thecorresponding transistors affecting its value, i.e., transistors M1and M3 are increased in order to achieve higher transconduc-tance values for the best possible RY . Nevertheless, it needs tobe noted that transistors M1, M2, M3 and M4 form a translinearloop and changes in M1–M3 will lead to alterations in M2–M4.The parameters of various transistors in the designed module(ITOPT) are given in Table III.

TABLE IIIPARAMETERS OF AN ITOPT CNFET CCII± MODULE

TABLE IVPERFORMANCE COMPARISON OF CNFET-BASED CCII REALIZATIONS

The ITOPT designed CNFET CCII± module provides im-proved resistance at port Y, as its value increases 1.5 folds from153 to 231 kΩ. The resistance at port X also follows suite andits value decreases to 0.93 kΩ from 1.45 kΩ, exhibiting anotherimproved parameter; however, the resistance at port Z decreasesfrom 362 to 304 kΩ, presenting the tradeoff involved. Slight im-provement is also observed over the preceding design in thecase of frequency response, but at the cost of higher power dis-sipation as illustrated in Table IV. In order to get a fair idea,where the design obtained by selectively choosing parametersof individual CNFET of CCII± module (ITOPT) stands withrespect to the state-of-the-art CMOS CCII±, the 32-nm cus-tomized model parameters used for the simulation purpose ofthe CMOS CCII± module are generated from a specific toolknown as “Nano CMOS” [35].

Although CMOS-designed CCII shows good high-frequencyresponse in deep submicrometer but still its performance is muchinferior to the CNFET-based realization. It is also important toinvestigate the performance of the two designs at a scaled sup-ply voltage. Therefore, the supply voltage for both CNFET andCMOS-based modules has been varied from 0.9–0.7 V in orderto see its effect on the module’s performance. It can be inferredfrom Table V that for both technologies, with the decrease insupply voltage from 0.9 to 0.7 V, there is a significant deteri-oration in the 3-dB bandwidth. This happens because of muchlower driving current and hence transconductance. However, itis to be noted that, even at a lower supply voltage of 0.7 V, theCNFET-based module provides better performance compared tobulk CMOS. Hence, the supply voltage scaling of CNFET-basedCCII can be carried out from 0.9 to 0.7 V for achieving slightlybetter performance in all key parameters along with lower powerconsumption. Hence, an ITOPT CNFET-designed module could

1108 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 6, NOVEMBER 2012

TABLE VPERFORMANCE COMPARISON OF ITOPT CNFET DESIGN WITH BULK CMOS

be utilized for low power high performance analog circuits inthe microwave range of frequencies.

VII. CONCLUSION

This paper has successfully presented the design of a CNFET-based dual output current conveyor at 32-nm technology nodethat is based on optimum parameters of CNFET. The perfor-mance of CNFET-based CCII is further improved by optimizingparameters of individual CNFET giving rise to ITOPT. ITOPTprovides excellent voltage and current bandwidths along withgood port resistances, thus making it a viable proposition forultrawideband systems. The overall design and analysis clearlyindicates that a CNFET can significantly achieve better perfor-mance than CMOS even at a scaled supply voltage of 0.7 V withthe added advantage of lower power consumption.

REFERENCES

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IMRAN et al.: OPTIMIZED DESIGN OF A 32-nm CNFET-BASED LOW-POWER ULTRAWIDEBAND CCII 1109

Ale Imran (S’10–M’11) received the B.Tech.(Hons.) and M.Tech (Hons.) degrees in electronicsengineering with major in electronic circuits and sys-tem design from Aligarh Muslim University (AMU),Aligarh, India, in 2007 and 2010 respectively.

He has been currently a Lecturer in the Departmentof Electronics Engineering, Aligarh Muslim Univer-sity (AMU) since 2008. He is the author or coauthorof more than 20 research papers in reputed journalsand conference proceedings. His current research in-terests include simulation studies of circuits employ-

ing technologies beyond CMOS (that include emerging technologies such asfin-shaped FETs, carbon-nanotube FETs, etc.)

Mr. Imran is a member of The Institution of Electronics and Telecommuni-cation Engineers (IETE).

Mohd. Hasan (M’10) received the B.Tech. degreein electronics engineering from Aligarh Muslim Uni-versity, Aligarh, India, in 1990, the M.Tech. degreein integrated electronics and circuits from the IndianInstitute of Technology Delhi, New Delhi, India, andthe Ph.D. degree in low-power architectures for multi-carrier systems, under a Commonwealth Scholarship,from the University of Edinburgh, Edinburgh, U.K.,in 2004.

He has been currently a Full Professor at AMUsince 2005. From 2008 to 2009, he was a Visiting

Postdoctoral Researcher on a project funded by the prestigious Royal Academyof Engineering, U.K., on low-power field programmable gate array (FPGA)architecture with the School of Engineering, University of Edinburgh. He is theauthor of more than 123 research papers in reputed journals and conferenceproceedings. He received both the best International journal paper and interna-tional conference paper awards. His research interests include low-power VLSIdesign, nanoelectronics, batteryless electronics along with spintronics.

Aminul Islam (M’10) received the B.Tech. degree incomputer engineering from The Institution of Engi-neers (India), Kolkata, India, in 2001 and the M.Tech.degree in electronics and communication engineeringfrom the Birla Institute of Technology (BIT) (DeemedUniversity), Mesra, Ranchi, India, in 2006. He is cur-rently working toward the Ph.D. degree in the field ofvery large scale integrated (VLSI) design at the De-partment of Electronics Engineering, Aligarh MuslimUniversity, Aligarh, India.

Since November 2006, he has been in the De-partment of Electronics and Communication Engineering, BIT, where he iscurrently an Assistant Professor. He is the author or coauthor of more than 37research papers in reputed journals and conference proceedings. His researchinterests include VLSI/computer-aided design for classical CMOS, nonclassicalCMOS, and non-CMOS technologies (that include emerging technologies suchas fin-shaped FETs, carbon-nanotube FETs, nanowire FETs and tunnel FETs),robust design of ultralow-power nanoscale circuit for portable computing andwireless communications, and spin transfer torque–magnetic tunnel junction(STT–MTJ)-based logic and memory design.

Shuja Ahmad Abbasi (M’80–SM’98) was born atAmroha, India, in 1950. He received B.Sc. (Eng.) andM.Sc. (Eng.) degrees in electrical engineering fromAligarh Muslim University (AMU), Aligarh, India,in 1970 and 1972, respectively, with first position inthe University. He received the Ph.D. degree in mi-croelectronics from the University of Southampton,Southampton, U.K., in 1980.

He joined the Department of Electrical Engineer-ing at Aligarh Muslim University, Aligarh, India, in1971, as an Assistant Professor, and was promoted to

the positions of Associate Professor and Professor in 1982 and 1986, respec-tively. He shifted to the newly created Department of Electronics Engineeringat AMU as a Professor in 1988. He served as the Chairman of the Depart-ment of Electronics Engineering, AMU, from 1996 to 1999. He held manyAcademic/ Administrative positions in the past at AMU and outside. He joinedas a Professor of Electronics Engineering at the College of Engineering, KingSaud University, Riyadh, Saudi Arabia, in 1999. He has more than 100 researchpublications to his credit so far. He has completed many client funded projectsfrom various organizations. His current interests include Nanoelectronics, VLSIdesign and technology.

Dr. Abbasi is a Fellow of the Institution Electronics and TelecommunicationEngineers (IETE).