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Tugas Kelompok
Mata Kuliah Elektronika Telekomunikasi
DPLL
OLEH
AHMAD HUSNAN D411 07 020
NOVATRI BULO D411 07 041
PINGKAN WALUKOW D411 07 045
ENDAH DWI WARDHANY D411 07 081
FARADILA MUSTAFA D411 07 086
FEBRIYATI D411 07 104
FIKHA CHRISTINE D411 07 108
TRIMURTI FEMININA R. D411 07 161
JURUSAN ELEKTRO FAKULTAS TEKNIK
UNIVERSITAS HASANUDDIN MAKASSAR
2009
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If a digital phase detector (EXOR gate or J-K flip flop) is used, and
everything else stays the same, the system is called a digitalPLL (DPLL).
DPLLs have:
(a) digitally controlled analog oscillator (DCAO),
(b) frequency divider,
(c) time-to-digital converter (TDC) and
(d) digital loop filter (LF).
The DCAO is an analog oscillator whose frequency is controlled by a
digital word. The intrinsic oscillator can be an LC-tank or ring type
architecture. Frequency tuning in an LC-tank oscillator is achieved by
switching a parallel bank of capacitors. Similarly, a ring oscillator can be
controlled by switching parallel current sources to control the tail current in
the delay element. The output of the DCAO is divided to enable comparison
with the input reference. The TDC compares the phases of the reference and
the DCAO divided output to generate the phase error as a digital word. The LF
filters the phase error to produce the control word for the DCAO.
These noise sources can be broadly classified into two types:
P F D+
T D C
N
L F ( z )
D i g i t a l L o o pF i l t e r D C A O
F r e q u e n c y D i v i d e r
i n
o u t
P E C T R L
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3. Keep the inductor Q as high as possible. Typical off-the-shelf coils
provide a Q of between 50 and 60.
4. Choose an active device that has minimal noise figure as well as
low flicker frequency. The flicker noise can be reduced by the use
of feedback elements
5. Most active device exhibit a bowlshaped Noise Figue vs Bias
Current curve. Use this information to choose the optimal
operating bias current for the device.
6. Maximize the average power at the tank circuit output.
7. When buffering the DCO, use devices with the lowest possible
Noise Figure.
A dual-loop frequency synthesizer has been proposed for reducing the
phase noise introduced by the DCO. Simulations have shown an improvement
of 10us in the lock time and a 7dB improvement in signal-to-noise plus
distortion ratio over the DPLL-based frequency synthesizer.
It is necessary to accurately characterize the noise performance
because each of the components contributes noise which affects the system in
a non-linear fashion. Major contributors of noise are phase detector/ charge
pump and the DCO. The proposed architecture with two feedback loops has
shown to reduce the DCO phase noise in the loop.
Applications such as transceiver require the synthesizer to maintain its
phase noise and spurious tone performance in the presence of current and
voltage perturbations in both the substrate ground and supply. Fully
differential implementation of the complete synthesizer path is important for
this reason. A differential cell ring oscillator is designed for DCO to reduce the
substrate noise introduced. A differential charge pump with active loop filter
can be implemented to minimize spurious tones and to maximize the
frequency tuning range of DCO by making the synthesizer fully differential.
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In the DPLL-based frequency synthesizer the phase noise can be
reduced by using a fractional-N-divider in the feedback. Using the fractional
divider allows the use of higher reference frequencies thereby reducing the
phase noise. The integer divider in the proposed dual-loop synthesizer
architecture can be replaced by a fractional divider to suppress the phase
noise further.