Theoretical comparison between sequential redundancy addition and removal and retiming optimization...

Journal of Systems Architecture 49 (2003) 529–541

www.elsevier.com/locate/sysarc

Theoretical comparison between sequentialredundancy addition and removal and retiming

optimization techniques

Enrique San Mill�aan *, Luis Entrena, Jos�ee Alberto Espejo, Celia L�oopez

Universidad Carlos III de Madrid, Butarque 15, 28911 Legan�ees, Madrid, Spain

Abstract

This paper attempts to determine the capabilities of existing redundancy addition and removal (SRAR) techniques

for logic optimization of sequential circuits. To this purpose, we compare this method with the retiming and resynthesis

(RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG

transformations by other authors. Following these works, we first formally demonstrate that logic transformations

provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that

cannot be found by RaR. This way we prove that the sequential redundancy addition and removal technique provides

more possibilities for logic optimization.

� 2003 Published by Elsevier B.V.

Keywords: Logic synthesis; Sequential circuits; Redundancy addition and removal; Retiming

1. Introduction

Optimization of synchronous sequential circuits

is still an open and challenging problem. The

optimization can be made in two different levels of

abstraction: the state machine level and the logic

level. At the state machine level, optimization can

be achieved in different ways: through the mini-

mization of the finite state machine [16], throughstate encoding and decomposition [5–7,9]. The

limitation of the optimization at this level is that

* Corresponding author. Tel.: +34-91-6249430/6249194; fax:

+34-91-6249194.

E-mail address: [email protected] (E. San Mill�aan).

1383-7621/$ - see front matter � 2003 Published by Elsevier B.V.

doi:10.1016/j.sysarc.2003.06.002

the estimation of the area of the final circuit is notaccurate. For this reason, further optimization can

be obtained at the logic level (sequential logic

optimization) where better area estimation is pos-

sible.

Given an initial circuit description at the gate

level, sequential logic optimization aims at com-

puting an equivalent circuit with a smaller area

occupation usually estimated through the gate,connection or literal counts.

There are several approaches for sequential

logic optimization. The most extended method

consists in the separation of the flip-flops in the

circuit from the combinational part, and then

apply well-known combinational logic optimiza-

tion techniques [1,10] to the combinational part of

mail to: [email protected]

530 E. San Mill�aan et al. / Journal of Systems Architecture 49 (2003) 529–541

the circuit. The limitation of this method is that

the sequential behaviour of the circuit is not used

for optimization and therefore a better optimiza-

tion of the circuit is possible.

A second method for optimization is an

improvement of the first method by adding somesequential information to the circuit with sequen-

tial do not cares extracted from the STG [9]. The

main problem of this technique is that it has been

shown to be NP-complete in the case of completely

specified finite state machines.

Finally, the two main approaches to sequential

logic optimization are retiming and resynthesis

(RaR) [14,15] and sequential redundancy additionand removal (SRAR) [8]. Both are efficient meth-

ods and use the sequential behaviour of the circuit

for the optimization. The retiming technique con-

sists in moving the flip-flops across combinational

gates, merging combinational blocks and optimiz-

ing the resulting logic with combinational tech-

niques in a resynthesis step. This method has

become quite attractive, despite its limitations.Recently, the set of transformations that can be

provided with RaR has been formalized [11].

The redundancy addition and removal tech-

nique is based on the iterative addition and re-

moval of redundancies. This technique has

demonstrated to produce excellent results for

combinational circuits [8,18], being the major

advantages the low memory usage and the shortrun times. Sequential logic optimization is also

possible using this technique by considering

sequential redundancies [8].

In this work we compare the sequential trans-

formations that can be obtained by RaR and by

SRAR, working towards a formalization of the set

of transformations that can be obtained with the

latter technique. In particular, we demonstratethat the SRAR technique covers all the possible

optimizations that can be provided by the RaR

technique. Then we will show that SRAR is able to

optimize some typical circuit cases that cannot be

optimized by RaR. This way, we demonstrate the

superiority of the SRAR technique.

The rest of this paper is organized as follows.

Section 2 reviews the SRAR technique forsequential logic optimization. Section 3 reviews the

RaR technique and the set of transformations that

it allows to obtain. Then Section 4 demonstrates

that SRAR is able to cover all RaR transforma-

tions and Section 5 shows that there are transfor-

mations that are not possible with RaR but are

possible with SRAR. Finally, Section 6 presentsthe conclusions of this work.

2. Logic optimization by sequential redundancy

addition and removal

Redundancy addition and removal has been

shown to be a powerful logic optimization methodby several authors [4,8,13,18]. With this method,

a logic network is optimized by iteratively add-

ing and removing redundancies that are identi-

fied using Automatic Test Pattern Generation

techniques based on the implication of manda-

tory assignments. If the addition of k redundant

wires/gates creates more than k redundant wires/

gates elsewhere in the network, the removal ofthe created redundancies will result in a smaller

area.

Redundancy addition and removal is also

applicable to sequential circuits [8]. In this case,

sequential redundancies can be considered for

addition and removal. Sequential redundancies

can be identified by using the well-known time

frame model and performing the implication pro-cess across time frames. Sequential redundancy

addition may involve also the addition of flip-flops

[17] in order to temporarily expand the state set

and reduce it later on with redundancy removal.

Along with other general improvements that have

been proposed, such as using BDDs for implica-

tion [2] and multiple wire/gate addition [4], a large

set of sequential optimization transformations canbe identified.

The basic redundancy addition and removal

approach can be summarized as follows. A wire

is selected and tested for stuck-at fault. If no test

is possible, then the wire is redundant and can be

removed. Otherwise, we try to add a wire or a

gate to the circuit in order to make the target

fault redundant. Candidates for addition are alsotested for stuck-at fault in order to verify that

FF1FF2

ab

z

(b)

b / 1

(a)

a+b / 0 S0

a+ b / 1

b / 0

S1

FF1

FF2

ab

z

(c)

FF2

a b

z

(e)

FF1

FF2

ab

z

(d)

Fig. 1. Example of SRAR. (a) A two-state machine, (b) a one-hot coded implementation (S0¼ 01, S1¼ 10), (c) adding a sequentially

redundant connection do not after the behaviour of the circuit, (d) another connection in the circuit becomes now redundant, so it can

be removed, (e) the resultant equivalent circuit has one flip-flop only.

E. San Mill�aan et al. / Journal of Systems Architecture 49 (2003) 529–541 531

the addition preserves the functionality of the

circuit.

Example (taken from [8]). Fig. 1 shows the state

graph of a two-state machine and a one-hot coded

implementation of this machine. The machine has

two inputs, a and b, and one output. Since this

sequential circuit contains no redundancies, we tryfirst to add some sequential redundancy, as shown

in Fig. 1(c) with a dashed line. To prove that the

new circuit has the same functionality, we test the

stuck-at-0 fault at the new wire. These fault re-

quires that the mandatory assignments FF1¼ 1

and FF2¼ 1, i.e., the circuit must be in state 11,

which is unreachable, and therefore the connection

added is sequentially redundant. Because of theaddition of the new connection, another connec-

tion becomes redundant, as shown in Fig. 1(d).

After removing this connection and its fanins

which become floating, the circuit has only one

flip-flop and is a minimal-bit encoded machine

(Fig. 1(e)).

3. Retiming and resynthesis

3.1. Logic optimization by retiming and resynthesis

RaR [14] is a sequential optimization method

that can be applied, as redundancy addition and

removal, to optimize sequential designs described

at the logic level.

In retiming, the flip-flops are relocated acrosscombinational gates, changing the interaction

Forward (i)

Forward (iii)

Backward (ii)

Backward (iv)

Fig. 2. Primitive retiming operations.

ab

out

ab

out

outab

(a)

(b)

(c)

Fig. 3. RaR example. (a) Original circuit, (b) retimed circuit,

(c) resynthesized circuit.


between different combinational blocks, and with

the resynthesis step it allows to make logic opti-

mizations not possible by combinational methods

alone. A sequence of retiming and combinational

resynthesis steps provides the way to optimize

sequential circuits at the logic level.RaR consists on the application of a sequence

of two basic steps, synthesis and retiming, which

are described as follows:

• Synthesis: In this step the flip-flops are un-

touched and the flip-flop inputs and outputs

are treated as primary circuit inputs and out-

puts. This step provides simple combinationaloptimization alone.

• Retiming: Moves the flip-flops across combina-

tional blocks under certain rules, with the fol-

lowing effects:

(a) Change in cycle time: The delay along the

combinational path between flip-flops can

change, because those flip-flops are moved.

(b) Change in area: The number of flip-flopscan increase or decrease due to the move-

ment across combinational blocks.

(c) Change the interaction between combina-

tional blocks: This is the most important ef-

fect of retiming, as it provides the way to

further optimization of the circuit by combi-

national optimization.

(d) Changes on the state transition graph: Ret-iming may change the state transition graph

of the original circuit by changing the differ-

ent encodings of the state transition graph,

or changing the transition between states.

The possible movements of flip-flops across

combinational gates can be built from a sequence

of four primitive retiming operations, as stated inthe following lemma [11]:

Lemma. A general retiming operation can be con-structed as the sequence of retiming moves acrossprimitive transformations (i), (ii), (iii) and (iv) shownin the Fig. 2. These transformations are:

ii(i) moving flip-flops forward across a NAND gate,i(ii) moving flip-flops backward across a NAND

gate,

(iii) moving flip-flops forward across a multiple fan-out point,

(iv) moving flip-flops backward across a multiplefanout point.

An example of RaR is shown in Fig. 3. The

initial circuit has two registers and three combi-

national gates (Fig. 3(a)). The step of retiming

reduces the number of registers to one, and pro-duces the interaction between the combinational

gates (Fig. 3(b)). The next step, resynthesis, allows

a better optimization. The final circuit results in

only one register and only one gate (Fig. 3(c)).

s1s11

s12

2-way merge

2-way split

s

s11

s12

s

s11

s12

2-way switch

i1

i2

i1

i2

i2

i1

i3

i2

i1

i3

Fig. 4. State graph transformations.

s

s11

s12

s1

s s

s11

s12

2-way merge 2-way split

2-way switch

i3

i2

i1

i2

i1

i3

i2

i1

i3

Fig. 5. 2-way switch as a sequence of 2-way merge and 2-way

split.


3.2. Power of logic optimization by retiming and

resynthesis

The method of RaR has been widely studied,

and the optimization capability of these methodshave been formally established by several authors

[3,11,12,14].

The approach to establish the capabilities of the

method has been characterized by relating them to

the STG transformations. The characterization of

the relationship between RaR and STG transfor-

mations is given by the following definitions and

theorems [11,14]:

Theorem (Malik). Given a machine implementationM1, corresponding to a state transition graph G,with a state assignment S1, it is always possible toderive a machine M2 corresponding to the samestate transition graph G, and a state assignment S2

by applying only a series of resynthesis and retimingoperations on M1.

This theorem from Malik considers the case of

identical STGs with different state assignments. It

shows the encoding power of RaR. However, in

the case where the STGs of M1 and M2 are dif-

ferent, where not only a change of state assignment

is needed in the circuit, not is always possible to

derive the machine M2 from M1. The followingdefinitions and theorem show exactly when it is

possible.

Definition 1. For a given STG, two states s1 and s2

are 1-step equivalent if they have the same output

and if for all inputs i, the next state of s1 on i is the

same as the next state of s2.

Given a machine implementation M1 corre-

sponding to a state transition graph G1, and a

machine M2 corresponding to a state transition

graph G2, then G1 may be modified to obtain G2

though a series of three basic transformations.

These transformations may create states that are

equivalent to existing states, merge states that are

equivalent to existing states, and modify statetransitions to go to states equivalent to the original

destinations. The definitions of these basic trans-

formations are given below:

• 2-way split: A state s1 in G1 is split into two 1-

step equivalent states in G2 (Fig. 4).• 2-way merge: Two 1-step equivalent states s11

and s12 in G1 are merged to a single state s1

in G2 (Fig. 4).

• Switch: A transition in G1 to state s11 is modi-

fied to go to an 1-step equivalent state s12 in G2

(Fig. 4).

The 2-way split and 2-way merge constituteprimitive transformations. A 2-way switch, multi-

way splits and merges can be accomplished by a

sequence of 2-way splits and merges. In Fig. 5 it is

shown how to make a 2-way switch using a 2-way

split and a 2-way merge.

Definition 2. A transformation of an STG G1 into

another STG G2 is a 1-step equivalent transfor-mation if F2 has been obtained from G1 by either

splitting a state into 1-step equivalent states, or

merging two 1-step equivalent states, or switching

between two states that are 1-step equivalent.

Definition 3. Two STGs G1 and G2 are 1-step

equivalent if one can be obtained from other by a

sequence of 1-step equivalent transformations.

s-a-01 1

Propagation path blocked

s-a-0

1

1


1

(b)

(a)

ab

ab


Theorem. Let M1 be an implementation corres-ponding to state assignment S1 and STGG1 andM2

be an implementation corresponding to state assign-ment S2 and STG G2. Then M2 can be obtainedfrom M1 using only a sequence of RaR operations ifand only if G1 and G2 are 1-step equivalent.

The definitions and theorems shown in this

section formalize the type of transformations that

can be obtained with RaR. It shows exactly the

possible transformations provided by retiming: the

1-step equivalent transformations. Any other

transformations in a circuit, that are not 1-stepequivalent, are not possible to obtain with just

series of RaR moves.

ab

(c)

s-a-101

1


Fig. 6. Circuit of Fig. 3 optimized with SRAR. (a) Addition

step 1, (b) elimination step 1, (c) elimination step 2.

4. Possible retiming transformations with redun-

dancy addition and removal

Although redundancy addition and removaltechniques have been shown to be efficient opti-

mization techniques, the power of optimization of

these methods has not been formalized yet. In this

section we will show some of the capabilities of

these methods by comparing them with the reti-

ming methods and then showing that SRAR is

able to cover all RaR transformations.

First we will illustrate with one example thatRaR optimizations can also be obtained by

redundancy addition and removal. Consider again

the example in Fig. 3. The optimization of this

example with SRAR is described in Fig. 6.

To reach circuit in Fig. 3(c) from circuit in Fig.

3(a) the following transformations can be made:

(a) The OR gate highlighted in Fig. 6(a) is redun-dant, and thus can be added without changing

the functionality of the circuit. This redun-

dancy can be proved by taking into consider-

ation the fault stuck-at-0 shown in Fig. 6(a).

(b) The wire at the input of the second flip-flop in

Fig. 6(b) is redundant because the fault shown

in that figure is not detectable, and can be re-

moved, leading to circuit in Fig. 6(c).(c) The wire at the second input of the AND gate

in Fig. 6(c) is also redundant, so it can be re-

moved.

In the following result we will show that this

example is only a particular case, and in general,

all the optimizations available to retiming are also

available to redundancy addition and removal.

Theorem. All possible retiming transformations in acircuit can be obtained by redundancy addition andremoval transformations.

Proof. As all possible retiming transformations are

compositions of four primitive operations, we just

need to proof that each one of these primitives can

be performed by a redundancy addition and re-

moval transformation. We consider the four cases

(i), (ii), (iii) and (iv) shown in Fig. 2:(i) Moving forward two registers across a NAND

gate can be accomplished in two steps: moving firstthe inverter, and then the and gate. So we considerboth cases:

• Moving forward an and gate:

Consider the circuit in Fig. 7(a). We need tomove forward g1 across FF1. First we can add g2

FF1

FF1

FF1

FF1

FF2

FF2

FF2

g1

g2g1

g1g2

g2

s-a-1

0

0

00

s-a-1

0

0

0



(a)

(b)

(c)

(d)

Fig. 7. Moving forward an AND gate.

FF2

FF2

FF2

FF1

FF1

FF1

g

g

s-a-1

00

1

0

1

1

s-a-1

01

0

1

(a)

(b)

(c)

(d)



0

Fig. 8. Moving forward an inverter.


and FF2 as shown in Fig. 7(b) because the con-

nection between g2 and FF2 is redundant. Toshow this redundancy, consider the stuck-at-1

fault shown in Fig. 7(b). To justify the fault, FF2

needs a mandatory assignment of 0, and by

implication, g1 and FF1 have assignments of 0.

FF1¼ 0 prevents the fault propagation, and thus,

connection FF2 to g2 is redundant.

Now, by adding this redundancy to the circuit,

a new redundancy has appeared as shown in Fig.7(c). Stuck-at-1 fault shown in that figure produces

a mandatory assignment of 0 in g2, which blocks

the fault propagation. So the second input to g1 is

redundant, and by eliminating this redundancy we

get 7(d), reaching the transformed circuit we were

looking for.

• Moving forward an inverter:

Consider the circuit in Fig. 8(a). We need to

move the inverter across FF1. First we add FF2

followed by an inverter and g as shown in Fig.

8(b), because the second input of g is redundant.

To proof this redundancy, consider the fault stuck-

at-1 shown in 8(b). To justify this fault a manda-

tory assignment of 0 is needed at the output of thepreceding inverter. Now, by implication a man-

datory assignment of 0 is obtained at FF1, which

prevents the fault propagation.

Once this redundancy is added, FF1 becomes

redundant. This can be proved by taking into ac-

count the stuck-at-1 fault shown in Fig. 8(c). The

condition of justification of the fault is FF1 having

a mandatory assignment of 0. By implication, thesecond input of g gets a value of 0, which prevents

the fault propagation, and thus it is redundant.

Removing this redundancy leads to 8(d).

(ii) Moving backward a register across a NANDgate:

It can be accomplished as in (i) in two steps:

moving first the and gate and then moving the

inverter.

• Moving backward an and gate:

Starting from circuit in Fig. 9(a), transforma-

tions to reach circuit in Fig. 9(d) are the following.

FF1

FF1

FF1

FF1

FF2

FF2

FF2

g1

g2g1

g2g1

g2

s-a-10

1

0

0

s-a-1


00

00


(a)

(b)

(c)

(d)

Fig. 9. Moving backward an AND gate.

FF1

FF2

FF2

FF2

FF1

FF1

s-a0

1

0

1

1

s-a-10

01

0

1

1

(a)

(b)

(c)

(d)

Fig. 10. Moving backw


First gate g2 is added as shown in Fig. 9(b) be-

cause it is redundant. To show the redundancy,

consider the stuck-at-1 fault at the second input of

g2. This implies a mandatory assignment of 0 at

FF2, which prevents the fault propagation at g1.

By the addition of this redundant gate, nowFF2 becomes redundant: consider stuck-at-1 fault

at the output of FF2 as shown in Fig. 9(c). Then

FF2 has a mandatory assignment of 0 to activate

the fault, and by implication g2¼ 0, FF1¼ 0. FF1

having a value of 0 prevents the fault propagation

at g1, and then FF2 is redundant. Elimination of

FF2 leads to circuit in Fig. 9(d).

• Moving backward an inverter:

Starting from circuit in Fig. 10(a), the following

transformations lead to circuit in Fig. 10(d):

First, addition of g and inverted FF2 is shown to

be redundant. Consider the fault stuck-at-1 at the

first input of g, shown in Fig. 10(b). A mandatory

assignment of 0 in FF2 is needed to activate the

fault. By implication FF1 has a value of 1 and thesecond input of g has a value of 0. This input with a

value of 0 prevents the fault propagation.

Now, the addition of this logic makes the sec-

ond input of g redundant. Consider the stuck-at-1

g

g

-1

0


ard an inverter.


fault in the second input of g, shown in Fig. 10(c).

To activate the fault, an assignment of 0 is needed

at the output of the preceding inverter. By impli-

cation, FF2 has a value of 0, which prevents the

fault propagation.

(iii) Moving forward a register across a multiplefanout point:

Circuit 11(a) can be transformed into circuit

Fig. 11(d) applying the following transformations:

First, addition of g and FF2 as in Fig. 11(b) is

redundant. Consider the stuck-at-0 fault at the

second input of g. To activate the fault FF2 gets an

assignment of 1. By implication the first input of g

gets a value of 1 which prevents the fault propa-gation.

Once this logic is added, the first input of g

becomes redundant. Consider the stuck-at-0 fault

at the first input of g shown in Fig. 11(c). To

activate the fault, FF1 has an assignment of 1, and

by implication the second input of g gets an

(d)

(b)

(c)

(a)

s-a-0

11

1

1

s-a-0

11

1



FF1

FF1

FF1

FF1

FF2

FF2

FF2

g

g

Fig. 11. Moving forward a register in a multiple fanout point.

assignment of 1, which prevents the fault propa-

gation. Removing this redundant connection leads

to circuit in Fig. 11(d).

(iv) Moving backward registers across a multiplefanout point:

Circuit 12(a) can be transformed into circuit12(d) applying the following transformations:

First, addition of g as shown in Fig. 12(b) is

redundant. Consider the fault stuck-at-0 at the first

input of g. To activate the fault, FF1 has a man-

datory assignment of 1, and by implication FF2

has an assignment of 1 which prevents the fault

propagation.

Once this redundant gate is added, FF2 be-comes redundant. Consider the stuck-at-0 fault

shown in Fig. 12(c). To activate this fault, FF2

needs to have a mandatory assignment of 1.

Implicating this value, FF1 gets an assignment of

1, and prevents the fault propagation at g.

After removing FF2, circuit 12(d) is obtained.

Having proved that all the primitive retiming

transformations can be achieved by redundancy

s-a-0

1

1

1

s-a-01

1

FF1

(a)

(b)

(c)

(d)

1



FF2

FF2

FF2

FF1

FF1

FF1

g

g

Fig. 12. Moving backward registers in a multiple fanout point.


addition and removal transformations, the proof is

finished. h

This theorem shows that the optimization

power of redundancy addition and removal tech-

niques is at least the same as the one stated forretiming methods.

It is remarkable that for the proof of the theo-

rem only a subset of all the possible redundancy

additions is used. Addition of multiple wires/gates

at the same time is not needed for the proof.

As we have characterized the possible retiming

transformations by relating them to the STG

transformations, we can apply those results toredundancy addition and removal methods as

follows:

s-a-0

(a) Original Circuit

(c)

(d)

11

1

Camin

1

Fig. 13. Exam

Corollary (encoding power of redundancy addi-

tion and removal). Given a machine implementationM1, corresponding to a state transition graph G,with a state assignment S1, it is always possible toderive a machine M2 corresponding to the samestate transition graph G, and state assignment S2 byapplying only a series of redundancy addition andremoval operations on M1.

Corollary. Let M1 be an implementation corre-sponding to state assignment S1 and STG G1 andM2 be an implementation corresponding to stateassignment S2 and STG G2 such that G2 is 1-stepequivalent to G1. Then M2 can be obtained fromM1 using only a sequence of redundancy additionand removal operations.

s-a-0

(b) Equivalent Circuit

g1

1

o de propagación bloqueado

ple 5.1.

x

e

y

e

x

e

0

y

e

e

e

s-a-10

0

00 0


s-a-1

1

1

1 1x

y

(a) Original Circuit

(c)

(d)

(b) Equivalent Circuit

g1

g1

g1

g2

g2

0

Fig. 14. Example 5.2.


5. Redundancy addition and removal transforma-

tions which are not possible with retiming and

resynthesis

In the previous section we have establishedsome of the capabilities of the redundancy addi-

tion and removal methods. Now we will show that,

opposed to the retiming methods, these are not the

only possible STG transformations that these

techniques provide. In particular, we will show

some examples where optimization by RaR is not

possible, but optimization by redundancy addition

and removal is.

Example 5.1. In the example shown in the Fig. 13,

is not possible to reach circuit 13(b) from circuit

13(a) by a sequence of RaR transformations. This

result is shown in [12]. However, the redundancy

addition and removal technique can perform this

optimization. To this purpose, consider first the

addition of a redundant gate, as it is shown in Fig.13(c). To prove that this gate is redundant, we test

the stuck-at-0 fault at the second input of g1 and

obtain that the activation of this fault requires

both flip-flops assigned to 1 (state 11). The impli-

cations of the flip-flop assignment in the previous

time frame results in a conflict, leading to the

conclusion that state 11 is unreachable and the

fault is sequentially redundant.After adding gate g1, we can also prove that the

XOR gate becomes redundant. To this purpose,

consider stuck-at-0 fault at the the second input of

the XOR gate. To activate this fault, the second

flip-flop needs to have a mandatory assignment of

1, which prevents fault propagation at g1.

Example 5.2. In the example shown in the Fig. 14,is not possible to reach circuit 14(b) from circuit

14(a) by a sequence of RaR transformations. This

result is shown in [11].

As in the previous example there is a transfor-

mation of redundancy addition and removal that

can transform one circuit into the other. This

transformation consists in the following steps: the

addition of the redundant AND gate shown in Fig.14(c) makes the wire shown in Fig. 14(d) redun-

dant, and then the removal of this redundant wire

leads to circuit 14(b).

These two simple examples show that there are

more possible transformations provided by

SRAR than by RaR. The limitation of the reti-

ming operations is that flip-flops can not be

moved outside a feedback loop. This limitation

makes impossible to perform the operations nee-

ded to optimize the simple circuits in Examples5.1 and 5.2. However, the SRAR techniques do

not have this limitation, and therefore there are

more possible transformations available for opti-

mization.

6. Conclusions

Logic optimization for synchronous sequential

circuits is still an open issue. The two main ap-

proaches to sequential logic optimization are RaR

and SRAR. In this work we have compared the

sequential transformations that can be obtained

with both methods.


We have formally demonstrated that all the

possible transformations that can be obtained in a

circuit by a sequence of RaR operations can also

be obtained by a sequence of SRAR transforma-

tions. It is remarkable that for the proof of this

result only a subset of the possible transformationsprovided by SRAR is used.

We have also shown with some examples that

SRAR is able to perform transformations that

cannot be found by RaR. As there are more pos-

sible transformations provided by SRAR than by

RaR we can finally conclude that the SRAR

techniques have more potential for optimization

than the RaR methods.

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Enrique San Mill�aan received the M.Sc.degree in Mathematics at La RiojaUniversity (Spain). He is an assistantprofessor at University Carlos III ofMadrid (Spain) and currently is adoctoral student in MathematicalEngineering. His main research inter-ests include CAD tools for designautomation of digital integrated cir-cuits dealing with synthesis and verifi-cation of digital systems.

Luis Entrena received the M.E. in 1988from University of Valladolid (Spain)and the Ph.D. degree in 1995 fromPolitechnic University of Madrid.From 1990 to 1993 he was with AT&TMicroelectronics, New Jersey, USA.From 1993 to 1996 he was with TGI,Spain. Since 1996 he is Associate Pro-fessor at University Carlos III of Ma-drid, Spain. His current researchinterest include logic synthesis andtest. He is a member of IEEE.


Jos�ee Alberto Espejo obtained the de-gree in electronics engineering in 1992from Politechnic University of Ma-drid. Since 1995 he is teaching elec-tronics at University Carlos III ofMadrid where obtained the Ph.D. de-gree in 2002. Currently he is workingon logic synthesis for VLSI circuits.His research work is focused on thestudy of the application of structuraloptimization methods to FPGAs andASICs and CAD tools for digital de-sign automation.

Celia L�oopez received the IndustrialEngineering degree in 1995 and thePh.D. degree in 2000 from PolitechnicUniversity of Madrid, Spain. She iscurrently Associate Professor at Uni-versity Carlos III of Madrid, Spain.Her main research interests includeCAD tools for design automation ofdigital integrated circuits dealing withsynthesis aspects, functional validationquality metrics and fault tolerancemeasurement for RTL designs inVHDL language.

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