Symmetry within the sequence-pair representation in the context ofplacement for analog design

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 7, JULY 2000 721

Symmetry Within the Sequence-Pair Representationin the Context of Placement for Analog Design

Florin Balasa, Member, IEEE,and Koen Lampaert

Abstract—This paper addresses the problem of device-levelplacement for analog layout, focusing mainly on symmetry-relatedaspects. Different from most of the existent analog placementapproaches, employing basically simulated annealing optimizationalgorithms operating on flat (absolute) spatial representations [4],our model uses a more recent topological representation calledsequence-pair[14], which has the advantage of not being restrictedto slicing floorplan topologies. In this paper, we are explaininghow specific features essential to analog placement, as the abilityto deal with complex symmetry constraints (for instance, anarbitrary number of symmetry groups of cells), can be easilyhandled by employing the sequence-pair representation. Severalanalog examples substantiate the effectiveness of our placementtool, which is already in use in an industrial environment.

Index Terms—Analog placement, device matching, nonslicingfloorplan, sequence pair, symmetry, topological representation.

I. INTRODUCTION

I N ORDER to automatically produce analog device-level lay-outs matching in density and performance the high-quality

manual layouts, a placement tool must not only provide a goodrectangle packingfunctionality (which must be common toany placement method) but, additionally, it must include alsoanalog-specific capabilities. Such specific features are, forinstance; 1) the ability to deal with topological constraints forsymmetry and device matching; 2) the ability to arrange devicessuch that critical structures are shared in common (also knownasdevice merging) in order to reduce both layout density andinduced parasitics; and 3) the existence of a (built-in) libraryof predefined module generators and the ability to exploit theirreshaping capabilities during the placement process.

Besides these specific features of analog placement, themain goal of optimally packing arbitrarily sized modules issimilar to that of other very large scale integrated circuits(VLSI) placement problems—chip floorplanning, standardcell and macro cell digital placement. Due to the complexityof the basic problem,1 several heuristic classes of placementtechniques have been attempted.

Manuscript received August 25, 1999; revised December 9, 1999. This paperwas recommended by Associate Editor M. Sarrafzadeh.

F. Balasa is with the Univ. of Illinois at Chicago, Chicago, IL 60607 USA(e-mail: [email protected]).

K. Lampaert is with the Conexant Systems Inc., Newport Beach, CA 92660USA.

Publisher Item Identifier S 0278-0070(00)05853-X.

1The decision whether a given set of fixed-oriented rectangles, having widthsand heights real numbers, could be packed onto a chip of known width andheight was proven to be NP-complete [1] while the problem of finding a min-imum area packing is NP-hard.

A. Overview of Analog Placement Methods

The constructive placement techniques, which consist inevolving gradually the placement solution by selecting onemodule at a time and positioning it in the “best” available loca-tion, were among the first developed for VLSI layout. Severalsystems for analog placement employ constructive methods:Kayal et al. developed an expert knowledge base to guidethe placement [8]; Mehranfar suggested a schematic-drivenapproach, using a constructive scheme based on connectivityand relative positioning in the input schematic [15]. Althoughthese methods are fast, scaling well with the problem size,the results can be poor due to the order dependence, lackingof global view in dealing with a variety of interacting qualitymeasures.

Branch-and-bound placement techniques use a controlledenumeration of all possible layout configurations in the searchspace, where a lower bound of the chosen cost function isused to prune the search. The branch-and-bound algorithmseventually find the optimal solution as they explore exhaus-tively the search space. However, they are effective onlyfor problems of very small size (the manageable number ofblocks in [17] is six), as the number of visited configurationsgrows exponentially with the size of the problem. The relatedinteger linear programming (ILP) placement models [21] sufferthe same scaling drawback (see also Section VI), as mostILP packages are based on branch-and-bound approaches.Even if the placement problems are tackled hierarchically,the branch-and-bound methods are less attractive for analogdevice placement due to usually a much larger search spacethan digital problems of similar size (for instance, due to thepresence of “soft” capacitors which can be implemented in alarge number of versions).

More recently, a placement technique iteratively combiningmin-cut partitioning and force-directed placement (DLP) hasbeen employed in an interactive environment for full-custom de-signs [13].

For the time being, the simulated annealing [9] and geneticalgorithms [5] are the most effective choice for solving indus-trial analog placement problems. These algorithms use stochas-tically controlled hill-climbing to avoid local minima during theoptimization process. In addition, they do not impose severeconstraints on the size of the problems or on the mathematicalproperties of the cost function. While efficiently trading off be-tween a variety of layout factors as area, total net length, as-pect ratio, maximum chip width and/or height, cell orientation,“soft” cell shape, etc., they are very flexible—supporting in-cremental addition of new functionality, and they are relativelyeasy to implement (although good tunning needs more time).

0278–0070/00$10.00 © 2000 IEEE

722 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 7, JULY 2000

This is why simulated annealing, the most mature of the sto-chastic techniques, provided the engine for effective softwarepackages both in digital (TimberWolfSC v7.0 [20]) and analogdesign: ILAC [19], KOAN/ANAGRAM II [3], PUPPY-A [12],and LAYLA [10].

B. Absolute and Topological Representations

A simulated annealing algorithm can equally operate withtwo distinct spatial representations of placement configurations.The first is the so-calledflat or absoluterepresentation intro-duced by Jepsen and Gellat [7], where the cells are specified interms ofabsolutecoordinates on a gridless plane. The movesare simple coordinate shifts or changes in cell orientation. Cellsare allowed to overlap in possibly illegal ways,2 as no restric-tion is made referring to the relative position of a cell with re-spect to another cell. A (weighted) penalty cost term is associ-ated with infeasible overlaps, and this penalty must be driven tozero in the optimization process. The flat representation is well-suited to handle device matching and symmetry constraints, typ-ical to analog layout; it also allows to explore the beneficialdevice overlaps. For these reasons, the flat representation wasthe choice for KOAN/ANAGRAM II [3], PUPPY-A [12], andLAYLA [10] systems.

However, this representation has also revealed a drawback,for instance, in [20]. Due to the complexity of the cost func-tion, the total (infeasible) overlap in the final placement solu-tion is not necessarily equal to zero: a final step eliminatingthe gaps and overlaps must be performed, degrading the com-putation time and the solution optimality (in terms of the costfunction). Moreover, the weight of the overlap term must becarefully chosen: if it is too small, the cells may have the ten-dency to collapse; if it is too large, the search ability of the an-nealer for a good placement (in terms of area, total net length,etc.) may be impeded. To combat this effect, an earlier versionof the TimberWolf system [20] used a sophisticated negativecontrol scheme to determine the optimum values of the costterm weights.

The flat representation approach trades off a larger numberof annealing moves for easier and quicker to build layout con-figurations—which may not be always physically realizable,though. On the other hand, a second class of placement repre-sentations—namedtopological—allows trading off more com-plex, physically correct, layout constructions per each annealingmove for a smaller number of moves.

In contrast to the flat representation where cell positions aredefined in terms of absolute coordinates, in the topologicalrepresentations cell positions are specifiedrelatively, basedon topological relations. The most popular representationsare based on the slicing model, first introduced by Otten[18], assuming the cells are organized in a set of slices whichrecursively bisect the layout horizontally and vertically. Thedirection and nesting of the slices is recorded in aslicing treeor, equivalently, in anormalized Polish expression[22]. Theannealing algorithm does not move the cells explicitly: it ratheralters their relative positions, modifying the slicing tree or

2In analog layout, cells can overlap not only inlegalbut alsobeneficialways(“device merging” or “geometry sharing” [3]).

Polish expression. In this representation, cells cannot overlap,which may lead to an improved efficiency in the placementoptimization.

However, the slicing representation limits the set of reach-able layout topologies. This can degrade layout density, espe-cially when cells may be very different in size, which is oftenthe case in analog layout. Furthermore, symmetry and matchingconstraints are difficult to maintain: for instance, slicing styleplacement tools have to implement symmetry constraints in thecost function through the use of virtual symmetry axes [11],which is a less efficient solution. Although the ILAC system[19] employs this model, it is widely acknowledged that slicingplacement is not a good choice for high-performance analog de-sign.

More recently, several novel topological representations,not restricted to slicing floorplan topologies, have beenproposed. Murataet al. suggested to encode the “left-right”and “up-down” positioning relations between cells usingtwo sequences of cell permutations, namedsequence-pair[14]. Nakatakeet al.devised a meta-grid structure (calledbounded-sliceline grid(BSG) without physical dimensionsto define orthogonal relations between modules [16]. Veryrecently, Guoet al. proposed theordered tree(O-tree) datastructure to reduce the drawback of redundancies in the twoprevious representations [6].

The goal of our paper is to show that sequence-pair—themost popular nonslicing topological representation—is ade-quate for high-performance analog layout, as symmetry anddevice matching constraints can be easily handled. In thisway, the superior efficiency of the topological representationsis combined with the completeness of the search space ofplacement configurations and the ability to handle typicalanalog constraints. The results obtained so far with ourplacement tool, already active in an industrial environment,will substantiate the validity of these claims. The analogexamples shown in [2] contain only one symmetry group ofcells; this paper displays a complex frequency divider withselectable ratio having five symmetry groups. In addition, acomplete proof of the theoretical computation of the solutionspace size is also included.

This paper is organized as follows. Section II will brieflydescribe the sequence-pair representation. Section III will ex-plain the nature of the symmetry constraints in analog design,while Section IV will thoroughly analyze the symmetry han-dling during simulated annealing, when this optimization oper-ates on sequence-pair representations. Section V briefly reviewsthe device-matching constraints and Section VI proves the ef-fectiveness of our analog placement solution. Then, Section VIIconcludes with final remarks, while the Appendix presents athorough evaluation of the solution space size for placementproblems with symmetry constraints.

II. THE SEQUENCE-PAIR REPRESENTATION

The basic idea of the sequence-pair representation, brieflydescribed below for the sake of consistency, is to encodeany rectangle packing as an ordered pair of cell sequences

. In [14], a method of deriving such an encoding is

BALASA AND LAMPAERT: SYMMETRY WITHIN THE SEQUENCE-PAIR REPRESENTATION 723

Fig. 1. Placement configuration encoded by the sequence-pair(CDAFBGE;DCBGAFE).

informally described.3 In particular, there exists at least asequence-pair encoding corresponding to (one of) the optimalrectangle packing.4 In addition, all the encodings are feasiblein the sense that a placement configuration can be derivedfrom any encoding; moreover, the solution is optimal in termsof area and it can be constructed in time, whereis the number of placeable cells. As the total number ofencodings is finite although large5 , the solution space can beeffectively explored employing simulated annealing or geneticalgorithms.

Denoting by the cell occupying the positionin sequence, and by the position of the cell in the sequence,6 the

topological relations between two cellsand are given bythe following:

if and then cell is to the left ofcell ; (T)

if and then cell is above cell .Example: The sequence-pair encoding of the seven- cell

placement configuration in Fig. 1 is(see Section IV). With the notations em-

ployed, we have, for instance, , and also,, etc. As and (

and ), it follows that cell is positioned above cell .Murataet al.have conceived the sequence-pair representation

as a general rectangle packing method [14]. In order to apply thistopological representation to analog placement, handling sym-metry is an essential requirement. Section IV will show how tohandle the symmetry constraints within the sequence-pair topo-logical representation.

III. SYMMETRY CONSTRAINTS IN ANALOG LAYOUT

In high-performance analog circuits, it is often required thatgroups of devices are placed symmetrically with respect to oneor several (vertical) axes. The main reason of symmetric place-ment and routing is to match the layout-induced parasitics in

3A procedure which builds the encoding(�; �) from the configuration ofm placeable cells inO(m ) time is also given in Section IV.

4This property is not valid for the normalized Polish expressions [22] en-coding the slicing structures, as the optimal (in terms of area) packing maynot have a slicing topology.

5The search space form fixed-oriented “hard” cells has the size(m!) .If the cells can be rotated, or rotated and mirrored, the size is(m!) 4 or(m!) 8 , respectively.

6� and� are one-to-one mappings and, therefore, the inverse mappings arewell defined.

Fig. 2. Schematic of a high-speed CMOS comparator.

the two halves of a group of devices. Failure to match theseparasitics in, for instance, differential analog circuits can leadto higher offset voltages and degraded power-supply rejectionratio [4].

Placement symmetry can also be used to reduce the circuitsensitivity to thermal gradients. Failure to adequately balancethermal couplings in a differential circuit can even introduceunwanted oscillations. In order to combat potentially inducedmismatches, the thermally sensitive device couples should beplaced symmetrically relative to the thermally radiating devices.The typical forms of symmetry which should be handled by ananalog placement tool are as follows [4]:

1) mirror symmetry—which consists in placing a symmetrygroup of cells about a common axis such that the cells inevery pair have identical geometry and mirror-symmetricorientation;

2) perfect symmetry—which differs from the previous bythe identical (rather than mirror-symmetric) orientationsof the paired devices. This type of symmetry is sometimesrequired in order to meet very stringent matching require-ments;

3) self-symmetry—characteristic for devices presenting ageometrical symmetry and sharing the same axis withother pairs of symmetric devices.

A subset of cells is called asymmetry groupif all cells areexhibiting a form of symmetry and, in addition, they all share acommon symmetry axis.

Usually, the analog circuits have a mix of symmetric andasymmetric components. Fig. 2 shows the schematic of a high-speed CMOS comparator, circuit used in a CMOS A/D con-verter. This comparator converts a differential input signal intoa single-ended output value. Therefore, the input stage is sym-metric while the single-ended output stage introduces an asym-metric part.

IV. HANDLING SYMMETRY CONSTRAINTS WITH THE

SEQUENCE-PAIR REPRESENTATION

Assuming that a given subset of the placeable cells mustconstitute a symmetry group, not all the sequence-pair codesare feasible any more. For instance, suppose the cell couple

in the Section II example should be symmetric relativeto a vertical axis: the encoding


is not feasible as it leads to a placement config-uration where cell lays above .

At a first glance, one would be tempted to perform minorchanges to the search space exploration: if the current encodingproves to be consistent with the symmetry constraints then thecost of the placement configuration is evaluated and the an-nealing algorithm operates normally; otherwise, the current en-coding is infeasible (in symmetry point of view) and, there-fore, disregarded. Unfortunately, such a simple solution is noteffective: taking into account that the size of the search spacewithout symmetry constraints is (the total number of se-quence-pairs), the size of the solution space becomes signifi-cantly smaller if the placement configuration must contain asymmetry group. Indeed, the size of this new search space isgiven by the formula (see Appendix for a proof)

(1)

where is the number of symmetric pairs, andis the numberof self-symmetric cells in the group.

Formula (1) shows that the size of the search space isif . Therefore, when there are only

two pairs of symmetric cells more than 95.83% of the fullsequence-pair search space contains symmetric-infeasiblesolutions. This has been confirmed experimentally when tryingto place the cells in Fig. 1 such that the pairs of cells and

are, respectively, symmetric relative to a common axis:the CPU time was several times higher and, in addition, thefinal solution was poor because the number of feasible codesinvestigated during the simulated annealing was insufficient(most of the codes being rejected).

A better strategy is to exploreonly those sequence-pairswhich comply with the symmetry constraints. This sectionwill show 1) how to recognize such sequence-pairs and 2)how to efficiently restrict the annealer exploration only to theirsubspace.

Let be the sequence-pair of a placement configurationcontaining a symmetry group composed of several pairs of(mirrored/perfect) symmetric cells and self-symmetric cells rel-ative to a common vertical axis.7 We denote by the sym-metric of cell , and we consider by convention that

when is a self-symmetric cell.Definition: The sequence-pair is called symmetric-

feasibleif

cells in

Choosing and taking into account that, condition shows that any symmetric

pair of cells appears in the same order in both sequencesand

cells in

7The case of multiple symmetry groups can be similarly approached, as it willbe shown further.

Fig. 3. Placement configuration with symmetry group = ((C;D);(B;G); A; F ).

According to condition of symmetric-feasibility, two cellsbelonging to distinct symmetric pairs and, respectively,

their symmetric cells appear in reversed order in the twosequences of the encoding. In addition, any two self-symmetriccells appear in reversed order in the sequencesand , as itcan be easily seen taking and in .

Example (Continued):Assumming there is a symmetrygroup composed of two symmetricpairs and two self-symmetric cells and , the encoding

(see Fig. 1) is notsymmetric-feasible: for instance, the symmetric cellsanddo not satisfy condition as they do not appear in the sameorder in the sequencesand ( , but ).

On the other hand, the encoding, derived from the placement configuration in

Fig. 3, is symmetric-feasible. Taking, for instance, the self-sym-metric cell and comparing its positions and in thesequences and, respectively, to the corresponding positionsof the other cells in the symmetry group, it may be concluded,from the pairs of valid inequalities

, thatcondition is satisfied whenever cell is involved. Similarcomparisons involving the positions of the other cells inwillconclude the verification.8

The following two lemmas will prove that, in order to find acell packing of minimum area, containing a symmetry group ofcells, it is sufficient to explore the subspace ofsymmetric-fea-siblesequence-pairs, rather than the entire sequence-pair space,which is significantly larger (as mentioned above, e.g., 24 timeslarger for only two pairs of symmetric cells).

Lemma 1: Any placement configuration containing asymmetry group can be encoded with a symmetric-feasiblesequence-pair.

Proof: According to [14], any placement configurationcan be encoded with a sequence-pair. In particular, this is truealso for those configurations containing symmetry groups.

The procedure described below is similar to theGriddingen-coding in [14]. However,ConstructSequenceAlphaavoids theambiguity of theGriddingencoding by providing priority to thehorizontal relation. In addition, the resulting sequence-pair has

8Checking the symmetric-feasibility of a given sequence-pair is not a neces-sary operation in the context of our placement method. As it will be explained inmore detail toward the end of Section IV, constructing an initial symmetric-fea-sible sequence-pair and performing only transformations which preserve thesymmetric-feasibility entail an efficient exploration of placement configurationssatisfying the given symmetry constraints.


the property when the procedure is applied to a placementconfiguration with a symmetry group.

sequence procedure ConstructSequenceAlpha (set of fixed,

nonoverlapping cells)

a similar procedure ConstructSequenceBeta builds

sequence (differences are notified)

sequence (resp. ) is initially zeroed;

for to is the current position in the

sequence

let be any cell which is not yet in the sequence

(resp., );

for (every cell not in the sequence) looking

for a candidate for position

if the horizontal projections of cells and are

overlapping

then if cell is above (resp., below) cell then

*

else if cell is to the left of cell then **

(resp., ) (resp., )

return sequence (resp., );

First, it must be noticed that the topological relationsspecific to the sequence-pair representation (see Section II) aresatisfied due to lines (*) and (**). In particular, for a pair ofsymmetric cells being placed to the left of, the rou-tinesConstructSequenceAlphaandBetayield, due to line (**),a sequence-pair where and, respectively,

. Therefore, cells and satisfy condition .It can be verified by analyzing all the possible relative po-

sitions between two pairs of symmetric cells that the encodinggenerated by the procedures described above satisfies condition

. For the sake of clarity, the pairs and in theexample from Fig. 3 will be considered. There are two cases ofrelative positions of the two pairs (less the possible cell inter-changes within the same pair, or interchanges between pairs) asfollows.

1) The pair lies between cells and , as shownin Fig. 3. Due to line (**), the proceduresConstructSe-quenceAlphaand Beta generate a sequence-pairsuch that

and

2) The pair lies below the pair , such that thehorizontal projections of cells and and, respectively,

and , are overlapping. Due to line (*) in the proce-dures, and

. In addition, due to line (**)

and

The two inequalities above and their equivalent ones obtainedby interchange operations show that any two cells in the subset

satisfy condition .The relative positions between two self-symmetric cells, or

between one symmetric pair and one self-symmetric cell, maybe similarly analyzed: in all cases, condition is satisfied forevery two cells in the symmetry group.

Example (Continued):Applying the encoding procedure tothe illustrative placement configurations in Fig. 1 and Fig. 3, thesequence-pairs and,respectively, are ob-tained. The latter encoding is symmetric-feasible, as alreadyshown.

Lemma 1 shows that there is at least one symmetric-feasiblesequence-pair corresponding to a placement configuration witha symmetry group, optimal in terms of a cost function (for in-stance, area).

Lemma 2: Given a set of placeable cells containing a sym-metry group and a symmetric-feasible sequence-pair, then onecan build in polynomial time an optimal placement configura-tion (in terms of area) satisfying the positioning and symmetryconstraints.

Proof: Denoting the coordinates of the left-bottomcorner of cell of width and height

, and given a symmetric-feasible sequence-pair , aconstruction with the properties stated inLemma 2is describedbelow.

First, the coordinates of the cells are computed such thatthe positioning constraints (compatible with the given sequence-pair) are satisfied

initialize symmetryAxis

computation of the coordinates

for to

choose cell having the position in sequence

for to

for all cells positioned after in sequence

if if cell is positioned after also in

sequence

then then is to the right of

cell

if cell has a symmetric cell such that

if cell has a symmetric which is to its left (thus,

is known), or it is self-symmetric

then symmetryAxis symmetryAxis max ;

This part of the algorithm determines in time thecoordinates of the cells such that the horizontal positioning con-straints resulting from the sequence-pair are satisfied. Inthe absence of a symmetry group, the computation of theco-ordinates is over; otherwise (symmetryAxis ), the coor-dinates must be trimmed in order to satisfy also the conditions


of symmetry. This is done in two steps: first, a “sweep to theright” which finds the final positions for the cells to the right ofthe symmetry axis, including the self-symmetric ones; second,a “sweep to the left” which determines thepositions of thecells to the left of the symmetry axis.

for to the sweep to the right



then

if cell has a symmetric which is to its left, find

the potential displacement for

symmetryAxis *

if then if is self-symmetric, the dis-

placement is only half

if then

push cell to the right (**)

for to

all cells to the right of

if then are equally pushed to

the right

for downto 1 the sweep to the left



then

if cell has a symmetric which is to its right,

find the potential displacement for

symmetryAxis *

if then displacement indeed

push cell to the left **

for to

all cells to the left of

if then are equally pushed

to the left

It must be noticed that the symmetric-feasibility conditionis sufficient in order to ensure the correct-positioning afteronly two sweeps—one to the right and one to the left. If thesequence-pair does not satisfy the condition, itcould happen that two pairs of symmetric cellsand may prevent each other from being simul-taneously symmetric about the axis if, for instance,ispushing to the right when achieving the symmetry of thefirst pair, and afterwards is pushing to the leftachieving the symmetry of but destroying againthe symmetry of . Moreover, the complexity ofthe algorithm is still , the same as in the absence ofany symmetry constraint.

Finally, the coordinates of the cells are computed such thatthe positioning constraints (compatible with the given sequence-pair) are satisfied.

initialize computation of the coor-

dinates

for downto 1


for downto 1

for all cells positioned before

in sequence

if then if cell is positioned after

in sequence

then is above cell

if cell has a symmetric cell then

***

In order to prove the statement ofLemma 2, it must be shownthat the construction described above yields avalid placementconfiguration (i.e., cells do not overlap), satisfying the posi-tioning constraints specific to the given sequence-pair,and verifying also the conditions of symmetry; in addition, theresulting placement has minimum width and minimum heightsubject to the topological and symmetry constraints.

During the “computation of coordinates”, we have(as ). If, in addition, then cell will

be placed to the right of, as : these cellsdo not overlap. The “sweep to the right” will not alter thissituation: when a cell is pushed to the right, all the cellssuch that and are equally displacedto the right. The “sweep to the left” preserves the left-rightrelations as well.

During the “computation of coordinates”, we have(as ). If, in addition, then cell will be

positioned above, as : neither these cellsdo overlap. As any two cellsand appear in the sequencesand either in the same order or inreversed order , at least one of therelation types holds. Itfollows that no overlap occurs in the resulting placement config-uration; moreover, the topological constraints derived fromthe given sequence-pair are satisfied.

Due to lines (*) and (**), together with (***), for any pairof symmetric cells , cell is pushed in order to make itsatisfy the symmetry conditions symmetryAxis

and . (For self-symmetric cells ,the symmetry condition is symmetryAxis .)As explained earlier, when the value of is trimmed inorder to satisfy the symmetry constraints, no alteration ofthe previously trimmed coordinates can occur due to thesymmetric-feasibility of the given sequence-pair. It followsthat the resulting placement configuration satisfy also thesymmetry constraints.


Finally, it must be shown that the resulting placement con-figuration has minimum width and height, while satisfying theconstraints.

Suppose for the time being that there are no symmetry con-straints and let us construct the horizontal- and vertical-con-straint graphs and as described in [14]. These are twovertex-weighted directed acyclic graphs, having asourceanda sink, and nodes labeled with the cell names. In , thearcs represent the left-right relations between cells, while thevertex-weights are the cell widths; in the arcs representtop-down relations between cells, and the vertex-weights are thecell heights (the weights ofsourceandsinkbeing zero). It mustbe noticed that the first part of the construction algorithm (“com-putation of coordinates”) determines in fact the longest pathlengths (denoted ) from sourceto the nodes in . Simi-larly, the “computation of coordinates” determines the longestpath lengths (denoted ) from sourceto the vertices in .Due to the absence of symmetry constraints, the “sweep to theright/left” operations are not taking place.

The width and the height of the placement configuration re-sult to be the longest path lengths betweensourceandsink in

and, respectively, in . The width and height have in-dependently minimum values (relative to the positioning con-straints derived from the sequence-pair): lesser values wouldimply violations of positioning constraints in and/or .

In the presence of a symmetry group, the constraint graphswill be modified in order to encompass the additional symmetryconstraints. Let be two nodes corresponding to symmetriccells. Then, for every arc in , an additional arcmust be added (unless it already exists), and vice versa. In thisway, the longest paths from thesourceof to and to willhave same lengths .

At the same time, an extra node of zero weight, corre-sponding to the symmetry axis, along with the new arcsand for every pair of symmetric cells are addedto . The first part of the construction algorithm determinesas before the longest path lengthsfrom thesourceof toevery vertex . (symmetryAxiswill be the length of the longestpath to node .) Afterwards, in topological order, for everycell having a symmetric cell to the left, wheneversymmetryAxis symmetryAxis (i.e.,

in “sweep to the right”), the arc is replaced by anadditional node of weight equal to , and the arcsand . The longest path lengths from thesourceto the de-scendents of in are also updated in topological order. Asimilar operation, but in reversed topological order, has to bedone for every cell having a symmetric cell to the right, newnodes being added betweenand in order to compensatethe symmetry violations.9

In the modified graphs and , which model both thetopological and symmetry constraints, and still representthe longest path lengths in and from the respectivesource to node . The width and height of the placementconfiguration are still the longest path lengths between the

9If the weights of the “compensation” nodesj ; k are chosen larger withthe same amount for any pair of symmetric cells(j; k), the topological andsymmetry constraints will still be satisfied: the width of the placement will resultlarger, though.

sourceand sink in the two constraint graphs. Due to similararguments, they have minimum values subject to both typesof constraints.

The two lemma’s presented above show that, in order to findan optimal cell packing containing a symmetry group, it is notnecessary to explore the entire space of sequence-pairs; itsuffices to explore the significantly smaller space ofsymmetric-feasiblesequence-pairs.

The annealing algorithm can be easily adapted to explorethe space of symmetric-feasible sequence-pairs taking the fol-lowing caveats.

1) The initial sequence-pair must be symmetric-feasible.Such a sequence-pair is, for instance

where are the pairs of symmetriccells and are the self-symmetric cells.10

The initial sequence-pair can be built in different ways:our tests show that the choice is irrelevant with respect toCPU time and the quality of the final solution.

2) The move-set of the annealer must be selected such thatthe property of symmetric-feasibility is preserved for allthe visited sequence-pairs. The modifications of cell posi-tions or cell interchanges in sequenceand/or are validmoves for the cells outside the symmetry group. How-ever, if two cells from distinct symmetric couples are in-terchanged in sequence, then their symmetric counter-parts must be also interchanged in sequence.

The requirement of several symmetry groups—that is, groupsof cells having distinct symmetry axes—can be modeled in asimilar way: the cells within every group must comply with the

condition; in addition, the construction of the placement so-lution from a given sequence-pair must be refined, along withthe move-set of the annealing algorithm. This extension is quitestraightforward and it will be subsequently exemplified in Sec-tion VI (Fig. 7).

The symmetry about a horizontal symmetry axis can beequally modeled starting from the modified condition

cells in

and inverting the construction of theand coordinates pre-sented in the proof ofLemma 2. Actually, the last remarks leadto the conclusion that, within the sequence-pair representation,one can model symmetry relative to any number of vertical andhorizontal axes.

V. HANDLING DEVICE-MATCHING CONSTRAINTS

The degree to which the electrical properties of identicallyspecified components fail to match can often limit the circuitperformance in analog design. Device mismatches are due both

10This sequence-pair corresponds to a configuration where the pairs of sym-metric cells are disposed in line, like several embedded brackets, surroundingthe self-symmetric cells which are disposed one on the top of the other.


to random events in the manufacturing process—leading tosmall unpredictable variations in the electrical characteristicsof devices—and to dissimilar geometrical choices for matchingdevices during the design process.

The latter systematically induced mismatches are handledduring placement. For instance, in order to reduce the degreeof electrical mismatch due to area effects, matching groupsof cells can be defined, all members being constrained to thesame orientation and device variant. The matching groups arehandled as constraints at the move-set level of the annealer[15], [3], [10].

In addition, device proximity constraints which offer the de-signer the possibility to specify devices to be placed in closeproximity are modeled both with an imaginary proximity netof a relatively high weight, similar to the method employed byother layout systems (e.g., [3]), and also restricting the move-setby keeping together the cells in the matching group in the se-quences and .

The device separation constraints which allow the designer tospecify a maximum separation distance between pairs of criti-cally matched devices are modeled with a penalty quadratic termin the annealer’s cost function. Performance constraints speci-fying the maximum capacitance of certain critical nets are han-dled similarly.

In addition to handling matching constraints, the shape opti-mization of parametric cells with a discrete number of possibleimplementations [10] and of “soft” cells—with the aspect ratiovarying continuously between given limits—is also performedduring placement.

VI. OVERVIEW OF THE MAIN RESULTS

The placement tool is currently implemented in Main-sail—object-oriented language which is a trademark of Xidak,Inc. The tool is embedded in ROSE, an in-house retargetableobject symbolic environment for layout design, which is in usefor industrial purpose and is available on HP UX and SunOSplatforms. The results presented below have been obtained onan HP 9000/777 workstation.

The simple illustrative example in Fig. 3 has been processedby our tool in 4 s. In contrast, the same example with only sevencells was processed in over 15 min by an ILP-based placer, im-plementing for testing purpose the analytic model described in[21]. This result shows clearly that the branch-and-bound andrelated ILP-based techniques are ineffective (unless the numberof blocks on each hierarchical level is at most six [17], which isnot common).

Fig. 4 shows a more realistic example which allows to eval-uate the packing capability of the placement tool. The 116-blockexample represents a frequency divider with selectable ratio(two or four). Without specifying any symmetry constraint, theplacement has been performed in 50 min. This example is rele-vant due to the fact that analog circuits seldom contain more than100 cells per hierarchical level. The placement of analog cells isvery demanding not because of their size, but due to the charac-teristics and constraints explained in the previous sections, likesymmetry, existence of “soft” cells, device matching.

Fig. 4. Placement for a frequency divider with selectable ratio (no symmetryconstraints).

Fig. 5 shows the final layout of a gain-boost amplifier con-taining several self-symmetric and pairs of symmetric devices.As already mentioned, Murata’s rectangle packing algorithmbased on sequence-pair [14] cannot handle directly this exampledue to the symmetry constraints.

Fig. 6 shows a telescopic opamp with gain-boost amplifiers(one of which is displayed in Fig. 5). The placement has beenperformed in 7.8 min. Although the theoretical complexity isnot affected, the symmetry constraints increase the computa-tion time as they affect the construction of the placement con-figuration corresponding to a sequence-pair encoding (see Sec-tion IV). Without any symmetry constraint, the placement forthe 36 cell telescopic opamp took only 3.2 min and the area wasabout 15% smaller.

Finally, the frequency divider—which placement hadbeen initially performed without symmetry constraints (seeFig. 4)—was processed once again, the second time derivingthe five symmetry groups of cells specified in the attribute sec-tion of the netlist. This time the placement took (as expected!)longer (68 min) and the area was about 26.7% larger. The final


Fig. 5. Final layout of a gain-boost amplifier.

Fig. 6. Placement for a telescopic opamp with gain-boost amplifiers.

solution—displayed in Fig. 7—clearly proves the ability of theplacement tool to deal simultaneously with several symmetrygroups.

Table I displays the results obtained for several benchmarkanalog circuits. The computation time is dependent not onlyon the circuit size and on the number and type of constraints,but also on the schedule employed during the simulated an-nealing. This is why comparative time evaluations with otherannealing-based placement techniques are somewhat difficult tomake.11 However, because of the schedule similitude, we canreport that our experiments indicate a better speed performanceby a factor of 1.2–1.4 compared to the analog placement tooldescribed in [10] which operates on flat Gellat-Jepsen spatial

11Murata et al. reported three results [14]: theami49 example (from theMCNC benchmark) processed in 31.36 min; a 146 cell example solved in 29.9min, and a large example containing 500 blocks processed in 18.83 h. Noconstraints (like symmetry or device matching) are mentioned for any of thoseexamples.

representations [7]. Due to the good capability in handling sym-metry, device alignment and matching, the sequence-pair repre-sentation proves to be very effective for device-level placementof analog circuits.

VII. CONCLUSION

This paper has addressed the problem of device-level place-ment for analog layout. Different from most of the existent toolsbased on a simulated annealing algorithm employing flat, ab-solute representations, this paper has advocated the use of se-quence-pair, a topological representation not restricted to slicingstructures. Handling of symmetry constraints, essential require-ment for any analog placement method, has been thoroughlystudied in the context of the sequence-pair representation. Theeffectiveness of our placement tool, already employed in an in-dustrial environment, has been demonstrated by typical exam-ples from analog design.


Fig. 7. Placement for a frequency divider with selectable ratio (five symmetry groups).

TABLE IPLACEMENT RESULTS

The solutions of the designs marked with * are displayed.

APPENDIX

If the number of sequence-pairs for placeable cells is, the number ofsymmetric-feasiblesequence-pairs (there-

fore, the size of the search space in the presence of symmetryconstraints) is given by the following:

Lemma: The number of symmetric-feasible sequence-pairscorresponding to a placement configuration withcells andsymmetry groups, each containing pairs of symmetric cellsand self-symmetric cells , is given by theformula

(2)

where each factor —denoting the contribution of thesymmetry group —is equal to .

Proof: We may assume without any lack of generality thatthe number of symmetry groups is . This is possible dueto the fact that the contributions of the asymmetric componentof the circuit and those of each of the symmetry groups are inde-pendent and, therefore, the total number of symmetric-feasiblesequence-pairs is the product of these contributions. Then, wemay consider the simplified formula (1) to be proven.

The contribution of the asymmetric part (havingcells) of the circuit is as there are

sets of positions in sequence(and the same numberin sequence ) for the cells, and there are also

possibilities of assigning these cells to the selectedpositions in both sequences. It may be noticed that when thereare no symmetry constraints , the contributionresults to be , which is the total number of sequence-pairs.

When the symmetry group containspairs of symmetriccells , and self-symmetric cells


, the set of symmetric-feasible sequence-pairsmay be constructed recurrently as the union of

the following sets:

1) ;2) .

where are the symmetric-feasible sequence-pairsgenerated by all the cells in the symmetry group exceptin

and except in ; similarly, are the sym-metric-feasible sequence-pairs generated by all the pairs of sym-metric cells and all the self-symmetric cells except.

It follows that

where is a permutation and is the reverse permuta-tion of . (Example: .

Therefore, the number of symmetric-feasible sequence-pairsis equal to the number of permutations

, and the lemma is proven.Example (Continued):Given the example in Fig. 3 having

the symmetry group , the numberof symmetric-feasible sequence-pairs is

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Florin Balasa (S’93–M’95) received the M.Sc.and Ph.D. degrees in computer science from thePolytechnical University of Bucharest, Bucharest,Romania, in 1981 and 1994, respectively. Hereceived the M.Sc. degree in mathematics fromthe University of Bucharest in 1990 and the Ph.D.degree in electrical engineering from the KatholiekeUniversiteit Leuven, Leuven, Belgium, in 1995.

He is currently an Assistant Professor of ElectricalEngineering and Computer Science at the Universityof Illinois, Chicago. He worked over seven years at

the R&D Institute for Electronic Components, Bucharest, Romania. From 1990to 1995, he worked at the VLSI System Design Methodology division, the In-teruniversity Microelectronics Center (IMEC), Leuven, Belgium. In the fall of1995, he joined as a Senior Design Automation Engineer the Advanced Tech-nology division, Conexant Systems (former Rockwell Semiconductor Systems),Newport Beach, CA. He was also a Lecturer at the University of California,Irvine. He coauthoredCustom Memory Management Methodology: Explorationof Memory Organization for Embedded Multimedia System Design(Norwell,MA: Kluwer Academic, 1998). His research interests include high-level syn-thesis, physical design, combinatorial optimization and mathematical program-ming.

Koen Lampaert was born in Roeselare, Belgium, in 1968. He received theM.Sc. and Ph.D. degrees in electrical engineering from the Katholieke Univer-siteit Leuven, Belgium, in 1992 and 1998, respectively.

From 1992–1996, he was a Research Assistant with the ESAT-MICAS lab-oratories of the Katholieke Universiteit Leuven, Leuven, Belgium, working inthe field of analog design automation. Since 1996, he is working for ConexantSystems Inc., Newport Beach, CA, where he is responsible for physical designof analog, radio-frequency and high-performance digital integrated circuits. Hehas authored or coauthored one book and more than 20 papers in edited books,international journals, and conference proceedings.

Symmetry within the sequence-pair representation in the context ofplacement for analog design

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