2014 International Conference on Reliability, Optimization and Information Technology -

ICROIT 2014, India, Feb 6-8 2014

Simulation of Energy Eficient Bi-directional Visitor Counting Machine on FPGA

S. M. Mohaiminul Islam, Md. Mahbub-E-Noor, S. M. Tanvir Siddiquee, T Das, T Kumar, K Gaurav, B Pandey Deparment of Computer Science

South Asian University New Delhi, India

safunohmmadm@gmail.com, mahbub060 1001@gmail.com, tanvirhstu@gmail.com

Abstract- In this paper we are presenting result of simulation based energy eicient bi-directional visitor counting machine VC) on FPGA(Field Programmable Gate Array). In this work, we have used Xii in x sotware. We have used different lOs standards that include HSTL_I, HSTL_II, HSTL_I_18, HSTL_II_18, LVCMOSI2, LVC MOSI5, LVCMOSI8, LVCMOS25, and LVCMOS33. For these lOs standard we have collected the total energy dissipation for this bi-directional VCM on FPGA and compared them. It is observed that at 5GHz frequency HSTL_II is the lowest energy dissipation for this Bi­directional Visitor Counting Machine (VCM) on FPGA. FPGA is more effective than using any microcontroller in perspective of energy eiciency.

Keywords- Simulation, Energy Eicient, Bi-directional, Visitor Counting Machine VC), I/O Standard, HSTL, LVCMOS.

I. INTRODUCTION Norder to reduce the overall energy dissipation of Bi­

Directional VCM ( Visitor Counter Machine), we are using different lOs standards such as HSTL _I, HSTL _II, HSTL _1_18, HSTL _11_18 at diferent requencies, like 5GHz, 25GHz, 125GHz, 625GHz, 1 THz. HSTL means High-Speed ransceiver logic, is a technology independent standard for signaling between integrated circuits or IC For this nominal signal range is OV to 1.5. It is designed for operation beyond 180 MHz. HSTL_I means High Speed ransceiver logic, Class I (un­terminated or symmetrically parallel terminated), HSTL_II refers to High Speed transceiver logic, Class II (series terminated), HSTL_I_18 means High Speed transceiver logic Class I , and 18 represents operating voltage is 1.8Volt, HSTL _11_18 coresponds to High Speed transceiver logic Class II , and 18 represents operating voltage is 1.8Volt.

8iDirectionaiVisitorCounterMachine .. 1II c LK a (; 2 : 0 )

RES ET w

i.. .. BiDirectionalVisitorCounterMachine

Fig. I.Block diagram of Bi-directional Visitor Counter Machine

Here Bi-directional VCM will give 3 bits output which is QO, Qland Q2. Bi-directional VCM have three inputs: one is CLK

978-1-4799-2995-5/14/$31.0 0©20 14 IEEE 466

means clock input, another is RESET input which will give the opportunity to reset the program and last input is w, which will connect with the sensor device like Inrared sensors (IR) . That means depending on the changes of IR sensors values it will count the visitors. Starting rom 0, VCM can count 7 entities and ater that it will reset and start rom O.

II. LITEATURE REVIEW In previous section we have implemented Bi-directional

Visitor Counting Machine in PIC16F887 Microcontroller in our South Asian University, New Delhi, India. We have used IR sensor, IR receiver, and D 162A LCD display. That was implemented in Hardware Simulation Lab. We have written code in C by using MPLAB sotware. We have completed that project in Embedded System Course. Now we have implemented in Xilinx sotware and analyze the energy for that project.

Fig. 2 Prototype of VCM Machine by PIC 16F887 Microcontroller

We know that, Power is proportional to requency. If requency is increasing, there will be increase in power consumption irrespective of 10 standard. Only the LVCMOS have 10 standard, which takes less power when we upgrade our design to latest FPGA [1]. LVCMOS standard bufers are general purpose lOs, given that the single ended interface. In bottomless sub-micron technology nodes such as the 65 m and beyond, issue such as small channel effect, hot carrier produce, Negative-bias temperature unsteadiness, gate oxide integrity, leakage domination and the like are conirm hard to ight [2]. Even though in our practical life like in Indian Metro Railway station it can also implement. Now a day, the hot discussion of FPGA or microconroller, which one should to use for any project. Now, FPGAs are going to rule in research ield because of their lexibility, better power eiciency and decreasing prices. A sot processor is added in the FPGA design to get microcontroller like unctionality along-with other concurrent processing. FPGAs are concurrent, able to take sequential functionality like adding soft processor core . The

microcontroller is always sequential. FPGAs better applications for real-time, DSP [4]. IR (Inrared) sensor is a device which is able to emit and/or able to detect the inrared radiation. IR sensors can measure the heat of an object or detect motion [5]. Many kinds of sensors are available in market one of them is PIR. PIR means passive inrared sensor. PIR is an electronic sensor which can measure IR light radiating rom in its ield [6]. PIR-sensor able to consume the power [7] and its application is in motion detection, ulra sonic signal coding [8], and wireless networks [9]. Most applications for the monitoring of human activities in an environment are based on video sensor data [10].

III. RESULTS

A. Results for HSL 110 Std

TABLE I. TABLE FOR HSTL_I I/O STD

S GHz 2S GHz 12SGHz 62SGHz lTHz Clocks 0.026 0.128 0.642 3 .208 5.13 3

Logic 0.001 0.002 0.008 0.03 8 0.060

Signals 0.002 O.Oll 0.056 0.281 0.450

lOs 0.lO9 0.486 2.3 74 1l.812 18.890

Leakage 0.081 0.083 0.095 0.3 76 0.812

Total 0.219 0.7lO 3 .l75 15.715 25.3 45

In Table I, Selected 10 standards is HSTL class I i.e. HSTL_I. Here we are taking 5 diferent device operating requencies that start rom 5 GHz and end with 1 THz. Intermediate requencies are 25GHz, 125GHz and 625GHz. When we scale down rom 1 THz to 5GHz, there is 99.49%, 98.3 3 %,99.56%,99.42%,90.02%,99.14% reduction in clock energy, logic energy, signal energy, lOs energy and leakage energy respectively.

30.000 i E 20.000 __ n 10.000 e 0.000

�v �v � g y

,0 ° )- �v � > ,j ,0 ,-� o" �

Frequency

• Leakage .10s • Signals • Logic • Clocks

Fig. 3. Energy vs Frequency curve for HSTL_I I/O STD

In Figure 3 , leakage energy, lOs energy, signal energy, logic energy and clocks energy is reperesentaed using blue color, red color, olive green color, purple color and aqua color and its magnitude are 0.219J, 0.7lOJ, 3 .175J, 15.715J and 25.3451. These energies are the lowest at 5 GHz and highest at 1 Thz.

Total O.21g ·

710 3.175

Fig. 4. Total energy dissipation for diferent frequency for HSTL_I I/O STD

467

In Figure 4, total energy on 5GHz, 25GHz, 125GHz, 625GHz and 1 THz. We are representing using aqua color, purple color, olive green color, red color and blue color. These consumption are the lowest at 5 GHz and highest at 1 THz.

B. ResultsforHSLjlllOStd

TABLE II. TABLE FOR HSTL_II I/O STD

S GHz 2S GHz 12SGHz 62SGHz lTHz Clocks 0.026 0.128 0.642 3 .208 5.l3 3

Logic 0.001 0.002 0.008 0.03 8 0.060

Signals 0.002 O.Oll 0.056 0.281 0.450

lOs 0.085 0.3 3 5 1.582 7.818 12.495

Leakage 0.081 0.083 0.092 0.220 0.553

Total 0.195 0.559 2.380 1l.565 18.691

In Table II, Selected 10 standards is HSTL class II i.e. HSTL_II. Here we are taking 5 diferent device operating requencies that start rom 5 GHz and end with 1 THz. Intermediate requencies are 25GHz, 125GHz and 625GHz. When we scale down rom 1 THz to 5GHz, there is 99.49%, 98.3 3 %,99.56%,99.3 2%,85.35%,98.95% reduction in clock energy, logic energy, signal energy, lOs energy and leakage energy respectively.

20.000 -----E n 10.000 e 0.000 r ." . g � 3 0� 0-" ." -" ' > �3 � Y - 0"

Frequency

• Leakage

.10s • Signals

• Logic

• Clocks

Fig. 5. Energy vs Frequency curve for HSTL_II I/O STD

In Figure 5, leakage energy, lOs energy, signal energy, logic energy and clocks energy is reperesentaed using blue color, red color, olive green color, purple color and aqua color and its magnitude are 0.195J, 0.559J, 2.380J, 1l.565J and 18.691J. These energies are the lowest at 5 GHz and highest at 1 Thz.

Total 0559

0.195 2.380

.5GHz

.25 GHz

.125GHz

.625GHz

Fig. 6. Total energy dissipation diferent frequency for HSTL_II I/O STD

In Figure 6, total energy on 5GHz, 25GHz, 125GHz, 625GHz and 1 THz. We are representing using aqua color, purple color, olive green color, red color and blue color. These energies conswnption are the lowest at 5 GHz and highest at 1 THz.

C. Results for HSL j _ J SIlO Std

TABLE III. TABLE FOR HSTL_I I/O STD

S GHz 2S GHz 12SGHz 62SGHz lTHz Clocks 0.026 0.128 0.642 3 .208 5.13 3

Logic 0.001 0.002 0.008 0.03 8 0.060

Signals 0.002 0.011 0.056 0.281 0.450

lOs 0.13 1 0.585 2.853 14.192 22.696

Leakage 0.083 0.085 0.100 0.524 0.813

Total 0.243 0.811 3 .659 18.243 29.152

In Table III, Selected 10 standards is HSTL class I (1.8 V) i.e. HSTL_I_18. Here we are taking 5 diferent device operating requencies that start rom 5 GHz and end with 1 THz. Intermediate requencies are 25GHz, 125GHz and 625GHz. When we scale down rom 1 THz to 5GHz, there is 99.49%, 98.3 3 %,99.56%,99.42%,89.79%,99.17% reduction n clock energy, logic energy, signal energy, lOs energy and leakage energy respectively.

30.000 E 20.000 • Leakage n 10.000 e 0.000 .10s

." . • Signals

g ,5 )- )-" ." -" '� ,? �5 � • Logic

Y - o" • Clocks

Frequency

Fig. 7. Energy vs Frequency curve for HSTL_I_18 I/O STD

In Figure 7, leakage energy, lOs energy, signal energy, logic energy and clocks energy is reperesentaed using blue color, red color, olive green color, purple color and aqua color and its magnitude are 0.243 J, 0.8111, 3 .659J, 18.243 J and 29.1521. These energies are the lowest at 5 GHz and highest at 1 Thz.

Total O.24� ·

811 3.659

_SGHz

.25 GHz

.125GHz

.625GHz

Fig. 8 Energy dissipation with diferent frequency for HSTL_I_18 I/O STD

In Figure 8, total energy on 5GHz, 25GHz, 125GHz,

468

625GHz and 1 THz. We are representing using aqua color, purple color, olive green color, red color and blue color. These energies conswnption are the lowest at 5 GHz and highest at 1 Thz.

D. ResultsforHSLj1_JSIOStd

TABLE IV. TABLE FOR HSTL I I/O STD -

S GHz 2S GHz 12SGHz 62SGHz lTHz Clocks 0.026 0.128 0.642 3 .208 5.13 3

Logic 0.001 0.002 0.008 0.03 8 0.060

Signals 0.002 0.011 0.056 0.281 0.450

lOs 0.098 0.3 71 1.73 5 8.557 13 .673

Leakage 0.083 0.084 0.093 0.243 0.652

Total 0.210 0.596 2.53 4 12.3 27 19.968

In Table IV, Selected 10 standards is HSTL class II (1.8 V) i.e. HSTL I 18. Here we are taking 5 diferent device operating requencies that start rom 5 GHz and end with 1 THz. Intermediate requencies are 25GHz, 125GHz and 625GHz. When we scale down rom 1 THz to 5GHz, there is 99.49%, 98.3 3 %,99.56%,99.28%,87.27%,98.95% reduction in clock energy, logic energy, signal energy, lOs energy and leakage energy respectively.

20.000 -----E n 10.000 e 0.000

." . 5 )- ." . -" g � � �5 0-y

" -" o> �

Frequency

• Leakage

.10s

• Signals

• Logic

• Clocks

Fig.9. Energy vs Frequency curve for HSTL_II_ 18 I/O STD

In Figure 9, leakage energy, lOs energy, signal energy, logic energy and clocks energy is reperesented using blue color, red color, olive green color, purple color and aqua color and its magnitude are O.21OJ, 0.596J, 2.53 4J, 12.3 27J and 19.9681. These energies are the lowest at 5 GHz and highest at 1 Thz.

Total 0596

0.210 2534

_SGHz

.125GHz

.625GHz

Fig. 10. Energy dissipation with frequency for HSTL_II_ 18 I/O STD

In Figure 10, total energy on 5GHz, 25GHz, 125GHz, 625GHz and 1 THz. We are representing using aqua color,

purple color, olive green color, red color and blue color. Theseenergies consumption are the lowest at 5 GHz and highest at 1Thz.

In Table V, Selected IO standards are LVCMOS12 (LowVoltage Complementary Metal Oxide Semiconductor, whichhas operating voltage1.2 V). Here we are taking 5 differentdevice operating frequencies that start from5GHz and endwith1 THz. Intermediate frequencies are 25GHz, 125GHz and625GHz. When we scale down from 1 THz to 5GHz, there is99.49%, 98.33%, 99.56%, 98.85%, 89.46%, 98.67% reductionin clock energy, logic energy, signal energy, IOs energy andleakageenergy respectively.

InFigure 11, leakage energy, IOs energy, signal energy, logicenergy and clocks energy is represented using blue color, redcolor, olive green color, purple color and aqua color and itsmagnitude are 0.303J, 0.740J, 2.934J, 14.054J and 22.747J.These energies are the lowest at 5GHz andhighest at 1Thz.

In Figure 12, total energy on 5GHz, 25GHz, 125GHz,625GHz and 1THz.We represent using aqua color, purple color,

E. Results forLVCMOS12 I/OStd

0.026 0.128 0.642 3.208 5.133

0.001 0.002 0.008 0.038 0.060

0.002 0.011 0.056 0.281 0.450

0.188 0.512 2.130 10.220 16.288

0.086 0.087 0.098 0.307 0.816

0.303 0.740 2.934 14.054 22.747

5 GHz 25 GHz 125GHz 625GHz 1THz

Clocks

Logic

Signals

IOs

Leakage

Total

TABLE V. TABLE FOR HSTL_I I/O STD

Fig. 11. Energy vs. Frequency curve for LVCMOS12 I/O STD

Fig. 12. Energy dissipation with different frequency for LVCMOS12 I/O STD

olive green color, red color and blue color. These consumptionare the lowest at 5GHz andhighest at 1Thz.

In Table VI, Selected IO standards are LVCMOS15 (LowVoltage Complementary Metal Oxide Semiconductor, whichhas operating voltage1.5 V). Here we are taking 5 differentdevice operating frequencies that start from 5GHz and end with1 THz. Intermediate frequencies are 25GHz, 125GHz and625GHz. When we scale down from 1 THz to 5GHz, there is99.49%, 98.33%, 99.56%, 98.85%, 89.46%, 98.67% reductionin clock energy, logic energy, signal energy, IOs energy andleakageenergy respectively.

In Figure 13, leakage energy, IOs energy, signal energy, logicenergy and clocks energy is represented using blue color, redcolor, olive green color, purple color and aqua color and itsmagnitude are 0.201J, 0.678J, 3.073J, 15.238J and 24.628J.These energies are the lowest at 5GHz andhighest at 1Thz.

In Figure 14, total energy on 5GHz, 25GHz, 125GHz,625GHz and 1THz.We represent using aqua color, purple color,olive green color, red color and blue color. These consumptionare the lowest at 5GHz andhighest at 1Thz.

G. Results forLVCMOS18 I/OStd

F.Results forLVCMOS15 I/OStd

0.026 0.128 0.642 3.208 5.133

0.001 0.002 0.008 0.038 0.060

0.002 0.011 0.056 0.281 0.450

0.091 0.454 2.272 11.358 18.173

0.081 0.083 0.095 0.353 0.812

0.201 0.678 3.073 15.238 24.628

5 GHz 25 GHz 125GHz 625GHz 1THz

Clocks

Logic

Signals

IOs

Leakage

Total

TABLE VI. TABLE FOR HSTL_I I/O STD

Fig. 13. Energy vs. Frequency curve for LVCMOS15 I/O STD

Fig. 14. Energy dissipation with different frequency for LVCMOS15 I/O STD

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TABLE VII. TABLE FOR HSTL I I/O STD -

5 GHz 25 GHz 125GHz 625GHz lTHz Clocks 0.026 0.128 0.642 3 .208 5.13 3

Logic 0.001 0.002 0.008 0.03 8 0.060

Signals 0.002 0.011 0.056 0.281 0.450

lOs 0.122 0.608 3 .041 15.205 24.3 27

Leakage 0.083 0.085 0.101 0.602 0.813

Total 0.23 4 0.83 4 3 .848 19.3 3 4 3 0.783

In Table VII, Selected 10 standards are LVCMOS18 (Low Voltage Complementary Metal Oxide Semiconductor, which has operating voltage1.8 V). Here we are taking 5 diferent device operating requencies that start rom 5 GHz and end with 1 THz. Intemediate requencies are 25GHz, 125GHz and 625GHz. When we scale down rom 1 THz to 5GHz, there is 99.49%,98.3 3 %,99.56%,99.50%,89.79%,99.24% reduction in clock energy, logic energy, signal energy, lOs energy and leakage energy respectively.

E • Leakage

n .10s

e r • Signals

g • Logic

Y • Clocks Frequency

Fig. IS. Energy vs. Frequency curve for LVCMOS 18 I/O STD

In Figure 15, leakage energy, lOs energy, signal energy, logic energy and clocks energy is represented using blue color, red color, olive green color, puple color and aqua color and its magnitude are 0.23 4J, 0.83 4J, 3 .848J, 19.33 4J and 3 0.783 1. These energies are the lowest at 5 GHz and highest at 1 Thz.

Total 0.834

0.234 3.848

.5GHz

.25 GHz

• 125GHz

.625GHz

.1THz

Fig. 16. Energy dissipation with diferent frequency for LVCMOS 18 I/O STD

In Figure 16, total energy on 5GHz, 25GHz, 125GHz, 625GHz and 1 THz. We represent using aqua color, purple color, olive green color, red color and blue color. These consumption are the lowest at 5 GHz and highest at 1 THz.

H Results/or LVCMOS25110Std

470

TABLE VIII. TABLE FOR HSTL I I/O STD -

5 GHz 25 GHz 125GHz 625GHz lTHz Clocks 0.026 0.128 0.642 3 .208 5.13 3

Logic 0.001 0.002 0.008 0.03 8 0.060

Signals 0.002 0.011 0.056 0.281 0.450

lOs 0.214 1.070 5.3 51 26.756 42.810

Leakage 0.086 0.090 0.125 0.816 0.816

Total 0.3 29 1.3 01 6.182 3 1.099 49.269

In Table VIII, Selected 10 standards are LVCMOS25 (Low Voltage Complementary Metal Oxide Semiconductor, which have operating voltage 2.5 V). Here we are taking 5 different device operating requencies that start rom 5 GHz and end with 1 THz. Intemediate requencies are 25GHz, 125GHz and 625GHz. W hen we scale down rom 1 THz to 5GHz, there is 99.49%,98.3 3 %,99.56%,98.50%,89.46%,99.3 3 % reduction in clock energy, logic energy, signal energy, lOs energy and leakage energy respectively.

E n e

g Y

60.000 40.000 20.000

0.000 �" . �G 0� 0�" �"

> ,? �G - O" Frequency

• Leakage

. 10s

• Signals

�" � • Logic

.Clocks

Fig. 17. Energy vs. Frequency curve for LVCMOS25 I/O STD

In Figure 17, leakage energy, lOs energy, signal energy, logic energy and clocks energy is represented using blue color, red color, olive green color, purple color and aqua color and its magnitude are 0.329J, 1.3011, 6.182J, 3 1.099J and 49.2691. These energies are the lowest at 5 GHz and highest at 1 Thz.

Total 1. 301

0.329 6.182

.5GHz

.25 GHz

• 125GHz

.625GHz

.1THz

Fig. 18. Energy dissipation with frequency for LVCMOS25 I/O STD

In Figure 18, total energy on 5GHz, 25GHz, 125GHz, 625GHz and 1 THz. We are representing using aqua color, purple color, olive green color, red color and blue color. These energies consumption are the lowest at 5 GHz and highest at 1 THz.

1. Results/or LVCMOS33110Std

TABLE IX. TABLE FOR LVCMOS33 I/O STD

5 GHz 25 GHz 125GHz 625GHz lTHz Clocks 0.026 0.128 0.642 3 .208 5.13 3

Logic 0.001 0.002 0.008 0.03 8 0.060

Signals 0.002 0.011 0.056 0.281 0.450

lOs 0.3 64 1.819 9.094 45.469 72.750

Leakage 0.090 0.096 0.188 0.819 0.819

Total 0.483 2.056 9.988 49.815 79.212

In Table X, Selected 10 standards are LVCMOS3 3 (Low Voltage Complementary Metal Oxide Semiconductor, which has operating voltage 3 .3 V). Here we are taking 5 diferent device operating requencies that start rom 5 GHz and end with 1 THz. Intermediate requencies are 25GHz, 125GHz and 625GHz. When we scale down rom 1 THz to 5GHz, there is 99.49%,98.3 3 %,99.56%,99.50%,89.01%,99.3 9% reduction in clock energy, logic energy, signal energy, lOs energy and leakage energy respectively.

E n e

g y Frequency

• Leakage

. 10s

• Signals

• Logic

.Clocks

Fig. 19. Energy vs. Frequency curve for LVCMOS33 I/O STD

In Figure 19, leakage energy, lOs energy, signal energy, logic energy and clocks energy is represented using blue color, red color, olive green color, puple color and aqua color and its magnitude are 0.483 J, 2.056J, 9.988J, 49.815J and 79.2121. These energies are the lowest at 5 GHz and highest at 1 Thz.

Total

• 125GHz

.625GHz

.1THz

for LVCMOS33 I/O STD

In Figure 20, total energy on 5GHz, 25GHz, 125GHz, 625GHz and 1 THz. We are representing using aqua color, purple color, olive green color, red color and blue color. These energies consumption are the lowest at 5 GHz and highest at 1 THz. For previous graph we analyzed that only at 5GHz requency we can get low energy consumption, so if we calculate again at 5 GHZ with diferent lOs, then the igure. 21

471

0.400

E 0.350

n 0.300

0.250

0 .200

0.150

g 0.100 V 0.050

0.000

-

IDs Power

/ - /

105 Standard

7 7 J

-ID-Power

Fig. 2 I.Total energy dissipation at 5GHZ frequency for HSTL lOs Standard

will be like given below.

In Figure 21, total energy dissipation at 5 GHz requency for different HSTL lOs standard curve has given. In this curve, energy dissipation of HSTL II lOs Standard is much lesser than others. And again we have

-seen that this curve is increasing

linearly, like 0.085, 0.092, 0.109, 0.13 1 accordingly to HSTL_II, HSTL_II_18, HSTL_I, HSTL_I_18, LVCMOSI5, LVCMOSI8, LVCMOSI2, LVCMOS25 and LVCMOS33 lOs Standard. If we fmd the diference between rom HSTL I 18 to HSTL I,HSTL l to HSTL II 18 and HSTL II 18 to HSTL II then their value �ill be like 0.022,0.011 and 0.013 . Again, If �e fmd the diference between rom LVCMOS3 3 to LVCMOS25, LVCMOS25 to LVCMOSI2, LVCMOS12 to LVCMOS18 and LVCMOS18 to LVCMOS15 then their values will be like O.150, 0.026, 0.066 and 0.03 1.That means it's power is increasing whenever we want to use high standard lOs and the inal result is in between HSTL and LVCMOS, HSTL takes low power and in HSTL the only HSTL_II take less power dissipation.

I. CONCLUSION Total energy dissipation increases linearly at 5GHz

requency for HSTLS lOs. In total power, 5 GHz requency dissipates less power. For this reason, we have created the curve of Total energy dissipation at 5GHz requency dissipation for different lOs standard. From the curve we can easily conclude that only HSTL_II dissipated less power which is consuming more energy in Bi-directional VCM on FPGA. FPGA is more effective than using any microcontroller in perspective of energy eiciency .

. FUTURE SCOPE We have implemented this design on 28nm FPGA, there is

open scope to redesign this MBCCS on next generation ulra scale 20nm FPGA and even lower 7nm uture FPGA. Here, we have used diferent lOs standards of HSTL_I, HSTL_II, HSTL_I_18, HSTL_II_18 for diferent requencies, where requencies are 5GHz, 25GHz, 125GHz, 625GHz, 1 THz. HSTL means High Speed Transceiver Logic, is a technology independent standard for signaling between integrated circuits or IC to make energy eicient MBCCS. There is open scope to use other energy eicient technique like Mapping, Clock Gating, Power Gating, SSTL 10 standards, LVCMOS 10 standards, LVDCI 10 standard, Clock Enable for urther reduction of power dissipation of MBCCS to make this the most

energy eficient MBCCS. Here target circuit is MBCCS, There is open scope to design other circuit using the same technique on which we have worked here.

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[2] P. Kannan, "Fundamental blocks of single ended LVCMOS output bufer- a circuit level design guideline" 18th European Conference on Circuit Theory and Design (ECCTD), 2007, pp. 392 -395, 2007.

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[9] R. A. Sajana, R. Subramanian, P.V. Kumar, S. Krishnan, B. Amrutur, J. Sebastian, M. Hegde, S. Anand, "A low-complexity algorithm for intrusion detection in a PIR-based Wireless Sensor Network", Intenational Conference on Intelligent Sensors, Sensor Networks and Information Processing (ISSNIP), pp. 337-342,2009.

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