RELIABILITY CONSIDERATIONS FOR IMPLANTABLE MEDICAL ICS Mark Porter1, Paul Gerrish1, Larry Tyler1, Sharon Murray1,

Rob Mauriello1, Frank Soto1, Gaylene Phetteplace1, Scott Hareland2

1Medtronic Microelectronics Center, Tempe, AZ 2Medtronic, Mounds View, MN

ABSTRACT

Implantable medical devices continue to grow in complexity, mirroring the ascent of the semiconductor industry along the Moore’s Law curve. Traditionally, implantable applications have taken a fast-follower approach to silicon adoption, using more mature technologies to reduce risk. While commercial manufacturers, in some circumstances, may be able to trade off lifetime requirements for performance, this is decidedly not the case for implantable use, where 10 to 12 year requirements are typical. On the other hand, hardware and software redundancy solutions employed by high reliability avionics, telecommunications, and servers are difficult to implement in a battery-powered device, where current drain restrictions are severe. This paper discusses some of the reliability challenges faced by implantable device manufacturers as the need to provide more sophisticated therapy and diagnostics requires increasingly advanced technologies. [Keywords: medical electronics; implantable devices; high-reliability electronics]

INTRODUCTION

Implantable medical device applications continue to grow as new possibilities emerge for new or improved therapies and monitoring to facilitate better outcomes for chronic disease management. Implantable systems incorporate a number of different target applications. Traditionally, bradycardia pacemakers (Figure 1) and tachyarrthymia defibrillators have represented the largest markets, but this has evolved, as heart failure devices have joined the cardiac rhythm management portfolio, and a host of products for pain suppression and neurological dysfunction, including a variety of emergent cranial applications, have started to gain adoption.

Figure 1. Implantable pacemaker with non-rechargeable battery lasting 7-10 years

Implantable applications have grown in complexity and processing horsepower mirroring that of the general semiconductor industry, but the key differentiator in these systems is that they must follow a very stringent power management environment in order to meet their objectives [1]. As the complexity of the closed loop feedback systems and diagnostic data sets grows, there is a need for advanced technologies to facilitate the boost in performance, without a corresponding increase in energy usage.

IMPLANTABLE APPLICATIONS

Most new implantable applications incorporate closed-loop systems involving sensing, control, information transmission, and therapy delivery based on the data. This involves obtaining data that can create actionable information in the right place at the right time and may also involve data storage for later retrieval that could include trends, decisions, and actions taken based off the data. New applications in this space tend to require more sophisticated signal processing and associated algorithms, such as the rich data content in neurological applications requiring spectral analysis of the incoming data to be sensed (Figure 2). In addition, there is a need for further orthogonal sensing vectors beyond the traditional electrical signatures. These could be sensors such as 3-axis accelerometers (Figure 3) to monitor movement and position, blood pressure sensors, or optical blood oxygen sensors. These additional sensing vectors help ensure that decisions will be made based upon appropriate physiological inputs, minimizing the chances of therapy delivery in response to false input signatures.

Figure 2. Spectral coding of neural activity over the visual cortex vs. time. Frequency is plotted along the x-axis and time is plotted along the y-axis.

All of this enriched data content drives the need for increased real-time processing bandwidth. Traditional systems have been able to meet demand utilizing 8-bit systems due to the fact that cardiac and neurological events occur on a very slow time scale compared to many electronic systems. Increasingly there is a need to move to 16-

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bit and 32-bit architectures in order to meet all of the demands in a timely and power-efficient manner.

Figure 3. Three-axis accelerometer datastream.

Typical digital subsystem requirements of a 32-bit CPU system might feature a clock speed of 1Mhz with 1Mbyte ROM and perhaps 128 – 256Kbytes of SRAM for cache, with a larger memory of 8 – 32Mb for data storage, and up to 1M dedicated logic gates. This subsystem needs to be robust to soft error upsets and feature exceedingly low static and dynamic power usage in the range of approximately 10µA of current drain running off a regulated power supply of less than one Volt.

Traditional systems have utilized a large amount of analog signal processing, but with the growing demands on signal analysis to implement more complex detection algorithms, the use of Digital Signal Processing (DSP) has grown significantly. Often the DSP is implemented in dedicated hardware blocks to improve on energy utilization. Reduced dynamic power consumption for a given feature in advanced semiconductor nodes offers the ability to perform ever more sophisticated analyses.

Implantable systems of the future will consist of a very sensitive analog sensing front end from multiple sensor streams with efficient A/D conversion, followed by sophisticated processing and decision making resulting in the generation of multiple electrical stimulation outputs. Electrical inputs are usually on the order of 10s to 100s of microVolts, while outputs tend to be on the order of 10 Volts, or very high voltages up to 100s of Volts, in the case of implantable defibrillators, resulting in the need for additional strategies to be able to avoid collisions between input and output data to the body. Additionally, large external voltages from a variety of sources require adequate protection schemes to prevent damage to the sensitive input electronics.

In addition to sensing and delivering data, implantable systems also have to store and transmit data to the outside world. Traditional systems transmitted through a two-way telemetry system that utilized very short range transmission of pulse codes in the 100 KHz frequency range. As data content has grown and the expectation for seamless wireless connectivity has also encompassed implantable devices, these telemetry systems have moved to RF transmission of data to facilitate longer distance communication to both hubs in the home as well as in the clinic. The development of the MICS standard (Medical Implant Communications) at 402 –405 MHz [2] serves to

facilitate RF transmission in a body-friendly frequency band that is relatively free of aggressors, particularly in electromagnetically noisy hospital environments.

Implantable systems servicing chronic disease management have to be long-lived in the body, both from the perspective of minimizing required interventions, as well as maintaining an appropriate reimbursement cost by payers in the healthcare system. Many dedicated pacing systems last from 7 to 10 years in the body on a non-rechargeable battery. Non-rechargeable systems have been favored for several reasons, but most often cited is the predictability that comes with their application. Reliable operation is achieved without requiring the clinician or patient to intervene. However, for many non life support systems, rechargeable systems are gaining popularity as they facilitate smaller form factors that can enable new therapy delivery options for physicians, or improved site locations that have reduced morbidity concerns.

The regulatory environment within which implantable devices are developed and manufactured also places constraints on these systems. The goal of this environment is to help ensure due diligence and rigor is applied in developing new systems or changes to existing systems. Like any system, there are advantages and disadvantages associated with this environment. The regulated environment does require a longer development time compared to the commercial semiconductor industry and this industry is also a much smaller volume than the commercial world. This creates challenges for system development, as technologies need to be targeted that will still have appropriate production volume for manufacturing in the future across the implantable system’s market lifetime. This often requires specific supply agreements with reliable long-term suppliers that have a strong commitment to quality. Appropriate volume content in a technology helps improve reliability and manage costs at the same time.

HISTORICAL RELIABILITY

The commercial semiconductor industry in general, and implantable devices in particular, have historically benefited from the wide reliability margin available in early generation technologies. As long as no extrinsic defects were allowed to escape into a product population, failures due to material wearout were extremely unlikely.

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However, performance demands required to stay on the Moore’s Law curve have increasingly reduced that margin, to the point that wearout due to some failure mechanisms is an important product consideration. Figure 4 gives a schematic illustration of this problem, showing new technology generations pushing the envelope out closer to the intrinsic failure point.

This is a serious issue for implantable electronics, as the areas of concern faced by the commercial world are generally not the same areas as this ultra-low power application. Especially for high-speed, high-volume electronics, the phrase ‘reliability margin is performance left on the table’ drives the industry to invest in solutions that provide adequate reliability for ever shorter product cycles. Unfortunately, the success criteria that allow timely introduction of new products to the consumer market, are not always applicable to the implantable device world.

One particular concern of deep submicron technologies is the characteristic of soft breakdown and SILC (Stress-Induced Leakage Currents). Much of the discussion in the reliability community for these effects has centered around the ability of digital circuits to continue to function after the first breakdown event[3,4], or marginal increases in leakage through the gate oxide. While this may push out the definition of failure in commercial applications, for implantable electronics, any increase in gate leakage during the useful life of the product has the potential to prematurely deplete the battery.

Product-level stress testing performed to-date on advanced technologies has shown adequate SILC margin, although this comes at the expense of performance, where a thicker than usual gate oxide is used to ensure low standby current. Figure 5 gives some early data that we have acquired, showing a shift in SRAM read access time, but no systematic change in standby current.

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One area where low power requirements continue to provide benefit, is in the use of IDDq as a defect-screening technique. While much of the commercial world has seen a reduction in efficacy, or an increase in complexity, of this tool [5,6], the need for low static

leakage currents in implantable electronics ensures that this method will continue to be viable in the future. Figure 6 plots relative IDDq values for products built with two CMOS technology generations. Although the measured background currents are increasing, they have not ballooned dramatically.

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Given the importance of screening latent defects at wafer probe, the impact of over-voltage stress (OVS) on oxide lifetime is also an important issue, especially as oxides become thinner. Figure 7 shows example data illustrating that up to seven passes through highly accelerated voltage screening did not damage the intrinsic properties of the oxide such that a change in measured IDDq values was seen. In this case, the delta IDDq values were comparable to the measurement error of the instrument.

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COMMERCIAL TECHNOLOGIES

Use of commercial off-the-shelf (COTS) ICs has traditionally been a challenge for implantable device manufacturers due primarily

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to the extremely high reliability requirements, the unique application space, and the comparatively long development and product life cycles. The implantable product drivers, in order of priority, are reliability, features, miniaturization, and cost. Digital processing speed and extreme temperature operation are typically not limiters. Smaller, less invasive implantable devices with increased feature sets are desirable. Device size is dominated by battery size and battery size is driven by power needs. Therefore, from an IC standpoint, smaller process technology migration is an indirect enabler for device miniaturization as long as low level leakage currents can be maintained. Understanding the drop off point and process stability is critical to use.

Past sourcing strategies relied heavily on captive wafer fabs for critical IC manufacture and close partnerships with select suppliers for support components. Suppliers were reluctant to be exposed to potential medical liability, especially for products with life support functions and therefore required medical liability protection. In return, the medical companies required advanced notice on process issues, several years notice on process obsolescence, and life-time buy agreements. Design, wafer processing, test, and hybrid assembly were typically performed in-house by the medical manufacturer as commercial vendors were reluctant to customize their processes for low volume users requiring ultra-low leakage and ultra-high reliability in a limited (i.e. -20°C to +135°C) temperature range. As a result, device manufacturers tended to possess specialized hands-on, in-house expertise on all facets of IC engineering across fabrication, characterization, test, packaging, and failure analysis. Quality systems target single digit FIT (Failures per 109 hours) and PPMM (Parts Per Million per Month) indices which can only be attained by interdisciplinary engineering teams. Key experts on low power, high voltage, ESD, data retention, etc. worked closely with fab, modeling, design automation, and packaging engineers to predict and prevent root cause IC issues like low level leakage and reliability latencies through customized layouts, modified fab targets, custom designs and device-specific architectures.

Initial ventures into COTS for implantable use started approximately 10 years ago with SRAM and EEPROM memories used for non-life support functions. A significant reworking of the traditional customer/supplier relationship was required. Medical device manufacturers typically need higher confidence levels and lower FIT rates over a much longer product life cycle than commercial standards. In that sense, their needs are similar to those of automotive and aerospace applications, but the temperature range and power requirements are still quite different. It has therefore been necessary to dive deeper into the suppliers’ design and process details than suppliers are accustomed to or comfortable with for a low volume user. In many cases, it is also necessary for the medical user to conduct their own application-specific process characterizations on custom test vehicles to compensate for supplier IP which is not available. In the latter case, a “black box” strategy is often used where creative application engineers throw every conceivable test condition at a significant number of parts to see where the performance envelope breaks. Results of the characterization are then used to develop lengthy test flows which are used to re-screen parts which had previously been screened at the commercial supplier. This method has proven successful and has resulted in millions of commercial memories in implanted devices with few issues.

The following examples illustrate several issues seen on medical COTS ICs that would probably not be an issue with commercial use. The first example involved an implantable device that was working properly when it left the factory, was flown to the medical sales representative, and was discovered to have a dead battery when the

carrier box was opened. It worked normally when the battery was replaced. Subsequent failure analysis showed that a commercial memory in a plastic package was the root cause. The 1Mbit SRAM stand-by current increased significantly at temperatures lower than 10°C, as shown in figure 8. It is believed that the IC went into the high current state while in the aircraft storage hold during flight at sub-freezing temperatures and depleted the battery. Since body temperature is typically well-maintained at 37°C, this IC would not have gone into the high current state in vitro. However, a low temperature exposure of shorter duration might have partially depleted the battery thereby shortening the working life of the device and resulting in a premature explant.

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A second example involves low-current popcorn noise. Sensing channels failed noise testing at IC test. The issue was determined to be due to popcorn noise which did not occur at higher current levels. Standard device layouts had to be modified to accommodate the medical device ultra-low current levels, as illustrated as figures 9 and 10.

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Figure 10. Output-Referred Current Noise with transistor popcorn noise degradation.

Economic and market pressures have drastically changed the supply landscape in the last 10 years. Many commercial IC manufacturers are less reluctant to join the growing medical market and are forming partnerships with existing medical device manufacturers to create custom process flows to accommodate the medical industry and are starting up their own medical divisions. Standard commercial offerings are also attaining lower power consumption, making them more attractive for off-the-shelf use. The economic realities of maintaining captive fabs have also contributed to the momentum for the medical device companies to become dependent on the standard commercial foundries and key strategic semiconductor partners. As always, there are challenges.

The drive for smaller and cheaper devices is still balanced against the need for ultra high reliability and ultra low power with outsourcing strategies that include all aspects of IC design, manufacture, test, packaging, and failure analysis. This can cause the strain within supplier/customer relationships. IP protection on both sides is often an antagonist factor. Design requirements for ultra-low leakage, low noise, low drift, and high voltage (for defibrillation therapy delivery) often push the envelope of the existing fab process flows and require extensive modification of device models, device layouts, digital libraries, process targets, and test limits. Process migration protocols for our custom designs in the standard foundries are similar to those used in the captive fab scenario: ROM and SRAM are typically used as the canary circuits, followed by microprocessors, non-volatile memory, mixed signal, then high voltage mixed-signal designs. At each new process node, design environment customizations, process characterization/verification, and IC and packaging interaction reliability studies require significant effort. Since full visibility into fab process changes and improvements is not possible, Wafer-Level Reliability monitors (WLR), outlier detection, and Design for Reliability and Manufacturing (DFx) have also been implemented.

DESIGN OUTSOURCING

Outsourcing an IC design presents unique challenges for an implantable device. Rigorous oversight and documentation of the entire development process is necessary, both to ensure reliability goals are met and to adequately assess and mitigate potential risks. The design tradeoffs and final implementation must be evaluated with respect to the safety of the patient and the effect on the overall

operation of the device, some aspects of which may not be visible to the vendor. For example, although a brief spike in current drain would not have a significant impact on longevity and may appear to be insignificant, it could affect the functionality of other parts of the device or cause it to POR (Power On Reset), endangering the patient. For this reason, every silicon pass requires extensive verification both at the IC and system level. The goal is to limit design changes by performing thorough simulations and evaluation prior to IC fracture. As a result, the design process for medical devices is inherently slower and more methodical than for commercial devices where time-to-market is of utmost importance.

Design verification testing (DVT) is typically more formal and complex than for a commercial product. All testing is performed to a mutually agreed upon and released test plan that provides details on the methodology for verifying each design specification over all corners. Regression testing for subsequent silicon passes is acceptable, but must ensure that there is no degradation to the other blocks in addition to validating the intended design changes. All test data must be included in the final report and deviations and failures must be documented and explained. The DVT results and the risk analysis from the design phase will be used to determine the scope of the production test program. The need to ensure product reliability through the inevitable process changes over the life of the device drives comprehensive test programs with long test times.

Verification of the vendor’s electrical test program and audits of their quality systems and factories are key components of the qualification acceptance criteria. Formal test verification requires independent confirmation of each parameter forced or measured with external test equipment to ensure the sequences were properly implemented. This minimizes the possibility of test escapes and potential field failures. To maintain the same traceability of an IC manufactured in-house, all production probe and final test data must be transferred or retained by the vendor and made available on request. A decrease in yields or changes to key parametrics or critical process controls may require customer review prior to shipment to ensure product reliability.

The primary difference between implant grade and commercial devices is the need for extensive verification, test and documentation, much of which is driven by regulatory requirements. Ensuring reliability is best accomplished by working closely with the IC design vendor throughout the entire development process.

SCALING CONSIDERATIONS

As the implantable electronics industry migrates into deep submicron design rules, challenges arise that must be evaluated and understood. Moving to thinner oxide, halo/extension source/drain implants, and a copper backend with low-k dielectrics, process stability and predictability must be determined, and design rules to mitigate risk must be rigorously followed.

Front End Concerns

In the front end of the process, five notable differences are observed with scaling. Along with these changes, come reliability and design challenges that must be understood, especially with respect to the low power and high reliability requirements of the implantable electronics world.

1. Movement from a Lightly Doped Source/Drain (LDD) scheme to a Halo/Extension Implant scheme under the channel of the transistor

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2. Reduction in polysilicon gate length 3. Supply voltage reduction 4. Gate oxide thickness reduction 5. Reduction in the source/drain junction depth

As the industry moved to halo/extension implants, doping concentrations increased under the gate, generating a smaller depletion width. With continued scaling, source and drain depletion regions tend to migrate closer together, however ultra-shallow junctions and more abrupt junctions should improve some short channel effects (DIBL/VT roll-off). With this more abrupt junction, higher electric fields result and leakage mechanisms associated with this phenomenon could come into play.

Laterally (across the channel), the effects due to subthreshold leakage and larger band bending of the junctions including band-to-band tunneling and hot carrier injection must be accommodated. With the use of shallower junctions, end of range implant/RTA anneal defects must not lie within the depletion region of the source/drain junctions.

Vertical fields are exacerbated with the use of thinner oxides. Moving from earlier technology generations, the vertical electric fields could as much as two times higher on advanced process nodes. Gate Induced Drain Leakage (GIDL) could then potentially become an issue, as the drain electric field bends, resulting in band-to-band tunneling across the source/drain to body junction. With these thinner oxides, Stress Induced Leakage Current (SILC) could be an issue as well.

All of these concerns are addressed by semiconductor manufacturers during process development, but are a source of risk for implantable applications, as acceptable performance tradeoffs for the commercial world may not translate well to the ultra low power space.

Back End Concerns

The obvious back end differences in deep submicron involve moving from tungsten plugs with etched metal lines to a dual damascene copper inlay of integrated via and metal. Since the metal is now polished, metal density requirements must be strictly enforced. Also, since copper stress voids now becomes an issue, the use of a redundant via scheme and metal x to metal x-1 volume differences are now the major layout/design concern.

In older technologies, single isolated vias were allowed as long as proper enclosure is met above and below the via. However, in deep submicron nodes, design rules require that these single (potentially resistive/voided) vias are eliminated wherever possible. This creates a new realm of design rules that medical device designers must be understand to minimize these effects.

As an example, the general rule of thumb for redundant vias states that if either metal width can support redundant vias, it is required. As seen in Figure 11, metal-2 (dark) overlays metal-1 (light) in two different locations in this sample layout. In older technology design rules, a single via would be allowed at each intersection as long as proper enclosure was observed. However, in newer technologies, the design rules require that at least two vias are required (based on metal width) along the length of the underlying metal (metal-1 in this case). In the implantable electronics world, with reliability as a top concern, wherever possible, layouts and design are more restrictive than foundry design rules.

Figure 11. Use of multiple vias is an accepted practice in deep submicron technologies, and its use is increasing among medical device manufacturers in earlier technology nodes.

Mitigating Concerns

In order to minimize the impact of scaling effects, there are several strategies that will become critical to the successful implementation of deep submicron technologies within the implantable medical electronics industry.

1. Use the low power (thicker gate oxide) Foundry process. Using this oxide option will minimize the effects of GIDL and SILC.

2. Use a higher Threshold Voltage device (dual VT process) in all circuits wherever possible, as well as apply a body back-bias scheme. This minimizes the effects of off-state leakage.

3. Use a slightly greater than minimum drawn gate length. This minimizes the effects of Drain Induced Barrier Lowering (DIBL) and VT roll off.

4. Reduce VDD by the maximum amount possible. Lateral electric fields will be reduced, thereby lowering hot carrier and Band-to-Band (BTB) tunneling leakages. Gate voltage reductions in turn, will help minimize the effects of GIDL and SILC.

5. Strictly adhere to backend design rules. Following these rules in real circuits ensures new products leverage the full development and characterization efforts of suppliers, without having to reinvent the wheel.

NEW MATERIALS

The long history of aluminum metallization, tungsten vias, and silicon dioxide dielectrics provides medical electronics IC design with a stable and reliable platform. While this material set is not without reliability and yield issues, those topics are widely understood and controlled today. As all deep submicron interconnect schemes changed into the dual damascene Cu, low-k ILD processes around the 180 – 130nm technology nodes, there was a great loss in historical and physical understanding around interconnect performance and reliability. While the material change was driven largely by performance considerations (lower resistivity Cu) and reliability (electromigration performance), medical electronic IC design is not usually limited by these factors. However, the medical electronics industry has to adapt to this change in order to take advantage of modern IC processes.

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During the development of Cu-based interconnects, there was a great emphasis on the study of new failure modes including the risk of line-to-line leakage currents and transistor threshold drifting due to the potential for rapid Cu migration through the ILD materials [7]. The Cu deposition method of choice, electro-plating, coupled with the need to contain the Cu in the ILD trenches forced the use of higher resistance, refractory metals as barrier/seed layers in the design. During evaluation of these additional materials, reliability studies were conducted to ensure that there was a low risk of catastrophic-line leakage currents or transistor threshold drift. While these experiments and technology integration choices demonstrated highly reliable platforms, medical electronics IC design is not yet convinced. As discussed previously, a typical implantable pacemaker, consisting of several ICs, consumes about 105 – 106 times less power than a standard microprocessor, and leakage currents are a key consideration for acceptable system longevity. There is a need to better understand if the leakage current and defectivity levels that were good enough for commercial ICs in high volume are still appropriate for implantable electronics.

Stress migration in copper also poses a new reliability risk [8], especially given the changes in dielectric materials that accompany modern IC processes. This failure mode can lead to catastrophic IC functionality issues unless more rigorous design practices, such as forced redundant vias, are rigidly enforced. These new dielectric materials, which have moved away from stoichiometric SiO2, and entered the realm of more fragile porous glasses and softer polymers impact the assembly process as well [9]. Rigid adherence to assembly design rules and understanding their basis, in order to ensure that the requirements are consistent with ultra-low leakage medical electronics, is key for future use of advanced IC technologies.

As the medical electronics industry relies more heavily on commercial IC foundries, it is important that designers used to yesterday’s IC technologies are prepared to adapt to the new material realities.

FAILURE ANALYSIS

Because the medical device industry is regulated by various government agencies around the world, failure analysis plays an important role, where timely reporting is mandated by law. Also because of the life sustaining aspect of the product there tends to be higher degree of litigation involving medical products. Failure analysis plays a crucial role in understanding the impact of defects throughout device populations.

Quick understanding and resolution of issues is invariably of high priority. Failure analysis plays a key role in resolving/understanding performance issues and therefore plays a critical role in both preventative and corrective activities.

Design for failure analysis (DFFA) is an important part of ensuring timely information about failures. Building analysis tools into products is vital to ensuring quick localization of failures. Implantable medical device packaging tends to be complex and dense because volume and weight are important features for the customer. DFFA is an effective strategy to minimized complications from de-processing the IC from its final form factor. Many DFFA features can be designed into the product that allows minimally invasive testing of the IC. This IC testability can be performed at the system level in order to guarantee testability of the IC even while in its final form factor. It is critical to have close integration that allows

interaction between the system designer, the IC designer, and the FA engineer.

Failure analysis of medical device ICs is just as complex and challenging as the rest of the semiconductor industry. But there are some unique considerations for implantable electronics that pose additional challenges. Because of the battery operated nature of implantable products, operating currents tend to be orders of magnitude lower than what is typically seen in non-battery applications. Because of this, many techniques available for detecting and localizing excess currents are either not practical or require special sample preparation to work optimally.

One such technique is infrared emission microscopy which requires temperature-generating currents that may not be present in low current failures. Low current failures often require overdriving the device power supply in order to detect a thermal emission. Figure 12 shows an example of this technique.

Figure 12. Thermal infrared emission image of low current failure after overdriving the power supply.

Failure modes that may not be detectable in other applications become quite noticeable for low current applications, and failure rates that may not necessitate action in other applications are very noticeable in medical applications where even one failure may be significant. This subset of failures tends to be very unique, including new types of failure modes because they either are not detectable or of no consequence in most other applications. The failure analysis has to be especially cognizant of the fact that most of the failures are going to be related to distributions tails, or very unusual compound scenarios (perfect storm) that will not have been anticipated by rigorous reliability and design mitigation strategies already employed by semiconductor manufacturers and system designers.

SUMMARY

The implantable medical electronics market continues to strive for increased performance, just as the commercial semiconductor world. Because the performance metrics and design constraints of these two application arenas are notably different in several important ways, care must be taken to ensure that new medical products comprehend the changes that have taken place in moving into the deep submicron realm.

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With the increased cost of a modern wafer fab, reliance upon a vertically integrated semiconductor supply chain is not feasible, given the pressure to innovate and expand the therapy options that can be delivered by higher gate counts available in advanced technologies. More than ever, medical device manufacturers must take advantage of the knowledge gained throughout the microelectronics industry when making decisions on the appropriateness of a given technology, and the design, test, and qualification procedures necessary to ensure its continuing operation in a high reliability market with significant failure consequences.

At the same time, assuming that development processes of the commercial world address all the unique concerns of the implantable electronics industry is not a defensible position. This creates an interesting and quickly changing dynamic in the design of ever more complex systems.

REFERENCES

[1] Gerrish, P., et al, “Challenges and Constraints in Designing Implantable Medical ICs,” IEEE Trans. Dev. & Mat. Rel., Vol. 5, No. 3, Sept. 2005.

[2] Medical Implant Communications, http://wirelesss.fcc.gov. [3] Marras, A., et al, “Impact of gate-leakage currents on CMOS

circuit performance,” Microelectronics Reliability, v 45, 2005, p 499 – 506.

[4] Kaczer, B., et al, “Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability,” Microelectronics Reliability, v 47, 2007, p 559 – 566.

[5] International Technology Roadmap for Semiconductors (ITRS), 2006 Update, Semiconductor Industry Association.

[6] Gattiker, A., Nigh, P., “Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions,” International Test Conference (ITC), 2004, p 309 – 318.

[7] Loke, A.L.S., et al, “Kinetics of copper drift in low-κ polymer interlevel dielectrics,” IEEE Trans. on Electron Devices, Volume 46, No. 11, Nov. 1999, p 2178 – 2187.

[8] Ogawa, E.T., et al, “Stress-induced voiding under vias connected to wide Cu metal leads” Reliability Physics Symposium Proceedings, 2002, p 312 – 321.

[9] Saran, M., et al, “Elimination of bond-pad damage through structural reinforcement of intermetal dielectrics”, Reliability Physics Symposium Proceedings, 1998, p 225 – 231.

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