Performance evaluation of Carbon Nanotube based devices and circuits for VLSI design

Performance evaluation of Carbon Nanotube based devices and circuits

for VLSI design

Presented by: Under the Guidance of: Gaurav Soni Mr. Sanjeev Agrawal

2011PEV5030 Associate ProfessorVLSI Design ECE Dept., MNIT

A Presentation

on

Contents:1) Today’s requirements2) Why Carbon Nanotube?3) Carbon Electronics.4) Geometrical parameters of a Nanotube.5) Types of Nanotube and their application

in VLSI.6) CNT Field Effect Transistor.7) Simulation and Results.8) Conclusion.9) Challenges.10)References.

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Today’s Requirements

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Ultra high speed processors.Portable devices (low chip area).More functionality.Low power consumption.

“To fulfill above requirements we need to scale the devices and interconnects and follow Moore’s law.”

Why Carbon Nanotube (CNT)?

Problems in CMOS device scaling:Short channel effects (SCEs)-DIBL, velocity saturation,

mobility degradation.Leakage currents.Channel length and doping control.

Problems in copper interconnect scaling:Electro-migration-Grain boundary scattering, Surface

scattering.Hillock and void formationDiffusion barrier width.

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Why Carbon Nanotube (CNT)?

Electrical properties: high speed, compatibility with high-k dielectric layer, reduced short channel effects (SCEs), high current densities.

Physical properties: ideal candidate for nanotechnology due to small size (nm), strongest material.

Thermal properties: high thermal conductivity than copper. Hence, more tolerant to electro migration.

A promising candidate for future CMOS circuits and interconnects.

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Carbon Allotropes

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Carbon Electronics

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2-D Honeycomb lattice structure

Carbon Nanotube

Carbon Electronics

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2-D hexagonal Brillouin zone

Mobility of electrons and holes in graphene is equal, hence, high speed .

Band structure

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Chirality = (6,6)

Chirality= (7,0)

Depending on their band gap, the CNTs are either metallic or semiconducting. Metallic nanotubes are suitable as interconnects and semiconducting are suitable as transistor channel.

Ninithi Software

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(10,0)

(19,0)

(18,0)

(19,50)

Geometrical parameters

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Geometrical parameters:1. Chiral vector

C.2. Translational

vector T.3. Chiral angle θ.

C = 3a1+3a2= (3, 3)Hence (n, m)= (3,3)

(n, m)= Chiral indices

Chiral and Achiral Carbon Nanotube

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Carbon Nanotube types: A-Armchair; B-Zig-Zag; C-Chiral

For armchair: n=mFor zigzag: n=0 or m=0Chiral : n ≠m ≠0

Diameter of Nanotube

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Here, ‘a’ is lattice constant of graphene=0.246nm

Different chiralities can produce the same nanotube diameter. Hence diameter is not a unique parameter for characterizing CNTs.

If (n, m)= (19,0) then diameter= 1.489nm~1.5nm

Types of NanotubeDepending on the number of concentrically rolled up shells, CNTs can be further classified as:

SWCNT (Single walled CNTs) andMWCNT (Multi-walled CNTs)

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CNTFET-technology

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The operation principle and the device structure are similar to CMOS devices.

We can reuse the established CMOS design infrastructure and CMOS fabrication process.

CNTFET has the best experimentally demonstrated device current carrying ability.

CNT Field Effect Transistor

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Semiconducting CNTs are grown on quartz or silicon substrate in a straight and parallel pattern.Segments which are covered by gate are intrinsic CNT regions.Drain and source segments of CNTs are heavily doped to form P-type or N-type transistor


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Dielectric constant (SiO2, k2)=4, Gate dielectric (HfO2, k1)=16

Threshold voltage

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Vπ is carbon π to π bond energy (3.033 e V).

If (n, m)= (19,0), diameter = 1.489nm, then threshold voltage is 0.181 volts

CNTFET can work well at low supply voltages but the Si-MOSFET fails.

Multiple threshold circuit design possible using tubes of different diameter.

Simulation and Results

CNTFET Parameters used:1. Chirality= (19,0)2. Pitch(S)= 20nm.3. Diameter= 1.5nm4. Threshold voltage (N-CNTFET)= -0.1815. Threshold voltage (P-CNTFET)= 0.1816. No. of tubes(N)=3 7. Length=32nm8. Width=N*S=60nm9. Supply voltage=0.9V10. Load capacitance=20fF.

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Si-MOSFET Parameters used:1. Length=32nm2. Width (NMOS)=64nm3. Threshold voltage (NMOS)=

0.50884. Threshold voltage (PMOS)=

-0.455. (W/L)PMOS=3*(W/L)NMOS

6. Supply voltage=0.9V.7. Load capacitance=20fF.

For comparison of CNTFET and Si-MOSFET technology: Stanford University’s CNFET model and 32nm bulk BSIM-PTM model is used.

For performance evaluation power–delay product (PDP) metric is used. Power-delay product is a figure of merit for digital technologies. Its unit is joules.

Note: The sizing of a CNTFET is equivalent to adjusting the number of tubes.

Assumption

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CNTFETs are made of homogeneous, identical CNTs (i.e. well aligned parallel semiconducting CNTs that have the same chirality, same doping level and same inter-CNT pitch).

Inverter

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INVERTERTechnology Avg. power (in

watts)(from 1ns to 5ns)

Delay (in ps) PDP (in joules)

Si-MOSFET(supply=0.6V)

0.991 µW 24.858 24.634*10-18

Si-MOSFET(supply =0.9V)

2.199 µW 5.1916 11.416*10-18

CNTFET(supply=0.6V)

1.025 µW 1.3782 1.413*10-18

CNTFET(supply=0.9V)

2.201µW 1.0809 2.379*10-18

Effect of Chirality

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Chiral Number Average Power Delay

(5,5) 1.8871µw 5.3822ps

(10,0) 2.2068µw 3.6467ps

(10,5) 2.5301µw 2.1653ps

(19,0) 2.2015µw 1.0809ps

(19,5) 2.2465µw 1.1392ps

(19,19) 2.5037µw 0.9268ps

(18,0) 2.2572µw 1.3984ps

For supply voltage =0.9V, no. of tubes=3, pitch= 20nm

Effect of No. of tubes

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Number of tubes Average Power Consumption

Delay

1 2.187µw 1.078ps2 2.221µw 1.075ps3 2.202µw 1.080ps4 2.233µw 1.082ps5 2.233µw 1.083ps6 2.252µw 1.084ps7 2.275µw 1.084ps8 2.230µw 1.084ps9 2.275µw 1.085ps10 2.331µw 1.085ps20 3.611µw 1.086ps30 4.036µw 1.086ps50 5.245µw 1.086ps70 6.886µw 1.087ps100 8.797µw 1.046psFor supply voltage=0.9V, pitch= 20nm,

chirality=(19, 0)

Effect of Pitch

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Pitch Average power Delay4nm 2.1506µw 1.3291ps6nm 2.1701µw 1.4919ps8nm 2.1808µw 1.1518ps12nm 2.2100µw 1.1091ps16nm 2.2003µw 1.0905ps20nm 2.2015µw 1.0809ps30nm 2.2019µw 1.0709ps40nm 2.2022µw 1.0673ps50nm 2.2023µw 1.0656ps

For supply voltage=0.9V, chirality= (19,0), no. of tubes=3

FO4 Inverter

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Fan–out of 4 is a process-independent delay-metric used in digital CMOS technologies.

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FO4-INVERTER

Technology Delay (in ps)

Si-MOSFET(Size of successive inverters in ratio 1:4:16:64:256)

15.151

CNTFET (For no. of tubes in successive inverters in ratio 1:4:16:64:256)

2.648

CNTFET(For no. of tubes in successive inverters in ratio 3:12:48:192:768)

2.543

Increasing the number of tubes in CNTFET decreases the delay.

NAND Gate

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NAND GATE

Technology Avg. power (in watts)


Si-MOSFET 1.4180*10-7 11.788 16.7154*10-19

CNTFET 0.9766*10-7 5.0012 4.8842*10-19

NOR Gate

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NOR GATE



Si-MOSFET 1.3456*10-7 9.5237 12.815*10-19

CNTFET 0.7323*10-7 6.3952 4.683*10-19

EX-OR Gate

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EX-OR GATE



Si-MOSFET 1.428*10-7 16.941 24.192*10-19

CNTFET 0.67181*10-7 9.051 6.081*10-19

2:1 MUX

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2:1 MUX Technology Avg. power (in watts) Delay (in ps) PDP (in

joules)Si-MOSFET 2.1146*10-7 34.308 72.547*10-19

CNTFET 1.1147*10-7 11.552 12.770*10-19

Low power D-LATCH

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Truth table

D Q

0 0

1 1

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D-LATCH


Si-MOSFET 7.6005*10-7

CNTFET 0.7912*10-7

Low power SRAM Cell

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Technology Parameters Avg. power (in watts)

Si-MOSFET (W/L)PMOS = 3*(W/L)NMOS

(W/L)ACCESS NMOS = (W/L)NMOS3.2125*10-7

Si-MOSFET (W/L)PMOS = 3*(W/L)NMOS

(W/L)ACCESS NMOS = 5*(W/L)NMOS3.2331*10-7

CNTFET No. of tubes in allp-CNTFET=1 and n-CNTFET=1

and No.of tubes in access n-CNTFET=1

0.8035*10-7



1.6345*10-7



2.4293*10-7



1.9923*10-7

Conclusion

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The power-delay product of CNT based devices and circuits is low as compared to Si-MOSFET based.

“CNT technology is a potential candidate for next generation VLSI design.”

Challenges

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•It is not possible to guarantee perfect alignment and positioning of all carbon nanotubes in large scale CNTFETs circuits. Mispositioned CNTs can cause incorrect logic functionality.

•Separation of metallic and semiconducting CNTs. Metallic CNTs can cause source to drain shorts inside CNTFETs.

•It is difficult to control the energy band gap of the nanotubes. The band gap of a CNT is dependent on its diameter and chirality, which is uncontrollable during growth.

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•The diameter variation also affects the threshold voltage.

•Variation in the density of grown CNTs.

•Susceptibility of CNTFETs to noise.

•High contact resistance with metal contacts.

References

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[1] Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S.P. Wong and Subhasish Mitra, “Robust Digital VLSI using Carbon Nanotubes”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.31 ,no. 4, April 2012.[2] J. Deng and H.-S. P. Wong “A compact SPICE model for carbon nanotube field effect transistors including non-idealities and its application-part I: Model of the intrinsic channel region”, IEEE Trans. Elec. Dev., vol. 54, no. 12, pp.3186 -3194 2007.

[3] J. Deng and H. S. P. Wong “A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-part II: Full device model and circuit performance benchmarking”, IEEE Trans. Elec. Dev., vol. 54, no. 12, pp.3195 -3205 2007. [4] Yuji Awano, Shintaro Sato, Mizuhisa Nihei, Tadashi Sakai, Yutaka Ohno and Takashi Mizutani, “Carbon Nanotubes for VLSI: Interconnect and Transistor Applications”, Proceedings of the IEEE, Volume: 98, Issue: 12, Dec. 2010 [5] Naushad Alam, A.K.Kureshi, M. Hasan and T. Arslan, “Carbon nanotube interconnects for low-power high-speed applications”, IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009.

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[6] Hong Li, Chuan Xu and Kaustav Banerjee, “Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs”, IEEE Design & Test of Computers, Volume: 27, Issue: 4, 2010.

[7] H.-S.P. Wong, S. Mitra, D. Akinwande, C. Beasley, Yang Chai, Hong-Yu Chen , Xiangyu Chen , G. Close, Jie Deng , A. Hazeghi, Jiale Liang, A. Lin, L.S. Liyanage, Jieying Luo, J. Parker, N. Patil, M. Shulaker, Hai Wei, Lan Wei and Jie Zhang , “ Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection”, IEEE International Electron Devices Meeting (IEDM), Dec. 2011.[8] A Quick User Guide on Stanford University Carbon Nanotube Field Effect Transistors (CNFET) HSPICE Model v. 2.2.1, 2008.[9] S. M. Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits (Analysis and Design)”, 3rd ed. McGraw-Hill 2007.

[10] H.-S.Philip Wong and Deji Akinwande, “Carbon Nanotube and Graphene Device Physics”, 1st ed. Cambridge University Press, 2011.

[11] R. Jacob Baker, “CMOS: Circuit Design, Layout, and Simulation”, 3rd. ed.Wiley 2010.[12] Franz Kreupl. Carbon Nanotubes in Microelectronic Applications, “Carbon Nanotube Devices: Properties, Modeling, Integration and Applications”, Christofer Hierold (Ed.), Wiley-VCH, 2008

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[13] Davood Fathi and Behjat Forouzandeh (2010). Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits,“Carbon Nanotubes”, Jose Mauricio Marulanda (Ed.), ISBN: 978-953-307-054-4, InTech.

[14] Mayank Rai and Sankar Sarkar (2011). Carbon Nanotube as a VLSI Interconnect, “Electronic Properties of Carbon Nanotubes”, Prof. Jose Mauricio Marulanda (Ed.), ISBN: 978-953-307-499-3, InTech.

[15] Rafael Vargas-Bernal and Gabriel Herrera-Pérez (2012). Carbon Nanotube- and Graphene Based Devices,Circuits and Sensors for VLSI Design,“VLSI Design”, Dr. Esteban Tlelo-Cuautle (Ed.), ISBN: 978-953-307-884-7, InTech.

Performance evaluation of Carbon Nanotube based devices and circuits for VLSI design

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