CAD for VLSI: Symple: a symbolic layout tool for bipolar and MOS VLSI

CAD FOR VLSI

Symple: a symbolic layout tool for bipolar and MOSVLSI

K.S.B. SzaboJ.M. LeaskM.I. Elmasry

Indexing terms: Integrated circuits, Computer-aided design, Circuit theory and design, semiconductor devices and materials

Abstract: Symbolic layout offers a powerful andflexible methodology for the design of bipolar andMOS cells. An integrated set of symbols thataddresses both bipolar and MOS devices was pre-viously reported. A design tool that implementsthe symbolic methodology based on that set hasbeen developed; Symple is a process-independent layout editor that allows the designerto symbolically create cells in bipolar, NMOS,CMOS, mixed BIMOS, or a mixed BICMOStechnology. While the program abstracts most ofthe process complexities from the designer, it alsoretains the relevant layout features. Mechanismsfor compaction, mask generation and circuitextraction are included.

1 Introduction

Symple is a symbolic process-independent /ayout editorwhich implements the symbolic layout methodology pre-sented in References 1-3. The methodology has theunique feature of providing a small set of symbolic primi-tives that allow construction of bipolar and MOS circuitstructures. Thus, it can be used for cell design in anyavailable bipolar, NMOS, CMOS, BIMOS, or BICMOStechnology. In Symple, mechanisms for editing, compac-tion, mask generation and circuit extraction are available.Symple also allows incorporation of other mask filescreated by mask level editors, or module generators,within the symbolic design.

In the implementation of Symple we have used exist-ing software engineering techniques whenever they areappropriate. For instance, Symple uses virtual-grid com-paction (with grid breaking), sparse-matrix techniques forstoring and editing data, a device-independent graphicspackage for graphical I/O, and multiple edit windowswith a menu-driven user interface. Symple also intro-duces some new techniques, and modifications to existingones. For example, Symple uses a new method for rep-resenting technology where mask constructuion detailsand design rules are written in an interpreted language,and a new method of expressing user interaction as astate machine (this machine ties together menu-contents,presentation of menus, state transitions according to

Paper 59781 (E3, C6), first received 30th September 1986 and in revisedform 15th December 1987Mr Szabo and Mr Leask are with Bell Northern Research, PO Box3511, Ottowa, Ontario Canada K1Y 4H7

Mr Elmasry is with the Department of Electrical Engineering, Uni-versity of Waterloo, Waterloo, Ontario, Canada N2L 3G1

menu choices, gathering user input, and interfacing withthe program that implements the editing functions). Asingle data structure (neighbour-pointers) is used forcompaction, circuit extraction, mask generation, andediting processes. Implementing a new methodology,which uses a different notation from previous systems [1,4, 5], allows a simplified compaction process to operateon the basis of symbol-to-symbol rules, rather than onthe basis of mask (design) rules. Compaction is imple-mented as an editing step where the designer is free tomodify the compactor's symbolic output, which is in thesame form as its input.

This paper briefly reviews the symbolic notation pre-sented in References 1-3 and reports on the implementa-tion of the CAD tool which supports it; Symple is asymbolic layout system that runs on turn-key as well asopen systems. It has been ported to the Sun and Apolloworkstations, Daisy chipmaster, DEC Vax systems withAED512 colour terminals and Ikonas 3000 frame buffers,and Orcatech 3000 workstations.

2 Brief overview of notation

The symbolic language used by Symple was originallydeveloped by Elmasry [3] and was extended by Leask[5] and Szabo [4] for bipolar/CMOS design. The sym-bology consists of point and line symbols. Point symbolsdenote a device feature; line symbols are used to inter-connect these features. Metal, poly, and diffusion linesprovide electrical interconnection while the buried-layerand well-wire line symbols provide physcial intercon-nection. Physical connection allows bipolar devices to bebuilt from the point symbol primitives; many differentbipolar structures can be expressed with the small symbolset. MOS devices are built by crossing diffusion and polylines. Interconnection with well wire indicates that thesedevices may be merged into a single well. Figs. 1-4 showthe symbol set and devices constructed with thesesymbols. Reference 1 contains a detailed discussion of thenotation.

3 Structure of the Symple system

Symple's overall structure is divided into three levels asshown in Fig. 5. The top level is a symbolic editor thatprovides for the manipulation of line and point symbolsusing a graphical display. The second level of Sympledefines the symbol syntax or legal combination of lineand point symbols which make up the symbolic notation.Only legal constructs are defined and errors such as n-diffusion crossing p-diffusion are recognised. The thirdlevel defines the technology rules for a specific symbol set

IEE PROCEEDINGS, Vol. 135, Pt. I, No. 2, APRIL 1988 29

and given technologies. For any one symbolic notationseveral technology files may exist. An example would bethe MOS symbol set which could have 3 /mi and 1.5 /mi

with each symbol, the geometry associated with eachsymbol and all design rules. Geometry is described in atextual form based on EDIF [6]. Device generating func-

B/W colour

orange

green

blue

red

-magenta

grey

purple

symbol

well-wire

n-diff usion

p-diffusion

gate poly

poly 2

first metal

secondmetal

Fig. 1 CMOS/NMOS symbol set

B/W

OXV\y

1 1

2ZZZ2

colour

(__) green

X «<.V7 green

^ J ^ black

[><] red

[ | white

orange

grey

purple

red

symbol

emitter

base

collector

Schottky

II L injector

VIA

buried n +

first metal

second metal

polysilicon

B/W

V

a

xa

colour

black

V green

blue

r~l yellow

red

Xblack

black

symbol

contactpoly,diff,met

pwellcontact

nwellcontact

implant

capacitor

polyresistor

VIA

bondingpad

devices in symbolic form

oooxvH § V

HOOOV

X X V

i y\y

n ~Y 'ia

I ^&

description

npn

pnp

II L

resistor

nMOS

pMOS

n-depletion

met, di f f ,

well contact

Fig. 2 Bipolar symbol set and devices made from symbols

a Gnd b

Fig. 3 Schematic and symbolic forms of an STTL NAND gate

design rules, as well as n-well, p-well or twin-tub CMOStechnologies. The technology level describes all tech-nology specific data such as the mask levels associated

tions may be parametrised by process, technology, anduser variables; they may also use conditional statementsto modify geometry according to various parameters andthe symbolic description.

The Symple symbolic editor consists of five majormodules; these are database, file system interface, menuplus interaction control, graphical input/output, andtechnology scetions. Data are not shared between any ofthese modules. Instead they communicate through welldefined interfaces, illustrated in Fig. 6. In the followingsections we will examine the most significant character-istics and the design issues of these modules.

30 IEE PROCEEDINGS, Vol. 135, Pt. 1, No. 2, APRIL 1988

4 Database

The database module is the only portion of the programwhich manipulates the symbolic data storage. The data-base represents wires, point symbols, and cells. At this

symbolic editor

manipulate linesand points

symbol syntax rules

J_symbol set 1

2 11

legal symbolsand symbolcombinations

technology rules

" _[

rules 2 |_|

mask layersgeometriesdesign rules

Fig. 4 Schematic and symbolic forms of a BICMOS differential ampli-fier

user interface- menus- windows- editor command

sequence

symbol editing- add symbols- delete symbols- legal constructs

technology information- compaction- mask generation- other tools

Fig. 5 Symple system structure

level the database manipulation routines do not recog-nise the Symple symbol set or electrical devices. For effi-ciency, the compactor has access to the data of thismodule. A set of interface routines allows the database tobe edited and searched; the rest of Symple regards thedatabase as an abstract data type.

Data structures for a program such as Symple need tosupport rapid insert/delete operations and inexpensivesearches for neighbouring features. The former require-ment allows the structure to support the editor, the latterallows the compaction process to work efficiently. Weconsidered using two data structures (one optimised forcompaction, the other supporting editing), but rejectedthis because the normal use of the tool would result inmuch redundant conversion between the two representa-tions. The connections and symbols of the stick diagramsuggest that the data should be stored in a linked form;we examined a number of standard data structures fortheir applicability. A binary tree supports rapid areasearches, insertion, and deletion, but is weak for connec-tivity and neighbour searching. For example, finding aleaf-node's neighbour could involve a search that goes tothe root of the tree before it finds the branch that has theneighbouring point. Fig. 7 shows the neighbour findingproblem in a simplified single dimension tree. Rosenberg[7] recently investigated K-D Trees for VLSI databases.While it is true that the K-D tree provides faster region

searches and other advantages, the structure is also ineffi-cient for determining connectivity and nearness of neigh-bouring features. Alternatively, Ousterhout [8] has

draw

symbols

draw

userinterfacecontroller

add/delete

query

displaymanager

redraweditoryankbufferundobuffer

deviceindependentgraphics

text/vectorst

interactionget coordsmove wind

1menusystem

DaisyChipmaster

Fig. 6 Major modules of Symple

neighbours

nodes are doubly linked to allowlocation of parent nodes

Fig. 7 Binary tree data structure

proposed a data structure for compaction and routing,called corner-stitching. One advantage of this system isthat the corner stitched database explicitly representsempty space in the data; this allows one to find spacethat can be squeezed from the mask or used for routingsignals. The structure breaks the layout into rectangulartiles of occupied and empty space. Tiles are linkedtogether via pointers at the lower left and upper rightcorners, in a patchwork fashion. However, for Symple, itis preferable that the data structure explicitly representpoints, lines, and areas. Corner-stitching represents sym-bolic mask information as rectangular areas but it doesnot support zero and one-dimensional objects well.


A superior data structure for Symple is one in whicheach item of interest (i.e. symbol) is a node in a twodimensional matrix of linked nodes. This arrangement iscalled 'neighbour pointers'. There are variations of neigh-bour pointers employed in other layout editors; e.g. theElectric system [9, 10] sorts all nodes on the basis ofx and y coordinates, and maintains two linked listswith the nodes inserted at the appropriate point. Thisarrangement is costly because all additions, deletions andsearches require O(N) time. Electric must also maintaina separate data structure to represent connectivity.

The data structure adopted in Symple is based on thearrangement of neighbour pointers illustrated in Fig. 8;

data node

Y l is t

X l is t

root of structure

Fig. 8 Linked array of nodes using neighbour pointers

this is an adaptation of sparse-matrix techniques [11]. Toillustrate the use of this structure a simple symboliclayout is shown in Fig. 9. The schematic represents amulti-emitter transistor and a base pull-up resistor (Fig.9a); its associated symbolic layout [1, 2] id shown in Fig.9b and the data generated for this layout is in Fig. 10.Each node in the structure has the type NODE asdefined in Fig. 11. Pointers are bidirectionally linkedallowing quick insertion and removal, plus bidirectionalsearching. The data also allow one to quickly determineconnectivity between elements. Neighbour pointers deter-mine which nodes are topologically adjacent, and thewire information represents the size of a wire between thenode and its neighbours. Note that wire information doesnot explicitly specify the connection to other nodes sinceadjacent nodes are found by the up_ptr, down_ptr,left_ptr, and right_ptr pointers. A size of zero representsunconnected neighbours. The actual wire size informa-tion is represented in separate strictures. Each wire type(nplus, first and second metal) can have one of 1 ...max_wire_size wire sizes (see Fig. 11). Symple has 255different wire sizes for this implementation, thus allowingeach wire type to fit into a 32 bit value. The wire sizereferences a structure (wire info) which stores the actualwire width (for metal) or resistance/transistor size (forwell wire). Indirection not only results in compact

storage, but simplifies alterations to the design. One mayattach names to the different component 'sizes' e.g.Pullup-Tran, Load-Res, Base-Res 1, Base-Res2 and design

inputsoutput

v \y v~7

inputso

output

Fig. 9 Simple bipolar circuit

a Schematic diagram of multiemitter npn transistorb Symbolic representation

empty node (supports wire endpoints and intersections)

node points to list of nodes at X=2

symbol of type X (base)resides at this node

bidirectionally linked nodes

C_J (J) nodes linked, metal extends between them

nodes linked, buried layer extends between them

nodes linked, buried and metal extends between them

Fig. 10 Data generated for the circuit of Fig. 9

with these names. If a change to all load resistors isrequired one simply changes the resistor value that corre-sponds to load-res; this is a form of cell parametrisa-tion.

Cells are represented as a node in the data whichpoints to the root of the 'called' cell, and are outlinedwith cell wire (to represent the cell's area). Wires cannotextend into the cell, they must terminate on 'pins' at thecell's edge. After compaction the cell fixes the spacing ofthese pins; pitch matching between cells is accomplished

32 IEE PROCEEDINGS, Vol. 135, Pt. I, No. 2, APRIL 1988

through user constraints which force the pins to exist atknown positions.

Editing operations such as deleting wires and movingareas are easily implemented since it is straightforward to

TYPEdirection = (up, down, left, right);wire_item = record

size : integer;aspect_ratio : real;resistance : integer;end;

wire_ = (0 ... max_wire_sizes);wire_info = array [wire_index] of wire_item;wire = array [direction] of wire_index;ndtype = (root, yaxis, xaxis, data);symboltype = (emitter, base, collector, schottky,

injector, PMOS, NMOS, depletion,PsubContact, NsubContact, contact,polycapacitor, bondingpad, via, label,pin, cell);

nodeptrNODE

= * node;= recordnodetypesymbolswellwiren-diffp-diflFpolypoly2first_metalsecond_metalup_ptrdown_ptrleft_ptrright_ptrx_positiony_positionend;

: ndtype;: set of symboltype: wire;: wire;: wire;: wire;: wire;: wire;: wire;: nodeptr;: nodeptr;: nodeptr;: nodeptr;: integer;: integer;

Fig. 11 Data structure for a node

isolate the extent of the object in question and performan operation on it. Basic operations on this structure areshown in Fig. 12. The algorithm SearchArea() returns allobjects within a given area and has n1/2 average run timefor typical VLSI layouts. A high-aspect-ratio layout,where the x (or y) dimension is very much larger than they (or x) dimension, would force the worst-case linear (n)run time; however, such layouts do not usually occur inpractice.

The neighbour pointer data structure is not new, butnormally is only used in the compaction process (e.g.Mulga [12] uses them there); in Symple, neighbour poin-ters are used as the main data representation. This allowsSymple to quickly place the data in a format for compac-tion. Another advantage of this scheme is that the layoutpreserves the notion of a connection; when altering thelayout (editing), movement of circuit-blocks will stretchconnections but not break them unless explicitlyrequested. Most mask design systems available todayonly represent the circuit as polygonal data on differentplanes and movement of one portion of the circuitusually requires the designer to manually reconnect thebroken metallisation paths.

5 Circuit extraction

In conventional mask-based CAD systems, circuit (ornetlist) extraction from mask level data involves identify-ing basic devices, finding interconnections, and propagat-ing the signal and labels through the circuit. Since

Symple keeps its database in a sorted, symbolic form itdoes not require any mask analysis steps; thus circuitextraction is an inexpensive operation which can be per-formed interactively.

Search Area (area: AREA)var

xPtr, ndPtr:NodePtr;begin

xPtr ~ root". right_ptr;while (xPtr'.nodeType = XLIST)(xPtr'.xPos < area.xMin) dobegin

xPtr ••= xPtr".right_ptr;endwhile (xPtr'.nodeType = XLIST)(xPtr.xPos <= area.xMax) dobegin

ndPtr == ndPtrA.up_ptr;while (ndPtr'.nodeType = DATA) and(ndPtr'.ypos < area.yMin) dobegin

ndPtr := ndPtr".up_ptr;endwhile (ndPtr'.nodeType = DATA) and(ndPtr'.yPos <= area.yMax) dobegin

outputNode (ndPtr);ndPtr ~ ndPtr".up_ptr;

endxPtr ~ xPtr~.right_ptr;

and

and

endend

Deleteltem (location: AREA)var

xPtr, ndPtr:NodePtr;begin

Search Area (location);ndPtr ~ getOutputNode();

if ndPtr < > 0 thenbegin

ndPtr".right_ptrMeft_ptr := ndPtrMeft_ptr;ndPtr.lefr.right_ptr — ndPtr~.right_ptr;ndPtr".up_ptr".down_ptr; := ndPtr*.down_ptr;ndPtr/>.down_ptr.".up_ptr := ndPtr".up_ptr;free (nodePtr);

end

Fig. 12

end

Operations on the database

Connectivity analysis consists of propagating the nodelabels, or names, to all connected nodes. Symple uses adepth-first graph search to propagate labels (a simplifiedversion is shown in Fig. 13). Since the connectivity graphusually has cycles, the algorithm records and avoidsthose nodes that have been visited. Labels are initiallynumerals assigned by the system. Once the whole datastructure has been traversed, the system determineswhich nodes have already been named by the designerand substitutes these labels. A subsequent scan of thedatabase locates devices. As each device is encountered itis written out to a net list with its node label.

Symple provides a SPICE [13] compatible net list forexact circuit simulations. In the future we plan to addgate level descriptions of the various modules and haveSymple provide an input for logic simulation. The gatelevel descriptions would allow automatic verification ofthe cell's function and thus further guarantee design cor-rectness.


6 Compaction

Compaction refers to the conversion of topological (i.e.relative placement) data to a correctly spaced masklayout. It is considered to be a linear programming

init_propagate()begin

for all nodes beginnode ".visited — FALSE;

endend

propagate (node)begin

if (node".visited) return;node ".visited := TRUE;if (node ".metaljeft) propagate (node Meft_ptr);if (node~.metal_right) propagate (node".right_ptr);if (node".metal_up) propagate (node".up_ptr);if (node".metal_down) propagate (node".down_ptr);

node".node_number = current_node_name;end

propagate_labels()begin

init_propagate();current_node_name — 1;for all nodes begin

if (rnode".visited) then beginpropagate (node);

current_node_name :=current_node_name + 1;

endend

end

Fig. 13 Propagate labels through the data structure

problem; the goal is usually minimum area with the con-straints consisting of process design rules. True two-dimensional compaction is very difficult to solve in bothalgorithm design and computer time. Only very recentlyhave algorithms for solving this problem appeared in theliterature [14]. However, the compaction process may besimplified into two steps, a horizontal and a vertical com-paction. This technique is used in many compactors (e.g.Cabbage [15], Mulga [16], Rest [17], Slim [18], Vivid[19] etc.) and generally gives acceptable results. Since thistechnique cannot consider placement in both dimensionsthe compaction is not optimum. In the Mulga [16] andVivid [19] systems the layout resides on a virtual grid;the designer specifies a topology with no initial regard forspacing or design rules. An efficient compaction algo-rithm uses the grid system to find the smallest possiblegrid spacing for the symbolic diagram. The inter-gridconstraints are calculated during compaction; these setthe grid spacing. It is up to the designer to ensure that apoor layout does not force intergrid spacing to be detri-mentally large. The Cabbage [15], Rest [17], Slim [18],SLS [20], and other systems employ a one-dimensionalgraph based compaction technique. These systems aresaid to be gridless; compaction is based on intradeviceconstraints which are solved by the compaction algo-rithm (usually using graph techniques). In general, thegraph based compaction is superior to the virtual gridtechnique [21].

In many symbolic layout systems the compactionoperation is often used in a global sense, e.g. a design isgenerated, flattened, and compacted as a whole. Forexample Slim [18] and Cabbage [15] take this approach.In these systems, it is rarely possible to optimise the

layout by modification and recompaction of the com-pactor's output. Use of a global compaction step can beavoided in an interactive environment (such as Symple)since it is usually necessary to compact only the circuit ofpresent interest. Single cell compaction does not need thecomplicated multiple goal, multiple strategy compactionused in Slim; this greatly simplifies the compactor.

Compaction, as implemented in the prototype ofSymple, is based on the virtual grid scheme, extendedwith grouping and grid-breaking. Virtual grid compac-tion (without grid-breaking) is a degenerate case of theone-dimensional graph-based compactor, but mucheasier to implement. In this system symbols are nevermoved from their assigned position on the integer Carte-sian plane. The space that is represented by adjacentabscissa (and ordinate) is, however, nonuniform; it is cal-culated by examining neighbouring symbols on adjacentgrid lines. This is equivalent to constraining unrelateditems, which happen to share the same x or y coordinate,to 'line up' after the compaction process. Grid breakingremoves these constraints and gives results similar tograph-based compaction. The process of compactionalong the x axis is shown in Fig. 14. The actions along

COMPACTION:Parse layout to determine symbol size, type, and devices thatthe symbols are part of.Identify electrical and 'physical' nets. (Physical nets consistof symbols that are physically connected, but not in the sameelectrical net).Set scanline to leftmost grid line. All symbols are unplaced;frontier of interfering symbols is empty.REPEAT

Identify a group of symbols (usually a physical net,groups must move as a unit).Determine group to placed-symbols spacing(look left for interfering symbols, using 'mostrecently interfering symbols' technique).Move group to consume unused space.Update frontier data structure for interfering symbols.Check user (upper bound) constraints.IF constraints not satisfied THEN

Move group that failed upper bound con-straints(this group will be part of the previouslyplaced symbols).Back up compaction scan line to this gridline.

Rebuild frontier for this scan line.ELSE

IF no more groups on this scanline THENAdvance scanline to next grid.

Fig. 14 Virtual grid compaction with grouping and grid breaking

the y axis are a separate pass; they are identical. An addi-tional check for oblique interference is performed in thesecond pass. After the two passes the symbolic layout willsatisfy the design rules and have a smaller grid spacing.The groups that are tagged form the critical path, i.e. thepath from left to right (or top to bottom) which preventsany further compaction. Symple highlights the 'marked'nodes and components once compaction is finished. Thisallows the user/designer to quickly isolate the criticalspacing in her circuit.

In Symple, compaction takes place without mask con-version; design rules are specified in symbol-to-symbol


spacings. This is sufficient because the notation providessymbols that represent the major physical and electricalpieces of the device, and these basic parts closely conformto the various protection frames which are associatedwith the device [22, 23]. The symbol-per-device notationof most existing symbolic layout systems prevents themfrom efficiently using this technique because there is nosymbolic differentiation between the different regions of adevice. Compaction in the symbolic domain also has theadvantage of producing symbolic output; this output canbe subject to further editing and compacting steps. Thecompactor is process-independent, but not notation-independent.

During the compaction phase the compactor keepstrack of the 'most recently interfering symbols'. The mostrecent layers algorithm, which we are using at the sym-bolic level, was originally proposed for virtual grid com-paction [24] (it maintained a list of interfering masklayers), and has been used in the Vivid system [19]. Thistechnique reduces the amount of searching and back-tracking required to determine spacing. If one looks at acompaction in progress, the compacted section looks likean uneven frontier of obstructing symbols (see Fig. 15).

bipolarsticklayout

y--3 [

y=2

current grid line

mostrecentsymbolinformation

y=1 •M

Fig. 15 Most recent layers algorithm

M metaln+ device

After each symbol is repositioned the frontier is updatedto show that this symbol may interfere with symbols notyet compacted. Many of these interfering structures aredifficult to locate via neighbour pointers, and the com-pacter needs to locate diagonally interfering featureswhich cannot easily be found through neighbour pointersalone.

The compactor must also look for 'over-constrained'structures which create a cycle in the positional depen-dence graph (Fig. 16 illustrates this problem). The com-pactor of Liao and Wong [25] identifies over-constraintsby counting iterations over the constraint graph; Sympleuses the same detection algorithm. At this time, Symplecannot relax constraints and continue with the compac-tion.

This compaction scheme was straightforward toimplement, and is quite reliable. Our approach convertsthe compaction step into an interactive editing process;the designer regains control over the mask outputwithout reassuming the tedium of mask layout. We arealso investigating wire length minimisation methods(Schiele [26]) for placing the unconstrained elements;these algorithms couple horizontal and vertical compac-tion passes, thus improving the performance of the com-pactor and the electrical performance of the circuit. Inour prototype, jog insertion was not included due to the

necessary increase in compactor complexity and becauseof Weste's observation that jogs did not improve virtual-grid layouts substantially. However, graph-based com-paction does perform better with jog insertion (Wolf

resistor length = 10units

v ;

o r

b a s e to c o l l e c t o r d i s t a n c e = 1 un i t

Fig. 16 Over-constrained structure

[21]) and future work will look at algorithms for auto-matic jog insertion in our data structure.

7 Technology database and mask generation

Processing technologies tend to defy all attempts torationalise and generalise; ideally the symbol-to-maskconversion routines should be written anew for eachmajor process. To avoid altering Symple's internal sourcecode, an EDIF [6] (electronic data interchange format)based geometry-oriented language is provided for defin-ing mask construction. Adopting EDIF has simplifiedand amplified the capabilities of our design and tech-nology databases. EDIF resembles Lisp [27] in syntax(Fig. 17), resulting in an easily parsed, and easily

(keyword-operation argument 1 arg2 arg3 arg4 ...)( -open a statement

keyword-op -define operationarguments -arguments for the keyboard

can contain other statements,) -close statementThe following statement describes a rectangle of metal.

(figureGroup METAL_1(rectangle

(point -400 -400)(point +400 +400)))

Fig. 17 EDIF syntax

extended, language. It has high level constructs fordescribing mask features and simple control structuressuch as loop and if then else. At program startup, theprocess section reads a technology file that describes thephysical structure, simulation information, separations,and legal combinations of symbols. The physical struc-ture, symbol separations, and simulation information arecompiled into code for an abstract stack machine. Thecode is interpreted and results conveyed to the mask gen-erator, compactor, or circuit extractor when required.Legal symbol combinations (e.g. syntax) are defined byregular expressions; these are also compiled into an inter-nal form at program startup.

Symple's compactor uses design rules which specifysymbolic spacing rather than physical mask spacing. This


major simplification is possible because the symbolicnotation reflects key constraints of the process as inter-symbol spacing; e.g. mask level design rules, whenapplied to the symbolic layout, manifest themselves as aset of spacings between symbols. The onus is on theauthor of the process file to ensure that the symbolspacing and mask-conversion routines are consistent;these may be parametrised as functions of device typeand size.

Fragments of a technology file are shown in Fig. 18and Fig. 19. Symple requires devices to have collinear

;values in microns;the symbolic variable 'symplesymboF is used to communicate;between SYMPLE and the technology file interpreter.(assign contact_size 5)(assign metal l_size 7)(assign metal2_size 9)

(keyword makepoint(formal size)(build point size size))

(keyword wire_to_rectangle(formal endl end2 size)(build rectangle

(build + endl (build makepoint size))(build — end2 (build makepoint size))))

(cell metal 1(view maskLayout Physical)(contents

(figureGroup METAL 1(wire_to_rectangle

(wirevalue symplesymbol)metal 1 size))))

(cell via

(contents(view maskLayout Physical)

(figureGroup METAL 1(wire_to_rectangle

(pointvaluesymplesymbol)metal l_size))

(figureGroup METAL2(wire_to_rectangle

(pointvaluesymplesymbol)metal2_size))

(figureGroup CONTACT(wire_to_rectangle

(pointvaluesymplesymbol)contact_size))))

Fig. 18 Process file description of wires

ports and Manhattan interconnection. The processmodule allows any geometry within devices but the com-pactor assumes devices have a rectangular bounding box.To generate the masks for a device, Symple parses thesymbolic layout using regular-expression matching tech-niques, and then invokes the mask constructors for eachpoint and line symbol. The mask constructors accessthree main pieces of information.

(a) the type of device the symbol is part of (as deter-mined by the parsing operation)

(b) a symbolic device type that is assigned by thedesigner (e.g. W/L, ohms, etc.)

(c) context information which indicates neighbouringsymbols and wire interconnect.

Fig. 20 illustrates the process of mask generation. Theburied layer generates a set of cap masks and the ele-

ments of the transistor (emitters, bases and collectors)generate partial masks that form a transistor whenbutted. Note that the example technology creates a tran-

; description is simplified

(cell emitter(view maskLayout Physical

(contents(figureGroup PDIFFUSION

(rectangle base_diffusion_size))(figureGroup NDIFFUSION

(rectangle diffusion_size))(figureGroup CONTACT

(rectangle contact_size))(figureGroup METAL 1

(rectangle metal_size))))

(cell base(view maskLayout Physical

(contents(if (= neighbour_symbol base)

; make a resistor betweenthe two base symbols.(make_resistor (symbolizesymplesymbol))

;else;make a base contact for a transistor((figureGroup PDIFFUSION

(rectangle base_diffusion_size))(figureGroup CONTACT

(rectangle contact_size))(figureGroup METAL 1

(rectangle metal_size)

Fig. 19 Process file description of transistors

cap emitter emitter base collector cap

I • I GO 0 I a I

Fig. 20 Output from a mask generation step for a single transistor

sistor in a very simplistic fashion. More intelligence ispossible since the technology description allows decisionlogic (control structures) in the transistor description.

8 Symbol syntax rules

The symbol syntax of Symple defines the symbolic nota-tion used in an editing session. There are two major oper-ations performed by this section; the first defines all lineand point symbols in the notation. This includes namingeach symbol and describing the visual characteristicssuch as shape and colour that is associated with thesymbol. The second is the definition of the legal com-binations of symbols. These syntax rules are shared withthe technology section but, at this level, do not havegeometries associated with them.

The syntax information for a symbol indicates othersymbols which must be present, cannot be present, or are


optional. It is only necessary to explicitly list the requiredand optional symbols. Unmentioned symbols are notallowed to coexist. Adding and deleting symbols are twobasic editing operations that require syntax checking.

The handling of MOS transistors illustrates an inter-esting feature of the symbol syntax file. An MOS tran-sistor is represented as the crossing of two line symbols,however a transistor point symbol is required to store thedetails of the transistor at that location. By using theintersect feature, illustrated in the definition of the p-diffusion in Fig. 21, Symple allows a special operation tobe executed if the new symbol intersects with the symbolin the database. A similar intersect statement would bepresent in the definition of the gate poly line symbol,allowing a PMOS transistor to also be formed by cross-ing gate poly with an existing p-diffusion.

5; This is a partial description of the CMOS symbolic notation; create a symbolic constant(assign RED (100 0 0)); define a cross symbol(assign cross ((path (point —10 —10) (point 10 10))

(path (point 10 -10) (point -10 10))))(symNotation CMOS

(symPoint Resistor(shape cross (colour Red))(mustSym WellWire)

10 Conclusions

A layout for bipolar and CMOS VLSI has been present-ed. Symple addresses full custom layout and is also usefulin the construction of standard cells for process-independent cell libraries. Such designs are portableacross process lines and resistant to changes in pro-cessing technology. Notable aspects of the Symple systemare its symbolic notation, support of bipolar and CMOSprocesses, compaction, elimination of design rule check-ing, and process representation as an interpreted lan-guage. The system simplifies the design layout task ofbipolar and combined bipolar/MOC circuits.

Work on interfacing Symple to the Icewater pro-cedural layout language [30] is in progress. The verylowest level of cell construction will be performed in

(optSym Metal 1 Metal2))(symPoint VIA

(shape box (colour Black))(optSym Metal 1 Metal2))

(symPoint PMOS(mustSym P_diff GatePoly))

(symLine WellWire(colour Orange)(thickness 3))

(symLine P_diff(colour Blue)(intersect GatePoly

(autoPlace PMOS)))Fig. 21 Symbol syntax file

; Define point symbolHow symbol is displayedOther symbols required forpoint symbol to be legalOptionally present symbols

; Non-visible symbol

; Define line symbol

; line width scaling, default = 1

; Recognise MOS transistor; automatically add point symbol

Each different symbolic notation is described in asymbol syntax file. The file of Fig. 21 is a partial descrip-tion of the CMOS notation and illustrates most of thefeatures. The symbol syntax file is read at startup andinitialises the database, display manager, and other com-ponents of Symple that use the symbolic notationdirectly.

9 User interface

The system is menu driven, with the menu presented aslight buttons on a high resolution display. All actionswithin Symple are designed to only require one selectoperation. This allows use of a single button mouse orstylus; it also eliminates any uncertainty about whichbutton executes the desired function [28]. Depending onthe input device, extra physical buttons may be available;they are used, by experienced users, instead of the menus.The system is contolled by a state machine that is con-structed at run time. The configuration file is similar tothe EDIF technology description, providing a very flex-ible user interface. Much effort was expended onSymple's user interface, unfortunately a full description isbeyond the scope of this paper. Reference 29 contains adetailed examination of the interface issues and imple-mentation.

Symple. The designer would then have the power of pro-cedural languages to perform placement, instantiationand interconnection of these cells. New silicon compilersmay also use Symple's symbolic notation as the targetprocess and rely on Symple to perform compaction andmask rendering; this is analogous to modern compilerscompiling to a machine independent intermediate form.It provides a useful partitioning of the compilationproblem, and makes the compiler process-independent.

Symple is currently used for graduate and under-graduate IC layout courses, and has been well received.The package is available as part of the University ofWaterloo CAD Tools distribution; it works under theUNIX* operating system and has been ported to anumber of systems (Sun, Apollo, VAX11/780, 785, Micro-VaxII, Orcatech 3000, Daisy Chipmaster). Graphicalinput/output is handled by a device independent graphicspackage developed at the University of Waterloo by theVLSI Group and the Computer Graphics Lab [31]. Theprogram is written in C [32].

11 Acknowledgments

Discussion and comment from members of the WaterlooVLSI group is greatly appreciated. We thank the

• UNIX is a trademark of AT&T.


members of the Waterloo Computer Graphics Labor-atory for their help in implementing the graphicalsupport for Symple. We also thank the referees for theirmany useful comments on earlier drafts of this paper.

12 References

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CAD for VLSI: Symple: a symbolic layout tool for bipolar and MOS VLSI

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