[Lab Report] PSpice

�ód¹ University of Technology

Microelectronics

The MOS Transistor and CMOS

Technology

Author:

Pedro Mourão

no 900862

Professor:

Dr. Marcin Janicki

April]2014

Contents

1 Introduction 2

2 MOS Transistor 32.1 Device Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.2 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.3 MOS Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.4 Temperature E�ect on MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.5 Laboratorial simulation of an nMOS . . . . . . . . . . . . . . . . . . . . . . 7

3 CMOS technology 103.1 CMOS technology Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.2 Laboratory simulation of an inverter . . . . . . . . . . . . . . . . . . . . . . 11

1

Chapter 1

Introduction

In this report we will study some properties and behaviors of the electronic device MOSFETTransistor and after CMOS technology.

We will use PSpice Software R© do to the simulation of the devices and after that theanalysis of them.

Mosfets are one of the more used electronic devices mostly because their small dimen-sions, relative simple process of manufacturing and low power requirements. In terms ofdimension the evolution in the last twenty years was so big that today it's possible to havebillions of MOSFETS in a single IC. A good example of their using are the memories andmicroprocessors for digital circuits.

CMOS technology uses MOS transistors of both technologies (nMOS and pMOS)andnowadays it's the more used IC technology.

2

Chapter 2

MOS Transistor

2.1 Device Structure

The MOSFET is fabricated on a p-type or n-type substrate (depending if is nMOS or pMOS),which is a single-crystal silicon wafer that provides physical support for the device. Twoheavily doped n-type regions, indicated in the �gure as the n+ source and the n+ drainregions, are created in the substrate. A thin layer of silicon dioxide (SiO2) of thickness tox(typically 1 to 10 nm), which is an excellent electrical insulator, is grown on the surface ofthe substrate, covering the area between the source and drain regions. Metal is deposited ontop of the oxide layer to form the gate electrode of the device. Metal contacts are also madeto the source region, the drain region, and the substrate, also known as the body. Thus fourterminals are brought out: the gate terminal (G), the source terminal (S), the drain terminal(D), and the substrate or body terminal (B).

Figure 2.1: Structure of NMOS and PMOS transistors with gates identi�ed

There are two types of MOSFETS, the nMOS and the pMOS, both with the commonworking concept but with di�erent electrodes and carriers polarization type. The basics ofworking are: The current �ows through the source (S) and drain (D) ; Current is controlled byan electric �eld applied to an insulated gate. However the working behavior will be describinglately.

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Laboratory Report, Microelectronics CHAPTER 2. MOS TRANSISTOR

nMOS

The depletion n-type MOSFET has similar structure as the enhancement type one, howeverthe �rst one has a n-type silicon region connecting the heavily doped n-type n+ source and n+drain regions on top of the p-type substrate. This means that, when applying a voltage VDSbetween the drain and the source, the current iD �ows for when VGS is equal to 0. This allowsto say that the transistor is normally on. Since the VGS control the conductivity and channeldepth, by applying negative VGS electrons are attracted to be repelled from the channel andso, channel conductivity decrease, ending up depleted. Applying negative voltage amountto threshold voltage charge carriers are depleted from the channel and ID is reduced to 0.Additionally, positive voltage enhances the channel by attracting more electrons onto it.

pMOS

A p-channel enhancement type MOSFET, fabricated on an n-type substrate with p+ regionsfor the drain and source, has holes as charge carriers. The device operates in the same manneras the n-channel device except that VGS and VDS are negative and the threshold voltage Vtis negative. Also, the current ID enters the source terminal and leave through the drainterminal. PMOS technology originally dominated MOS manufacturing. However becauseNMOS devices can be made smaller and thus operate faster, and because NMOS historicallyrequired lower supply voltages than PMOS, NMOS technology has virtually replaced PMOS.Nevertheless, it is important to be familiar with the PMOS transistor for two reasons: PMOSdevices are still available for discrete-circuit design, and more importantly, both PMOS andNMOS transistors are utilized in complementary MOS or CMOS circuits, which is currentlythe dominant MOS technology.

�ód¹ University of Technology 2013/2014 4


2.2 Modes of operation

We can divide the operation of a MOSFET into three di�erent modes, depending on thevoltages between its terminal:

Figure 2.2: MOSFET characteristic curves

• Cuto� or sub-threshold (VGS<Vth)-Where VGS is gate-to-source bias and Vth isthe threshold voltage of the device. The transistor is turned o�, no conduction betweendrain and source, I=0A. Exists a weak-inversion current, called sub-threshold leakagecurrent.

• Triode mode or linear region (VGS>Vth), VDS<(VGS-VV th)-The transistor isturned on, and a channel has been created wich allows current �ow between drain andsource. The MOSFET operates like a resistor, controlled by the gate voltage relativeto both the source and drain.

• Saturation or active mode (VGS>Vth), VDS>(VGS-VV th)-The switch is turnedon, and a channel has been created, which allows current to �ow between the drain andsource. Since the drain voltage is higher than the gate voltage, the electrons spreadout, and conduction is not through a narrow channel but through a broader, two- orthree-dimensional current distribution extending away from the interface and deeper inthe substrate.



2.3 MOS Capacitances

In analysis of the MOS operation, transistor capacitances are important parameters. Theseare unwanted capacitances, but still are part of the transistor. Together with the resistancesin the circuit, they put an upper limit to the speed of the transistor.

C1 and C3 are due to overlap between the gate poly-silicon and the Source and Drainregions. C2 is the oxide capacitance (between Gate and channel). C4 is the depletioncapacitance between channel and Substrate. CBS and CBD are the nonlinear capacitancesof depletion regions.

Figure 2.3: Mosfet's Capacitances

2.4 Temperature E�ect on MOS

In the design of MOS circuits is interest to see the variation of the MOSFET characteristicswith temperature, illustrated in Fig.4. There are two MOS parameters depending on thetemperature:

• Mobility of carriers in channel

• Threshold voltage (Ur). This parameters decrease if the temperature increases.

In coe�cient point, we have a compensation of charges of mobility and threshold voltage.

Figure 2.4: Mosfet's Capacitances



2.5 Laboratorial simulation of an nMOS

During the laboratory sessions we investigated the MOS transistors. We simulate the nMOStransistor with pSpice.

Figure 2.5: Output characteristics

MN2 is the power transistor, for the same VDS, the current is smaller. This meets theexpectations because this device have bigger N-layer in order to block higher voltages, alsothe voltage drop is bigger.

Figure 2.6: Varying temperature

Dependence on temperature, for both transistor types is well seen. Was made measure-ments at di�erent values of temperature (0, 30, 60, 90) Celsius degrees. It's possible to



observe that the carriers mobility and consequently conductance decreases with the increaseof temperature.

Figure 2.7: Width(left) and Gate(right) length variation

The ID dependence in physical parameters (width and gate length) can be seen in theupper plots. We can see ID is proportional with the gate width and inversely proportionalto its length, agreeing with the equation 2.



Transfer characteristics

The threshold voltage for non-power MOS agree with the expected near 0.5V like the curves.

Figure 2.8: nMOS transfer characteristics for di�erent temperatures

As expected, when temperature increase, the threshold voltage decreases and the currentdecreases relating with VGS.

Figure 2.9: Transfer characteristics for channel parameters: Width and gate length variation(respectively)

On red characteristic curve the distortion in can derive from some wrong PSPICe model.


Chapter 3

CMOS technology

3.1 CMOS technology Overview

CMOS Technology, complementary metal oxide semiconductor technology uses MOStransistors of both technologies (nMOS and pMOS). CMOS are, currently, the more used ICtechnology.

Two important characteristics of CMOS devices are high noise immunity and low staticpower consumption. Once transistor of the pair is always o�, the series combination drawssigni�cant power only momentarily during switching between on and o� states. For exampletransistor-transistor logic (TTL) or NMOS logic, which normally have some standing currenteven when not changing state. CMOS also allows a high density of logic functions on achip. It was primarily for this reason that CMOS became the most used technology to beimplemented in VLSI chips.

Figure 3.1: CMOS inverter equivalent circuit, symbol and transfer characteristics (respec-tively)

When the input voltage equals to the supply voltage(Vin=Vdd), n-channel transistorconducts and p-channel one is blocked. The output voltage equals to 0V which represents

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Laboratory Report, Microelectronics CHAPTER 3. CMOS TECHNOLOGY

the logic state: 0. When the input voltage is equal to 0, n-channel does not conduct, andp-channel does. The output voltage equals to the supplying voltage and we have the logicstate: 1. The power consumption in CMOS circuits is very low. In static state, always one oftransistors is blocked. The dissipation increases while switching and the power losses increaseproportionally to working frequency.

3.2 Laboratory simulation of an inverter

In the laboratory we studied CMOS inverter, also using PSpice Software R©. In this partwe found the transfer characteristics and investigated how it is in�uenced by β parameter.

Finally, we observed the transient characteristic of our inverter with di�erent load andwe tried to choose the optimal resistance.

Figure 3.2: CMOS transfer characteristics for di�erent CMOS inverters widths

Figure 3.3: Optimal β


Laboratory Report, Microelectronics CHAPTER 3. CMOS TECHNOLOGY

The β parameter has an in�uence on the inverter threshold voltage. The higher is theβ, the lower the Vinv. During the laboratory session we tried to select the CMOS transfercharacteristics for which the β parameter is 1, as it is the most optimal case, commonly usedin practice the result is presented on �gure above.

Figure 3.4: CMOS transient simulation of an iverter for di�erent loads

Figure 3.5: CMOS transient characteristics for the best load


[Lab Report] PSpice

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