IR-Drop Based Electromigration Assessment - NIST

IR-Drop Based Electromigration AssessmentMaterials Data and Characterization Requirements

Valeriy Sukharev1, Jun-Ho Choy1, Armen Kteyan2, and Xin Huang3

1Mentor Graphics, Fremont, CA, USA

2Mentor Graphics, Armenia

3UCR, Riverside, CA, USA

© 2010 Mentor Graphics Corp.

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Outline

• Introduction and motivations

• Chip design verification for sign-off EM assessment- On-chip interconnect elemental unit for EM reliability vs. standard test-structures- A role of interconnect redundancy in the resistance degradation- Power/ground grid vs. signal nets

• A role of residual stress and temperature in EM-induced degradation

• Methodology of across-interconnect residual stress assessment

• Methodology of across-interconnect temperature assessment

• Voiding-induced IR-drop degradation – parametric failure

• Multi-scale materials data as input for the simulation

• Characterization techniques for models/methodology validation

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Reliability vs. Performance

• Current assessment of chip reliability kills chip performance!

• Reduction of the operation frequency or voltage at the instance in time when IR drop degradation (increase) exceeds a projected value is killing the chip performance while not affecting the chip EM reliability.

∆IRth = 7%

Required life-time

Question:How can one predict an IR-drop degradation for a particular chip design?

Answer:• Accurate physics• Solid models• Fast and clever algorithm

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Electromigration Basics

Material depletion and accumulation occurringat the sites of atomic flux divergence results thelocalized tensile and compressive stresses

Resulting stress gradient creates a backflowatomic flux

If the electron-wind and back-stress forcesbalance each other before the critical stressesneeded for void nucleation or metal extrusionare developed the interconnect segment will beimmortal.

DC AC

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General Physical Model

dxxx +

W

H x

y

z

ejJa(x)

Ja(x+dx)

If atom an flux divergences somewhere inside metal line then accumulation or depletion of atoms is happening there:

0=∇+∂

∂A

A Jt

N rr

Fast diffusion

Slow diffusion Slow diffusion

∂

∂+

Ω∂

∂=

∂

∂

x

jeZ

xt

HydHyd σρκ

σ

Evolution of the hydrostatic stress (a) along the metal line loaded with DC current, and at the cathode end of line, (b) j = 5x109A/m2, T = 400K.

je

Anode area

je

Cathode area

critσ

critσ

nuct

Solution of Korhonen’s equation:

Condition for the stable void formation:

Nucleation time for stable, growing void:

( ) ( )( )( )

++

Ω−= ∑

∞

=0222 exp

21cos4,

n nn

nres

Ltmm

LxmLx

jeZtx

κ

ρσσ

( )( )( )

⋅

++

Ω−= ∑

∞

=0222 exp

21cos4

n nucnn

nrescrit

Ltmm

LxmLx

jeZ

κ

ρσσ

−Ω

+

ΩΩ

≈

−Ω−+

critres

Tk

jLeZEE

Bnuc jLeZ

jLeZ

eB

Tk

D

Lt B

TVDV

σρ

σ

ρρσ

2

2ln2

2

0

2*

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V. Sukharev, “Beyond black’s equation: Full-chip Em/Sm assesment in 3D IC stack,” Microelectronic Engineering, vol. 120, pp. 99–105, May 2014.


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Black’s equation based MTTF

jaccel

jaccel

EM accelerated test: Taccel and jaccelDifferent lines characterizing by different microstructures reveal different times to failure (TTF)

• TTF averaged with the accepted distributionfunction provides mean time to failure (MTTF).

• A set of calculated MTTF obtained for differentTaccel and jaccel is used for extraction of the currentdensity exponent n and apparent activation energyE used in the Black’s equation:

• Assuming an “universal” character of the extractedn and E, the MTTF at the used conditions is:

=kT

E

j

AMTTF

nexp

( )

−=

acceluse

n

useaccelacceluseTTk

EjjMTTFMTTF

11exp

Experiments demonstrates that n and E by themselves are the functions of j and T

M. Hauschildt, C. Hennesthal, G. Talut, et al. (GF & Fraunhofer), 2C.1.1, IRPS 2013

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EM Assessment – PROBLEM!

• Stress and temperature dependency of the current density exponent,• Current density and temperature dependency of the activation energy• Across-interconnect temperature and residual stress variation

ALL THESE FACTORS MAKE QUESTIONABLE USING BLACK EQUATION and BLECH LIMIT (CRITICAL PRODUCT) FOR ACCURATE EM ASSESSMENT!

( )

( )

=kT

TjE

j

rAt

resTn

resnuc

,exp

),(,σ

σr

( ) ( )( )ρ

σσ

eZ

TrLj resEM

crit

,r

±Ω=×

σresid

σcrit

Hydrostatic stress

σEM

Interconnect line, arc-length

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EM assessment requires:

• Current density assessment• Temperature assessment• Residual stress assessment

V. Sukharev and E. Zschech, “Multi-scale simulation flow and multi-scale materials characterization for stress management in 3D through-silicon-via integration technologies –Effect of stress on 3D IC interconnect reliability”, AIP Conference Proceedings 1601, 18 (2014); DOI: 10.1063/1.4881339


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Chip-scale EM assessment

Interconnect functionality• interconnectivity for signal propagation

-bidirectional pulsed currents

• voltage delivery-unidirectional current- power grids, moresusceptible to EM effect

Traditional segment-based EM assessment• single segment based stress analysis

- assume individual segment is confined by diffusion barriers- however, in power grids, atoms can diffuse inthe interconnect tree, stress redistribution

• EM induced failure rate of the individual segment

EM induced degradation in power grids• high level of redundancy• Failure: loss of performance, parametric failure

- cannot deliver needed voltage to any point of the circuitry

New methodology for EM assessment:• IR drop based assessment• physics based models for void initiation and evolution

Interconnect tree

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STRESS ASSESSMENT

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IC Problem

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Consumer demand is driving the need for thinned substrates, introduction of new connectivity structures (e.g. 3D stacking, TSVs, C4- and u-bumps) that cause unexpected device performance

Mechanical stress caused by IC architecture and packaging impacting MOSFET characteristics/performance – Chip-Package-Interaction (CPI)

IMEC


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What is 3D TSS (Through Si Stacking) Technology

Die Integration Technology

— using Through Si Vias

— electrical connection from

front to back (on die or

interposer)

Value Proposition

— Small form factor (in X-Y &Z)

— Improved Performance

— Heterogeneous Integration

Typical Implementation— e.g. WIO Memory-on-Logic

– stacking orientation: F2B– TSV via diameter ~ 5u– wafer thickness ~ 50

— e.g. Die on (Active) Interposer– stacking orientation: F2F– TSV via diameter ~ 10u– wafer thickness ~ 100u

~20 um

~100 um

~20 um

DIE 1 : Si Substrate

Backside Insulator

TS

VTS

V

Device

M1

M2

Mn

FC Bump

uBump

ILD

DIE 2 Substrate

DIE 1 BEOL

Device

DIE 2 BEOL

~50 um

~100 um

~5 um

TSVBRDLF2BF2B

Die 1

Die 2

uBump

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R. Radojcic, E. Zschech, V. Sukharev, “Managing the Effects of Mechanical Stress on Performance of Modern SoCS”, iMAPS 2013, Hand-out for Tutorial T7.


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Multiscale methodology for calculation of device-to-device variation of stress: Stress Exchange Format

Package-scale simulation (FEA)Input: geometry; material properties;smeared mechanical properties for RDLs,Silicon/TSV bulk, interconnect.

Output: field of displacementcomponents on the die faces.

Die-scale simulation (FEA)Input: geometry; field ofdisplacements on the die faces;coordinate-dependent mechanicalproperties for RDLs, Silicon/TSV bulk,interconnect.

Output: Distribution of the straincomponents across device layer.

Layout-scale with feature-scale resolution :Input: GDS. Output: distribution of the stress components across interconnect metal layer.

Package scale

Die scale

Feature scale

Package simulations

(FEA)

TSV induced stress

(compact model)

Bump effect

(compact model)

Design (GDSII, OASIS);

Design tech file

Composite interconnect

layers (compact model)

Transistors layout effect

(compact model)

CPI stress/strain

(FEA)

Stress and strain

components (per transistor);

mobility shift

Package tech file

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Effective mechanical properties of BEoL, BRDL interconnects and Si/TSV bulk layer

Theory of the mechanical properties of anisotropic composites is employed.

Required input: (a) Thermo-mechanical properties of each material – metal, dielectric: CTE, Young’s moduli, Poisson factors; (b) fraction of dispersed phase; (c) routing direction of the metal layer.

For each bin of each layer of interconnect, depending on routing direction: for example the Young’s modulus:

( )ji

MD

ji

MM

ji EEE ,,,

|| 1 ρρ −+=

( )ji

MM

ji

MD

DMji

EE

EEE

,,

,

1 ρρ −+=⊥

bin i,j layer l

z

x

y

Young’s modulus components for M1 layer Ex for bulk Si/TSVs: bin size 20 (left) and 100nm (right), TSV 6nm, spacing 40nm.

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V. Sukharev et al., “Multi-scale simulation methodology for stress assessment in 3D IC: effect of die stacking on device performance,” J. Electron. Test. 28(1), 63–72 (2012).


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Supported Compact Models

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Stress component distributions obtained with: “smeared” (dashed line) and non-uniform (solid line) interconnects.

1. Package-scale: Warpage-Induced Stress

2. Compact Model for Bump-Induced Displacements

3. Effect of Non-Uniform Interconnect

4. Compact Model for TSV-Induced Stress: Based on: S. Ryu, K. Lu, X., et Al., , “Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects”, IEEE TDMR, VOL. 11, NO. 1, (2011) pp. 35-43

( )D

uEEP

W

yx

ubyx

)(

)( ~∆

− ( )

∆−+

∆T

H

uEP ub

W

zbz αα~

Tier2 die edges

A. Kteyan, et al. “Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow”, J. Micro/Nanolith. MEMS MOEMS 13(1), 011203 (Jan–Mar 2014)


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Residual stress in on-chip interconnect

Interconnect face warpage

Residual (hydrostatic) stress distribution across M1 layer with the overlaid C4 bumps, (left) and u-bumps (right).

Hydrostatic stress in M1 layer

TREE 41

TREE 37

0

30

60

90

120

150

180

0 50 100 150 200

MP

a

M1 tree=37 VDD

0

30

60

90

120

150

180

0 50 100 150 200

MP

a

M1 tree=41 VDD

TREE 1296

0

30

60

90

120

150

180

0 50 100 150 200

MP

a

M3 tree=1296 VDD

TREE 41 VDD zoomed

Interconnect tree is a elemental EM reliability unit representing a continuously connected, highly conductive metal (Cu) lines within one layer of metallization, terminated by diffusion barriers.

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TEMPERATURE ASSESSMENT

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Major components

kx

ρρρρM

ky

kz

Effective thermal properties of a die

MGC’s effective thermal properties extractor.- Each interconnect layer is considered as a composite: a mixture of metal fibers

included in a dielectric matrix.- Calculates the effective thermal conductivity (ki, i=x,y,z), specific heat of each interconnect layer as a function of local metal density (ρM).

• Lateral components Kx,y inside each metal layer are determined by a routing direction:

- Parallel to the routing direction:

- Normal to the routing direction:

- A vertical component:

Thermal Netlist Builder.- A die is represented by a 3D array of cuboidal thermal cells. Each cell contains a

thermal node, and is characterized by local effective thermal properties(Rth, Cth).- The array transforms into a thermal netlist.

SPICE simulator.- Calculates transistor power consumption.

- Solves for temperature for each thermal node.

( ) ILDMMMII kkk ρρ −+= 1

( ) ( )

−+−+=⊥

2/1/1

MILDMILD

MILD

kkkkk

ρ

ρ

( ) ILDMMMZ kkk ρρ −+= 1

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From effective thermal props to thermal netlist

Construct an array of cuboidal cells of dimension, LxLxt : “L” is user-supplied binSize.

For each cell, MGC’s engine uses Calibre to extract local metal density, and calculates effective thermal properties.

Thermal netlist builder transforms effective thermal properties into Rth and Cth.

The array transforms into a thermal netlist.

Consideration on boundaries- Fixed T with V source & R=0; Insulation with large R.

Cth

L

LtM6

tV5

tM5

.

.

.

.

.

.

Cell i: (ρMi, kxi,kyi,kzi,Si )

x // east

y // northz // top

( )6,

6,

,/

6,

,/2

6

,

./

2/1;

2/1;

2/1

Miicell

Mix

iwesteast

Miy

isouthnorthM

iz

ibottomtop

tLLSC

Lt

L

kR

Lt

L

kR

L

t

kR

⋅⋅⋅=

===

Design Power map Temperature across M1

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INTERCONNECT SCALE EM MODELING

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Chip-scale EM assessment

Interconnect functionality• interconnectivity for signal propagation

-bidirectional pulsed currents

• voltage delivery-unidirectional current- power grids, moresusceptible to EM effect

Traditional segment-based EM assessment• single segment based stress analysis

- assume individual segment is confined by diffusion barriers- however, in power grids, atoms can diffuse inthe interconnect tree, stress redistribution

• EM induced failure rate of the individual segment

EM induced degradation in power grids• high level of redundancy• Failure: loss of performance, parametric failure

- cannot deliver needed voltage to any point of the circuitry

New methodology for EM assessment:• IR drop based assessment• physics based models for void initiation and evolution

Interconnect tree

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Interconnect segment vs. wire

Current density Hydrostatic stress

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P. Gibson, M. Hogan, and V. Sukharev, “Electromigration analysisof full-chip integrated circuits with hydrostatic stress,” in 2014 IEEEInternational Reliability Physics Symposium, 2, pp. 2.1–2.7, 2014.


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Closed-form analytical solution for stress evolution in the multi-branched interconnect tree

T-shaped interconnect tree with shown directions of the electron flows.

Evolution of the stress distribution along the segment of the shown T-shaped tree; (a) line 1, (b) line 2, and (c) line 3.

(a) (b) (c)

If we disassemble these brunches a standard stress evolution will take place in each of them:

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V. Sukharev, X. Huang, H.-B. Chen, and S. X.-D. Tan, “IR-Drop Based Electromigration Assessment: Parametric Failure Chip-Scale Analysis” in Computer-Aided Design (ICCAD), 2014 IEEE/ACM International Conference on, pp. 428–434, 2014.


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• Assume (just for a moment) that the void less steady state was achieved in the tree.

• Consider the redistribution of the atoms between sub-segments due to unblocked sub-segment ends:

σ i

cathod − σ j

anode = ∆σ ij =eZρ jij Lij( )

ΩFor the steady state:

( )∑

=

−

=

Ω+

+−

7

1

023i

ij

ijijkT

E

iTi L

LjeZe

RBZS

V ρ

δσσ

If , this sub-segment is suspiciousto EM failure.

Example of an interconnect tree

jmn is the density of electron flow

(opposite to the current direction).

criti σσ ≥

Distribution of the steady state hydrostatic stressalong the considered tree

• Previously, we use uniform temperature distribution:The shortest void nucleation time is characterized by the biggest steady state stress ,

tnuc

m ≈Lmax/min

2

2D0

eEV +ED

kTkT

ΩBexp −

f Ωσ m j1, j2,..., jn( )kT

⋅lnσ m j1, j2,..., jn( ) −σ Res

σ m j1, j2,..., jn( ) −σ crit

j23

j34

j54

j46

j68

j76

j13

1

3

2

5

4

7

6

8

• With temperature variation: Void nucleation time is affected by both T and hydrostatic stress. Consider both factors to find the first nucleated void (mintnuc

i)

σ m j1, j2,..., jn( )

Steady state distribution of the hydrostatic stress inside interconnect tree in void-less regime

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X. Huang, T. Yu, V. Sukharev, and S. X.-D. Tan, “Physics-basedelectromigration assessment for power grid networks,” in DesignAutomation Conference (DAC), 2014, 51th ACM/EDAC/IEEE, 2014.


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Voiding

When void is nucleated the stress at the void surface is zero. The solution of the stress kinetics equation with the zero-flux condition at the downstream (anode) end of the line is[J. He and Z. Suo, AIP Conf. Proceedings, vol. 741, 2004]:

( ) ( )( )

( )

−−

−

−

−+

Ω−= ∑

∞

= τπ

π

π

ρσ

tn

L

xn

nL

xjLeZtx

n

n 2

022 2

12exp

2

12sin

12

18, Here, Ω

==DB

TkLL B

22

κτ

Once the stress field is solved, the void volume is calculated from the volume of atoms drifted into the line:

( )( )

−−

−

−+

Ω=

−=

Ω−=Ω−= ∑∫∫∫

∞

= τπ

π

ρσσ tn

nB

AjLeZdx

BAdxN

BAdxNAV

n

nLL

A

L

PL

2

023

2

0002

12exp

12

1321

2

There are two limiting cases for volume void:1. Short time; stress in the line is small, so

( ) jeZTk

Dr

B

ρΩ

=Γr and

Tk

jDAteZAtV

B

ρ=ΩΓ=

2. Steady state was reached; the atomic flux vanishes,void volume is saturated:

( )Ω

−=jxeZ

xρ

σ andB

AjLeZdx

BAV

L

satΩ

=

−= ∫ 2

2

0

ρσ

( )nuctt ≥

Void Atoms from area occupied by void

Je electron flow

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Void

Atoms from area occupied by voidJe electron flow

hH

W

Cu

Ta

( ) ( ) ( )

( ) ( )( )

( )( )

( )( )HWWHh

tV

WHhtt

HWWHhtttR

HW

ttR

hW

ttR

hH

ttR

RRRR

RRR

TavoidTa

nuc

CuTa

nuc

nuc

Ta

Void

Cu

nuc

Ta

bottomvoid

Ta

nuc

Ta

wallvoid

Ta

bottomvoid

Ta

wallvoid

Ta

wallvoid

Ta

Void

Ta

Void

Cu

Void

Ta

222

;;

1111

__

___

+=

+−∗≈

−

+−∗=∆

−∗=

−∗=

−∗=

++=

−=∆

ρρϑ

ρρϑ

ϑρ

ϑρ

ϑρ

Once V(t) is known the kinetics of line resistance can be easily calculated.For a void volume at an instance in time t we have:

Or, when current density depends on time:

kT

jDeZρϑ =( ) ( )HWtttV nucvoid −∗= ϑ

For the corresponding change in the line resistance we can write:

( ) ( )∫=t

t

void

nuc

dttjkT

DeZHWtV

ρ

Void growth-induced line resistance change

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Void nucleation time and void growth time as the functions of the current density and test temperature

J/Ttest 323 373 423 473 523 573 623 373 423 473 523 573 623

1.00E+09 T-void 1.55E+10 IMMORT IMMORT IMMORT IMMORT IMMORT R<Rcrit IMMORT IMMORT IMMORT IMMORT IMMORT

2.00E+09 T-void 6.98E+09 7.09E+08 IMMORT IMMORT IMMORT IMMORT R<Rcrit R<Rcrit IMMORT IMMORT IMMORT IMMORT

3.00E+09 T-void 4.51E+09 3.52E+08 3.85E+07 IMMORT IMMORT IMMORT R<Rcrit R<Rcrit R<Rcrit IMMORT IMMORT IMMORT

4.00E+09 T-void 3.33E+09 2.38E+08 1.87E+07 4.16E+06 IMMORT IMMORT R<Rcrit R<Rcrit R<Rcrit R<Rcrit IMMORT IMMORT

5.00E+09 T-void 2.64E+09 1.80E+08 1.29E+07 1.63E+06 IMMORT IMMORT R<Rcrit R<Rcrit R<Rcrit R<Rcrit IMMORT IMMORT

6.00E+09 T-void 2.19E+09 1.45E+08 9.93E+06 1.13E+06 2.19E+05 IMMORT R<Rcrit R<Rcrit R<Rcrit R<Rcrit R<Rcrit IMMORT

7.00E+09 T-void 1.87E+09 1.22E+08 8.09E+06 8.76E+05 1.49E+05 3.98E+04 R<Rcrit R<Rcrit R<Rcrit R<Rcrit R<Rcrit R<Rcrit






3.00E+10 T-void 4.28E+08 2.59E+07 1.57E+06 1.49E+05 2.11E+04 4.00E+03 9.09E+09 1.19E+08 3.93E+06 2.53E+05 2.66E+04 4.01E+03




Void nucleation Void growth T

jL

( )BT

confMe

ritan

αα

σ

−−

void less

void

y = 2E+19x-1.025

R² = 0.9996

0

5E+09

1E+10

1.5E+10

0 5E+10 1E+11

t_n

uc, s

j, A/m^2

y = 9974.8x - 5.0488

R² = 0.9978

10

12

14

16

18

20

22

1.5E-3 2.0E-3 2.5E-3 3.0E-3

LN

(t_

nu

c)

1/T, K

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

350 450 550 650Cu

rre

nr

de

nsi

ty e

xpo

ne

nts

Ttest, K

Sim. 1

Sim. 2

Exp. 1

Exp. 2

0.75

0.8

0.85

0.9

0.95

0E+00 1E+10 2E+10 3E+10Ap

pa

ren

t a

ctiv

. e

ne

rgy,

eV

j, A/m2

Sim. 1

Exp. 2

Extracted dependencies of n on (a), and on j (b) for Sim. 1 (TZS=653 K, scrit=500MPa) and Sim. 2 (TZS=723 K, scrit=600MPa) vs. experimental data.

testT aE

Critical product as a function of temperature.

Extraction of the current density exponent, (a), and the apparent activation energy, (b), based on the calculated .nuct

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t1

- Nucleated void - Growing void

t2 t3 t4

12 14 16 18 20 22 24 26 281.62

1.625

1.63

1.635

1.64

1.645

1.65

1.655

Simulation Time (yrs)

Node V

oltage (

V)

Reaches minimum nucleationtime, begin to degradate

Reaches thresholdvoltage, TTF

EM induced voltage degradation in IBMPG power net

- Saturated void

EM-induced supply voltage degradation

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EM effect is sensitive to temperature

- TTF exponentially relates to temperature

(the same as Black’s equation)

Reducing chip temperature/ temperature gradient could extend TTF

EM Assessment Results in IBM Benchmarks

12 14 16 18 20 22 24 26 281.62

1.625

1.63

1.635

1.64

1.645

1.65

1.655

Simulation Time (yrs)N

od

e V

olta

ge

(V

)

Reaches minimum nucleationtime, begin to degradate

Reaches thresholdvoltage, TTF

Current source values are modified to ensure initial IR drop of any node is smaller than the threshold value

TABLE: COMPARISON OF POWER GRID MTTF USING BLACK’S EQUATION AND PROPOSED MODEL

Both Black’s equation based series and Mesh modelslead to pessimistic predictions

Voltage at the first failed node over time

In this work, the first failure is most likely to happen at the nodes where the initial hydrostatic stress is large

(b)

360 364 368 372 376 380

20

40

60

80

100

Temperature (K)

Tim

e t

o F

ailu

re (

yrs

)

360 370 3802

4

6

Temperature (K)

ln(T

TF

,(ye

ar)

)

2

4

6

8

10

12

14

250 350 450 550

thermal stress(MPa)

Timeto

Failure

(yrs)

(a) Voltage drop (V) distribution and (b) Initial steady statehydrostatic stress (Pa)distributionpredicted by initial current density in IBMPG2.

(a)

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EXAMPLE OF IR-DROP EM ASSESSMENT

CHIP-SCALE EM ASSESSMENT CONSIDERING THE IMPACT OF TEMPERATURE AND CPI STRESS VARIATIONS

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Layout

Design: 7-metal layer 32nm Dimension:184um ×184um

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power net

Initial current density and initial IR-drop-power net, M1 layer

power net

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suspicious to EM failure

σcrit = 500Mpa

Initial hydrostatic stress -power net, M1 layer

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Temperature distribution

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16300

320

340

360

380

400

420temperature variation

layer number

tem

pra

ture

(K)

average T of the layer

max T in the layer

min T in the layer

bottom top

12

Metal 1 layer

FCMN2015, Dresden

M. Chew, A. Aslyan, J.-H. Choy, X. Huang, “Accurate Full-Chip Estimation of Power Map, Current Densities and Temperature for EM Assessment”, in Computer-Aided Design (ICCAD), 2014 IEEE/ACM International Conference on, pp. 440–445, 2014.


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EM induced IR drop change- power net

Initial IR drop distribution

Final IR drop distribution (at lifetimeth)

Significant IR drop changes in M1 layer

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Voids mainly locate in M1 layer, some voids locate in M3 layer

Branches with voids- power net


Chip fails when the maximum IR drop > threshold level

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CALIBRATION/VALIDATION

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How to calibrate/validate verification tools?

• Both types of tools predicting the effect of CPI on chip performance and chip reliability need as inputs: Measured foundry and process dependent thermal-mechanical properties of

the involved materials. Calibrated compact models employed for calculation of the stresses and

temperature across a device layer and across the whole chip. Calibrated models for calculating effective thermal-mechanical properties of all

composite layers (BEoL and RDL interconnects, underfill with C4 and u-bumps, silicon bulk with TSVs, etc.).

• Both types of tools need to be validated by a direct comparison between the predicted characteristics and measured: Comparing the measured characteristics of individual transistors and predicted

by verification tools is a validation of the CPI effect on chip performance. What kind of test-structures should be used to validate the effect of

CPI on chip reliability (EM as an example)?

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Calibration of the models for effective thermal-mechanical properties

New approach to determine CTE for Cu/ULK for a partially de-processed 3DIC, by combination of FIB cutting and SEM (heating stage holder).• isolate a bar• separate into two bars of same length, and measure the gap in the middle as a function of temperature up to 250°C

Layout file (GDSII & Oasis) allows to calculate all three components of the effective CTE for different bin sizes.

Following FEA simulation could allow to calibrate the effective CTE model.

Similar approach can be employed for calibration of the models for effective Young’s modulus and Poisson factor.

There is a need in experimental methodology for calibrating the models for thermal properties of on-chip interconnects and other composite layers.

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Proof Electrical vs. Mechanical

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H-Bar –TEM Lamella

Distance to TSV

After FIB processing Before FIB processingStrain distribution in lamella ( after FIB, before FIB)

Reconstructive FEA simulation

TEM CBED measurement of strain

MECHANICAL DOMAIN

A

CB

ELECTRICAL DOMAIN

0

1

2

3

4

5

6

7

8

0 2 4 6

de

lta

_Id

, %

Distance to TSV, um

Measured

Simulated

( ) SPICE

z

I

zy

I

yx

I

x

simulII σπσπσπ ++−=∆

θν

εσσ 2cos

421 2

2

r

DE TSV

Si

thSiyx

−=−=

Calibrating εth :

Good fit between simulated and measuredelectrical characteristics of transistorslocated at different distances from TSVallows to calibrate the developed tool withrelatively easy accessible electrical data.



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Validation with the Foundry calibrated Model

Test-chip segment

y = 0.9504x + 0.1289R² = 0.9492

-2

0

2

4

6

8

10

-5 0 5 10

Prediction

Fab data

n-ch Id_lin

y = 0.8711x + 0.2115R² = 0.8514

-5

0

5

10

15

-5 0 5 10 15

Prediction

Fab data

p-ch Id_lin

y = 0.941x - 0.0011R² = 0.9235 -0.08

-0.06

-0.04

-0.02

0

0.02

-0.08 -0.06 -0.04 -0.02 0 0.02

Prediction

Fab data

n-ch Vt

y = 0.9001x - 0.0036R² = 0.8881

-0.07

-0.06

-0.05

-0.04

-0.03

-0.02

-0.01

0

-0.08 -0.06 -0.04 -0.02 0

Prediction

Fab data

p-ch Vt

Calibration was performed on ~100 gatesPrediction was made for all (~4000) gates

FCMN2015, Dresden

V. Sukharev et al., “Multi-scale simulation methodology for stress assessment in 3D IC: effect of die stacking on device performance,” J. Electron. Test. 28(1), 63–72 (2012).


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Die Corner Array: Test-chip 28nm node

41

Schematics of the test structures used for model calibration: die corner

Die corner

1

1

1

1

45

67

8

910

11

12

16

17

18

3

2

1

13

14

15

FC bumps

Device location

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Validation related tasks

• How can we validate the predicted stress distribution inside the interconnect metal of the die stacked by 3D IC technology?

• How can we validate the distribution of the EM- or SM-induced voids inside BEoL interconnect?

• How can we monitor the accelerated kinetics of IR-drop degradation? What kind of test-structures should be developed?

• Test-chips with the temperature sensors?

• Itc., etc.

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CONCLUSIONSA NOVEL METHODOLOGY FOR FULL-CHIP POWER/GROUND NETS

REDUNDANCY-AWARE EM ASSESSMENT BASED ON IR-DROP ANALYSIS WAS DEVELOPED.

PHYSICS-BASED MODEL FOR TEMPERATURE- AND RESIDUAL STRESS-AWARE VOID NUCLEATION AND GROWTH WAS DEVELOPED AND

IMPLEMENTED IN THE FLOW.A DEVELOPED TECHNIQUE FOR CALCULATING THE HYDROSTATIC STRESS DISTRIBUTION INSIDE A MULTI BRANCH INTERCONNECT TREE ALLOWS TO AVOID OVER OPTIMISTIC PREDICTION OF THE TIME TO FAILURE MADE

WITH THE BLECH-BLACK ANALYSIS OF INDIVIDUAL BRANCHES OF INTERCONNECT SEGMENT.

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IR-Drop Based Electromigration Assessment - NIST

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