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POLITECHNIKA L6DZKA WYDZIAt ELEKTROTECHNIKI I ELEKTRONIKI

Andrzej Materka

Analog Electronics Lecture notes

L6dz,1998

Recenzent / Reviewer Prof, dr in?. Jersgi Ludnski

Sklad komputerowy, przygotowanie rysunkow i przelamanie tekstu / Computer text-editing, figure artworks, text formatting Andrgj Materka

Projekt graficzny okladki / Cover graphics design Wojtek Materka

© Copyright by Wydzial Elektrotechniki i Elektroniki Politechniki Lodzkiej

ISBN 83-87202-06-1

Na okladce: Seria dziewi^ciu analogowych ukladow scalonych, z ktorych kazdy pelni funkcje. sztucznej sieci neuronowej Kohonena. Uklady zaprojektowano w zespole naukowo-badawczym kierowanym przez Autora w Instytucie Elektroniki Politechniki Lodzkiej, we wspolpracy z prof. Alexisem De Vosem z Uniwersytetu w Gandawie. Zostaly one wyprodukowane przez fabryke. ukladow scalonych 'Alcatel' w Belgii. Uklad sieci Kohonena pozwala na praktyczna. realizacje. idei uczenia nienadzorowanego, m. in. do celow rozpoznawania obrazow.

Front cover: A lot of 9 analog integrated circuits, each performing the function of Kohonen-type artificial neural network. The research team led by the Author in the Institute of Electronics, Technical University of Lodz - in cooperation with Professor Alexis De Vos of Gent University - has designed the circuits. The 'Alcatel' silicon foundry in Belgium fabricated the ICs. The Kohonen network implements the idea of unsupervised learning for pattern recognition - among many other applications.

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Contents

1 Introduction, 9 1.1 Signals and Their Spectra, 9 1.2 Analog and Digital Signals, 12 1.3 Electronic-System Block Diagrams, 15 1.4 Information-Processing Electronics Versus Power Electronics, 16 1.5 Behavior of Circuit Components Versus Frequency, 16 1.6 Summary, 17

2 Amplifiers: Behavioral Description, 18 2.1 Basic Concepts, 18 2.2 Cascaded Amplifiers, 22 2.3 Power Supplies and Efficiency, 23 2.4 Decibel Notation, 25 2.5 Frequency Response, 26 2.6 The Miller Theorem, 34 2.7 Linear Distortion, 37 2.8 Pulse Response, 39 2.9 Nonlinear Distortion, 44 2.10 Summary, 46

3 Diode Circuits, 48 3.1 The Ideal Diode, 48 3.2 Terminal Characteristics of Semiconductor Diodes, 52 3.3 Analysis of Diode Circuits, 56 3.4 The Diode Small-Signal Model at Low Frequencies, 61 3.5 Rectifier Circuits, 66 3.6 Zener-Diode Voltage Regulator Circuits, 70 3.7 Wave-Shaping Circuits, 73 3.b Switching and High-Frequency Behavior of thepn Junction, 76 3.9 Special Diodes, 84 3.10 Summary, 86

4 Field-Effect Transistor Circuits, 88 4.1 The »-channel Junction FET, 88 4.2 Metal-Oxide-Semiconductor FETs, 91 4.3 Load-Line Analysis of a Simple JFET Amplifier, 94 4.4 The Self-Bias Circuit, 96 4.5 The Fixed- Plus Self-Bias Circuit, 98 4.6 The Small-Signal Equivalent Circuit, 100 4.7 Basic Small-Signal FET Amplifier Circuits, 103 4.8 The FET as a Voltage-Controlled Resistance, 113 4.9 CMOS Analog Switch, 115 4.10 CMOS Logic Circuits, 116 4.11 FET Dynamic Circuit Model, 121 4.12 Summary, 125

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5 Bipolar Transistor Circuits, 127 5.1 Load-Line Analysis of a Common-Emitter Amplifier, 130 5.2 The pnp Bipolar Junction Transistor, 133 5.3 Secondary Effects, 135 5.4 Large-Signal dc BJT Models, 139 5.5 Large-Signal dc Analysis of BJT Circuits, 141 5.6 Four-Resistor Bias Circuit, 145 5.7 Small-Signal Equivalent Circuits, 149 5.8 The Common-Emitter Amplifier, 150 5.9 The Emitter Follower, 153 5.10 Review of Small-Signal Equivalent Circuit Analysis, 156 5.11 The Common-Emitter Hybrid-Parameter Small-Signal Model, 160 5.12 The Hybrid-* Model, 161 5.13 Bipolar Transistor Behavior at High Frequencies, 164 5.14 Large-Signal Dynamic Model for die BJT, 173 5.15 Switching Behavior of die BJT, 177 5.16 Summary, 181

6 Feedback Circuits, 183 6.1 Effects on Sensitivity, Bandwidth and Distortion, 184 6.2 Feedback Types, 194 6.3 Effect of Feedback Types on Input and Output Impedance, 196 6.4 Summary of the Effect of Various Feedback Types, 198 6.5 Practical Feedback Networks, 199 6.6 Stability of Feedback Amplifiers, 202 6.7 Sinusoidal Oscillators, 205 6.8 Summary, 221

References, 223

Review Questions, 224

Problems, 230

Appendix A. Nominal Values and the Color Code for Resistors, 256 B. Introduction to PSpice, 258 C. English-Polish Dictionary of Selected Terms, 266 D. Manufacturers' Date Sheets for 2N2222A transistor, 272

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Przedmowa / Preface

Niniejszy skrypt powstal w wyniku zebiania i uporzajikowania notatek z wykladow Analog Electronics oraz Electronic Devices and Systems, ktore mialem przyjemnosc prowadzic w Politechnice Lodzkiej dla kilku grup studenckich IFE (International Facility of Engineering) w latach 1995-1997. Opisuje. w nim zasady dzialania i wlasciwosci podstawowych ukiadow elektronicznych - analogowych.

Zakres materialu opisanego w skrypcie w niewielkim jedynie stopniu obejmuje olbrzymia, rozmaitosc znanych ukiadow elektronicznych. Staralem si? zawrzec w nim informacje podstawowe, zdefiniowac terminologie. i omowic elementarne obwody zawieraja.ce diody, tranzystory polowe, bipolarne a takze obwody ze sprz?zeniem zwrotnym. Oprocz wiadomosci teoretycznych i przykladow symulacji komputerowych skrypt zawiera cwiczenia rachunkowe, ktore pozwalajq. na ilosciowe zilustrowanie wlasciwosci ukiadow, a w niektorych przypadkach lepsze zrozumieiiie zalozeri projektowych. Pytania powtorkowe zwracaj% uwage na zasadnicze elementy tresci merytorycznej poszczegolnych rozdzialow i moga. bye pomocne w porza_dkowaniu wiedzy przed egzaminem.

Program studiow inzynierskich w IFE zawiera zmniejszona^ liczbe. godzin zajee z ukiadow elektronicznych w porownaniu ze studiami magisterskimi na Wydziale Elektrotechniki i Elektroniki PL. Dla lepszego wykorzystania przydzielonych limitow czasowych i zwi?kszenia skutecznosci przekazu wiedzy, wyklady swoje ilustrowaiem dose obficie przyktadami obhezen za pomoca. programu SPICE. W tym celu prowadzilem wyklady w laboratorium komputerowym, w ktorym kazdy ze studentow mogl samodzielnie realizowac symulacje omawianych ukiadow. Ta forma zajec dydaktycznych dowiodla swojej uzytecznosci i jest godna polecenia innym, zainteresowanym wykladowcom. Przyklady wybranych programow w j?zyku SPICE zawarlem w skrypcie. Zachecam Czytelnikow do korzystania z tych przykladow, a takze do pisania wlasnych programow i wykonywania symulacji ukiadow. Symulacje takie nie moga. zastapic, bez wa_tpienia, doswiadczeri praktycznych i pomiarow rzeczywistego obwodu. Sa_ one jednak mniej kosztowne, trwaj% krocej, a w przypadku projektowania ukiadow scalonych sa. jedyna. forma, sprawdzania poprawnosci projektu przed faza. realizacji. Zainteresowanym mog? udost?pnic darmowa. edukacyjna_ wersje. programu PSpice (dwie dyskietM 3.25"). Przy tej okazji chcialbym podziekowac Wydawnictwu Prentice Hall, ktore przyslalo mi ten program wraz z ksia^zka. [12] do oceny, kiedy pracowalem jako wykladowca w Monash University w Australii.

Z faktu, iz studenci IFE — sluchacze moich wykladow — z niecierpliwoscia. pytali o kolejne porcje notatek wnosz?, ze napisanie skryptu bylo potrzebne. Wypelnia on okreslona. iuk? w krajowym pismiennictwie akademickim, dotyczaca. zwlaszcza materialow optacowanych w jezykach obcych, co jest szczegolnie wazne w okresie otwierania si? Polski na swiat Z drugiej strony, polskoj?zyczni studenci IFE powinm miec mozliwosc zapoznania si? z rodzima. terminologie w dziedzinie ich studiow. Na ich potrzeby opracowalem slownik angielsko-polski terminow uzywanych w skrypcie, zawarty w Dodatku. Trzeba podkreslic, ze lektura niniejszego skryptu nie moze zastaj>ic prawdziwie pogl?bionych studiow przedmiotu. W tym celu odsylam Czytelnikow do

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http://zawieraja.ce

dziel obszetniejszych, z ktotych kotzystalem przygotowujajc notatki do moich wykladow. List? tych prac zawieta spis literatury.

Na koniec chc? zaznaczyc, ze optacowanie niniejsze nie mogloby powstac gdyby moja Zona i moj Syn nie zgodzili si? na to, abym 30 weekendow toku 1997 sp?dzil z edytotem tekstu. Setdecznie Im za to dziekuj?. Jestem towniez wdzi?czny Dziekanowi Wydzialu Elekttotechniki i Elekttoniki Politechniki Lodzkiej, Panu Ptofesotowi Doktotowi Janowi Leszczyriskiemu za ufundowanie honotatium, ktote pozwoli mi na modetnizacj? mojego komputeta. Dzi?ki temu zmniejsz? troch? dystans do czolowki tego fascynuja.cego i ptzeiazaja_cego wyscigu powszechniej komputetyzacji, u ktoiej podstaw znajduje si? post?p w dziedzinie elekttoniki. No doubts it is...

Zycz? Panstwu ptzyjemnej i owocnej lektuty -

Andrzej Materka.

Lodz, wlutym 1998.

Preface / Przedmowa

This textbook is a systematized collection of the notes of lectures that I had a pleasure to deliver in 1995-1997 to a number of student groups at the International Faculty of Engineering (IFE), Technical University of Lodz. It describes the principle of operation and properties of basic analog electronic circuits.

The material included in this textbook covers the huge variety of known electronic circuits to a very limited degree only. I have made efforts to introduce fundamental concepts, define terminology, and discuss elementary circuits that comprise diodes, field-effect and bipolar transistors, as well as circuits with feedback. Besides the theory and computer simulation examples, the lecture notes include problems and exercises for the student, which help quantitatively illustrate various circuit properties and provide better understanding of design specifications in some cases. Review questions'provided turn the reader's attention to essential elements of the theory presented in individual chapters; they can be helpful to sort things out before exams.

The 4-year BEng study program at IFE allows less class time for Analog Electronics than the 5-year MSc studies at the TUL's Faculty of Electrical and Electronic Engineering do. To make better use of the student contact-hours allocated, I kept amply illustrating my lectures with computer simulation examples, using the SPICE program. To achieve that, a computer laboratory was chosen to be the place to give the lectures, where almost every listener had an access to a PC terminal to individually exercise the virtual experiments with the circuits under study. This form of carrying on the teaching has proven its usefulness and deserves recommendation to other interested lecturers. I integrated examples of the SPICE code with the text of the lecture notes. I encourage the readers to use these examples and to write their own programs for circuit simulation. Simulations can not, of course, replace practical experiments and measurements of physical circuits. They are, however, less expensive, last shorter, and in the case of integrated circuits are the only means of verifying the circuit correctness before its fabrication. The interested readers can copy a free educational version of the PSpice program (two 3.5 inches floppies) from my resources. On this occasion I wish to thank the Prentice Hall publishing house representative who sent me this program along with the book [12] for evaluation when I was with Monash University, Melbourne, Australia, working as a lecturer.

From the fact that IFE students - the listeners to my lectures — kept impatiently asking me about consecutive printouts of the lecture notes I gather writing the textbook was needed. It fills up a gap in the country's academic literature that concerns especially foreign-language material that is particularly important in the period of Poland's opening to the outside world. On the other hand, those of students who are Polish native speakers should be given an opportunity to familiarize with their mother-tongue terminology in the field of their studies. I then elaborated a short English-Polish dictionary of selected terms utilized in the textbook, which is included in the Appendix. It should be emphasized that reading this textbook can not replace truly thorough studies of ^he subject. To do such studies, I recommend the readers to refer to more extensive

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books that I used to prepare the lecture notes. The list of these works is provided at the end of the text

Finally, I wish to point out that this textbook would not appear if my wife and my son would not agree that I might spend 30 week-ends in 1997 with the text editor. I do sincerely thank them for this opportunity. I am also grateful to the Dean of the Faculty of Electrical and Electronic Engineering, Professor Jan Leszczynski, for founding a scholarship that will help upgrade my computer. Then I will be able to cut a litde bit die distance to the leaders of the fascinating and frightening race of widespread computerization that is actually based on the progress in electronics. Bez wa.tpienia tak jest. . .

I wish you enjoyable and fruitful reading,

Andrzej Materka.

Lodz, in February 1998.

Analog Electronics /Introduction

1. Introduction

In these lecture notes we shall study electronic devices and their interconnections that form discrete or integrated circuits (ICs). These circuits are devised to perform a variety of functions within electronic systems' of interest The well-known examples of contemporary electronic systems are Walkman radio, TV set, PC computer, TV satellite receiver, computerized monitors for patients in intensive-care units, cellular phones, and the like. There exist also a variety of complex systems, which do not operate based mainly on electrons' movement but nevertheless would not function properly without an embedded electronic circuitry. These include aircraft, photocopying machines, weather satellites, etc. Electronic systems control fuel mixture and ignition timing to maximize performance and minimize undesirable emissions from automobile engines. It is in fact impossible to overestimate the role of electronics in the modem society. Perhaps there is no human activity area, ranging from daily life to space exploration, in which we don't utilize the electronic devices.

The foundations of electronics were established by the observations of M. Faraday (1791-1867) and the discovery of electron by J. J. Thomson in 1897, but its development proceeded relatively slowly until the importance of radar became apparent at the beginning of World War II. During that period and extending until about 1955, the expanding field of electronics depended heavily on the principle of electron emission from the hot cathode of a vacuum tube. By modern standards, vacuum tube electronics was expensive, bulky, hot, unreliable and even dangerous because of the high voltages present in the tubes. With the discovery of the transistor by J. Bardeen, W. H. Brittain and W. B. Schockley in 1948, the stage was set for the solid-state electronics explosion of today. This technological explosion is often compared to the industrial revolution.

Since the invention of transistor the technology has progressed from an individually prepared laboratory device (a tube) to millions of components (diodes, transistors) on a single silicon wafer only a millimeter a side. Coupled with this astounding miniaturization has been a corresponding decrease in the price per component For example, a current popular microcomputer chip, containing more than one million components, costs about the same as one of the electron tubes of earlier electronics. At the same time, with the increased internal complexity and overall functionality of solid-1 tate chips, the number of external components is highly reduced as compared to vacuum tube electronic circuits. Also, the temperature of device operation is decreased. These two main factors lead to a much higher reliability of solid state electronic systems.

1.1 Signals and Their Spectra

The main function of most electronic circuits is either to process or to generate signals. Signals contain information about a variety of things in our physical world. For example, information about the weather is contained in signals that represent the air temperature, pressure, the wind speed, etc. The voice of a radio announcer reading the news into the microphone provides an acoustic signal that carries information about world affairs. To monitor and diagnose the status of the human body, biopotentials are measured on the surface of the skin to represent the activities of the heart (ECG - the electrocardiogram), the brain (EEG - electroencephalogram), the muscles (EMG -electromyogram) and others.

Processing of signals is needed to extract information from them, for an observer (be it a human or a machine). Electronic circuits and systems most conveniently perform the signal processing. For this to be possible, the signals, which are not originally in the form of an electrical signal, must first

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be converted into a voltage or current Devices known as transducers accomplish this process. A variety of transducers exist, each suitable for one of the various forms of physical signals. For instance, a microphone is in effect a pressure transducer. It is not our purpose here to study transducers; rather, we shall assume that the signals of interest already exist in the electrical domain.

For the purpose of our study the signals will be represented by one of the equivalent forms shown

in Fig. 1.1. In Fig. 1.1(a) the signal is represented by a voltage source v//) having a source resistance

R r In the alternate representation of Fig. 1.1(b), the signal is represented by a current source /,(/)

having a source resistance Rr Although the two representations are equivalent, the one shown in

Fig. 1.1(a) (known as the Thevenin form) is preferred when R, is low. The representation of Fig.

1.1(b) (known as the Norton form) is preferred when Rs is high.

From the discussion above it should be apparent that a signal is a time-varying quantity that can be represented by a graph such as those shown in Fig. 1.2. In fact, the information content is represented in changes in signal magnitude as time progresses. The overall level of the magnitude is one of the signal characteristic features. Table 1.1 gives examples of the range of magnitudes of different signals. In general, waveforms are difficult to characterize mathematically. In other words, it is difficult to describe succincdy an arbitrary looking waveform, such as one of those of Fig. 1.2.

TABLE 1.1 MAGNITUDE AND INTERNAL RESISTANCE OF SELECTED SIGNAL SOURCES

SIGNAL SOURCE RANGE OF MAGNITUDES

INTERNAL RESISTANCE

ECG <1mV 1kft-1Mto Dynamic microphone <10mV 100fl

Radio antenna 0.1uV-1mV 50-300Q Ionic chamber 10fA-10nA >1GQ

An extremely useful characterization of a signal is in terms of its frequency spectrum. Such a description of signals is obtained through the mathematical tools of Fourier series and Fourier transform. They provide a model for a signal, which is a sum of sine-wave signals of different frequencies, amplitudes and phase angles. (This makes the sine wave a very important signal in the analysis, design and testing of electronic circuits.) The Fourier series is utilized to represent signals, which are periodic functions of time. On the other hand, die Fourier transform is more general and can be used to obtain die frequency spectrum of a signal whose waveform is an arbitrary function of time. The frequency spectrum of a signal is the amplitude of its sine-wave components expressed as a function of their frequencies. Examples of signals and their spectra are shown in Fig. 1.3. Note diat periodic signals possess discrete spectra as illustrated by Fig. 1.3(a), whereas the spectrum of an arbitrary waveform is a continuous function of frequency, as shown in Fig. 1.3(b). In other words, for periodic signals of angular frequency CO^, the spectrum consists of discrete frequencies (at the fundamental frequency (O0 and its harmonics) and die spectrum of a non-periodic signal contains, in general, consists of components of all possible frequencies.

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The essential parts of the spectra of practical signals are usually confined to relatively shon segments of the frequency axis. For instance, die spectrum of audible sounds such as speech and music extends from about 20Hz to about 20kHz - a frequency range known as die audio band. This observation is very useful in the processing of such signals and important for electronic circuit designers. This is because the properties of signal processing circuits have to match the signal properties. For example, there is no point in amplifying the signal in the frequency range in which there is no signal component of significant energy. This would mean amplification of noise and interference, which corrupt the information. Sometimes the range of frequencies occupied by a signal can be changed. In radio communication, this is done so that different transmitter occupies

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different frequency ranges. Then a receiver can separate the desired signal from the others by the use of frequency-selective electrical circuits called filters.

When we approach the design of an electronic circuit to process a signal, one of our first questions should be "What is the frequency range of the signal?" For example, we will see that ICs known as operational amplifiers can be very useful but they are limited to fairly low frequencies, usually below 1MHz. If we need an amplifier for Channel 10 television we can rule out the use of operational amplifiers. Table 1.2 provides examples of the frequency ranges of some signals of practical interest.

We conclude this section by noting that a signal can be represented either by the manner its waveform varies with time or in terms of its frequency spectrum. The two alternative representations are known as the time-domain and the frequency-domain representations, respectively. The frequency representation of a signal v(t) will be denoted by the symbol V(o>).

TABLE 1.2 FREQUENCY RANGES OF SELECTED SIGNALS

SIGNAL FREQUENCY RANGE Electrocardiogram 0.05-100Hz Audible sounds 20 Hz-20kHz Video signals 0-6 MHz

AM radio broadcasting 150- 285kHz (LW) 525 - 1600kHz (MW)

TV broadcasting 48.5 - 56.5MHz (channel 1 VHF) 222 - 230MHz (channel 12 VHF) 470 - 478 MHz (channel 21 UHF) 790 - 798MHz (channel 61 UHF)

FM radio broadcasting 66 - 73MHz, 87.5 - 108MHz GSM cellular phone 890 - 915MHz, 935 - 960MHz

Satellite TV broadcasting 11.7 - 12.5GHz

1.2 Analog and Digital Signals

The voltage waveforms depicted in Fig. 1.2 are analog signals. The name derives from the fact that such a signal is analogous to the physical signal that it represents. The analog signal is a continuous function of time. Its magnitude can take on any value. Electronic circuits that process such signals are known as analog circuits. A variety of analog circuits will be studied in this subject.

An alternative form of signal representation is that of sequence of numbers, each number representing the signal magnitude at an instant of time. The resulting signal is called a discrete-time signal or, shortly, discrete signal The signal is converted from analog to discrete form in the process of sampling. This process is illustrated in Fig. 1.4. The time instants tv /„ /?,... are marked along the time axis. The magnitude of the signal is measured (sampled) at each of these time instants.

Yet another useful form of signal representation is that of digital signal. It is obtained from a discrete signal by encoding the magnitude of signal samples with the use of finite-word-length binary code. In the example shown in Fig. 1.4, each sample value is represented by a 3-bit code word, corresponding to the amplitude zone into which the sample falls. Each sample value is converted into a code word, which in turn can be represented by a digital two-level waveform as shown in the lower panel of the figure. The digital signal is thus a sequence of encoded numbers.

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The circuit for conversion of signals in this manner is called an analog-to-digital converter (ADC). Conversely, a digital-to-analog converter (DAQ converts digital signals back to analog form. Now if we represent the magnitude of each of the signal samples in Fig. 1.4 by a number having a finite number of digits, then the signal magnitude will no longer be continuous; rather, it is said to be quantized or digitized. The resulting digital signal then is simply a sequence of gn^n iypH numbers that represents the magnitudes of the successive signal samples.

An example of analog, discrete and digital signal for a real world ECG waveform is shown in Fig. 1.5. Please note that the discrete signal of Fig. 1.5(b) is defined only at the sampling instants. It no longer is a continuous function of time. However, since the magnitude of each sample can take any value in a continuous range, a discrete signal is still an analog signal. Perfect (error-free) reconstruction of analog signal is possible given the discrete-time signal, provided it has been sampled at sufficiendy high rate. Obviously, there is no way to recover the original analog signal from the digital signal. We will discuss these issues in more detail below.

1.5

1

0.5

0

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' l .5

vffltmV]

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 tim*[s)

v(n) [mV]

10 20 30 40 50 60 70 80 sampling instance indax, n

Figure 1.5 Sampling of continuous-time analog signal (upper panel) results in the discrete-time signal (lower panel). Quantization of the discrete signal produces the following sequence of numbers:

{0,0,5,11,14,14,11,7,4,1,0,1,1,1,2,3,3,3,3^6^0,51,90,105,77,27,-12,-28,-24,-10, -2,1,1,1,0,0,0,0,0,0,1,2,3,4,5,7,8,10,11,12,12,14,18^2^6,31,36,41,46,51,55,56,57,57,

56,54,49,43,36,29,23,17,12,8,5,2,1,0,0} which represents the digital signal.

The rate at which a signal must be sampled depends on the frequency content of the signal If a signal contains no components with frequencies higher than fy, the signal can be exacuy

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reconstructed from its samples, provided that the sampling rate is selected to be more than twice fb. (This is known as Shannon-Kotelnikov theorem.) For example, audio signals have a highest frequency of less than 20kHz. Therefore, the minimum sampling rate that should be used for audio signals is 40 kHz. Practical considerations require selection of a sampling frequency somewhat higher than the theoretical minimum. For instance, audio compact-disc technology converts audio signals to digital form with a sampling rate of 44.1kHz. Naturally, it is desirable to use the lowest practical sampling rate to minimize the amount of data (in the form of code words) to be stored, transmitted or manipulated.

The second consideration important in converting analog signals to digital form is the number of magnitude zones to be used. Exact signal amplitudes cannot be represented, because all amplitudes falling into a given zone have the same code word. Thus, when a DAC converts the code words to form the original analog waveform, it is only possible to reconstruct an approximation to the original signal - the reconstructed voltage is constant within each zone. This is illustrated in Fig. 1.6. Thus some quantization error exists between the original signals and the reconstruction. Using a large number of zones can reduce this error, which requires a longer code word for each sample The number N of amplitude zones is related to the number of bits k by

N = 2* (1.1)

Thus if we are using an 8-bit {k=S) ADC, there are N=f—256 amplitude zones. In compact-disc technology, 16-bit words are used to represent sample values. With this number of bits, it is rather difficult for a listener to detect the effects of quantization error on the reconstructed audio signal.

Reconstruction

CMfclMtftiS I .—Analog s i g n a l

j j I \ 1^ I Quantisation " *^I/ / *" ~ error

,p - f- - t- - i Y Figure 1.6 Quantization error occurs when analog signal is reconstructed from its digital form

Electronic circuits that process digital signals are called digital circuits. The digital computer is a system constructed mostly of digital circuits. Digital processing of signals has become quite popular primarily because of the tremendous advances made in the design and fabrication of digital circuits. Digital processing of signals is economic and reliable. Furthermore it allows a wide variety of processing functions to be performed - functions that are either impossible or impractical to implement by analog means. Nevertheless, most of the signals in the physical wodd are analog Also, there remain many signal-processing tasks that are best performed by analog circuits. They refer especially to high-frequency signals, but apply even to digital circuits themselves, which in fact are analog dynamical systems that we interpret as digital ones. It follows that a good electronics engineer must be proficient in both forms of signal processing. Such is the philosophy adopted in the contemporary electronic engineering study programs.

The advantages of digital electronics are either coming through the use of digital electronics or are related to limitations of analog electronics. They are listed below.

(1) Advantages of digital signal processing that originate in the features of digital electronic systems • flexibility (digital circuits are programmable), • lower sensitivity to external (e.g. temperature) and internal (e.g. aging and drift) effects,

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• accuracy can be controlled by selecting the word length to represent signal samples, • circuits are reproducible (no trimming or tuning during manufacture), • circuits are easier to manufacture in IC technology (no large Ls or Cs).

(2) Advantages of digital signal processing related to limitations of analog electronics • "ideal memory" to store signals for an infinite time is possible with the digital techniques;

thus very low frequency signals can be processed with no need for .large Ls and Cs, • linear phase filters - not available in analog electronics, • circuits for exact compensation of two effects, • adaptive systems, • precise signal transforms, • possibility of processing 2D signals (images).

The main disadvantages of digital electronics are as follows: • more supply power required (passive digital circuits do not yet exist), • restricted to low-frequency applications, • when used in analog environment, often complex AD and DA converters are required • difficulties with AD and DA conversion of very weak and very strong signals;

complicated analog pre- and post-amplifiers are required in such cases, • the same information (e.g. music signal) requires larger bandwidth as a digital signal than

it does as the analog one.

The analog circuits are • less accurate, • sensitive to noise, • advantageous for high-frequency, small- and large-signal applications.

Modem and future systems contain both analog and digital circuits. We call them mixed-sigi* «J systems.

1.3 Electronic System Block Diagrams

Electronic systems are composed of subsystems or functional blocks. These functional blocks can be categorized as amplifiers, filters, signal sources, wave-shaping circuits, digital logic circuits, power supplies and converters. Briefly, we can say that amplifiers increase the power level of signals, filters separate desired signals from undesired signals and noise, signal sources generate waveforms such as sinusoids or square waves, wave-shaping circuits change one waveform into anomer (sinusoid to square wave, for example), power supplies provide necessary dc (direct current) power to the other functional blocks, and converters change signals from analog form to digital form, or vice versa. In section 1.6 we will consider the external characteristics of amplifiers in some detail.

The block diagram of a typical AM radio is shown in Fig. 1.7, as an example of a simple electronic system. Notice that mere are three amplifiers and two filters. The local oscillator is an example of a signal source, and a peak detector is a special case of wave-shaping circuit The complete system description would include detailed specification of each block. For example, the gain, input impedance, output impedance, the bandwidth (range of frequencies where the gain does not drop below a specified value) of each amplifier would be given. (We define these terms later in uiis chapter.) Each functional block in turn consists of a circuit composed of resistors, capacitors, transistors, integrated circuits, inductive coils, and other devices.

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The main goal of this text is to introduce basic electronic circuits comprising diodes, bipolar transistors, field-effect transistors and opamps, in terms of their function and principle of operation. At present, due to the ever-increasing complexity of electronic circuits and systems, no circuit can be designed properly without the use of computers and adequate CAD software. We will then use one of the most popular programs for circuit simulation, called PSpice, to investigate the properties of the circuits under study. This approach, integrating the theory and simplified mathematical analysis with computer laboratory exercises will, we hope, prepare the readers for the circuit design methodologies they will "encounter as practicing engineers. A set of practical laboratory exercises is provided also to further strengthen the knowledge and to familiarize with measurement techniques typical for low-frequency analog electronics.

1.4 Information-Processing Electronics versus Power Electronics

Many electronic systems fall into one or more of the following categories: communication systems, medical electronics, instrumentation, control systems, and computer systems. A unifying aspect of these categories is that diey all involve collection and processing of information-bearing signals. Thus the primary concern of many electronic systems is to extract, store, transport or process information in a signal.

Often, systems are also required to deliver substantial power to an output device. Certainly, this is true in an audio system for which power must be delivered to a speaker to produce the desired sound level A cardiac pacemaker uses information extracted from the electrical signals produced by the heart to determine when to apply a stimulus in the form of a minute pulse of electricity to ensure proper pumping action. Although the output power of a pacemaker is very small, it is necessary to consider the efficiency of its circuits to ensure long battery life.

Many systems are concerned mainly with the power content of signals rather than information. For example, we might want to deliver ac (alternating current) electrical power, converted from dc supplied by batteries, to a computer even when the ac line power fails.

1.5 Behavior of Circuit Components versus Frequency

The way that a component behaves and the theoretical model we must use to represent it depend on the frequency of operation. For example, a simple 1000Q resistance can model the 1000Q-0.25W carbon-film resistor at frequencies of a few kilohertz, but at several hundred megahertz the more complex circuit model shown in Fig. 1.8 is needed for good accuracy. The small capacitance in parallel with the resistance has such a high impedance at low frequencies that it can be neglected.

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However, it cannot be neglected at high frequencies. Similarly, the inductance has very low impedance and can be neglected at low frequencies. (The inductance is associated with the magnetic field surrounding the leads when current flows in the resistor. Thus the exact inductance value depends on die length of the wire leads used in making connection to the remainder of the circuit.) We see later that the circuit models used for transistors at high frequencies include capacitances that can be neglected at low frequencies.

•A /W 1000 ohm w n H

Figure 1.8 Circuit model for a 1000ft 0.25W carbon-film resistor

Even the construction methods for a circuit depend on its operating frequency range. Many circuits intended to operate at low frequencies, say below 100 kHz, can be constructed by plugging individual components into a prototype board and wiring them together without much regard to the length of connecting wires or the distance between them. On the other hand, circuits intended to operate at several hundred megahertz must be carefully constructed with regard to the layout and lead length.

It is somewhat difficult to make a definite boundary between "low" frequencies for which stray inductance and capacitance are not troublesome and "high" frequencies, for which they must be considered. In a high-impedance circuit for which the components have impedance of several megaohms or more, stray capacitance will be significant at lower frequencies than for a lower-impedance circuits with impedance less than 100Q. In general, however, we do not need to consider stray wiring effects below about 100kHz. Usually, we must take them into consideration above about 10MHz.

1.6 Summary

Main function of electronic circuits is to process or generate signals. Either the Thevenin form or the Norton form can represent an electrical signal source. The sine-wave signal is completely characterized by its peak value (or rms value which is the peak/ V2 ), its frequency, and its phase with respect to an arbitrary reference time. A signal can be represented either by its waveform versus time, or as a sum of sinusoids. The latter representation is known as the frequency spectrum of the signal. Analog signals have magnitudes that can assume any value. Electronic circuits that process analog signals are called analog circuits. Sampling the magnitude of an analog signal at discrete instants of time and representing each signal sample by a number, results in a digital signal. Digital signals are processed by digital circuits. Modem and future systems contain both analog and digital circuits. Systems are composed of subsystems or functional blocks. The functional blocks are signal sources, amplifiers, niters, wave-shaping circuits, digital logic circuits, power supplies and converters. Electronic systems fall into the category of either information-processing or power-processing electronics. Any electronic system is made up of components (resistors, capacitors, inductors, semiconductor devices, etc.). Electrical properties of components depend on the signal frequency.

BIBLIOTEKA GtOWNA PL

W 3 6 ^ S I

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Analog Electronics /Amplifiers

2 Amplifiers: Behavioral Description

In this chapter we introduce most important functional blocks that are employed in almost every electronic system, namely signal amplifiers. We will define specifications and characteristics of amplifiers, which describe their behavior as seen by an external observer. In this system-like approach we will not discuss internal structure of amplifiers, leaving this topic for the later chapters.

2.1 Basic Concepts

Signal amplification is conceptually the simplest signal-processing task. The need for amplification arises because transducers provide signals that are said to be "weak", that is in the microvolt (uV) and millivolt (mV) range. An example is a signal from a microphone, which is of about lmV peak as one speaks to this transducer. Such a weak signal cannot produce any noticeable acoustic effect if used to drive a loudspeaker. Much stronger signal is needed for a loudspeaker in order to obtain a louder version of the sound entering the microphone. Thus the signal from the microphone is used as the input to an amplifier with a voltage gain of 10000 to produce an output signal which is a peak value of 10 V. This "strong" signal is applied to the loudspeaker which produces a loud replica of the microphone's input.

The concept of signal amplification is illustrated in Fig. 2.1. The signal source produces a signal t\(t) that is applied to the input terminals of the amplifier, which generates an output signal

vo(0 = 4,v,(0 (2-1) across the load resistance RL connected to the output terminals. The constant A^ is called the voltage gain of the amplifier. Often, the voltage gain is much larger than unity, but we will see later that useful amplification can take place even if the magnitude of A, is less than unity.

Sometimes A^ is a negative number, so the output voltage is an inverted version of the input, and he amplifier is then called an inverting amplifier. On the other hand, if A^ is a positive number,

we have a noninverting amplifier. These notions are illustrated in Fig. 2.2.

Equation (2.1) is a linear relationship; hence the amplifier it describes is a linear amplifier. A linear amplifier does not introduce any distortions to sinusoidal amplified signals. The output signal is an exact replica of the input, except of course for having larger amplitude (and possibly a nonzero phase shift with respect to the input, which is discussed in Section 2.6). Linearity is the much-needed feature of amplifiers so that the information contained in die signal is not changed and no new information is introduced. Any change in waveform is considered distortion and is obviously undesirable.

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Analog Electronics/Amplifiers

Figure 2.2 Input signal to an amplifier (upper panel), output signal of a noninverting amplifier of gain A, =8, output signal of an inverting amplifier of gain Ay =-8\

The signal amplifier is a two-port network. This is clearly seen in Fig. 2.1 where the two input terminals are distinct to the two output terminals. A more common situation however is illustrated in Fig. 2.3 where a common terminal exists between the input and the output The common terminal is used as a reference point and is called the circuit ground.

Figure 2.3 An amplifier with a common terminal (ground) between the input and the output ports.

Voltage amplification can be modeled as a voltage controlled voltage source as illustrated in Fig. 2.4. Because real amplifiers draw some current from the signal source, a realistic model of an amplifier must include a resistance r\ across the input terminals. Furthermore, a resistance R^ must be included in series with the output terminals to account for the fact that the output voltage of an amplifier is reduced when load current flows.

The input resistance R; of the amplifier is the equivalent resistance seen when looking into the input terminals. As we will find later, the input circuitry can sometimes include capadttve and inductive effects, and we would then refer to the input impedance. For example, the input amplifier of a typical oscilloscope has input impedance containing a 1-Mfi resistance in parallel with a 47-pF capadtance.

Figure Z4 Model of an electronic amplifier

The voltage-controlled voltage source in Fig. 2.4 models the amplification properties of the

amplifier. Notice that the voltage produced by this source is the input voltage times a constant A°.

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If the load is an open circuit, R^—°o, there is no drop across the output resistance R^ then vQ =

A%vt. For this reason the constant A% is called the open-circuit voltage gain. To summarize, the

voltage-amplifier model has three parameters: the input impedance, the output impedance and the

open-circuit voltage gain.

As shown in Fig. 2.4, the input current it is the current delivered to the input terminals of the amplifier and the output current to is the current flowing through the load. The cuttent gain Ai of the amplifier is the ratio of the output current to the input current

For linear amplifiers, the input current can be expressed as the input voltage divided by the input resistance. For linear load, the output current is the output voltage divided by the load resistance. (Linear amplifiers will be investigated in this chapter unless stated otherwise.) Thus we can find the current gain in terms of the voltage gain and the resistance as

in which

A = - (2-4)

is the voltage gain with the load resistance connected. Usually, A^ is smaller in magnitude than the

open-circuit voltage gain A°, because of the voltage drop across the output resistance.

The power delivered to the input terminals by the signal source is called the input power P^ and the power delivered to the load is the output power PQ. The power gain G of an amplifier is the ratio of the output power to the input power

G = £ (2.5)

Because we are assuming that the input impedance and the load are purely resistive, the average power at either set of terminals is simply the product of die root-mean-square (rms) current and the rms voltage. Thus we can write

Notice that we have used uppercase symbols, such as V0 and J0, for the rms values of the currents and voltages. We use lowercase symbols, such as v0 and i^ for the instantaneous values. Of course, since we have assumed that the instantaneous output is a constant times the instantaneous input, the ratio of the rms voltages is the same as the ratio of the instantaneous voltages, and both are equal to the voltage gain of the amplifier.

Exetcise 2.1 An amplifier has an input resistance l\ = 2000 Q, an output resistance of 25 Q, and

an open-circuit voltage gain of 500. The source has an internal voltage of Vs =20mV and a

resistance Rt =500Q. The load resistance is RL=750. Find the voltage gains Ay= VJV\ and A^=-

VJ Vs, the current gain and the power gain. Ans. ^ = 3 7 5 , ^ = 3 0 0 , ^ = 1 0 4 , G=3.75-106.

Exetcise 2.2 Assume that we can change the load resistance in Exercise 2.1. What value of load

resistance maximizes the power gain? What is the power gain for this resistance? Ans. RL=250,

G=5-106.

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There exist other models of amplifiers, alternative to the voltage model. The input and output resistances are the same for all models. They differ by the type of controlled source at the output. Current amplifier model employs a current controlled current source, transconductance amplifier uses a voltage-controlled current source and the transresistance amplifier is the one with current-controlled voltage source at the output. The choice of the particular model is the matter of analytical convenience or feasibility of measurement of the model parameters. An amplifier can be modeled by any of the four models, provided that neither of the resistances (input or output) is zero or infinity. For example, if JRj O, then t»,=0 and the voltage gain A^— v0/i\ is not defined.

One can easily show that if the input impedance of an amplifier is much higher than the internal impedance of the source, the voltage produced across the input terminals is-nearly the same as the internal source voltage. On the other hand, if the input impedance is very low, the input current is neady equal to the short-circuit current of the source. From this point of view, voltage amplifiers should be designed to have large input impedance and current amplifiers should have very low input impedance. Taking the output impedance level into consideration, we can force a desired voltage waveform to appear across a variable load by designing the amplifier to have very low output impedance compared to the load impedance. An example is an audio amplifier with a variable number of loudspeakers connected to i t On the other hand, we can force a given current waveform through a variable load by designing an amplifier to have very high output impedance compared to the load impedance. Here an example could be the amplifier in optical communication system where a light-emitting diode (LED). It is used to produce a light wave whose intensity is proportional to a message signal such as a voice waveform. Because LED has nonlinear relationship between voltage and current, light intensity "is not" proportional to the voltage across this device, whereas it is proportional to the current flowing through the diode. Thus LED should be driven from a current amplifier in this example.

We see that certain applications call for amplifiers with very high or very low input impedance (compared to the source) and very high or very low output impedance (compared to the load). Such amplifiers are classified as follows.

An ideal voltage amplifier (voltage-controlled voltage source) senses the open-circuit voltage of die source and produces and amplified voltage across the load - independent of the load impedance. Thus the ideal voltage amplifier has infinite input impedance and zero output impedance.

Figure 26 An ideal current amplifier (CCCS)

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Analog Electronics /AmpMers

An ideal current amplifier (current-controlled current source) senses the short-circuit current of the source and forces an amplified version of this current to flow through the load. Thus an ideal current amplifier has zero input impedance and infinite output impedance.

O 4 O Figure 2.7 An ideal ttansconductance amplifier (VCCS)

An ideal transconductance amplifier (voltage-controlled current source) senses the open-circuit voltage and forces a current proportional to this voltage to flow through the load. Thus it has infinite input impedance and infinite output impedance.

Figure 2.8 An ideal transresistance amplifier (CCVS)

An ideal transresistance amplifier (current-controlled voltage source) senses the short-circuit current of the source and produces a voltage proportional to this current to appear across the load. Thus the ideal transresistance amplifier has a zero input impedance and zero output impedance.

The amplifier models considered here are unilateral; that is signal flow is unidirectional, from input to output Most real amplifiers show some reverse transmission, which is usually undesirable but must nonetheless be modeled. We will return to this point later.

Recall that we originally defined the gain of an amplifier to be the ratio of the output signal to the input signal (2.4). This is true for amplifiers that do not contain any energy-storing element. However, if any time delay or linear distortion occur, the ratio of output to input is a function of time rather than a constant Thus we should not try to find the gain of an amplifier by taking the ratio of the instantaneous output to input. Instead we recognize that gain is a function of frequency and take the ratio of phasors for a sinusoidal input signal to find the (complex) gain at each frequency

2.2 Cascaded Amplifiers

Amplifiers are built using active devices - most often transistors. We will see later that the gain obtainable from a single-transistor amplifier is limited. Thus there is often a need to combine a number of amplifiers in order to amplify a weak signal to the desired level. This can be achieved by connecting the output of one amplifier to the input of another, as shown in Fig. 2.9. This is called a cascade connection of-the amplifiers. The overall voltage gain of the cascade connection is given by

Av = ^ (2.7)

Multiplied and divided by fol this becomes

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" vn v0l

However, referring to Fig. 2.5, we see that v^voV Therefore we can write

' v , i v ,2

(2.8

(2.9)

We note also ^3OSAA^X=VOX/ »A is the gain of the first stage andy4v2=fo2/ tfo is the gain of the second stage, so we have Av=AvlAv2 (2.10) Thus the overall gain of cascaded voltage amplifiers is the product of the voltage gains of the individual stages. (Of course, it is necessary to include loading effects in computing the gain of each stage. Notice that the input resistance of the second stage loads the first stage.) Similar rules can be derived for the number of cascaded amplifiers bigger than two can.

Exercise 2 J Show that the overall current gain of a cascade connection of amplifiers is the product of the current gains of the individual stages and that the overall power gain is the product of individual power gains.

2.3 Power Supplies and Efficiency

For appropriate operation of the internal circuitry of an amplifier, power must be supplied to it from an external power supply. The power supply typically delivers current from several dc voltages, see an example in Fig. 2.10. The average power supplied to the amplifier by each voltage source is the product of the average current and voltage. The total power supplied is the sum of the powers delivered by each source. For example, the total average power supplied to the amplifier of Fig. 2.10 is

*s - 'AA^A +*BB*B (2.11)

We have seen in Exercise 2.1 that the power gain of an amplifier can be very large. Thus the output power delivered to the load is much greater than the power taken from the signal source. This additional power is taken from the power supply. For example, a stereo audio system converts part of the power taken from the power supply into signal power that is finally converted to sound by the loudspeakers. Part of the supplied power is also dissipated as heat in the internal circuits of the amplifier. This dissipation is an undesirable effect since the dissipated power is lost in most cases and makes the battery discharged too fast in case of mobile battery-powered devices. We usually try to minimize this effect when designing the internal circuitry of amplifiers.

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_ Analog Electronics /Amplifiers

Figure 2.10 TTie power supply delivers power to the amplifier from several external constant voltage supplies.

From energy conservatiqn law, the sum of the power entering the amplifier from the signal P{ and the power from the power supply Ps must be equal to the sum of the output power the power dissipated Pd. pi+ps = p0+pd (2.12)

:>wer is negligible compared to the other terms in this percentage of the power supplied that is converted in

P. n =

P,+Ps

(2.13)

The power and efficiency values given in Exercise 2.4 below are typical of one channel of a stereo amplifier under high output test conditions. Maximi2ing the efficiency is one of the important design goals for battery-operated devices such mobile phones, hearing aids, implantable heart pacemakers, etc., as well as for high-power equipment, such as motor drivers, power regulators, DC-DC converters, etc.

Exercise 2.4 Find the input, output, supply and dissipated power in the amplifier shown in Fig. 2.6,

assuming the following values of its parameters: vs = 1 m V ^ , J^ = 0, ^ = 100 kQ, A% = 104, R^ =

2 Q , R L = 8 Q , Vj^ = 15 V, JA = 1 A, Vm = 15 V, JB = 0.5 A. Calculate the efficiency of the

amplifier. Am. Pk = 10 pW, P0 = 8 W, Ps = 22.5 W, Pd = 14.5 W, rj = 35.6%.

Most amplifiers discussed in this lecture notes are small-signal circuits. The power involved is very small and the efficiency was not a concern. We do not consider power amplifiers, or output stages that are expected to provide large signal power requited by their loads. Examples of loads for power amplifiers are stereo and public address loudspeakers, deflection coils in video monitors, and servomotors in X-Y plotters. Powers supplies are also good examples of power circuits; their function is to provide the dc power required by digital and analog components of all lands.

Several special concerns preoccupy the designer of an amplifier that must deliver a large amount of power to the load. One is the amplifier efficiency, as discussed above in this Section. Equation (2.13) shows that, for given output power, low efficiency directly means greater demand for supplied power. Furthermore, efficiency suggests a second issue - the ability of the circuit components to dissipate heat Any power that does not leave the circuit as the load power contributes to the heating of transistors and resistors. In power circuits special efforts should be

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made to ensure that components are not desttoyed by excessive heat. Finally, the large signal amplitudes necessary for large output signal power make nonlinear distortion (see Section 2.9) a matter of concern. Small signal models, based upon linearization of the device characteristic at some jj-point (Sections 3.4, 4.6, 5.7 and 5.11), no longer apply here. Large-signal dynamic models have to be used for circuit analysis and design, such as SPICE models discussed in Sections 3.8, 4.10 and 5.14.

Power amplifiers are classified according to the fraction of the time an output power transistor conducts the current during one signal cycle. Class A amplifiers have output transistors in which signal current is nonzero all the time. The FET amplifiers discussed in Sections 4.7 and 5.13 are all class A amplifiers. The dc current of a class A amplifier is the same, no matter the signal is zero or nonzero. For greater efficiency, class B amplifiers employ transistors that are active only half time -otherwise they are cut-off. At zero signal value, there is no dc current through- a class B output stage - and no power consumption. An example of PSpice simulation of a class B bipolar transistor amplifier is presented in Section 6.1.3. So-called crossover distortion appears in class B amplifiers (see Section 6.1.3), so for their reduction class AB amplifiers are designed. In class AB circuits, transistors conduct slightly more than half the signal cycle. Class AB circuits have efficiencies approximately the same as for class B circuits, but produce less distortion.

Class C amplifiers deliver large amount of output power at high efficiency by employing an output transistor that conducts output current for only small fraction of a cycle. The resulting short, periodic pulses of output current excite a resonant circuit, which suppresses the distortion components that arise from the nonlinear operation of the transistor.

Class D amplifiers produce binary output waveforms of very high power with efficiencies approaching 100% by using transistors as switches. In analog applications, the class D amplifier includes a modulator that first transfers information from waveform amplitude into a more suitable form as pulse width. A lossless filter than removes undesired high-frequency terms from the output.

Applications of power amplifiers, especially class C and D circuits, are somewhat specialized. Therefore, they are not discussed further in this text

2.4 Decibel Notation

As we have noticed from the Exercises, the gain of an amplifier can take on values spanning a very large range of magnitudes. To facilitate visualization of these extreme values, amplifier gain is often expressed with a logarithmic measure. Specifically, the voltage gain A^ can be expressed in decibels (dB)as ^ = 2 0 1 o g | ^ v | d B (2.14)

and the current gain A, can be expressed as ^ = 2 0 1 o g M , | d B (2.15)

Since power is related to voltage (or current) squared, the power gain G can be expressed in decibels as follows G ^ g ^ O l o g G dB (216)

A power gain of G=100 converts to 20dB, unky gain converts to OdB, and so on. The absolute

values of the voltage and current gains are used because in the case of inverting amplifiers A^oxA^

can be negative values. A negative gain Av means that there is a 180°-phase difference between die

input and output signals; it does not imply mat the amplifier attemiates the signal On the other

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AmJofElectronica/AinptiSen

hand, an amplifier whose voltage gain is -20 dB is, in fact attenuating the input signal by a factor of 10 (that is ^=0 .1 ) .

Recall that the overall gain for cascaded amplifiers is the product of the power gains of the individual amplifiers. Wbeti fa gm an e>pnssedmdecfals, the gons of cascaded stagum the properties of the logarithm function. To illustrate this point we have G = GXG2 (2.17) When expressed in decibels, this becomes G* = lOlogG - lOlogCG.Gj) = lOlogCG,)* 101og(G2) dB (2.18) Note, referring back to (2.6), that power gain in decibels is equal to voltage gain in decibels only

when RL=R}.

Electronics engineers often use decibel notation for voltages, currents, powers, or other quantities. To do so, a reference level must be stated or implied The quantity to be expressed in decibels is divided by the reference value and the ratio is converted to decibels by taking 20 times me logarithm of the ratio for voltages or currents. Ten times the logarithm of the ratio is taken for powers. Some commonly used reference levels are 1 volt (dBV), 1 mW (dBm), and 1 watt (dBW). For example, 40 dBV is a designation of 100 V, -10 dBm is for 0.1 mW, -40 dBW is also 0.1 mW, and so on.

2.5 Frequency Response

From Chapter 1.1 we know that the input signal to an amplifier can always be expressed as the sum of sinusoidal signals. So far we have considered the gain parameter to be a constant However, since physical amplifiers contain capatiuve and inductive elements, the gain is a function of frequency. Furthermore, the amplifier affects the amplitude as well as the phase of the input signal

It follows then that an important characterization of an amplifier is in terms of its response to input sinusoids of different frequencies. Such characterization of amplifier performance is known as the amplifier frequency response.

26

Analog Ehcttoaka/AmpWka

Figure 212 Measuring the frequency response of a Knear amplifier (a), phase characteristic of a two-transistor small-signal amplifier (b) whose amplitude characteristic is shown in Fig. 2.7

Figure 2.12a shows a linear voltage amplifier fed at its input with a sine-wave signal of amplitude V{

and frequency CD. As the figure indicates, the signal measured at the amplifier output is also sinusoidal with exactly me same frequency 0). This is always true for linear circuits. However, the output sinusoid will have in general different amplitude and a different phase relative to the input. The ratio of the amplitude of me output sinusoid (VJ to the amplitude of the input sinusoid (V$ is the amplifier gain or transmission at the test frequency 0). Hie angle <p is the phase of the output sinusoie relative the input If we denote the amplifier transmission or transfer function by ^(0)) then

arg{4, (o))} m /Ay (o ) = <p(a>)

(2.19)

(2.20)

The response of a linear amplifier to a sinusoid of frequency Q) is described by \Ay{(fy | and <p{o)). Now, to obtain the complete frequency response we simply change the frequency of the input sinusoid, wait for any transients to setde, and measure the new value of AJcfy. The end result will be a table and/or graph of gain magnitude \AJd) | versus frequency and a table and/or graph of phase an$e <p(o}) versus frequency. These two plots together constitute the frequency response of the amplifier. The first is known as the magnitude or amplitude response (amplitude characteristic), and the second is the phase response (phase characteristic). Examples of amplitude and phase characteristics for a two-transistor small-signal amplifier are shown in Fig. 2.7 and 2.8(b), respectively.

If one plots the magnitude of the gain of a typical amplifier, a plot such as one of those shown in Fig. 2.11 results. Note that the gain magnitude is constant over a wide range of frequencies known

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as the midband region. This is typical for wideband amplifiers. Wideband amplifiers are used for signals that occupy a wide range of frequencies, such as audio signals or video signals (see Table 1.1). In some cases, the frequency response of an amplifier is deliberately limited to a small bandwidth compared to the center midband frequency. Such an amplifier is called a nattowband or banpass amplifier. Bandpass amplifiers are frequency selective circuits used in radio receivers to amplify the signal from one transmitter and reject the signals from other transmitters in adjacent frequency ranges.

Figure 2.13 Gain versus frequency for wideband amplifiers: ac-coupled amplifier (a) and dc-coupled amplifier (b)

Usually we specify the approximate useful frequency range of an amplifier by giving the frequencies at which the voltage (or current where appropriate) gain magnitude is l / \ 2 times the midband gain magnitude. These are known as half-power frequencies (cut-off frequencies) because the output power level is half the value for the midband region if the constant-amplitude, variable-frequency sinewave test input is used. Expressing the factor 1 /"V2 in decibels results in -3.01 dB. Thus at the half-power frequencies, the voltage or current gain is approximately 3dB lower than the midband gain. The bandwidth B of an amplifier is the distance between the half-power frequencies, {fH -f{). This is illustrated in Fig. 2.13.

In the cases illustrated by Fig. 2.13(a), the gain drops to zero at dc (zero frequency). Such amplifiers are called ac-coupled, because only ac signals are amplified. These amplifiers are often constructed by cascading a number of amplifiers that are connected together by coupling capacitors, so that dc voltages of signal source, and individual amplifier stages are separated from each other. This is illustrated in Fig. 2.14 where; caparitive coupling prevents a dc input component from affecting the first stage, dc voltages in the first stage from reaching the signal source and the second stage, and dc voltages in the second stage from reaching the first stage and the load. Sometimes magnetic transformers are used for coupling, which also leads to an ac-coupled amplifier with a zero gain at dc.

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Other amplifiers have constant gain all the way down to the dc, as shown in Fig. 2.13(b). They are said to be dc-coupled or direct coupled. Amplifiers that are realized as integrated circuits are often dc coupled because the capacitors or transformers needed for ac coupling cannot be fabricated in integrated form.

Electrocardiograph amplifiers are deliberately ac-coupled because a dc voltage of nearly a volt often occurs in the input due to contact potentials developed on the electrodes placed on the skin. The ac signal generated by the heart is on the order of lmV, and therefore the gain of the amplifier is high -typically 1000 or more. A lV-dc input would cause the amplifier to produce an output of 1000V. It would be difficult and undesirable to design an amplifier capable of such large outputs. Therefore, it is necessary to ac-couple the input circuit of an electrocardiograph to prevent the dc component from overloading the amplifier.

Amplifiers for video signals need to be dc coupled because video signals have frequency components from dc to about 6MHz, see Table 1.1. Dark pictures result in a different dc component than bright on the average pictures. It is necessary to dc-couple a video amplifier in order to preserve dc component and to obtain proper brightness of the image.

As indicated in Fig. 2.13, the gain of an amplifier always drops off at high frequencies. This is caused either by small capacitance in parallel with the input or output terminals or by small inductances in series with the signal path in the amplifier circuitry. This is illustrated in Fig. 2.10. Recall that impedance of a capacitor is inversely proportional to frequency, resulting in effective short circuit at sufficiendy high frequencies. The impedance of an inductor is proportional to frequency, so it becomes an open circuit at very high frequencies.

Figure 2.15 Capacitance in parallel with the signal path and inductance in series with the signal path reduce gain in the high-frequency region

Some of these small capacitances occur because of stray wiring capacitance between signal-carrying conductors and ground. Other capacitances are integral parts of active devices (transistors) necessary for amplification. Small inductances result from the magnetic fields surrounding the conductors in the circuit For example, a critically placed piece of wire 1-cm long can have enough inductance to limit severely the frequency response of an amplifier intended to operate at several GHz.

2y

Analog Electronic* /AupttiBen

Fot frequencies up to several MH2, the circuit and device capacitances ate the main source of frequency response roll-off, either at low or high frequencies. To illustrate their impact on frequency response we will consider an amplifier that can be represented by a real transconductance amplifier model (Figure 2.16). Such a model is an ideal transconductance amplifier as shown in Figure 2.7, augmented with input nonzero resistance r, and output finite resistance r* It is an adequate low-frequency representative of amplifying devices, such as field-effect and bipolar transistors. For the field-effect transistor, the input resistance rt is infinite whereas for the bipolar transistor a base resistance is added in series with the input terminal as will be discussed in Chapters 4 and 5, respectively.

Figure 2.16 Low frequency non-ideal transconductance amplifier model

The input to the amplifier is voltage source it with internal resistance R». Resistance RL represents the load They are shown in Fig. 2.17. The symbol n used in Figs 2.16 and 2.17 to denote the short-circuit transconductance coefficient is equivalent to A& in Fig. 2.7. To illustrate the effect of the source resistance on the frequency response, we will use a voltage gain definition slightly different to that given by Equation (2.1), namely

4 . = 7T (2-21)

Figure 217 Transconductance amplifier

There is no capacitive or inductive element in the schematic diagram of Fig. 2.17. Therefore, the bandwidth of this circuit is infinite. Indeed, the output voltage

r0RL V0=-ZmVi r0+R]L

does not depend on frequency. The voltage gain of the amplifier in Figure 2.17 can be expressed as

Ays ~ ~8lH r0Ri

"" Ay, >so (2.23)

r0+RLr{+Rs The coefficient Ano in Equation (2.23) is a constant as plotted in Figure 2.18(a) wherein = 50 mS, R, = 600 Q, r, = 5 kO, r0 = 100 kQ, and RL = 5.6kft were assumed. The phase characteristic in Figure 2.18(b) is also constant and equal to 180 degrees that means the amplifier under consideration is an inverting one. Of course, the circuit discussed is an idealized model of real-world amplifiers. Nevertheless, for medium frequency range it is an adequate model of transistor amplifiers.

Low frequency effects. To illustrate the effect of coupling capacitances on the frequency response of amplifiers we consider the circuit of Figure 2.19. It contains a coupling capacitor C, in series with the input resistance rf The output voltage is described by Equation (2.22) and the input voltage can be expressed as

-30 -

Analog Ekctroak* /AnpUtten

Vi=Vt

Rs+rt + 1

= V, JartCs

l+JG>(Rs+rty:s (2.24)

= K n JG>(Rs+ri)Cs

* rt,+r, 1+ ./<»(*,+r,)C,

Ja>*L Rs+ril+ja>TL

Figure 219 Ac-coupled ttansconductance amplifier

where U=(*S+ri)Cs (2.25) is the low-frequency time constant of the amplifier. Combining Equations (2.22) and (2.26), one obtains the effective voltage gain of the amplifier in Fig. 2.19

n JQ>rL r0RL Ays ~ 8n

~~Ayso

Rs+ril + ja>TLr0+Rl (2.26)

1+JOTL Equation (226) indicates that in this case the voltage gain is a single-pole function of frequency. The voltage gain magnitude

Vl+(a>rJ2 (2.27)

- 3 1 -


tends to zero for frequencies approaching zero. Thus an ac-coupled amplifier does not provide a dc gain. This is shown in Figure 2.20a where Cs= \ \x¥ was assumed with the other circuit parameters taking the same values as for Figure 2.18.

The gain increases with frequency. For high frequencies, the gain magnitude is equal to AyM. Then one can say the ac-coupled amplifier acts as a highpass filter. At the lower cut-off frequency, jL, the

gain magnitude is equal to A\,so I-J2 . The same results (except for different expression to describe the low-frequency time constant) would be obtained if a coupling capacitor is connected in series with the load resistance RL-

It is easy to show that for a single-pole transfer function of the type given by Equation (2.26), the lower cut-off frequency is inversely proportional to the low-frequency time constant

h=^— (2-28)

Using Equation (2.26) one can find expression that describes the phase characteristic of the amplifier in Figure 2.19

ZA\,S =270° -tg-\coTL)

. - l i (2.29)

=-90 -tg-J(a>rL) The phase characteristic (2.29) of the ac-coupled amplifier, computed using PSpice program is plotted in Figure 2.20b.

High frequency effects. Capacitances in parallel with the signal path (as well as capacitances connected between the output and input terminals of inverting amplifiers that will be discussed later on) make the amplifier gain decreasing with frequency. To illustrate this effect, capacitance C0 is connected in parallel to the load resistance of the amplifier, as shown in Figure 2.21. The output voltage is now given as

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Analog Electronics /AmpliBets

vQ = -gmVi jcoC0

R0+—t— JoCo

= -gmVi Ro

\+jaC0R0

= ~Sm's n R0 = ~Sm's ri+Rs\+jaC0R0

- _ « T V 1- Ro

(2.30)

where TH ~ RoCo is the high frequency time constant of the amplifier and

Rn = _ rQRL

r0+RL

(2.31)

(2.32)

Figure 2.21 A transconductance amplifier with parallel capacitance at the output

Substituting Equation (2.23) into (2.31), dividing both sides by Vs and making use of the definition (2.21), one obtains the voltage gain

4 , = - , K ° (2-33)

that is a single-pole function of frequency. Its magnitude

I4«(<»)l=- (2.34) ^\ + {0)tH)2

is equal to A^o at low frequencies and decreases to zero as the frequency approaches infinity. This is a lowpass filter characteristic as shown in Figure 2.22a. At the higher cut-off frequency,^, the

gain magnitude is equal to A\so I -j2. The same results (except for different expression that describes the high-frequency time constant) would be obtained if a capacitor is connected in parallel with the input resistance r,.

It is easy to show that for a single-pole transfer function of the type given by Equation (2.26), the higher cut-off frequency is inversely proportional to the high-frequency time constant

fH=^— (2-35)

Using Equation (2.33) one can find expression that describes the phase characteristic of die amplifier in Figure 2.19

- l i ^ = 1 8 0 °-\g-\<QTH) (2.36)

-33 -

Antdog Electronics /Amplifiers

The phase characteristic (2.36) of the amplifier in Figure 2.21 with parallel capacitance C = 10 pF, computed using the PSpice program, is plotted in Figure 2.22b.

2.6 The Miller Theorem

It is often the case in transistor circuits that a capacitor is connected between the output and input ports of the amplifier. Such a capacitor may represent a base-collector junction capacitance of a bipolar device or drain-gate capacitance of FET or MOSFET field-effect devices. As an example, a simplified equivalent circuit of such an amplifier is shown in Figure 2.23, where g„ = 50 mS, R, = 600 CI, r,, = 5 kQ, r0 = 100 \£i, R^ = 5.6kQ and CF = 10 pF are assumed.

Figure 2.23 A transconductance amplifier with a feedback capacitor

The capacitive element connected between the input and output terminals causes difficulties in analysis since its presence leads to higher-order nodal equations. The difficulties can be overcome by applying Miller theorem to the circuit This theorem is a basis to one of approximate methods of transistor amplifier analysis. To derive it, we will consider a general amplifier with feedback impedance as shown in Figure 2.24a.

y,*

v, o 1 \ >

-OVo

O"o

(a) (b) Figure 2.24 Original amplifier with feedback impedance (a), equivalent amplifier with feedback element split

into two parts (b)

-34-


For the original circuit we have j _VJ-VQ JTi-AVi =Vj<X-A) 1 z z z I _Vo-Vir_Vo-Vo/A^V0(l-A)

2 Z Z -AZ Similarly, for the circuit of Figure 2.24b we can write

Zml

Zm2

(2.37)

(2.38)

(2.39)

(2.40)

Now we require the circuit of Figure 2.24b to be equivalent to the original circuit of Figure 2.24a. i i

The two circuits are equivalent if I\ = I\ and 1^ — 12 • After some manipulations we obtain the impedances diat satisfy die equivalence requirement

Z Zm\ =

2m2=Z

\-A -A

\-A

(2.41)

(2.42)

The term A in the above equations is me original amplifier gain with die impedance Z in place. Evaluating die value of A is usually not easy. Therefore, gain is often calculated for the amplifier with feedback impedance Z open-circuited. This introduces some approximation in the analysis based on the Miller theorem. It should be stressed, however, that Miller theorem itself does not involve any approximation.

The gain of a typical transistor amplifier is negative number, A < 0, of a reasonably large module, \A\ >>1. If Z is resistive, the impedances Zml and Zm2 are also resistive, with Zmi being much smaller than Z and Zm2 being approximately equal to Z. If Z is a capacitive element, Z=l/')(oC, the impedances Zmi and Zm2 are also capacitive Cml=C(l-A) (2.43)

Cm2=Cl-^j (2.44)

Figure 2.25 Circuit equivalent to the amplifier of Fig. 2.23

Figure 2.25 shows the equivalent circuit for the amplifier of Figure 2.23. The approximate values of die Miller capacitances are Cml=CF(l-Avo) (2.45)

Cm2=CF1-^- (2-46)

-A vo

where Am = Vo/V{. Now one can derive die formula for the voltage gain of die amplifier. The output voltage is given by

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Analog Electronics /AmpliGcra

"o ~ Sm"i, . l + JG>T2

where Ro is defined by Equation (2.32) and the output circuit time constant is described as T2 = R0C„2 In turn, for the input voltage we have

1

where Tl ~ R\Cm\ and

V/ *1 =

*s+n

(2.47)

:das

(2.48)

(2.49)

(2.50)

(2.51)

(2.52)

Combining Equations (2.47), (2.49) and (2.23), one obtains the voltage gain

A = _, __J L_ l + JCDTi l + JG)T2

which is a two-pole transfer function. The time constants are related to the angular firequendes

COX = — (2.53)

fi>2=— (2.54) *2

called break firequendes, since for CO exceeding a value of any of these firequendes the slope of the amplifier amplitude characteristic increases by 20 dB/decade. Using (2.53) and (2.54) one can rewrite Equation (2.52) as follows

AyS — ~AVS0 -T-CO

•I' CO

(2.55)

1 + 7 — l l + y

One can perform the multiplication in the denominator of (2.55) to obtain

A>5 = ~A\s VSO / 1 1

+ CO

(2.56)

0>1 Q}2) G>\<U2

For suffidently low firequendes the right-hand term in the denominator is negligible

CO « 1

coxco2

Then we have

A s.—A

(2.57)

1

s-A

l + jco

1

\ 1 1 —+ —

K*>1 *>2) (2.58)

VSO

where 1 1

l + y — <on

l

CO, >o °>\ <°2 (2.59)

- 3 6 -

Analog Electronics /AmpliGers

relates the approximate higher cut-off frequency fflb = (oH to the break frequencies CO, and 0)2. By using Equations (2.53) and (2.54) one obtains

a>0 s —— = - (2.60) r, + r 2 T0

It should be noted that Equation (2.60) underestimates the actual value of the higher cut-off frequency, which is the effect of dropping the right-side term in the denominator of Equation (2.56). The actual value of 0)H is higher than Oh and lower than minimum of CO, and cor It is then reasonable to write

o)0 <O>H <min{fi>i,0)2} (261)

The latter formula can be easily extended to three- and more-pole amplifiers.

Using the numerical values assumed above for the elements of our circuit, we have A.™ = 265.2, C,

= 2662 pF, C2 = 10.04 pF, R, s 536 Q and R, = 5.3 kQ. They give z, = 1.426 us, r2 = 52.83 ns, T0 =

1.479 us, which are respectively equivalent to co, = 701.36 krad/s, Q)2 S 18.93 Mrad/s, and flfc =

676.3 krad/s. Knowing t ha t ^ = <oH/(2n) one can write using Equation (2.61) 107.6 kHz <fH < 111.3kH2 (2.62) This compares very well with the actual value of the lower cut-off frequency being equal to 107.6 kHz as obtained from PSpice simulation.

The accuracy of the higher cut-off frequency prediction is very good in this case, because one of the time constants is much lower than the other, namely r, » T? As an effect of this property, the Inequality (2.57) is satisfied with a large margin. Lower accuracy is achieved typically when r, = r? Still, the Miller-theorem-based technique is a valuable tool for fast evaluation of the bandwidth of amplifiers with caparitive feedback. This technique will be used in Chapters 4 and 5 to investigate the properties of basic transistor amplifiers.

Please note that in the discussed case, a relatively small feedback capacitance (10 pF) has been transformed into a large Miller capacitance (2662 pF) connected to the input of the amplifying device. For large value of Cni, the input time constant becomes large, which according to Equation (2.54) decreases the bandwidth of the amplifier. The capacitance Cm\ increases with the magnitude of the voltage gain - see Equation (2.45). Thus with the feedback capacitance, the larger the gain, the lower the bandwidth. The gain, in turn, is proportional to the load resistance. If large bandwidth is of primary concern, one should keep the load resistance as small as possible. An inverting amplifier circuit that allows achieving large gain and low load resistance simultaneously is a two-transistor amplifier known as "cascode". It will be discussed in Chapters 4 and 5.

2.7 Linear Distortion

If the gain of an amplifier has a different magnitude for the various frequency components of the input signal, a form of distortions known as amplitude distortion occurs. As an example, suppose the input signal to an amplifier is a waveform that contains two sine-wave components, one of amplitude 3 mV and frequency 1kHz and the other of amplitude -2 mV and the frequency of 3kHz: v7(0 = [3s in(2000^)-2s in(6000^)]mV (2.63)

The gain of the amplifier at 1kHz is 10Z0° and the gain at 3kHz is 2.5Z00. Apparently, the gain is not the same for the two signal components. The plots of the input and the output signals are shown in Fig. 2.26. It is seen that the shape of the output signal is different than the shape of the input signal due to the amplitude distortion.

-37-


Zero phase characteristic of an amplifier results in an output waveform that is identical to the input (up to the scale factor). On the other hand, if the phase shift between the output and input signals of an amplifier is proportional to frequency, the output signal is a time-shifted version of the input, but their shapes are the same, so we do not say any distortions take place.

Figure 2.26 Linear amplitude distortion: input signal (upper panel), output signal (lower panel).

If the phase shift of an amplifier is not proportional to frequency, phase distortion occurs. As an example suppose the signal (2.63) is applied to uie inputs of three amplifiers A, B, C, which have a constant gain magnitude of 10. The amplifiers have different phase characteristics, as specified in Table 2.1

TABLE 2.1 TRANSFER FUNCTION OF EXAMPLE AMPLIFIERS

Amplifier GainatlkHz Gain at 3kHz A 10Z0° 10Z0° B 10Z-450 10Z-1350

C 10Z-450 10Z-450

Apparently, amplifier A has a zero-phase response. The phase response of amplifier B is proportional to frequency with a proportionality constant of-45 degrees per kilohertz, and amplifier C has the phase response which is not proportional to frequency (or more precisely, it is nonzero constant, so the proportionality factor is zero). The plots of the output signals of the amplifiers are shown in Fig. 2.27. It is clear that the amplifier A does not change the shape of the signal. (However, it cannot be realized physically, as there is no delay between the input and the output -compare with Fig. 2.26.) Amplifier B also does not introduce any signal distortion, as the shapes of the input and output are the same. (Note the time delay between the signals.) Amplifier C that does not have its phase proportional to frequency produces severe distortion of the signal.

We conclude that to avoid linear signal distortions, an amplifier should have constant gain magnitude and a phase response that is linear versus frequency for the range of frequencies contained in the input signal. For an audio amplifier it is required to have a constant gain for the frequency range from 20Hz to about 20kHz. However, since it turns out that the ear is not sensitive to phase distortion (at least for monophonic signals), we would not require the phase signals of an audio amplifier to be strictly proportional to frequency. Since the shape of the waveform ultimately determines the brightness of various points of an image, either amplitude or phase distortions of television signals would severely affect the image quality. Therefore we require the gain magnitude of a video amplifier to be constant and the phase response to be proportional to frequency in die whole range from dc to 6MHz.

-38-


2.8 Pulse Response

Often one needs to amplify a pulse signal such as the waveform v(l) shown in Fig. 2.28a. Pulses contain components that are spread over a wide range of frequencies; therefore amplification of pulses calls for a wideband amplifier. A typical amplifier output pulse is shown in Fig. 2.28a, denoted by v(7). The output waveform differs from the input in several important respects: the pulse is delayed, it displays overshoot and ringing, the leading and trailing edges are gradual rather than abrupt, and if the amplifier is ac-coupled, the top of the output pulse is tilted.

The gradual rise of the leading edge of the amplifier response is quantified by giving the rise time /„

which is the time interval between the point t10 at which the amplifier achieves 10% of the eventual

output amplitude K-and the point / j^ at which the output is 90% of the steady-state value. This is

illustrated in Fig. 2.29.

- 3 9 -

Analog Electronics/Amplifiers

ho ho ' Figure 2.29 Rising edge of a typical ac-coupied broadband amplifier output pulse

(Note: no tilt is shown. When it is present, some judgement is necessary to estimate the final amplitude Vj).

The rounding of the leading edge can be attributed to the roll-off of gain in the high-frequency region. A rule-of-thumb relationship between the half-power bandwidth B and the rise time tr of a wideband amplifier is

tr s ~Y (2-64)

This relationship is not exact,for all types of amplifiers; it is accurate for firs' order (single pole) circuits. Analogously, the fall time U can be defined for the trailing edge of amplifier's pulse response. Equation (2.64) approximates the value of tr as well, at least for linear wideband amplifiers.

Another aspect of the output pulse shown in Fig. 2.28 is overshoot and ringing, which are also related to the way the gain behaves in the high-frequency region. An amplifier that displays pronounced overshoot and ringing usually has a peak in its amplitude characteristic, as shown in Fig. 2.28b. The frequency of maximum gain approximately matches the ringing frequency. Because both rise time and overshoot are related to the high-frequency response, there is usually some tradeoff between these specifications. In a particular design, component values that reduce rise time often lead to more overshoot and tinging. Pulse amplifiers designed for fast rise time typically display about 10% overshoot because a higher amount of overshoot and associated ringing are usually undesirable.

Figure 2.30 Pulse response that does not display ringing (a) and corresponding amplitude characteristic (b) of an amplifier

Example 2.1 A television picture (25 pictures per second, 625 lines per picture) is produced by a TV camera that is able to reproduce about 765 distinguishable image elements within a 52^s active

-40-

Analog Electtoaica/AxapHSets

interval during each picture line. Estimate the bandwidth required for the video amplifier embedded within this camera. Solution. We estimate the bandwidth by the use of equation (2.22). Each picture element occupies die interval of 52)ls/765=68ns. Assume 80% of this interval is allowed to be the rise time: tr

=54.4ns. Thus we obtain

n 0.35 , A 5 = - — — = 6.4 MHz

54.4/w This is very close to die actual video bandwidth used in Europe.

(2.65)

Figure 2.31 Pulse responses (a) and amplitude characteristics (b) of ac-coupled amplifiers. (Tis the input pulse duration and r represents the shortest time constant of the coupling circuit)

v(2): T« T, v(3): T=T, v(4): T» T.

The tilt at the top of the output pulse, shown in Fig. 2.31a occurs if the amplifier is ac-coupled and originates from charging of coupling capacitors during the pulse. (After all, if the pulse lasted indefinitely, it would be the same as a new dc level at the input Since ac-coupled amplifiers do not pass me dc signal, output voltage would eventually return to zero.) Tilt (sag) is specified as a percentage of the initial pulse amplitude

AF% = — - 1 0 0 % (2.66)

where AV and V are defined in Fig. 2.32. As the duration of the input pulse increases (or die amplifier lower cut-off frequency is raised by changing the coupling circuits to have shorter time constants), output waveforms of consistently increased tilt result as shown in Fig. 2.31b.

For small amount of tilt, the following approximate formula relates the percentage tilt to the lower cut-off (half-power) frequency^ AV% = 2 0 0 ^ 7 (2.67) where Tis the duration of the pulse.

- 4 1 -

Analog Electronics /AmpliSera

Figure 232 Pulse response that displays tilt

Example 2.2 A cathode ray oscilloscope (CRO) is used to measure the pulse response of me amplifier shown in Figure 2.21. The equivalent impedance of the oscilloscope, including the cable connected between amplifies output and oscilloscope's input, is represented by a 1-MQ resistance in parallel with a 100-pF capacitance. This is illustrated in Figure 2.33. Find the output pulse rise time, as obtained from the measurement Compare with the value obtained for the circuit of Figure 2.21.

Figure 233 A transconductance amplifier with parallel capacitance and Oscilloscope + cable equivalent connected at the output

Solution. We will use Equation (2.56). For the amplifier under consideration, the bandwidth equals to the higher cut-off frequency. To find the higher cut-off frequency for the circuits in Figure 2.21 and 2.33, one can use Equation (2.35) with appropriate values for the equivalent resistance and capacitance to calculate the time constant In the case of Figure 2.21, we have

— = — + — (2.68) Ro ro &L

which for RL = 5.6 kQ and r0 = 100 kfi gives Ro = 5.303 kfl. The equivalent capacitance is equal to

Co = 10 pF. The time constant is the product RoG>, which is tti = 53.03 ns. This corresponds to the upper cut-off frequency of/k = 3 MHz and the rise time of £ = 0.12 ^ls. In the case of Figure 2.33, we have

1 1 1 • = — + • + -

1 (2.69)

Ro ro RL RCRO which for the assumed values gives Ro = 5.275 kQ. The equivalent capacitance is equal to (G> +

CCRO)= HO pF. The time constant is the product RO(G)+CCRO), which is m = 580.2 ns. This corresponds to the upper cut-off frequency offii = 274 kHz and the rise time of U = 1.28 |J.s.

One can see from the results of Example 2.2 that a substantial reduction of the apparent cut-off frequency can be experienced when measuring it by the oscilloscope, direcdy connecting die oscilloscope input to the amplifier output by a coaxial cable. Lower value of the cut-off frequency means that such an oscilloscope measurement setup introduces errors to the rise time and cannot be used to evaluate amplifier pulse response. The rise and fall times will apparency be much longer

-42-


than their true values. To get rid of this undesired effect a device known as probe is used. The oscilloscope probe is an RC voltage attenuator as shown in Figure 2.34, where V^i denotes the voltage at die amplifier output and V2 is the voltage at the oscilloscope input Typically, a probe introduces 10 times attenuation of the input signal. If the probe capacitance Cp is properly adjusted, the attenuation is constant over a very wide frequency range. Such a probe is said to be compensated. For a compensated ptobe with 10-times attenuation, the input capacitance is 10 times lower than the oscilloscope + cable capacitance. Thus the apparent reduction in the higher cut-off frequency is not as severe as it is with the CRO directly connected to the amplifier.

Figure 234 Schematic diagram of the oscilloscope probe

Example 2.3 Find the values of Rp and Cp of the oscilloscope probe in Figure 2.34 such that the attenuation V2/V\ is equal to 10 for all frequencies. Assume RCRO = 1 Mft and CCRO =100 pF. Solution. One can easily verify that the transfer function of the probe is described by

Av=^ = P ^ n (2-70) Vl Rr, +R l + J*>RCROCCRO ^

^R° P 1 + jaRpCp It will be a constant equal to Aw = *CRO ( 2 J 1 )

RCRO + Rp

for all frequencies if the following condition is satisfied

RpCp = RcROCCRO (2-72)

Putting Avo = 0.1 in Equation (2.71) one obtains.Kp = 9 MQ, which substituted into condition (2.72) gives Cp = 11.1 pF. It is suggested to the reader to find out that the input capacitance of the probe + oscilloscope arrangement is, under these circumstances, equal to Cm = 10 pF, whereas the parallel resistance Rin that loads the amplifier output is Rin = 10 MQ.

Example 2.4 Find the upper cut-off frequency of the amplifier in Figure 2.33, as measured using a 10-times attenuating compensated probe. Solution. We replace the oscilloscope equivalent RCROCCRO in Figure 2.33 by a parallel connection of Rin and Cm that represent the probe of Figure 2.34. Thus the equivalent output resistance of the amplifier is now equal to

1 1 1 1 — = — + — + — (2.73) R0

ro RL Rin which for the assumed values gives Ro = 5.300 kfl. The equivalent capacitance is equal to (Co + Cm)= 20 pF. The time constant is the product Ro(G+Cm), which is m = 106 ns. This corresponds to the upper cut-off frequency of jk = 1.5 MHz and the rise time of £ = 0.23 ^s. The latter value is much closer to the true value of 0.12 |is than the rise time of 1.28 |4.s, as measured straight by the oscilloscope with no probe. This illustrates the advantage of using die probe for wideband amplifier characterization.

-43 -


2.9 Nonlinear Distortion

Consider again an ideal resistive amplifier. Define its transfer characteristic as a ratio of the instantaneous output to instantaneous input For an ideal amplifier, the transfer characteristic can be plotted as a straight line on the output-input plane. For real amplifiers, diis characteristic remains linear over only a limited range of input and output voltages. For an amplifier operated from two power supplies the output voltage cannot exceed a specified positive limit and cannot decrease below a specified negative limit. Thus the output becomes saturated for large positive and large negative inputs. The resulting transfer characteristic is shown in Fig. 2.35, with the positive and the negative saturation levels denoted as L+ and L_, respectively. Each of the two saturation limits is usually within 1 or 2 volts of the corresponding power supply. The output signal becomes distorted when me input exceeds the respective values 2,+ / Ay and L_ I Ay. Obviously, in order to avoid distorting the output signal waveform, the input signal swing should be kept within the linear range of operation L_/A,Zv,ZLJA, (2.74)

Fig. 2.35 shows the input waveforms (1) and (2) and the corresponding output waveforms. We note that the peaks of the larger waveform have been dipped off because of the saturation effect In some applications, like audio signal amplification, clipping is perceived as a rather severe distortion. Even small departures from linearity can be considered to be very serious in such cases. Assume the output-input relationship of a nonlinear amplifier can be written as

vo(0 = M-(') + 2[v,(')]2 +4J[V,(013 +••• (2.75) where Au A& A3 and so on are constants selected so diat the equation (2.75) matches the curvature

of the nonlinear transfer characteristic. Obviously, for a linear amplifier, A2-A3 =...= 0. Consider

the case for which the input signal is a sinusoid given by

v / (0 = ^ocos(fl>or) (2.76) Now, we find an expression for the corresponding output signal. Substituting equation (2.76) into

(2.75), applying trigonometric identities for [cos(flJ^]*, collecting terms and defining V0 to be the

sum of all of the constant terms, V, to be the sum of the terms with frequency 0)^, and so on, we

find that v0 (0 = V0Q + Vol cos(<V) + Vo2 cos(2<V) + Vo3 cos(30)ot) + ••• (2.77)

Figure 2.35 An amplifier transfer characteristic that is linear except for output saturation

-44 -


The desired output is the VQ\ cos(co0t) term, which we call the fundamental component. The

KJQ term represents a shift in the dc level (which does not appear at the load if it is ac-coupled). In addition, terms at multiples of the input frequency have resulted from the second and higher order nonlinear terms of the transfer characteristic (2.75). These terms are called harmonic distortion. The 2co0 term is called second harmonic, the 3co0 term is die third harmonic, and so on. Harmonic distortion is objectionable in a wideband amplifier because the harmonic can fall in die frequency range of the desired signal In an audio amplifier, harmonic distortion degrades die aesthetic qualities of the sound produced by the loudspeakers.

The second harmonic distortion factor D2 is defined as die ratio of the amplitude of the second harmonic to the amplitude of the fundamental.

£ ) 2 = ^ 2 (2.78) V°l

Similarly the third-order harmonic distortion factor, and so on, are defined as

B-J-03 D 4 3 4 - (2.79) 3 v0{ vol

The total harmonic distortion (THD) denoted by D is defined as

D = VA2+^2+A2+- (Z8°) We can often find THD expressed as a percentage. A well-designed audio amplifier might have a THD specification of 0.01% (i.e. D- 0.0001) at rated output power.

Notice diat THD specification of an amplifier depends of die amplitude of the output signal because the degree of nonlinearity of the transfer characteristic is amplitude-dependent. Certainly, any amplifier clips me output signal if the input becomes large enough. When clipping occurs, THD becomes large.

Harmonic distortion is usually not a problem for bandpass amplifiers if the bandwidth is narrow enough so mat harmonics fall outside the frequency range of the desired signal. However, amplifier nonlinearity causes another type of distortion that can be very troublesome even for narrowband amplifiers. This is intermodulation and crossmodulation distortion that appear when die amplifier is excited by a sum of two or more sinusoidal components of close frequencies. Some of die intermodulation components generated due to amplifier nonlinearity fall into the original frequency band. The crossmodulation, which is the transfer of the amplitude of one input signal to a term wim a frequency of anodier input signal, is a very serious problem for radio receivers. These topics, however, fall outside the scope of this texdbook.

Exercise 2.5 For the bipolar transistor amplifier shown below, write the PSpice code, run .AC analysis and plot amplitude and phase characteristics in the frequency range from 1Hz to 10MHz, 100 points per decade. Identify the midband frequency range of this amplifier and find its half-power bandwidth. Calculate its voltage, current and power gains at 1kHz. Explain me role of die capacitors C: and C0 in the circuit

-45-


l> I RS CS | jg~""

" • • I T

cc

s

Exercise 2.5- bipolar transistor common-amitter amplifier Vs 1 0 ac InV Rs 1 2 Ik Cs 2 3 luF RBI 7 3 330k RB2 3 0 100k Ql 5 3 4 Q2N2222A .LIB EVAL.LIB RE 4 0 10k

470uF 12k luF 10k

4 7 5 6

CE RC Co RL VCC 7 0 10V .ac dec 100 1Hz 10MEGHZ .end

Exercise 2.6 For the bipolar transistor amplifier of Exercise 2.5, modify the PSpice code to run the transient and Fourier analyses for the time interval of 5ms, assuming that the input signal is a sinusoidal waveform of frequency 1 kHz and amplitude 1 mV. Repeat the simulation 10 times, each time for a different value of the input signal amplitude, covering the range from 2 mV to 20 mV. For each value of Vs: (a) plot the waveforms of v(6) and -A*ik on a common diagram and compare their shapes, (b) find the corresponding value of THD, as recorded in the output file. (c) make the plot of the total harmonic distortion of the output signal as a function of input signal

amplitude.

2.10 Summary

Linear amplifiers obey the- superposition principle. Their transfer characteristic, output voltage versus the input voltage, is a straight line with a slope equal to the voltage gain. Linear amplification can be obtained from a device having a nonlinear transfer characteristic by employing dc biasing and keeping the input signal amplitude small Depending on the signal to be amplified (voltage or current) and on the desired form of output signal (voltage or current), there are 4 basic amplifier types: voltage, current, transresistance and transconductance amplifiers. Amplifiers can be cascaded to increase the gain available, provided loading effects are taken into account Amplifiers increase

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the signal power and thus require dc power supplies for their operation, to convert the dc current energy from the power supply into the ac current energy of the signal amplified. Sinusoidal signals are invariant to linear operators; they are used to measure the frequency response of linear amplifiers. Amplifiers are classified according to the shape of their amplitude characteristic as lowpass, bandpass or highpass. The banpass amplifiers can be narrowband or wideband. Ac-coupled amplifiers are used to filter out dc component of the input signal and to break the dc current path between the signal source and the amplifier input, as well as between the amplifier output and the load. Ac-coupled amplifiers can never be classified as lowpass; they are either highpass or, more realistically, bandpass. In every physical amplifier there are always stray wiring or component capacitances in parallel with the signal path present At high frequencies they act as low-impedance shunting elements that reduce the amplifier gain. Thus every physical amplifier has a limited bandwidth. The amplifier gain remains almost constant over the midfrequency band. It falls off at high frequencies where stray capacitances of components and devices no longer have high reactance. For ac amplifiers the gain falls off at low frequencies as well, because the coupling capacitors no longer have very low reactance. The amplifier bandwidth is the frequency range over which the gain remains within 3dB of the value at midband. The limits of the bandwidth are the frequencies^, and^. (For dc amplifier only fr is meaningful). Variations of the amplitude and phase characteristics of an amplifier with frequency may cause distortion to the signal shape. Amplifiers do not distort signals if their gain is constant and phase is proportional to frequency for the range of frequencies contained in the input signal. If the frequency response of an amplifier is inadequate for a particular signal, there will be linear distortion — either amplitude distortion or phase distortion, or both. The shape of the unit step and pulse responses of the amplifier is related to its transfer function. Large bandwidth amplifiers produce pulses with a short rise time. Small values of the lower cutoff frequency give low percentage tilt. If the input signal amplitude is not sufficiently small, nonlinear distortion occurs due to inherent nonlinearities of amplifying devices. Nonlinear amplifiers do not obey the superposition principle. For sinusoidal input, sine waves of frequencies different to the input signal frequency appear in the output signal spectrum. Their amplitudes relative to the amplitude of the input sine-wave signal are the measure of nonlinear distortion introduced by an amplifier.

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Analog Electronics /Diodes

3. Diode Circuits

The simplest and most fundamental element of semiconductor circuits is the diode. Just like a resistor, it has two terminals; but unlike the resistor, it is a nonlinear element This chapter is concerned with the study of basic circuits that contain diodes. In order to understand the essence of diode function, we begin with a fictitious element, the ideal diode. We then introduce the real semiconductor junction diode, explain its terminal i-v characteristic and provide techniques for the analysis of diode circuits. The latter task involves the important subject of diode modeling, both for large-signal and small-signal applications.

Of the many applications of diodes, their use in the design of rectifiers (which convert ac to dc) is the most common. Therefore, we shall study rectifier circuit in some detail and briefly look at a number of other diode applications.

The semiconductor diode is a two-terminal device that incorporates a pn junction. The pn junction is the basis of many other solid-state devices, including the bipolar junction transistor. Thus an understanding of the/>» junction is essential to the study the material of this chapter.

3.1 The Ideal Diode

The ideal diode is a two-terminal device having the circuit symbol of Fig. 3.1(a) and the i-v characteristic shown in Fig. 3.1(b). One of its terminals is called the anode and the other is the cathode. The voltage v across the diode is referenced positive at the anode and negative at the cathode. The current is referenced positive when it flows from the anode to the cathode. The terminal characteristic of the ideal diode can be interpreted as follows: If a negative voltage is applied to the diode, no current flows and the diode behaves as an open circuit [Fig. 3.1(c)]. Diodes operated in this mode are said to be reverse biased, or operated in the reverse direction. An ideal diode has a zero current when operated in the reverse direction and is said to be cut-off.

(c) (d)

Figure 3.1 The ideal diode: circuit symbol (a), i-v characteristic (b), equivalent circuit in the reverse direction (c), equivalent circuit in the forward direction (d).

On the other hand, if a positive current is applied to the ideal diode, zero voltage-drop appears across the diode. In other words, the ideal diode behaves as a short circuit when biased in the forward direction [Fig. 3.1(d)]. It passes any current with zero voltage-drop. A forward-biased diode is called to be turned on or simply on.

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It is evident from Fig. 3.1(b) that the i-v characteristic is far away from a linear relationship. It contains two straight-line segments at 90 degrees one to another; thus it is highly nonlinear, although one may say it is piecewise linear. Other variations of piecewise-linear diode descriptions will be considered later in this chapter.

'D VD 'D .. _n l D =0 vD=0 VD

(d) Figure 3.2 Rectifier circuit (a): equivalent circuit for vs>0 (b), equivalent circuit for v^0 (c),

input waveform (d, upper panel),output waveform (d, lower panel).

The fundamental application of the diode, one that makes use of its severely nonlinear i-v curve, is the rectifier circuit shown in Fig. 3.2a. The circuit consists of a series connection of a diode D and a resistor R. Let the input voltage be the sinusoid shown in Fig. 3.2d, and assume the diode to be ideal. During the positive half-cycles of the input sinusoid, the positive vs will cause current to flow through the diode in its forward direction. It follows that the voltage drop across the ideal diode will be zero. Thus the circuit will have the equivalent shown in Fig. 3.2(b), and the output )ltage vQ will be equal to the input voltage rs. On the other hand, during the negative half-cyciits of pf, the diode will not conduct. Thus the circuit will have the equivalent shown in Fig. 3.2c, and the output voltage will be zero. Note that while vs alternates in polarity and has a zero average value, v0 is unidirectional and has a finite average value, or a non-zero dc component. Thus the circuit from Fig. 3.2a rectifiers the signal and hence is called a rectifier. It can be used to generate dc from ac. We will study more complex rectifier circuits later in this chapter.

Exercise 3.1.For the circuit in Fig. 3.2a, sketch the transfer characteristic vQ versus vs. Exercise 3.2 For the circuit in Fig. 3.2a, sketch the waveform of the voltage across the diode.

12V

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Example 3.1 Fig. 3.3 shows a circuit for charging a 12-V battery. If vs is a sinusoid with 24-V peak amplitude, find the fraction of each cycle during which the (ideal) diode is on. Also find the peak value of the diode current and the maximum voltage that appears across die diode and, finally, find the average current that charges the battery. Solution The diode conducts when ?s exceeds 12V, as shown in Fig. 3.3(b). The conduction angle is 20, where 6 is given by 24cos(6[)=12. Thus #=60° and the conduction angle is 120°, or one-third of a cycle. The peak value of the diode current occurs when the input voltage is maximum, and is given by 7d=(24-12)/10 = 1.2A. The maximum reverse voltage across the diode occurs when vs is at negative peak and is equal to 24V+12V = 36V. The average current which

1 * charges the battery is given as 1^ = —— J Id cos(g)d£ = 0.33 A, where £ is the integration

1 IT * In variable.

+5V

00 (b) Figure 3.4 Diode logic gates: (a) OR gate; (b) AND gate

Diodes together with resistors can be used to implement digital logic functions. Fig. 3.4 shows two diode logic gates. To see how these circuits function, consider a positive logic system in which voltage values close to 0 correspond to logic 0 (or low state) and voltage voltages close to +5V correspond to logic 1 (or high state). The circuit in Fig. 3.4a has three inputs, vA, vB, and vc. It is easy to see that diodes connected to +5V will conduct, thus clamping the output voltage vY

to a value equal to +5V. This positive output voltage will keep the diodes whose anodes are low (at zero voltage) cut off. Thus the output will be high if one or more inputs are high. The circuit in Fig. 3.4a therefore implements the logic OR function, which in Boolean notation is expressed as

Y = A + B + C

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Similarly, the reader is encouraged to show that the circuit in Fig. 3.4b implements the logic AND function, that is

Y = ABC.

In analysis of circuits containing ideal diodes we may not know in advance which diodes are on and which are off. Thus we are forced to make a considered guess. Then we analyze the circuit to find the currents in the diodes assumed to be on and the voltage across the diodes assumed to be off. If the current iD through the diodes assumed to be on is positive and the voltage vD across the diodes assumed to be off is negative, our assumptions are correct and we have solved the circuit. Otherwise, me must make another assumption about the diodes and try again. After a little practice, our first guess is usually correct, at least for simple circuits.

+I0V +I0V

r-10V

00 (b) Figure 3.5 Circuits for Example 3.2

Example 3.2 Assuming the diodes to be ideal, find values of J and Kin the circuits of Fig. 3.5. Solution In these circuits it might not be obvious at first sight whether none, one or both diodes are conducting. In such a case we make a plausible assumption, proceed with the analysis and then check whether we end up with a consistent solution. For the circuit in Fig. 3.5a, we shall assume that both diodes are conducting. It follows that VB=0 and V=0. The current through D2 can now be determined from ID2 = (10V-0V)/10k = 1mA. Writing the first Kirchhoff s law equation for node 8 we obtain 1+lmA^ (0-(-l 0V))/5k = 2mA. Thus I=2mA-lmA = 1mA is larger then zero and thus diode D l is conducting as originally assumed, and the final result is J=lmA, K=0. For the circuit in Fig. 3.5b, if we assume that both diodes are conducting, then VB=0 and V=0. The current through D2 is obtained from ID2 = (10V - 0V)/5k = 2mA The node equation at B is I+2mA = (OV - (-10V))/10k which yields I—1mA. The current is negative, so this result is not consistent with the assumption that diode D l is on. We start again, assuming that D l is off and D2 is on. The current through diode D2 is given by ID2 = (10V-(-10V))/(10k+5k)=1.33mA and the voltage at node B is VB = -10V +10k*1.33mA = 3.3V. Thus the voltage across D l is negative (the anode is at 2ero and the cathode is at +3.3V), which means diode D l is off as assumed, and the final result is 7=0 and K=3.3V.

Exercise 3.3 Find the current I and voltage V for the circuits shown in Fig.3.6. Ans. (a) 2mA, 0V, (b) 0mA, 5V, (c) 0mA, -5V, (d) 2mA, 0V, (e) 3mA, 3V, (f) 4mA, IV.

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(e) (0 Figure 3.6 Circuits for Exercise 3.3

Exercise 3.4 Find the state of the ideal diodes in the circuits of Fig. 3.7

lkQ

5mA

|6kfi

4kO

1 © T3V

10V

Figure 3.7 Circuits for Exercise 3.4

Exercise 3.5 Fig. 3.8 shows a circuit for an ac voltmeter. It utilizes a moving-coil meter that gives a full-scale reading when the average current flowing through it is 1mA. Hie moving-coil meter has a 50 Q resistance. Find the value R that results in the meter indicating full-scale reading

when the input sine-wave voltage rs is 20V peak-to-peak. Ans. R=3.133 kfi.

o—W-

Moving-coil 'oJ meter

Figure 3.8 Circuit for Exercise 3.5

3.2 Terminal Characteristics of Semiconductor Diodes

In this section we study the characteristics of real diodes - specifically semiconductor junction diodes made of silicon. Fig. 3.9 shows an example of the i-v characteristic of a silicon junction diode. As indicated, the characteristic curve consists of three distinct regions:

1. The forward-bias region determined by v>0.

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Analog Electronics / Diodes

2. The reverse-bias region, determined by v<0. 3. The breakdown region, determined by v< Vz.

The three regions of operation are described in the following.

Figure 3.9 The i-v characteristic of a silicon-junction diode (a), the diode i-v relationship with negative current scale expanded and negative voltage scale compressed.

The forward-bias region. The forward-bias region of operation is entered when the terminal voltage v is positive. In the forward region, the i-v relationship is closely approximated by the Shockley equation

i = /J«p(-£-)-l] (3-1) In diis equation, Is is the saturation current, which is constant for a given diode and given temperature. A better name for Is is the scale current - it is direcdy proportional to the crosv sectional area of the diode semiconductor structure. Thus doubling the junction area results in a diode with double the value of Is and, as (3.1) indicates, double the current / for a given forward voltage v. For low-power or "small-signal" diodes, which are small-size, diodes intended for low-power applications, Ty is in the order of 10"15A. The value of Is is a very strong function of temperature. As a rule of thumb, Is of a silicon diode doubles in value for every 10° rise in temperature.

The voltage VT in (3.1) is a constant called the thermal voltage, given by VT = kT/q (3.2) where k is Boltzmann's constant equal to 1.38-10-23 joules/kelvin, Tis the absolute temperature in kelvins and q is the magnitude of electronic charge equal to 1.602-10"19 coulomb. At room temperature, (20°C=293K) VT is 25.2 mV. In rapid, approximate circuit analysis we can use P/'r=25mV at room temperature.

The constant n in the diode equation has a value between 1 and 2, depending on the material and the physical structure of the diode. Diodes made using the standard integrated-circuit fabrication process exhibit n=\ when operated under normal conditions (low and moderate current). Diodes available as discrete two-terminal components generally exhibit n-2. For appreciable current /' in the forward direction, specifically for i»Is, equation (3.1) can be approximated by the exponential relationship

v « = / s e x P ( — ) (3.3)

The relationship between the voltage and the current in the forward direction takes the logarithmic form, as can be obtained from (3.3)

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v = nVT\n{—) (3.4)

The exponential relationship of the current / to the voltage v holds over many decades of current (a span of as many as seven decades - that is a factor of 1CK7- can be found). This is quite a remarkable property of junction diodes (and bipolar transistors as well), one that has been exploited in many interesting applications. The diode i-v characteristic is then most conveniently plotted on a semilog paper. One can show that using the vertical, linear axis for v and the horizontal, log axis for i, one obtains from (3.3) a straight line with a slope of 2.3«KTper decade of current.

Since both Is and VT in (3.3) are functions of temperature, the forward i-v characteristic varies with temperature as illustrated in Fig. 3.10. At a constant diode current, the voltage drop across the silicon diode decreases by approximately 2mV for every kelvin increase in temperature. This property has been exploited in the design of electronic thermometers.

A glance at the i-v characteristic in the forward region (Fig. 3.9) reveals that the current / is negligibly small for v smaller than about 0.5V. This value is usually referred to as the knee voltage. It should be emphasized, however, that this apparent threshold in the diode characteristic is simply a consequence of the exponential relationship. Another consequence of this relationship is the rapid increase of /'. Thus for a "fully conducting" diode; the voltage drop across it lies in a narrow range, approximately from 0.6 to 0.8V for silicon diodes. This gives rise to a simple model of a diode where it is assumed that a conducting diode is replaced by a 0.7-V battery. This constant-voltage-drop model is discussed later on in this chapter. Diodes with different ratings (i.e. different areas and different 1$) will exhibit the 0.7-V drop at different currents. For instance, a low-power switching diode may be considered to have 0.7V drop at /'=lmA, while a higher power diode may have a 0.7V drop at /-1A.

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The reverse-bias region. The reverse-bias region is entered when the diode voltage v is made negative. Equation (3.1) predicts that if v is negative and its absolute value is a few times larger than VT (25mV), the exponential term becomes negligibly small compared to unity and the diode current becomes i=-Is (3.5) that is, the current in the reverse direction is constant and equal to Is-.'m magnitude. This is the reason behind the term saturation current: the current saturates when-1 v\>Vj, v<0. In fact, the saturation current increases with | v\ for real silicon diodes, due to the charge carriers generation-recombination phenomena that occur in the depletion layer. Moreover, real diodes exhibit reverse currents that, though quite small, are much larger than Is. For instance, a low current or 1-mA diode whose Is is of the order of 10"14 A to 10"15 A could show a reverse current of the order of 1 nA. A good part of the reverse current is due to the leakage effects. These leakage currents are proportional to the junction area, just as Is is. Note that because of the very small magnitude of the current these details are not clearly evident on the diode i-v characteristic such as on that of Fig. 3.9.

The breakdown region. The third distinct region of diode operation is the breakdown region, which can be easily identified on the diode i-v characteristic in Fig. 3.9. The breakdown region is entered when the magnitude of the reverse voltage exceeds a threshold value specific to the particular diode and called the breakdown voltage. This is the voltage at the left-hand-side "knee" of the i-v curve in Fig. 3.9 and is denoted Kz, where the subscript Z stands for Zener (regardless of the Zener or avalanche breakdown phenomenon takes actually place within the device as is discussed below in this Section).

Zener diodes are intended to operate in the reverse breakdown region of the diode characteristic. Most desirable characteristics of Zener diodes in many of their applications are:

1. Precise voltage in the breakdown region. 2. Breakdown voltage that is independent of temperature. 3. Extremely low dynamic impedance in the breakdown region (i.e. nearly vertical

current versus voltage characteristic).

Two mechanisms are responsible for breakdown oipn junctions under reverse bias. One is called avalanche. As the reverse-bias voltage is increased, the width of the depletion region increases. Furthermore, in the center of the depletion region, the electric field becomes more intense. This field accelerates minority carriers from both sides of the junction that diffuse into the depletion region. In moving through the material, the charge carriers repeatedly collide with the atoms in die crystal lattice.

Under certain conditions of doping and applied voltage, the carriers gain sufficient energy between collisions to break a covalent bond. This liberates two additional free charge carriers, one hole and one electron, which are accelerated, eventually releasing additional charge carriers. The term avalanche is rather descriptive of the process. The result is a large current flowing through the reverse bias diode.

Avalanche does not occur until the field is strong enough so that the charge carriers can obtain enough energy between collisions to break a covalent bond. A junction very lightly doped on both sides has a very thick depletion region. Thus the field (volts/meter) is not sufficiently intense until the applied voltage is very high.

The average distance that frees charge carriers travel between collisions decreases with temperature. Therefore, at higher temperatures a slightly higher voltage must be applied before avalanche breakdown occurs.

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The second mechanism causing breakdown is called the Zener effect. It occurs in abrupt junctions having high doping levels. For such junctions, the depletion region is very narrow because die charge density of ionized dopant atoms is high and a large amount of charge can be stored in a very thin layer. As reverse bias is applied, the field in the depletion region increases in intensity. When the field strength is of the order of 1 V divided by the crystal lattice spacing, it is possible for covalent bonds to be broken by the field. In other words, the forces are so strong that electrons are pulled loose from their bonds.

The energy gap between the top of the valence band and the bottom of the conduction band becomes slightly smaller with increased temperature. Hence the force required to break the covalent bonds is slighdy smaller at higher temperatures. As a result, if the Zener effect is responsible for breakdown, the breakdown voltage tends to become smaller with increased temperature. This is opposite to the case for avalanche breakdown.

As a rule, the Zener effect is responsible if the breakdown voltage magnitude is less man 6 V, and the avalanche effect is responsible if the breakdown voltage is greater than 6 V. For diodes having breakdown voltages of approximately 6 V, a mixture of both mechanisms can occur. It is possible to obtain diodes having breakdown voltages of about 6 V with very small temperature coefficients, because the temperature effects of the two breakdown types offset one another. Dynamic impedance also tends to be a function of breakdown voltage, reaching a minimum for breakdown voltages of about 6 V. Thus, as circuit designers, we tend to select 6-V diodes.

As can be seen from Fig. 3.9, in the breakdown region the reverse current increases rapidly, and the associated increase in the voltage drop is very small. Diode breakdown is normally not destructive, provided that the power dissipated in the diode is limited by external circuitry to a "safe" level. This safe value is normally specified on the device data sheets. It therefore is necessary to limit the reverse current in the breakdown region such that the product of the dc current and the dc voltage is lower than the permissible power dissipation.

The fact that the diode i-v characteristic in breakdown is almost a vertical line enables it to be used in voltage regulation (stabilization). This subject will be studied in Section 3.6.

3.3 Analysis of Diode Circuits

In this section, we shall study methods for the analysis of diode circuits. We shall concentrate on circuits in which the diodes are operating in the forward-bias region. Operation in the breakdown region is considered in Section 3.5.

Consider the circuit shown in Fig. 3.11 consisting of a dc source VDDJ a resistor R and a diode. We wish to analyze this circuit to determine the diode current ID and the diode voltage VD.

R ID

Figure 3.11 A simple diode circuit

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The diode is obviously biased in the forward direction. Assuming that VDD is greater than 0.1V or so, the diode current will be much greater than Is and we can represent the diode i-v characteristic by the exponential relationship

/D = / S e x p ( - ^ - ) (3.6)

The other equation that governs the circuit operation is obtained by writing a Kirchhoff loop equation, resulting in ID=(VDD-VD)/R (3.7) Assuming that the diode parameters Is and n are known, Eqs. (3.6) and (3.7) are two equations in the two unknown quantities ID and Vp. Two alternative ways for obtaining the solution are graphical analysis and iterative analysis.

Graphical analysis. Graphical analysis is performed by plotting the relationship (3.6) and (3.7) on the i-v plane. The solution can then be obtained as the coordinates of the point of intersection of the two graphs. A sketch of the graphical construction is shown in Fig. 3.11; the curve represents the exponential diode equation (3.6) and the straight line represents (3.7). Such a straight line is known as the load line, a name that will become more meaningful in later chapters. The load line intersects the diode curve at point Q, which represents the operating point of the circuit. Its coordinates give the values of ID and VD.

Graphical analysis aids in the visualization of circuit operation. However, the effort involved in performing such an analysis, particularly for complex circuits, is too great to be justified in practice.

VDD/R 0-point

o vD vDD

Figure 3.12 Graphical analysis of the circuit in Fig. 3.11

Iterative analysis. Equations (3.6) and (3.7) can be solved using a simple iterative procedure, as the one illustrated in the following example.

Example 3.3 Determine the current ID and the diode voltage VD for the circuit in Fig. 3.11 with KDD=5V and R=lk. Assume t h a t ^ l O 1 0 , «=1.7. Solution Taking a look at Figure 3.11 one may arrive at conclusion that the diode is biased into the forward direction. Thus Equation (3.6) describes the diode current Taking a natural logarithm of both sides of (3.6) one obtains VD=»VTki(ID/Q. Now, substituting (3.7) for ID in the above formula gives VD=»VT]n((VDD-VD)/(RIs)) The last equation can be rewritten for iterative calculations, such that the diode voltage in iteration (k+1) is related to its value in the previous iteration (k) as follows VDW = »VT]n((VDD-VD<»)/(RIs))

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Assume the initial guess tor the diode voltage is VD —0.5V. Its values and the corresponding values of the current in successive iterations are

k vj> J « 0 0.5V 0.013mA 1 0.748942V 4.500mA 2 0.746524V 4.251mA 3 0.746524V 4.251mA 4 . . .

Thus the third iteration yields JD=4.251mA and KD=0.74624V. Since these values are not much different from the values obtained after the second iteration, no further iterations are necessary.

Figure 3.13 The effect of diode series resistance

The iterative analysis procedure utilized in the example above is simple and yields accurate results after two or three iterations. Nevertheless, there are situations in which the effort and time required to perform the iterative calculations are still greater than can be justified. Specifically, when one is doing a pencil-and-paper design of a relatively complex circuit, rapid circuit analysis is a necessity. Through quick analysis, the designer is able to evaluate various possibilities before deciding on a suitable circuit. To speed up the analysis process, one must be content with less precise results. This, however, is seldom a problem, as the more accurate analysis can be postponed until a final or almost final design is obtained. Accurate analysis of the final or almost final design can be performed with the aid of a computer-analysis program such as SPICE. The results of such an analysis can then be used to further refine or "fine-tune" the design.

Diode models. At high current levels, the ohmic resistance of the semiconductor forming the junction becomes significant. Addition of a series resistance Rt to the diode modeled by the Shockley equation (3.1) can account for this. The modified version of (3.4) becomes

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v-«FI.In(7-) + « J (3.8)

Typical low-current diodes have Revalues ranging from 10 to 100Q. The resistance R, decreases with the diode cross-sectional area. Thus for high-current diodes it is of the order of 0.1Q. The effect of die diode series resistance on the i-v characteristic is illustrated in Fig. 3.13. For a fixed value of current, the voltage drop across the diode external terminals increases with the series resistance value.

Slope=l/r£)

(c) Figure 3.14 Approximating the diode forward characteristic with two straight lines (a), (b);

equivalent circuit representation of the piecewise-linear model (c).

Although the exponential i-v characteristic plus a series resistance is an accurate model in the forward region, its nonlinear nature complicates the analysis of diode circuits. The analysis can be greatly simplified if we can find piecewise-linear relationship to describe the diode terminal characteristics. An attempt in this direction is illustrated in Fig. 3.14, where the exponential curve is approximated by two straight-line segments, line A with zero slope and line B with a slope of //rD. It can be seen that for this particular diode, over the current range from 0 to 10mA the voltages predicted by the straight-line model differ from those predicted by the exponential model by less than 50 mV. Of course, the choice of two lines is not unique; one can obtain a closer approximation by restricting the current range over which the approximation is required.

The straight-lines (or piecewise-linear) model of Fig. 3.14 can be described by

»D = °> VD ^ VDo

h = Do

vD>VDo (3.9)

where VD, is the intercept of line B on the voltage axis and rD is the inverse of the slope of line B. For the particular example shown, VD, = 0.65 V and rD = 20 Q.

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The equivalent circuit shown in Fig. 3.14c can represent the piecewise-linear model described by (3.8). Note that an ideal diode is included in this model to constrain iD to flow in the forward direction only. This model is also known as the "battery-plus-resistance" model.

Example 3.4 Repeat the problem in Example 3.3 utilizing the piecewise-linear model whose parameters are VDt — 0.65 V, rD = 20 Q. Solution Replacing the diode in Fig. 3.11 with the equivalent circuit model of Fig. 3.14c results in the circuit in Fig. 3.15, from which we can write the current ID

ID = {VDD - VJ/(R + rD) =4.26mA The diode voltage can now be computed VD = VD. + roID = 0.7353V Note that the values obtained using the simplified model are not very much different from the accurate values obtained in Example 3.3.

Figure 3.15 The circuit of Fig. 3.11 with the diode replaced by its piecewise-linear model of Fig. 3.14c.

An even simpler model of the diode forward characteristic can be obtained if we use a vertical straight line to approximate the fast-rising part of the exponential curve, as shown in Fig. 3.16a. The resulting model simply says that a forward-conducting diode exhibits a constant voltage drop VD. The value of VD for silicon diodes is usually taken to be 0.7V. The equivalent circuit shown in Fig. 3.16c can represent the constant-voltage-drop model. This model is the one most frequently employed in initial phases of analysis and design. Finally, note that if we employ the constant-voltage-drop model to solve the problem in Examples 3.3 and 3.4 we obtain IQ = (VDD -VD)IRID = 4.3 mA which is not too differ^ it from the values obtained with the more elaborate models.

V, D (b)

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Ideal VD

(c) Figure 3.16 Development of the constant-voltage-drop model of the diode forward characteristic with

two straight lines (a), (b); equivalent circuit representation of the model (c).

In applications that involve voltages much greater than the diode voltage drop (0.6 - 0.8V), we may neglect the diode voltage drop altogether while calculating the diode current The result is die ideal diode model, which we studied in Section 3.1.

The question of which diode model to use in a particular application is one a circuit designer faces repeatedly, not just with diodes but with every circuit element. One's ability to select appropriate device models improves widi practice and experience.

3.4 The Diode Small-Signal Model at Low Frequencies

We will encounter many examples of electronic circuits in which dc supply voltages are used to bias a nonlinear device at an operating point and a small ac signal is injected into the circuit. We often split analysis of such circuits into two parts. First, we analyze the dc circuit to find the operating point. In this analysis of bias conditions, we must deal with die nonlinear aspects of the device. In the second part of the analysis, we consider the small ac signal. Since virtually any nonlinear characteristic is approximately linear (straight) if we consider a sufficiendy small portion, we can find a linear small-signal equivalent circuit for the nonlinear device to use in die ac analysis.

The small-signal linear equivalent circuit is an important analysis approach that applies to many types of electronic circuits. In diis section we demonstrate the principles with a simple diode circuit. In the next chapter we use similar techniques for transistor amplifier circuits.

Now we will show that in the case of a diode, the small-signal equivalent circuit consists of a resistance. Consider a conceptual circuit in Fig. 3.17a and the corresponding graphical representation in Fig. 3.17b. A dc voltage Kp, represented by a battery, is applied to the diode; and a time-varying signal iy(/), assumed (arbitrarily) to have a triangular waveform, is added to (superimposed on) the dc voltage VD. In the absence of the signal ty(/) die diode voltage is equal to Vp, and correspondingly the diode will conduct the current ID given by the Shockley equation (3.1), which for VD»VT, (i.e. for sufficiently large forward current) simplifies to

/ D = / S e x p ( - ^ T ) (3-10)

When die signal ta(/) is applied, the total instantaneous diode voltage vD(t) will be given by vD(t) = VD+vd(t) (3.11)

Correspondingly, the total instantaneous diode current iD(t) will be

K'+V<('fl (3,2,

which can be rewritten

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Figure 3.17 Development of a diode small-signal model

Using (3.10) we obtain

/D(0 = /Dexp(^J

Now if the magnitude of the signal vt(t) is kept sufficiently small such that

v,(0 nVT

« 1

(3.14)

(3.15)

then we may expand the exponential of (3.14) into the Taylor series and truncate the series after the first two terms to obtain approximate expression

V ' ( ' ^ (3.16) iD(0 = ID ! + • nVT J

This is the small-signal approximation. It is valid for signals whose amplitudes are smaller than about lOmV.

From (3.16) we have

iD(0 = ID+^-vd(t) (3.17)

Thus superimposed on the dc current ID we have a signal component directly proportional to the signal voltage m(/). That is

where

<*(')=-F-^O nVT

(3.19)

The quantity relating the signal current it(t) to the signal voltage ty(/) has the dimensions of conductance, and is called the diode small-signal conductance. The inverse of this parameter is the diode small-signal resistance, incremental resistance, or dynamic resistance r&,

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r<=-f- (3-20)

Note that the value of rd is inversely proportional to the diode dc current JD.

Let us return to the graphical representation in Fig. 3.17b. It is easy to see that using the small-signal approximation is equivalent to assuming that the signal amplitude is sufficiently small such that the excursion along the i-v curve is limited to a short, almost linear segment. The slope of this segment, which is the slope of the i-v curve at the operating point J2 , is equal to the small-signal conductance. The reader is encouraged to prove that the slope of the i-v curve at i=ID is equal to 7D/(«KT), which is 1 /rd, that is,

di„ (3.21) rd=\/

dvD

Now, if we denote by VDo the point at which the tangent intersects the vD axis, we can describe die tangent by the equation

; D = l [ v D - F D o ] (3.22)

This equation is the model for the diode operation for small variations around the bias or quiescent point Q, in the forward region. The model can be represented by the equivalent circuit shown in Fig. 3.18, from which we can write vD = VDO + iDr„ =VDo+ IDrd + idrd =VD+ idrd (3.23) Thus, as expected, the signal voltage across the diode is given by Vd= id rd. We conclude that the small-signal approximation allows one to separate the dc analysis from the signal analysis. Eliminating all dc sources and replacing the diode with its small-signal resistance rd performs the signal analysis. The obtained small-signal equivalent circuit is then solved using linear circuit analysis techniques.

Ideal Vfo rd

Figure 3.18 Equivalent circuit model for the diode for small changes around a bias point Q. The incremental resistance r& is the inverse of the slope of the tangent at Q and the VDO is the intercept of

the tangent with the VD axis (see Fig. 3.17).

Note: Perhaps we should review at this moment the notation we have used for the diode currents and voltages, because we use similar notation throughout the book. • vD and iD represent the total instantaneous diode voltage and current. At times, we

may wish to emphasize the time-varying nature of these quantities and then we use vD{t) and iD(t).

• VD and ID represent the dc diode current and voltage at the quiescent point • Vd and id represent the (small) ac signals. If we wish to emphasize their time-

varying nature, we use Vd{t) and id(t)-

Now we consider an example of linear equivalent circuit analysis for a simple but useful small-signal diode circuit. The circuit is a voltage-controlled attenuator. It is shown in Fig. 3.19. The input to the circuit is a small ac voltage vs(t) and the output v0(t) is an attenuated version of the input. The amount of attenuation depends on the value of the dc control voltage Vc.

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Notice that the ac signal to be attenuated is connected to the circuit by a coupling capacitor. The output voltage is connected to the load R^ by a second coupling capacitor. However, the coupling capacitors are open circuits for dc. Thus die j2-point of die diode is unaffected by the signal source or the load. Furthermore, the coupling capacitors prevent (sometimes-undesirable) dc currents from flowing in the source or the load.

Figure 3.19 Variable attenuator using a diode as a controlled resistance

Because of the coupling capacitors, we only need to consider Vc, R^ and the diode to perform the dc analysis to find the =<2-point. The dc circuit is shown in Fig. 3.20. We can use any of the techniques discussed earliest in this chapter to find the jg-point. Once it is known the j2-point value of the diode current ID can be substituted into Equation (3.20) to determine the dynamic resistance of the diode.

Fig. 3.20 Dc circuit equivalent to Fig. 3.19 for jg-point analysis

Now we turn our attention to the ac signal. The dc control source should be considered as a short circuit for ac signals. In general, dc voltage sources have ac components of current, but no ac voltage -the dc voltage source is a short circuit for ac signals. This is an important concept that we will use many times in drawing ac equivalent circuits.

The equivalent circuit for ac signals is shown in Fig. 3.21. The capacitors have been replaced by short circuits, which means the signal frequency is assumed sufficiendy high for the capacitors' reacMnce to be much smaller than resistance R and R^ connected in series to capacitors C, and C2, respectively. The diode has been replaced by its dynamic resistance. This circuit is a voltage divider and can be analyzed by ordinary linear circuit analysis. The parallel combination of R^, RL

and rd is denoted as R^ given by 1

Rp \IRc+\IRL+\lrd.

Then the attenuation of the circuit is

^S vs R + Rp

Of course, Avs is less than unity.

(3.24)

(3.25)

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Figure 3.21 Small signal equivalent circuit for Figure 3.19

Exercise 3.6 Suppose that the circuit of Fig. 3.19 has R = 100 Q, R^ - 2 kQ, and R L = 2 kQ.

The diode has n - l and is at a temperature of 300K. For purposes of j2-point analysis assume a

constant diode voltage of 0.6 V. Find the j2-point value of the diode current and Avs for (a) Vc -

1.6 V and (b) Vc = 10.6 V. Ans. (a) 1D = 0.5 mA,Av = 0.331, (b) 7 D = 5 * 1 ^ , ^ = 0.0492.

An application for voltage-controlled attenuator occurs in tape recorders, as an example. A problem frequently encountered in recording a conversation is that some persons speak quietly, whereas others speak loudly. Furthermore, some may be far from the microphone, whereas others are close. If an amplifier with fixed gain is used between the microphone and the tape head, either the weak signals are small compared the noise level or the strong signals drive the recording nonlinear so that severe distortion occurs.

Figure 3.22 The voltage-controlled attenuator is useful in maintaining a suitable signal amplitude at the recording head

A solution is to use a voltage-controlled attenuator placed between the microphone and a high-gain amplifier in a system like that shown in Fig. 3.22. When the signal being recorded is weak, the control voltage is small and very little attenuation occurs. O n the other hand, when the signal is stron^, the control voltage is large, so the signal is attenuated, preventing distortion. Rectifying the output of the amplifier generates the control voltage. The rectified signal is filtered by a longtime-constant R C filter so that the attenuation responds to the long-term average signal amplitude rather than adjusting too rapidly. With proper design, this system can provide an acceptable signal at the recording heads for a wide range of input signal amplitudes. Eventually, we will discuss all of the circuits required in this system.

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Analog Electronics /Diode Circuits

3.5 Rectifier Circuits

Now that we have introduced the diode and some methods for analysis of diode circuits, we consider some practical circuits. First, we consider several types of rectifiers that convert ac power into dc power. These rectifiers form the basis for electronic power supplies and battery-charging circuits. Other applications for rectifiers are in signal processing, such as demodulation of a radio signal, or measuring the average amplitude of a signal from a microphone, as considered in the previous section. Another application is precision conversion of an ac signal to the dc in an electronic voltmeter.

Half-wave rectifier circuits. A half-wave rectifier with a sinusoidal source and resistive load is shown in Fig. 3.23a. (The same circuit has already been analyzed in Section 3.1, for the ideal diode case.). When the source voltage is positive, the diode is in the forward-bias region. If an ideal diode is assumed, the source voltage appears across the load. For a typical real diode, the output voltage is less than the source voltage by an amount equal to the drop across the diode, which is about 0.7V for silicon diodes at "room temperature". This can be seen in Fig. 3.23b.

(a) (b) Figure 3.23 Half-wave rectifier with resistive load (a); input and load voltages versus time (b)

If the source voltage is negative, the diode is reverse b;.. :d and no current flows through the load. Even for typical real diodes only a very small reverse current flows. Thus only the positive half-cycles of the source voltage appear across the load. One can use a half-wave rectifier to charge a battery, as shown in Fig. 3.3a. Current flows in that circuit whenever the instantaneous ac source voltage is higher than the battery voltage. As shown in the figure, it is often necessary to add resistance in series with the diode to limit the magnitude of the current. When the ac source voltage is less than'the battery voltage, the current is zero. Thus the current flows only in die direction that charges the battery.

Half-wave rectifier with smoothing capacitor. Often, we want to convert an ac voltage into a nearly constant dc voltage to be used as a power supply for our designs. One approach to smoothing the rectifier output is to place a large capacitor across the output terminals of the rectifier. The circuit and waveforms of current and voltage are shown in Fig. 3.24. When die ac source reaches a positive peak, the capacitor is charged to the peak voltage (assuming an ideal diode). Then when the voltage drops below the voltage stored on the capacitor, the diode is reverse biased and no current flows through the diode. The capacitor continues to supply current to the load, slowly discharging until the next positive peak of the ac input. As shown in the figure, current flows through the diode in pulses that recharge the capacitor.

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« (b) Figure 3.24 Half-wave rectifier with smoothing capacitor (a); voltage and current waveforms (b)

Because of the charge and discharge cycle, the load voltage contains a small ac component called ripple. Usually, it is desirable to minimize ripple, so we choose the largest capacitance value that is practical. In this case, the capacitor discharges for nearly the entire cycle, and the charge removed from the capacitor during one discharge cycle is QsJJ (3.26)

where IL is the average load current and T is the period of the ac voltage. Since the charge removed from the capacitor is the product of the change in voltage and the capacitance, we can also write Q=VrC (3.27)

where Vr is the peak-to-peak ripple voltage and C is the capacitance. Equating the right-hand sides of (3.27) and (3.26) allows one to solve for C

/ T

c = - £ - (3.28)

In practice, Equation (3.28) is approximate because the load current varies in time and because the cap; itor does not discharge for a complete cycle. However, it gives a good-starting value for the capacitance required in the design of power-supply circuits. We will return to the subject of power-supply design after we have introduced transistor circuits and operational amplifier feedback circuits.

The average voltage supplied to the load if a smoothing capacitor is used is approximately midway between the minimum and maximum voltages. Thus, referring to Fig. 3.24, the average load voltage is

V. vL=vm-vD- (3.29)

An important aspect of rectifier circuits is the peak inverse voltage (PIV) across the diodes. Of course, the breakdown specification of the diodes should be greater in magnitude than PIV. For example, in the half-wave circuit with a resistive load, shown in Fig. 3.23, the PIV is Vm. Addition of a smoothing capacitor in parallel with the load increases the PIV to (approximately) 2Vm. Referring to Fig. 3.24, for the negative peak of the ac input, we see that the reverse bias of the diode is the sum of the source voltage and the voltage stored on the capacitor.

Full-wave rectifier circuits. Several full-wave rectifiers are in common use. One approach uses a center-tapped transformer and two diodes as shown in Fig. 3.25a. This circuit consists of

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Analog Electronics/Diode Circuits

two half-wave rectifiers widi out-of-phase source voltages and a common load. The diodes conduct on alternate half-cycles.

Figure 3.25 Center-tapped-transformer full-wave rectifier

Besides providing the out-of-phase ac voltages, the transformer also allows adjustment of Vm by selection of turns ratio. This is an important function because the ac voltage available is often not suitable for direct rectification - usually either higher or lower dc voltage is required.

A second type of full-wave rectifier uses the diode bridge shown in Fig. 3.26a. When the ac voltage is positive at the top of the secondary winding, current flows through diode A, then through the load and returns through diode B as shown in the figure. For the opposite polarity, i.e. during the alternate half-cycle, current flows through diodes C and D. Notice that in either case the current flows in the same direction through the load. For real diodes, the peak voltage across the load is lower in the case of the diode bridge rectifier circuit compared to the center-tapped transformer rectifier circuit. This is because two diodes are connected in series with the load in the diode bridge circuit and, consequently, twice the voltage drop across a forward-biased diode is subtracted from the ac source voltage to obtain the load voltage. A single voltage drop across the diode is subtracted in the case of the circuit in Fig. 3.25a. This property is illustrated in Fig. 3.26b and Fig. 3.25b.

If one side of die load is connected to die ground as shown in Fig. 3.26a, neither of the ac source terminals of the diode bridge can be connected to the ground. The transformer with floating secondary winding helps to realize this condition. (If both the ac source and the load had a common ground connection and no transformer was used, part of die circuit would be shorted.)

If one wishes to smooth the voltage across the load, a capacitor can be placed in parallel with the load similar to the half-wave circuit discussed earlier. In the full-wave circuits, the capacitor

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discharges for only a half-cycle before being recharged. Thus the capacitance required maintaining a given level of ripple is only half as much in the full-wave circuit as for the half-wave circuit. Therefore, Equation (3.28) can be modified to obtain

C = -L-IV.

for the full-wave rectifier with a capacitor filter.

(3.30)

-5.9U + * •

n U U M I U ) •. UC2)

(b) Fig. 3.26 Diode-bridge full-wave rectifier

Power supply circuit. A diode rectifier forms an essential building block of the dc power supplies required to feed electronic equipment. A block diagram of such a power supply is shown in Fig. 3.27. As indicated, the power supply is fed from the 220-V (tms) 50-Hz ac line, and it delivers a dc voltage VL (usually in the range of 5 to 20V) to an electronic circuit represented by the load block. The dc voltage VL is required to be as constant as possible in spite of variations in the ac line voltage and in the current drawn by the load. Normally, the ripple at the output of a rectifier circuit, with a smoothing capacitor of practical value, are to big and do not fulfill the requirements of most electronic equipment Further means are necessary to stabilize (regulate) the voltage across the load.

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The first block in the power supply is the power supply. It consists of two separate coils wound around an iron core that magnetically couples the two windings. The primary winding, having N7 turns, is connected to the 220-V ac supply. The secondary winding, having N2 turns, is connected to the rectifier circuit We denote the turns ratio by n=N1/N2. Thus an ac voltage vs of 220/ ft V(rms) develops between the two terminals of the secondary winding. By selecting the appropriate turns ratio n for the transformer, the designer can step the line voltage down to the value required to yield the particular dc voltage output of the supply. For instance, a secondary voltage of 8-V rms is usually required for a dc output of 5V. This can be achieved with the «=28:1 turns ratio.

It should be noted that to simplify the discussion, zero-resistance transformer windings ate assumed for the rectifier circuits analyzed in this Section. Thus the results obtained are approximate only; however, they can still be sufficiently accurate for low-power applications.

In addition to providing the appropriate sinusoidal amplitude for the dc power supply, the power transformer provides electrical isolation between the electronic equipment and die power line circuit. The isolation minimizes die risk of electric shock to the equipment user.

The diode rectifier converts the input sinusoid vs to a unipolar output that can have a pulsating waveform indicated in Fig. 3.27. Although this waveform has a nonzero average, or a dc component, its pulsating nature makes it unsuitable as a dc source of electronic equipment, hence die need for a filter that suppresses high-frequency components of the rectifier's signal In its simplest form, the filter is a smoothing capacitor, as discussed above. The filter block in Fig. 3.27 significantly reduces the variations of the rectifier output.

The filtered rectifier output, though much more constant than without the filter, still contains a time-dependent component, known as ripple. To reduce the ripple and to stabilize the magnitude of the dc output voltage of the supply against variations caused by changes of in load current, a voltage regulator is employed. Such a regulator can be implemented using a Zener diode, which will be discussed, in the following section. Alternatively, an integrated circuit (IC) regulator can be used.

Exercise 3.7 A power-supply circuit is needed to deliver 0.1 A and 15V (average) to the load. The ac source available is 220V rms with a frequency of 50Hz. Assume that the full-wave circuit of. Fig. 3.26 is to be used with a smoothing capacitor in parallel with the load. The peak-to-peak ripple voltage is to be 0.4V. Allow 0.7V for forward diode drop. Find the turns ratio n needed and the approximate value of die smoothing capacitor. Verify your results using SPICE. Ans. »=18.74, C=2500nF.

Exercise 3.8 Repeat Exercise 3.7 using the circuit of Fig. 3.25 with a smoothing capacitor in parallel with the load resistance. (Define the turns ratio as the ratio of primary turns to the secondary, turns between the center tap and one end.) Verify your results using SPICE. Ans. »=19.58, C=2500nF.

3.6 Zenor-Diode Voltage Regulator Circuits

The circuit shown in Fig. 3.28 is used to provide a nearly constant output voltage from a variable source. (For its proper operation, it is necessary for the minimum value of the variable source voltage to be somewhat larger than the desired output voltage.) A Zener diode having a breakdown voltage equal to the desired output voltage is used. The resistor R limits die diode

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current to a safe value so that the Zener diode does not overheat Moreover, as will be shown later, the larger the value of R, the lower the output voltage variation for a given diode.

'o

Figure 3.28 A simple regulator circuit that provides a nearly constant output voltage from a variable input voltage

Assuming that the characteristic of the diode is available, one can use a load-line construction (see Section 3.2) to analyze the operation of the circuit. As before, we use Kirchhoff s voltage law to write an equation relating vD to ijy. In this circuit, the diode operates in the breakdown region with negative values of vD and /p. For the circuit of Fig. 3.28, one obtains Vss + RiD+vD=0 (3.31)

This is the equation'of a straight line, so location of any two points is sufficient to construct the load line. Inspection of (3.31) shows that the slope of the load line is -1/R. Thus a change of the input voltage changes the position but not the slope of the load line. The intersection of the load line with the diode characteristic yields the operating point.

Example 3.5 The voltage regulator circuit of Fig. 3.28 has R = 1 kfl and uses the Zener diode

having the characteristic shown in Fig. 3.29. Find the output voltage for Vss — 15 V. Repeat for

^ = 2 0 V .

Solution The load lines for both values of Vss are shown in Fig. 3.29: The output voltages are determined from the operating points where the load lines intersect the diode characteristic. The output voltages are found to be «y=10.0V for VSS=\5V and t^lO.SV for VSS=20V. Thus a 5 V change in the input voltage results in only a 0.5-V change in the regulated output voltage.

irfmA)

vjbOO

Figure 3.29 Graphical analysis of the circuit of Fig. 3.28

Actual Zener diodes are capable of much better performance than the one illustrated by Example 3.5. The slope of the Zener diode characteristic has been accentuated in Fig. 3.29 for clarity. Actual Zener diodes have a more vertical slope in breakdown.

The circuit of Fig. 3.28 is known as a shunt regulator because the Zener diode is connected in parallel (shunt with the load. The circuit is fed with a voltage that, as indicated in Fig. 3.27, is not very constant; it includes a large tipple component from a rectifier circuit. The load can be a simple resistor or a complex electronic circuit.

Analog Electronics / Diode Circuits

The function of the regulator is to provide an output voltage vL that is as constant as possible in

spite of the ripples in Vss and the variation in the load current IL. Two parameters can be used

to measure how well the regulator is performing its function: the line regulation and the load regulation. The line regulation is defined as the change in VL corresponding to 1-V change in

Vss

Line regulation = AV,

AK (3.32)

ss and is usually expressed in mV/V. The load regulation is defined as the change in VL

corresponding to a small change in IL

Load regulation = —— (3.33)

Variable supply

VL=-vD

0 (b) Figure 3.30 Piecewise linear model (a) for the Zener diode, valid for VD<VZ-

The shunt regulator equivalent circuit (b) with die Zener. diode replaced with its model.

Replacing the Zener diode can derive expressions of these performance measures by its equivalent piecewise-linear circuit model, shown in Fig. 3.30a. Using this model, the shunt-regulator circuit can be represented by its equivalent circuit shown in Fig. 3.30b. Straightforward analysis of this circuit yields

V =V — — L ^R+r + V,

R ~h

Rr, (3.34)

R + rz ~L R + rz

In the equation, only the second term on the right-hand side is a desirable one. The first and diird terms represent the dependence on the input voltage and the load current, respectively, and thus should be minimized. It follows that r2 should be kept low compared to R in order to obtain the best circuit performance.

Fig. 3.31a shows an example of a half-wave rectifier using a 1N4148 low-power diode with a smoothing capacitor of C — 47 uF and a lN750-type 5-V Zener diode regulator. It is seen in Fig. 3.31b that in spite of the capacitor voltage ripple, the output voltage is almost constant; it is equal to the breakdown voltage of the 1N750 diode.

Fig. 3.31c contains the SPICE code used to simulate the circuit operation that resulted in the waveforms plotted in Fig. 3.31b. Models for the diodes are included in the library file EVAL.LIB; their names are, respectively, D1N4148 and D1N750.

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3.7 Wave-Shaping Circuits

A wide variety of wave-shaping circuits find application in electronic systems. One of them is in function generators used to generate electrical test signals for laboratory work. In a function generator, a switching oscillator is used typically to generate a square wave. This square wave is then passed through a circuit that integrates it, resulting in a triangular waveform. Then the trianguk: waveform is passed through a carefully designed wave-shaping circuit to produce sinusoidal waveform. All three waveforms are available to the user. We will consider the design of such a function generator later. Numerous examples of wave-shaping circuits can be found in transmitters and receivers for television, as another example. In this section we discuss a few examples of wave-shaping circuits that can be constructed using diodes.

Clipper Circuits. Diodes can be used to form clipper circuits in which a portion of input signals waveform is "clipped" off. For example, the circuit of Fig. 3.32a clips off any part of die input waveform above 6V and below -9V. (We are assuming ideal diodes.) If the input voltage is between -9V and 6V, both diodes are off and no current flows through them. Then there is no voltage drop across R and the output voltage v0 is equal to the input voltage vs. On the other hand, if vs is larger than 6V, diode A. is on and the output voltage is 6V because the diode connects the 6-V battery to the output terminal. Similarly, if vs is lower than -9V, diode B is on and the output voltage is -9V. The output voltage resulting from 15V-peak triangular input is shown in Fig. 3.32b. The transfer characteristic of the circuit is shown in Fig. 3.32c.

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Figure 3.32 Clipper circuit (a), its input and output waveforms (b) and transfer characteristic (c)

The resistor R is selected large enough so that the forward diode current is within reasonable bounds (usually, a few milliamperes) but small enough so that the reverse diode current results in a negligible voltage drop. Often, we find that a wide range of resistance values provide satisfactory performance in a given circuit.

In Fig. 3.32 we have assumed ideal diodes. If low-current silicon diodes are used, we expect a forward drop of about 0.6V, so we should reduce the battery voltage to compensate. Furthermore, batteries are not desirable for use in circuits if they can be avoided, because may need periodic replacement. Thus a better design uses Zener diodes instead of batteries. Practical circuits equivalent to Fig. 3.32a are shown in Fig. 3.33. 'Tie Zener diodes are labeled with their breakdown voltage. The circuits shown in Fig. 3.33 have learly the same performance as the circuits of Fig. 3.32.

/f=2kii /f=2kn

vo(0

. 00 (b) Figure 3.33 Circuit of Fig. 3.32a with batteries replaced by Zener diodes and

allowance made for a 0.6 forward diode drop (a); simpler circuit (b)

Exercise 3.9 Sketch the transfer characteristic for the circuits of Fig. 3.34a and 3.34b. Allow for

a 0.6V forward drop for die diodes. Sketch the output voltage if *>s(/)=15sin(ey/).

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(a) (b) Figure 3.34 Clipper circuits for Exercise 3.9

Clamp Circuits. Another diode wave-shaping circuit is the clamp circuit that is used to add a dc component to an ac-input waveform, so that the positive (or negative) peaks are forced to take a specified value. In other words, the peaks of the waveform are. "clamped" to a specified voltage value. A simple clamp circuit example is shown in Fig. 3.35. In this circuit, the positive peaks of die input are clamped to -5V. As an application example, clamp circuits are used to restore die dc component (black picture level) of video signals transmitted through ac-coupled channels.

In the circuit of Fig. 3.35 the capacitor is a large value, so it discharges only very slowly and we can consider the voltage across the capacitor to be constant. Because the capacitance is large, die capacitor has very small impedance for the ac-input signal. Thus the output voltage of the circuit is given by

vo(0 = v 5 (0-^c (3-35) If die positive swing of the input signal attempts to force the output voltage to become more positive than -5V, the diode conducts, charging die capacitor and thus increasing the value of Vc. Thus the capacitor is charged to a value that adjusts the maximum positive value of the output voltage to -5V. A large resistor R is provided so that the capacitor can slowly discharge. This is necessary so that the circuit can adjust if the input waveform changes to smaller peak amplitude.

Of course, one can change the voltage to which the circuit clamps by changing the battery voltage in Fig. 3.35. Reversing the direction of the diode causes the negative peak to be clamped instead of the positive peak. Switched, or pulse operating clamp circuits are actually used in the video e upment.

v„(V)

Figure 3.35 Example clamp circuit (a); output waveform for triangular, 0 dc, 10-V peak-to-peak input (b)

Selection of R and C values for clamp circuits is a compromise. On one hand, we want die capacitor to have very small impedance compared to the resistor for the ac signal. This is necessary because we want the ac part of the output waveform to be identical to the input. On the other hand, if we make the RC time constant too long, the circuit takes a long time to adjust to changes in input amplitude. For now we can choose R to be a fairly large resistor, say about 100 kQ, so diat the peak diode currents are not required to be large (more than a few milliamperes). Then we pick C so that the RC time constant is large compared to the period of die ac input signal, say by an order of magnitude. (In the case of video signal, the discharge

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Antdog Electronics / Diode Circuits

period is equal to 64 |is, which is the duration of a single picture line.) This gives a clamp circuit with approximately the desired clamping action. Then we can simulate the circuit and adjust values until the performance is satisfactory. Finally, we can construct the circuit to measure its performance.

3.8 Switching and High-Frequency Behavior of the pn Junction

We have seen that the pn junction conducts little current when reverse biased and easily conducts a lot of current when forward biased. In many applications, such as high-speed logic circuits and high-frequency rectifiers, diodes that can switch rapidly between the conducting and nonconducting states are extremely desirable. Unfortunately, thepn junction displays two charge storage mechanisms that introduce delays and slow down the switching. Both of these mechanisms can be modeled as nonlinear capacitances.

Due to the presence of the charge-storage effects, one has to distinguish between static and dynamic properties of any electronic device, using the diode as the simple example. The diode's familiar i-v characteristic is a static characteristic. For a one-port the word "static" implies that operation is described by an algebraic equation, iD—fiv^j, that relates corresponding dc voltage and current values, this is Equation (3.1) in the case of ideal pn junction. A device's static characteristic also relates time-varying voltages and currents, but only if the time variations are not "too fast". Electronic devices always contain internal capacitances that modify device behavior for fast signals. Therefore, these devices are described by differential equations, which reduce to algebraic equations for sufficiently slow signals. Thus "static" means that the device variables are changing at such low rates that their time derivatives in the differential equation are small enough to ignore. At high frequencies, derivatives of the circuit variables cannot be neglected and the device capacitances significantly affect the circuit performance. Before we consider charge storage in pn junctions, we briefly review conventional linear capacitors.

A capacitor is constructed by separating two conducting plates by an insulator as shown in Figure 3.36a. If voltage is applied to the capacitor terminals, charge flows in and collects on one plate. Meanwhile, current flows out of the other terminal and a charge of opposite polarity collects on the other plate. Positive charge accumulates on the plate to which the positive voltage is applied. This is illustrated in Figure 3.36b.

Q

Conducting plates

Insulating dielectric + + + + + + + + + + + +

Figure 3.36 Parallel-plate capacitor (a), applying voltage to a capacitor causes a charge +J2 to accumulate on one plate and -Q to accumulate on the other plate (b)

The magnitude of the net charge Q on one plate is proportional to the applied voltage V. Thus we have Q=CV (3.36) For a parallel-plate capacitor such as that shown in Figure 3.36, the capacitance is given by

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- f (3.37)

where A is the area of one plate, d is the distance between the plates, and e is the dielectric constant of the material between the plates. Often, the dielectric constant is expressed as e = ere0 (3.38) where er is the relative dielectric constant and Eo = 8.85xl0"12 F/m'is the dielectric constant for vacuum. [Actually, (3.37) is an approximation valid for d much smaller than both the length and the width of the plates.] Notice that the capacitance of the parallel-plate capacitor is proportional to the area of the plates and inversely proportional to the distance between the plates.

Depletion Capacitance. Now consider ike. pn junction under reverse bias. As the magnitude of the voltage applied to the junction is increased, the field in the depletion region becomes stronger, and the majority carriers are pulled back farther from the junction. This is illustrated in Figure 3.37.

The charge in the depletion region is similar to the charge stored on parallel-plate capacitor. Unlike the parallel-plate capacitor, a larger distance separates each additional increment of charge stored in the depletion region. Thus the reverse-biased junction behaves as a capacitor, but its equivalent plates move apart with the voltage, so the capacitance is not constant. The stored charge is not proportional to the applied voltage. This capacitance is called the depletion capacitance. Because the relationship between the stored charge and the applied voltage is not linear, we say that the depletion capacitance is nonlinear.

Cj = dv D

(3.39)

in which dQ is the differential of the charge stored in one side of the depletion region, and dvD is the increment in the voltage which caused the charge increment. C\ is the capacitance of the diode for a small ac signal superimposed on a dc operating point.

It can be shown that the incremental depletion capacitance is given by

BIBLIOTEKA GLOWNA PL

QWb^ 5 -77


CJ=-

1 -VJ0]

~\m (3.40)

in which Cjo is the incremental depletion capacitance for zero bias, vD is the voltage across the diode (which is negative for reverse bias), V® is the built-in barrier potential (typically about 1 V), and m is called the grading coefficient. For a linearly graded junction m — 1 / 3 , and for an abrupt junction m— 1/2.

The zero-bias depletion capacitance Cjo is approximately proportional to the area of the junction. Thus it is larger for high-power rectifiers, which must be physically large to accommodate high power dissipation. The value of Cjo also depends on doping levels. In highly doped junctions, a large amount of charge can be stored close to the junction - similar to the parallel-plate capacitor with small plate separation. Thus we find high values of CJO for highly doped junctions and low values for lighdy doped junctions.

A reverse-biased diode can be used in circuits as a variable, voltage-controlled capacitor. A control signal reverse biases the diode, and as the control signal changes, the capacitance of the diode varies accordingly. -Diodes designed to have smoothly varying capacitance over a wide range of control voltage are called variable-capacitance diodes or varicaps. They can be used in. an JLC resonant circuit to vary the resonant frequency. Variable capacitance diodes can be used to design bandpass filters for which a control filter vary the center frequency, e.g. to tune in to an AM radio station. Varicaps are also useful in the design of voltage-controlled oscillators in which the frequency of oscillation depends on the diode capacitance. An application of this is the automatic frequency control (AFC) circuit of an FM radio. Manufacturers offer diodes intended for these applications having zero-bias capacitance Cp ranging from 10 to 1000 pF.

For the MV2201 variable-capacitance diode (Motorola), approximate values of the parameters of formula (3.40) are CJO = 15 pF, m = 0.43, and KJO = 0.75 V. A plot of the depletion capacitance versus bias voltage using these parameters is shown in Figure 3.38.

Figure 3.38 Depletion capacitance versus bias voltage for the MV2201 varicap diode

Diffusion capacitance. Another basic charge-storage mechanism occurs when thepn junction is forward biased. For simplicity, we consider an abrupt junction with much heavier doping on the p-side than on the »-side (Le. NA»N^). Sometimes this is called a/>+» junction, where "plus" refers to heavy doping of the />-material. For such a diode under forward bias, die current

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crossing the junction is due mainly to holes crossing from the/>-side to die /x-side. The current of electrons that are injected from the /r-side to the/>-side can be neglected.

P P

n-type n-type

Stored charge

Stored charge

(a)/D=J, (b)/D=^>I, Figure 3.39 Hole concentration versus distance for two values of forward current

Consider the hole concentration of the forward-biased p*n junction shown in Figure 3.39. The charge associated with the' holes that have crossed the junction is stored charge and is represented by the areas indicated in the figure. The charge is stored because a finite time passes before an average hole disappears due to electron-hole recombination. This time is called minority carriers lifetime. As the forward current is increased, more holes cross the junction and the stored charge increases. Because this charge is associated with ba in that ice diffusing across the junction, we call the effect diffusion capacitance.

It can be shown that the incremental diffusion capacitance is given approximately by

in which TT is a parameter known as the transit time of the minority carriers. For the p+n junction, xT— Z"p is the lifetime of the holes on the »-side of the junction. On the other hand, f *. r the n+p junction, we have TT = rn, which is the lifetime of the free electrons on the/>-side. For \ junction with comparable doping levels, rT is the weighted average of both lifetimes. Finally, I0 s the j2-point diode current, and VT is the thermal voltage.

9.2V It JT) c 40*B-9»IMlote>

Figure 3.40 Diffusion capacitance versus voltage for the 1N4148 diode

Notice that the diffusion capacitance is proportional to the diode current. Thus the diffusion capacitance, like the current, increases rapidly when the voltage VD exceeds approximately 0.6 V for silicon devices at room temperature. A plot of the diffusion capacitance- of the 1N4148 switching diode is shown in Figure 3.40. Under forward bias conditions, the diffusion capacitance is much larger than the depletion capacitance. (For the 1N4148 device, the depletion-capacitance

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parameter Cjo is approximately equal to 2 pF.) However, diffusion capacitance is negligible for reverse bias.

Small-signal diode model at high frequencies. A small-signal equivalent circuit for the pn-junction diode is shown in Figure 3.41. The resistance R* represents the ohmic resistance of die material on both sides of the junction; r& is the dynamic resistance of die pn junction that is discussed in Section 3.4. Its value is given by Equation (3.20), which is repeated here for convenience

nVT r*=-T (3-42)

1D

Cj is the depletion capacitance and Cdif is the diffusion capacitance.

All die equivalent circuit parameters except R» depend on the bias point Under reverse-bias conditions, Cdif is zero, and ra is an open circuit. Hence die equivalent circuit simplifies as shown in Figure 3.41b.

This equivalent circuit is vahd for the ptt junction over a wide range of frequencies, provided that small-signal conditions apply. At very high frequencies, lead inductances and stray capacitances of the diode physical structure are added to provide adequate accuracy.

Diodes are most often used with large signals, and their nonlinear behavior must be taken into account. Computer modeling does this most easily. We illustrate this widi a few examples.

(a) Forward bias Figure 3.41 Small signal linear circuits for the/>«-junction diode at high frequencies

Large-Signal Diode Switching. Consider the circuit shown in Figure 3.42. The waveform of die source voltage t>s is shown in Figure 3.43a. Until / = 10 ns, v, is +50 V and the diode is forward biased. At / = 10 ns, the source voltage jumps rapidly to -50 V, reverse biasing the diode.

rj] tf=5kO ryj

Figure 3.42 Circuit illustrating switching behavior of a/>«-junction diode

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(d) Voltage across the diode (expanded scale) Figure 3.43 Waveforms for the circuit of Figure 3.42

The resulting diode current is shown in Fig. 3.43b. As one might expect, the diode current is approximately (50 V)/(5 \£l) = +10 mA until / = 10 ns. Then the source voltage jumps to -50 V. Instead of dropping immediately to zero the diode current reverses to IR = -10 mA. At approximately / = 18.3 ns, -the current begins to fall in magnitude and approaches zero at / = 25 ns. In the interval immediately after the source reverses polarity, the diode continues to act as it were forward biased. This is called the storage interval ft, as labeled in Figure 3.43.

We can explain the behavior of the diode as follows. (To simplify the discussion, we assume a diode that is heavily doped on the/>-side compared to the «-side.) When forward bias is applied, holes flow across the junction into the »-side. The holes are minority carries there that diffuse into the «-side and eventually recombine with free electrons. When tfe reverses polarity, the holes stored in the »-side can again cross the junction back to the />-side. Until the supply of excess holes on the «-side is exhausted, current can easily flow in the reverse direction. This explains the storage interval of the diode current waveform.

It can be shown that the storage interval for a/>»-junction diode is given by

*,Z (3.43) B(l + B)

in which TT is the transit time for the minority carriers and B= \IR/IF\ • IF is the forward current before switching and JR is the reverse current during the storage interval. The storage time becomes shorter at larger ratios B.

After the excess holes have all recrossed the junction (or recombined with free electrons), the depletion capacitance of the diode is charged through the resistor. Thus, after the storage interval, we see an approximate exponential transient for the current in Figure 3.43b. (Since the depletion capacitance is nonlinear, the transient is not precisely exponential, as would be the transient in a linear RC circuit.) The interval for this transient, called transition time, is denoted by ft. By definition, the end of the transition interval occurs when the reverse diode current has reached a specific value, typically IR/10.

The total time interval for the diode to become an approximate open circuit, called the reverse recovery time, is denoted by ftr. It is the sum of the storage time and the transition time. ' « • = ' * + ' / (3-44) The transition time ft depends on the circuit resistance. Even though the depletion capacitance is nonlinear, the transition time is proportional to the circuit resistance.

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The diode voltage is shown in Figure 3.43c. To be able to see the details of the diode voltage during forward bias, an expanded-scale waveform is also plotted in Figure 3.43d. Notice that the diode voltage remains positive during the storage time, showing that the diode continues to act as if it were forward biased, even though the current is in the reverse direction. The terminal voltage of the diode does fall somewhat when the current reverses, because the voltage drop across the ohmic resistance R, of the diode reverses polarity. Prior to / = 10 ns, the terminal voltage is the sum of the junction voltage and the ohmic drop. On the other hand, between / = 10 ns and t -18.3 ns the terminal voltage is the junction voltage minus the ohmic drop.

Exercise 3.10 Consider the parallel-plate capacitor shown in Figure 3.36. The plates have dimensions of 20 |wm x 30 \ltn. (These dimensions are typical of the area of an integrated-circuit

/>»-junction diode.) The relative dielectric constant of the material is ft = 11.9. (This is the value for silicon.) The capacitance is 1 pF, which is a typical zero-bias depletion capacitance for a low-power diode. Find the distance between the plates. (The answer is the approximate zero-bias thickness of the depletion region.) Ans. d= 6.32x10-8 m.

Exercise 3.11 A certain abrupt-junction diode has a zero-bias depletion capacitance of 5 pF and a built-in barrier potential of 0.8 V. Compute the depletion capacitance for a reverse-bias voltage of (a) 5 V, (b) 50 V. Ans. 1.86 pF, 0.627 pF.

Exercise 3.12 A certain diode has a transit time of 10 ns. Find values for the small-signal resistance and diffusion capacitance at ID = 5 mA. Assume the emission coefficient n - \ and a temperature of 300 K. Ans. r& - 5.2 Q., Cm = 1920 pF.

Exercise 3.13 Consider the circuit of 3.42 with R changed to 50 kfi and with the source waveform of Figure 3.43a. (a) Think about the circuit and sketch the current versus time. Make use of results shown in Figure 3.43, use (3.43) to estimate / r Like the time constant of an RC circuit, /, is approximately proportional to R. (b) Write a PSpice program to obtain the plot of the diode current. Compare the results. Ans. The current waveforms are similar to Figure 3.43b with IF = 1 mA and IR = -1 mA, 4 = 8ns and A = 50 ns.

Exercit : 3.14 Consider the circuit of 3.42 with the input voltage "being equal to -50 V in die time interval from 0 to 10 ns, then jumping up to reach 50 V at 10.01 ns, staying at 50V until 30 ns and returning to -50 V at 30.01 ns. Write a PSpice program to obtain the plot of the diode current. Explain.

TABLE 3.1 SPICE PARAMETERS FOR INJUNCTION DIODES

Text notation

SPICE notation

Default value

I IS 1.0E-14A n N 1

V, BV oo V

h IBV 1.0E-3A

R, RS 0 Q

c* CJO OFyfV m M 0.5 yt V] 1.0 V brr TT 0s

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SPICE ParatL. j is for Diodes. Figure 3.41a is the SPICE equivalent circuit for th&pn junction diode. Table 3.1 lists nine parameters required to model the static and dynamic behavior of the diode. The first four, describe the static properties of the diode, as expressed by the Schockley equation (IS, N) and the following equation that approximates the breakdown component of the diode current

iD = -Iz exp -VZ+vD

(3.45)

in terms of parameters (VB and IBV), where VB = Vz is the breakdown voltage and IBV = Iz is die current that flows through the diode at vD = Vz. The remaining five parameters (RS, CJO, M, YJ, TT) describe the dynamic properties of the diode, following Equation (3.40) for depletion capacitance and (3.41) for diffusion capacitance. The default values of the two key dynamic parameters, CJO and TT, are both zero. This means that tbcdefault diode model in SPICE is a static model. To simulate dynamic effects, these default values must be overridden by nonzero values in .MODEL statement. An example diode model for the 1N4148 low-power general-purpose diode can be specified as follows:

.model D1N4148 D(I»-0.1p Rs=16 CJO=*2p Tt=12n Bv«100 Ibv=0.1p)

3.9 Special Diodes

3.9.1 Schottky diodes

The junction between certain metals (e.g. aluminum) and lightly doped n-type material forms a Schottky diode. A typical structure is shown in Figure 3.44. (On the other hand, a metallic contact with heavily doped »-type material results in an ohmic contact.)

The detailed theory of the Schottky diode is somewhat different from that of the pn junction. However, the form of the results is the same - the current in the Schottky diode is given by the Shockley equation. The saturation current 7, is much higher for Schottky diodes than for pn junctions of the same size. A typical value for a Schottky diode is 7S = 10"10 A, whereas for a typical IC pn junction it is 7S = 10"16 A. Because of the larper value of 7S, the forward voltage of the Schottky diode is significandy smaller (about 0.4 V compared to 0.7 V for a silicon pn junction diode).

Schottky j — Ohmic contact -v / contact

Figure 4.44 Schottky diode

Another important difference is that the Schottky diode does not display charge storage when being switched from forward conduction to reverse-bias conditions. This is because for forward bias electrons rather than holes are injected from metal anode into the n material. Thus majority carriers (i.e. electrons) carry the current, and storage of minority carriers does not occur. Hence switching tends to be faster for the Schottky diode. This fact can be used to advantage in die design of fast logic gates. An example of a bipolar transistor inverter with a Schottky diode is discussed in Chapter 6.

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Analog Electronics/Diode Circuits

3.9.2 Light-Emitting Diodes and Photodiodes

Light emitting diodes (LEDs) are junctions constructed of special semiconductor materials (compounds) such as gallium arsenide-phosphide. In these devices,' the injected minority carriers that result from forward biasing give up energy in the form of radiated light when they recombine. Wavelength ranging from ultraviolet through the visible and into die infrared bands is obtainable by use of different semiconductors and doping impurities. LEDs are widely used as display devices, for transferring information into optical fibers, and for optical isolation as discussed shortly

[••

'D

VD

+ 0.7V

Figure 3.45 Volt-ampere curves of photodiode/solar cell

A photodiode is a junction in which photons of energy in incident light break covalent bonds, adding the drift of these new carriers to the existing reverse saturation current. Figure 3.45 shows die volt-ampere curve of such a diode as a function of increasing incident light intensity. In tiie third and fourth quadrants the device functions as a (dependent) current source controlled by light. Is is the amount of current that can flows through the diode in dark, at a given temperature

Operation in the third quadrant represents passive conversion of light intensity information in electrical information. This is the photodiode functioning as an optical to electrical transduce-Applications include light meters and communication systems that receive information coded in the form of light. The obvious circuit model is a light-intensity-controlled current source.

Diodes designed for fourth quadrant operation are called photovoltaic cells or solar cells. Points on the curves in the fourth quadrant correspond to voltage and currents of opposite sign, implying an active device that delivers power to an external circuit. The curves emphasize that the solar cell is an active device for voltages not exceeding 0.7 V. Series connection of many solar cells produce large dc voltages. Parallel connection of solar cells of large area generates high output currents. Thus series-parallel interconnections can convert relatively large amounts of solar power into electrical power at convenient voltage levels. Solar cell efficiency (electrical output power divided by solar input power) is typically of the order of 10 -15 %.

Figure 3.46a shows how the light-emitting diode and the photodiode are combined in a useful device called an optical isolator. The signal th(t) is transferred to the load by means of light, with no physical connection whatsoever between the input and output circuits. The optical isolator is useful in many applications, including computer interfaces for biomedical instrumentation. In these applications, we want to transmit information while protecting a human subject and delicate equipment from dangers imposed by high voltages in the input circuit Figure 3.46b illustrates the principle. Notice that the hazard voltage that exists in the circuit on the left is not transferred to the load circuit on the right. Transformers also give isolation; however, die optical isolator operates at frequencies down to dc and is smaller, lighter and less expensive.

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3.9 Summary

The semiconductor diode is basically a pn junction. Such a junction is formed in a single semiconductor material crystal, most often silicon crystal. In the forward direction, the ideal diode conducts any current forced by the external circuit while displaying a zero voltage drop. The ideal diode does not conduct in the reverse direction; any applied voltage appears as reverse bias across the diode. The unidirectional current flow property makes the diode useful in the design of rectifier circuits. The diode i-v characteristic is described by Schockley equation; the forward conduction of practical silicon diodes is accurately described by the relationship i = 7sexp[f/(«l/T)]. A silicon diode conducts a negligible current until the forward voltage is at least 0.5 V. Then the current increases rapidly, with the voltage drop increasing by 60 or 120 mV (depending on the value of ») for every decade of current change. In the reverse direction, a silicon diode conducts a current of the order of 1 nA. This current is much greater than 7s and increases with the magnitude of reverse voltage. The diode i-v characteristic and parameters depend on temperature. Diodes designed to operate in the breakdown region are called Zener diodes. They are employed in the design of voltage regulators whose function is to provide a constant dc voltage tfiat varies litde with variation in power supply voltage and/or load current. A hierarchy of diode models exists, with the selection of an appropriate model dictated by the application. Analysis of diode circuits depends on viewing the diode as a 3-state device that, at a particular time operates in its ON, OFF or breakdown state. For each state, we replace the diode by a simple equivalent that approximates the diode's i-v characteristic and we then solve the resulting linear circuit to check our state assumptions. In many applications, a conducting diode is modeled as having a constant voltage drop, usually about 0.7 V. A diode biased to operate at a dc current ID has a small-signal resistance ra = nVT/ID. With the diode modeling and analysis techniques, we can describe many useful circuits such as half- and full-wave rectifiers, limiters, clamping circuits, voltage doublers and voltage regulators. These perform a variety of useful functions such as turning ac into dc, shifting waveform levels, modifying the shapes of time-

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varying waveforms, and producing dc that is relatively independent of changes in loading and source voltage. There are two sources of parasitic capacitance within the pn junction: depletion capacitance, associated with the layers of bound ions in the depletion region, and diffusion capacitance, associated with storing excess minority charge carriers just outside the depletion region. When signals change slowly in diode circuits, these capacitances are insignificant, and the diode satisfies its static equation (i.e. Schockley equation). For rapid.transitions or fast signals, however, a more appropriate diode description is needed, which is a differential equation that is nonlinear when posed in terms of diode current or voltage. Because of diode capacitances, delays occur in diode switching, and waveform processing predicted upon static diode theory deteriorates at high frequencies. SPICE models for diodes were introduced. By understanding how SPICE parameters relate to the diode parameters we use in circuit analysis, we can use simulation to study with increased accuracy and precision both static and dynamic operation of diodes. With SPICE we can formulate more realistic circuit descriptions, relying on computation to verify and reinforce our understanding of diode circuits. Accuracy of computer simulation, such as obtained from SPICE, is limited by the approximations we made when building models for real-world, physical devices. A Schottky diode is based on metal-semiconductor junction. It features fast switching and lower voltage drop when forward biased as compared to pn junction diode. Light-emitting diode, the photodiode and optical isolator are examples of optoelectronic devices useful in telecommunications and instrumentation technology.

Notes

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Analog Electronics / FET Circuits

4 Field-Effect Transistor Circuits

Now we turn our attention to devices that can amplify an input signal. In this chapter we consider the field-effect transistor (FET). In the first few sections of this chapter we describe the external characteristics of several types of FETs. Then we consider some simple but important circuits that use FETs, useful in amplifiers and logic circuits.

4.1 The n-Channel Junction FET

The simplified physical structure of an ^-channel junction field-effect transistor (FET) is shown in Fig. 4.1a, and the circuit symbol is shown in Fig. 4.1b. The device consists of a channel of »-type semiconductor with ohmic (nonrectifying) contacts at each end. These contacts are called the drain and the source. Alongside the channel, there are regions of ^-type semiconductor electrically connected to each other and to the gate terminal.

(a) (b)

Figure 4.1 Simplified physical structure (a) of an -channel FET; its circuit symbol (b)

The /w»-junction between the gate and the channel is a rectifying contact similar to />»-junction diodes discussed in Chapter 3. In almost all applications, this junction is reverse biased, so virtually no current flows in the gate terminal. Hence the gate is negative with respect to the channel in normal operation of an »-channel FET. (Recall that the/>-side is negative with respect to »-side for reverse bias of a/>»-junction.)

Applying reverse bias voltage between gate and channel causes the depletion layer of the gate-channel junction to become wider. The greater the reverse bias, the wider this nonconductive layer becomes. Eventually, for VQS<V?, the nonconductive layer extends all the way across the channel, and we say that pinch-off has occurred, where Vp is the pinch-off voltage which is a parameter of the transistor. Typically, it is a few volts in magnitude and is negative for ^-channel devices. As the voltage vGS is varied from 0 to Vp, the cross-sectional area of die conductive path from drain to source decreases toward zero. Therefore, the resistance between the drain and the source depends on the gate-to-channel bias.

In normal operation of art «-channel device, we apply a positive voltage to the drain with respect to the source, as shown in Fig. 4.2. Cvirrent flows into the drain, through the channel, and out of die source. Because the resistance of the channel depends on the gate-to-source voltage, die amount of drain current that flows is controlled by the gate-to-source voltage.

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'D

Figure 4.2 Circuit for discussion of drain characteristics of the ^-channel FET

Suppose that vGS is zero. Then, as vDS increases, iD increases as shown in Fig. 4.3. The channel is a bar of conductive material with ohmic contacts at the ends - exactiy the type of construction used for ordinary resistors. Therefore, it is not surprising the iD is proportional to vDSi for small values of t>DS.

VG5=0

Figure 4.3 Drain current versus drain-to-source voltage for zero gate-to-source voltage

However, for larger values of vDS, drain current increases more and more slowly. This is because the end of the channel closest to the drain is reverse biased by the (vDS + \ vGS\)

=vDS voltage. As vDS increases, the depletion layer becomes wider, causing the channel to have higher resistance. After the pinch-off voltage is reached, the drain current becomes nearly constant for additional

increases in p, DS-

Cutoff vcs<VP

Figure 4.4 Drain characteristics of an ^-channel JFET

A complete family of drain characteristics of a small-signal FET is shown in Fig. 4.4. For negative

values of vGS, the gate-to-channel junction is reverse biased even with vDS=Q. Thus the initial

channel resistance is higher. This is evident in Fig. 4.4 where the initial slope of the curves (i.e.

for vDS =0) is smaller for values of vGS closer to the pinch-off voltage. Thus for small values of

vDS, the FET behaves as a resistance between the drain and source. Furthermore, the resistance

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value is under the control of vGS. If vGS is less than the pinch-off voltage, vGS<V?) the resistance becomes an open circuit, and we say that the device is in cutoff

As in the case of vG^=-Q, the drain current for other values of PGS eventually becomes constant as vDS is raised, due to pinch-off at the drain end of the channel The region where the drain current is constant is called the saturation region. The region for which iD depends on vDS is called the linear region of the FET. These regions are labeled in Fig. 4.4.

Now we give the first-order equations for the drain current in terms of the voltages for the three regions of operation. (There are several second-order effects not taken into account by these equations. We discuss these effects as the need arises.)

Cutoff region. An ^-channel FET is in cutoff if vGS<Vp (4.1) In the cutoff the drain current is zero / D = 0 (4.2)

Linear region. An ^-channel FET is in the linear (triode) region if vGS>Vp (4.3) and if VGD=(VGS-VDS)>VP (4-4)

In the linear region, the drain current is given by

iD=K[2(vas-VJ.)vDS-vls] (4.5)

The constant K has units of current per volt2. Study of this equation for a fixed value of vGS

shows that it describes a parabola passing through the origin of the ip-Vps plane. Furthermore, the maximum of the parabola is on the boundary between the linear and saturation regions.

Saturation region. An ^-channel FET is in the saturation region if vG5 > V, (4.6) and if VGD=(VGS-VDS)<VP (4.7) In the saturation region, the drain current is given by

iD=K(vGS-Vpf (4.8)

A plot of Equation (4.8) is shown in Fig. 4.5. This plot represents the so-called transfer characteristic of the FET in saturation.

The drain current in the saturation region for vGS =0 is denoted as IDSS and is usually specified on

manufacturers' data sheets. Substituting vGS =0 into (4.8) we find that

Ioss=KV^ (4.9) Solving for K, we have

* = 7 T (4-10)

If values are given for IDSS and Vp, the static characteristics of the JFET can be plotted. Typical values for a small-signal »-channel JFET are: IDSS =5-rl0mA and KP=-3V.

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Analog Electronics/FET Circuits

IDSS

+ *GS

Figure 4.5 Plot of fa versus VDS in the saturation region of the FET

Breakdown. As we mentioned earlier, there are several effects not modeled by the device equations we have given. An example of one of these effects occurs if the reverse bias between gate and channel becomes too large - then the junction experiences breakdown and the drain current increases very rapidly. Usually, the greatest reverse bias is at the "drain end of the channel, so breakdown occurs when V^Q exceeds the breakdown voltage VB in magnitude. Because vDG = VDS ' VGS> breakdown takes place at smaller values of vDS as PGS takes values closer to pinch-off. This is illustrated in Fig. 4.6. We seldom operate FETs in breakdown; however, breakdown voltage value VB should be taken into design consideration to avoid the device entering into this operation region.

4.2 Me il-Oxide-Semiconductor FETs

Another important class of devices is the metal-oxide-semiconductor field-effect transistor (MOSFET). There are two types, known as depletion MOSFETs and enhancement MOSFETs. Each of them can be realized as an w-channel or a/(-channel device. Basically, all of these FETs have very similar characteristics. Once you master one type, such as the »-channel JFET, it is much easier to assimilate the relatively minor differences between them. Circuit symbols for the »-channel and for the />-channel MOSFET devices are shown in Fig. 4.7. The circuit symbols for/>-channel are the same as the circuit symbols for n-channel devices except for the directions of die arrowheads. The MOSFET terminal labeled as B denotes the substrate or the body contact.

Drain current versus vGS in the saturation region for »-channel devices is shown in Fig. 4.8. The depletion MOSFET has output characteristics nearly identical to those of die JFET. The main difference between die »-channel JFET and the »-channel MOSFET is in the fact diat the MOSFET can be operated with positive values of vGs. (This is usually not done with the JFET because it would result in forward bias of the gate-to-channel junction and the corresponding

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increase of gate current.) The equations we have given in Section 4.1 for the ^-channel JFET also apply for the //-channel depletion MOSFET.

Source

<g> (h) Figure 4.7 //-channel FETs circuit symbols (a, b, c),/(-channel FETs circuit symbols (d, e, f),

simplified physical structure of the //-channel enhancement MOSFET (g) and the //-channel depletion MOSFET (h)

No current flows in the //-channel enhancement MOSFET for vGS less than a certain positive value known as the threshold voltage which is denoted by VA. The equations we have given in Section 4.1 for the //-channel JFET also apply for the //-channel enhancement MOSFET if the (positive) threshold voltage Vth replaces the (negative) pinch-off voltage Vp. In particular, the enhancement MOSFET is cutoff for vGS < V&.

The characteristics of the /(-channel FETs are the same as for the respective »-channel devices except that voltage polarities and current directions are inverted. If we continue to reference the drain current into the drain, the algebraic signs of the currents and voltages must be inverted for /(-channel devices. As a consequence, for the /(-channel devices the drain current is negative and the pinch-off voltage Vp is positive for the JFET and for the depletion MOSFET. The threshold voltage Vfo for the/(-channel enhancement MOSFET takes on negative values.

Figure 4.8 Transfer characteristics for FETs: (a) //-channel JFET and depletion MOSFET, (b) //-channel enhancement MOSFET, (c) /(-channel JFET and depletion MOSFET, (d)/(-channel enhancement MOSFET.

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Gate protection. Because of their construction, MOSFETs have extremely high input impedance between gate and channel - in excess of 1000MQ. This high impedance is due to a thin insulating (silicon dioxide) layer placed between gate and channel. In handling these devices, it is easy to develop sialic electric voltages greater than the breakdown voltage of the gate insulation. Breakdown of the insulating layer is destructive, usually resulting in a short circuit between gate and chat?

To alleviate this problem, the gate terminals are usually protected by back-to-back Zener diodes as shown in Fig. 4.9. If the device is exposed to a static electric charge, one of the Zener diodes breaks down (depending on die voltage polarity, the other diode is on), providing a nondestructive discharge path. Usually, die diodes are fabricated on die same chip of semiconductor as the FET.

Variation in FET parameters with temperature. It is well known mat the semiconductor material mobility decreases with temperature. Because of more frequent collisions of charge carriers with the rapidly moving lattice ions. It turns out that the constant K in (4.5) and (4.8), which are valid for both JFETs and MOSFETs (with Vp = Kth where appropriate), is proportional to the carrier mobility. Consequendy, their transfer characteristics change as in Fig. 4.9b and 4.9c. It follows that the output characteristics for both devices crowd more closely as in Fig. 4.9d, juat opposite of bipolar transistor characteristics that are considered in Chapter 5.

The threshold and pinch-off voltages decrease by about 2 mV/°C with increases in temperature, causing the curves in Fig. 4.9b and 4.9c to shift to the left with temperature increases as they droop downward.

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4.3 Load-Line Analysis of a Simple JFET Amplifier

In this section we analyze the JFET amplifier circuit shown in Fig 4.10 by use of the graphical load-line approach. The batteries bias the JFET at a suitable operating point so that amplification of the input signal vs{f) can take place. We will see that the input voltage vs(t) causes vGS to vary with time, which in turn causes tD to vary. The changing voltage drop across RD causes an amplified version of the signal to appear at the drain terminal.

Figure 4.10 Simple JFET amplifier circuit

Applying Kirchhoff s voltage law to the input loop, we obtain the following expression: VGS(0 = V , ( 0 - K G C (4.11)

As an example, we assume that the input signal is a 1-V peak 1-kHz sinusoid and that VGG is IV. Thus we have vC5 (/) = sin(2000^) - 1 (4.12)

Writing a voltage equation around the drain circuit, we obtain VDD = RDiD{t) + vDS{t) (4.13)

For our example, we assume that RD=l]sQ and VDD=20V, so Equation (4.13) becomes

20 = *D(/) + v D S (0 (4.14)

where we have assumed that iD(t) is in milliamperes. A plot of this equation on the drain characteristic of the transistor is a straight line called the load line. To establish the load line, we first locate two points on it. Assuming zero drain current, iD — 0, in (4.14) we find that vDS —2QW. These values plot as the lower right-hand end of the load line shown in Fig. 4.11. For a second point, we assume that vDS = 0, which yields /D=20mA when substituted into (4.14). This pair of values (yDS — 0 and iD = 20 mA) plots as the upper left-hand end of the load line.

If vs{t) = 0, Equation (4.11) yields vGS = -VQQ — -1 V. Therefore, the intersection of the curve for

PGS = -1- V with the load line is the quiescent operating point. The quiescent values are 7p = 9 mA

a n d K D = l l V .

The maximum and minimum values of the gate-to-source voltage are J cj-max = 0 V and Vi GSnan = -2V [see Equation (4.12) and Figure 4.12]. The intersections of the corresponding curves with the load line are labeled as points A and 23, respectively, in Fig. 4.11. At point A, we find that ^nrmin= 4 V and 1 ^ = 16 mA. At point B, we find that VDSm2x = 16 V and 1 ^ = 4 mA.

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The plots of vs(t) and vDS(t) versus time are shown in Fig. 4.12. Notice that the peak-to-peak swing of the drain-to-source voltage is 12V, whereas the peak-to-peak swing of the input signal is 2V. Furthermore, the ac voltage at the drain is inverted compared to the signal at the gate. Therefore, this is an inverting amplifier. Apparently, one can calculate the circuit gain as equal to A^ = -12/2 = -6, where the minus sign is due to the inversion.

Figure 4.11 Drain characteristic and load line for the FET amplifier

Notice, however, that the output waveform shown in Fig. 4.12 is not a symmetrical sinusoid Wte the input. For illustration, we see that starting from the j2-point at VD = 11 V, the output voltage swings down to Vi>m^a — 4 V for a change of 7 V. On the other hand, the output swings up to 16V for a change of only 5V from the j2-point on the positive going half-cycle of the output We cannot properly define gain for the circuit because the ac output signal is not proportional to the ac input Apparendy the FET is a nonlinear device. Nevertheless, die output signal is larger th n die input signal even if it is distorted.

The distortion is due to the fact that die characteristic curves for the FET are not uniformly spaced. Of course, if much smaller input signal were applied, we would obtain amplification without appreciable distortion.

The rather modest gain (A^ = -6) that we see in this circuit is typical of RC-coupled FET amplifiers. In general, BJT amplifiers have much larger voltage gains. However, if we consider current gain, FET circuits have larger gains than most BJT circuits. For example, we have considered the input current for the circuit of Figure 4.10 to be zero. An infinite current gain would result if one attempts to calculate current gain as the ratio of the ac current in RD to tb-i input current. On die other hand, the current gain of a BJT ranges from about 10 to several hundred.

The amplifier circuit we have analyzed in this section is fairly simple. Practical amplifier circuits are usually much more difficult to analyze by graphical mediods. Later in this chapter we develop a small-signal equivalent circuit for the FET, and then we can use mathematical circuit-analysis techniques instead of graphical analysis. Usually it is more useful for investigation of practical amplifier circuits. However, graphical analysis of simple circuits provides an excellent way to understand die basic concepts of amplifiers.

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4.4 The Self-Bias Circuit

Analysis of amplifiers is undertaken in two steps. First, we analyze the dc circuit to determine the j2-point In this analysis, the nonlinear device equations and/or curves are used. Then, after the bias is found, we use a linear, small-signal equivalent circuits to find the input resistance, voltage gain, and so on. In this section and die next, we consider analysis and design of dc bias circuits for FETs.

The two-battery bias circuit used in the amplifier of Fig. 4.10 is not practical. Usually one battery is available only. Even more significant problem is that FET parameters vary considerably from device to device. For a given type of JFET, IDSS may vary by a ratio of 5:1. Furthermore, the pinch-off voltage is different from device to device.

Plots of iD versus vGS are shown in Fig. 4.13 for extreme FETs, all of which have die same manufacturer's type number. The range of variation shown is typical. Notice that if VGS were the same for all devices, a considerable variation in ID would occur. Some devices would be biased at one end of the load line and others at the opposite end. On the other hand, to obtain the maximum symmetrical swing of the output voltage without severe distortion, we require the operating point to be near the middle of the load line for all devices. Thus a fixed-bias circuit that maintains the same value of VGS independent of the device parameters is not suitable for mass production.

Figure 13 Transfer characteristics of extreme devices for JFETs having the same type number. Bias with fixed VGS results in a large variation of h.

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A more practical circuit, known as the self-bias circuit, is shown in Fig. 4.14. The resistor Rs is essential to the operation of this bias circuit. The resistor R^ is usually a large value (several megaohms) that maintains the dc voltage at the gate close to the ground and still provides high input impedance at the gate. Since only a small current (InA or less) flows in the gate, the dc voltage drop across RQ is negligible. In applications where input signal is not applied to gate, RQ can be replaced by a short circuit. The drain resistance RD is required to be present if we want an amplified signal to appear at the drain. However, in some circuits, the output is taken from the source terminal, and then we would replace RD by a short circuit.

DD

Figure 4.14 Self-bias circuit used for JFETs and depletion MOSFETs

The drain current flows out through the source and through the source resistor Rs, creating a voltage drop. Writing a voltage equation around the gate-source loop of Fig. 4.14 and neglecting the drop across RQ we have

vGs=-Rsh (4-15) A plot of this equation is called the bias line and is shown in Fig. 4.15, which also shows iD

versus vGS for extreme devices of a given type. The operating point is at the intersection of the

bias line and the device transfer curve. Notice that VGS is smaller in magnitude for the low-

current device than for the high-current device. Thus the self-bias circuit adjusts VGS to

compensate for changes in the device, thereby reducing variations in ID compared to a fixed-bias

circuit.

Bias line VQS=-RS'D

VGS

Figure 4.15 Graphical analysis of the self-bias. The device-to-device variation of drain current is much less than for the fixed-bias circuit.

The device curves shown in Fig. 4.15 are valid only if device operates in the saturation region. Usually, in FET amplifier circuits, operation in the saturation region is desired. However, we should check to make sure that VDS is large enough for operation in the saturation region before accepting results based on this analysis.

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Exercise 4.1 Design a self-bias circuit for an »-channel FET having IDSS=4toA and VP=-2V.

The circuit is to have RD=2.2kQ, VDD=20V, and Ij^ltnA. Use standard 10%-tolerance resistor

values. Ans. Ry=270Q.

Exercise 4.2 Analyze the self-bias circuit designed in Exercise 4.1. Repeat the analysis for a high-

current device having 7Dxr=8mA and VP=-4V. Ans. VQ^-OSGV, JD=2.07mA, VDS=U.9V;

VGS=-l.l2V,ID=4.UmA, VDS=9.11V.

4.5 The Fixed- plus Self-Bias Circuit

The self-bias circuit gives fair performance in maintaining a fixed ID from device to device, but sometimes better performance is needed. The fixed- plus self-bias circuit shown in Fig. 4.16 provides a solution.

For purposes of analysis, we replace the gate bias circuit with its Thevenin equivalent, as shown in Fig. 4.16b. The Thevenin voltage is

X Vr.=Vn Q DDR,+R,

(4.16)

and the Thevenin resistance RQ is the parallel combination of Rf and R2. Writing a voltage equation around the gate loop of Fig. 4.16b, we obtain VG = vGS + RsiD (4.17)

Notice &at we have assumed that the voltage drop across R^ is zero. Now, if we assume that the transistor is in the saturation, we have

iD=K(vGS-VPf (4.18)

Simultaneous solution of (4.17) and (4.18) yields the operating point (provided that it falls in the saturation region). Then we can find vDS by writing a voltage equation around the drain loop vDS=rD0-(tf0 + * s ) / , (4.19)

(a) (b) Figure 4.16 Fixed- plus self-bias circuit. Original circuit (a),

Gate t>ias circuit replaced by its Thevenin equivalent (b).

Figure 4.17 shows the graphical solution of Equations (4.17) and (4.18). Notice that higher values

of VG result in smaller variation in ID for extreme devices because die bias line becomes closer to

horizontal. (Also notice that VG=0 corresponds to the self-bias circuit.) However we must not

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choose VG too high because this raises the voltage drop across Rs and sufficient voltage must be

allocated for vDS and RD.

Exercise 4.3 Design for V^SV a fixed- plus self-bias circuit for the JFET of Exercise 4.1

having IDSS=4mA and VP=-ZV. The circuit is to have Rp=2.2kQ, VDD=20V, and I^lmA. Use

standard 10%-tolerance resistor values. Ans. Rj=2.7kfi.

Exercise 4.4 Analyze the self-bias circuit designed in Exercise 4.3. Repeat the analysis for a high-

current device having IDSS=SmA and VP=-4V. Ans. FGJ-=-0.564V, 7D=2.06mA, VDS=9.9V;

VGS=-\.76V,ID=2.50mA, VDS=7.73V.

Figure 4.17 Graphical solution for the fixed- plus self-bias circuit. Note that ID is nearly independent of the device if VG yz large.

Another advantage of the fixed- plus self-bias circuit is that it also works for enhancement MOSFETs. On the other hand, the self-bias circuit is not suitable for enhancement MOSFETs because the gate must be more positive than the source (assuming »-channel devices), which is not possible in the self-bias circuit.

Example 4.1 Design a bias circuit for an «-channel enhancement MOSFET having K/4=4V and K=10-3A/V2. The power supply voltage is VDD=\5V. A jg-point of ,KDJ-=5V and /p=5mA is desired. The circuit is to be used in an amplifier with the ac output taken from the drain terminal. Solution. Since an enhancement device is specified, we must use the fixed- plus self-bias circuit because the self-bias circuit would give a zero drain current regardless of the resistor value selected. The circuit is shown below. Values must be selected for R,, R^, RD and Rs.

Figure 4.18 Circuit of Example 4.1

Since the supply voltage is 15V and a bias value VDS=5V is specified, a total of 10V remains to

be divided between RD and Rs. The drain current flows through both resistors, so we have

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RS+RD= {yoD ~^DSr ID = 2 ^ • Equation (4.17) shows that larger voltages across Rs result in higher values for VG. As we have seen, large values of VG lead to good bias stability. Thus we are led to allocate a large portion of the available voltage to the drop across Rs. In the extreme case, this would produce RD=0 and Ry=2k£2. However, since an ac output signal is to be developed at the drain, RD=0 is not acceptable. Thus we select RD=Rj-=lkfi. (This choice is somewhat arbitrary - perhaps in a complete amplifier design, the ac performance required would dictate particular choice.) Assuming the MOSFET is operating in the saturation region, we have

Io = K{Vcs-Vlh)2

Substituting values and solving, we find that VGS= 6.24V. Thus the gate voltage is given by VG=VGS + RsID=n.2V

Now we must find values for R, and R , so that the 15-V supply voltage divides with 11.2V

across R^ and 15-11.2=3.8V across R ;. If we make somewhat arbitrary choice that

R,+R2=1.5MQ, then R,=380kQ and R2=\A2MQ provide the desired voltage division.

Therefore we choose the closest standard values, namely R,=390kfi and R2=1.1MQ

Exercise 4.5 (a) Analyze jhe circuit designed in Example 4.1 to find of VDS and ID. The answer should verify that the operating point achieved is close to the design objectives, (b) Repeat the analysis for an «-channel enhancement MOSFET having Vtb=5V and K=2taA/Vz. Ans. 7D=4.87mA, KDJ=5.27V; JD=4.56mA, VDS=5.STV.

Exercise 4.6 A certain «-channel enhancement MOSFET has Vlt=2V and K=2mA/V2 The bias

circuit (as shown in Fig. 4.18) has VDD=20V, R7=R2=1MQ, R D =lkO and Rj-=2.2kQ. Find VDS

and ID. Ans. JD=3.07mA, VDS=\0.2V.

Exercise 4.7 Find the largest value of RD that can be used in the circuit of Exercise 4.6 if the

MOSFET is to remain in saturation. Assume that R?, R2, and Rs remain fixed. Ans.

RDmax=3.91kQ.

4.6 The Small-Signal Equivalent Circuit

In the preceding two sections, we considered dc bias circuits for FET amplifiers. Now we consider the relationships, between the signal currents and voltages for small changes from Q-point. As usual, we denote total quantities by lowercase letters with uppercase subscripts such as /D(/) and vG5(t). The dc j2~point values are denoted by uppercase letters with uppercase subscripts, such as JD and VGS. The signals are denoted by lowercase letters with lowercase subscripts such as *d(/) and %i(^. The total current or voltage is the sum of the j2-point value and the signal. Thus we can write

iD(0 = ID+iAO (4-20) and

vGS(0 = f G S + v f f ( 0 (4-21)

In the following we assume that the FETs are biased in the saturation region, which is usually die case for amplifier circuits. Equation (4.8), repeated here for convenience, gives the total drain current in terms of the total gate-to-source voltage.

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iD=K(vGS-VPf (4.8)

Substituting (4.21) and (4.20) into (4.8), we obtain

ID+id(0 = tfycs + v^ -VP]2 (4.22)

The right-hand side of (4.22) can be expanded to obtain

ID + / , ( / ) = K(VGS -VPf +2K(VGS -VP)Vgs + Kv2m (4.23)

However, the j2-point values are also related by (4.8), so we have

Io=K{VGS-VP)2 (4.24)

Therefore the first term on either side of Equation (4.23) can be cancelled. Furthermore, we are interested in small-signal conditions for which the last term on the right-hand side is negligible and can be dropped [i.e. we assume that |fGj(^| is much smaller than | Vcr^pW- With these changes, Equation (4.23) becomes

(t) = 2K(vGS-VP)vgs (4.25)

We define the transconductance of the FET as

g„=2K(VGS-VP) (4.26)

Then Equation (4.25) can be written as '„(') = S.v,(0 (4-27> The gate current of the FET is negligible, so we have / f (0 = 0 (4.28) The small-signal equivalent circuit shown in Fig. 4.19 can represent equations (4.27) and (4.28). Thus die FET is modeled by a voltage-controlled current source connected between the drain and source terminals. The model has an open circuit between gate and source.

Figure 4.19 Small-signal equivalent circuit for FETs

Solving Equation (4.24) for the quantity (VGS - VP) and substituting into Equation (4.26), we obtain

gm = 24H~D (4.29) Then if we use Equation (4.10) to substitute for K, we have

which is often a convenient formula for computing the transconductance of a JFET or depletion MOSFET at a given j2-point. Of course, IDSS does not apply for enhancement MOSFETs, and Equation (4.29) applies for them.

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Figure 4.20 Small signal equivalent circuit that accounts for the dependence of ID on ws

Furthermore, the first-order equations we have given for the FET do not include a term to account for the small effect of (&. on the drain current Previously, we assumed that the drain characteristics are horizontal in the saturation region, but this is not exact — the drain characteristics slope slightly upward with increasing Pd>. If we wish to account for the effect of ?& in the small-signal equivalent circuit, a resistance r& called the drain resistance is added between the drain and source as shown in Fig. 4.20. Equation (4.27) becomes

U = Smv** + rds (4.31)

Figure 4.21 Determination of ra from the FET drain characteristics using (4.33)

The definition of the reciprocal of n (which actually is the drain conductance gd=l/rd) is the partial derivative of drain current with respect to %., evaluated at j^-point:

1 Sin

(4.32) Q-foial

which can be approximated as

1 A / " (4-33)

Sv DS

-t*a - uo

where AID is an increment of drain current centered at the j2-point. Similarly, Avds, is an increment of drain current centered at the jg-point. Equation (4.33) is useful to evaluate the drain resistance from the output characteristic of the FET plotted for a constant vGS=VGs. This is illustrated in Fig. 4.21.

Similarly, an alternative definition of the transconductance ^ is the partial derivative of ID with respect to vGS, evaluated at j2-point:

(4.34) Q-poinl

o n Sv, GS

which can be approximated as

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bm — ML

Av (4.35)

GS

where A t ^ is an increment of drain current centered at die jg-point. Equation (4.35) is useful to evaluate die transconductance from die FET output characteristics plotted for two different values of gate-to-source voltage. This idea is illustrated in Fig. 4.22.

+ VDS

Figure 4.22 Determination of g^ from die FET drain characteristics using (4.35)

The device equations and the equivalent circuit that we have derived from them describe only the static behavior of die device. For rapidly changing currents and voltages, the additional capacitances are required for an accurate model. A small-signal FET model suitable to represent die JFET behavior for high-frequency operation is shown in Fig. 4.23.

Thr^e capacitances are added to the circuit of Fig. 4.20 to obtain the circuit of Fig. 4.23. The gate-source and gate-drain capacitances, Cgs and Cgd, respectively, represent die junction capacitance of die gate-to-channel junction. These capacitances are nonlinear — they depend respectively on gate-drain and drain-source dc voltages, Cgs = J{VGs) a n d Qd = J^YGD)- Th e

function J{.) has die form of Equation (3.40) with vD = VGS for Cgs and vD = VDS for Cgd. The capacitance Cds. is mainly the stray capacitance between the drain and source terminals, so it is a linear (constant) capacitance to a first approximation.

It should be noted diat small-signal high-frequency model for a MOSFET device is a little more complicated than the circuit of Fig. 4.23. Namely it comprises diree other capacitances, connected between the gate, source and drain terminals and die bulk terminal, respectively. These capacitances are nonlinear (junction) capacitances, unlike die Cgs and Cgd capacitances diat are stray capacitances for the MOSFET. Such a model will be discussed in Section 4.11 for die purpose of SPICE simulation of MOSFET circuit behavior. For approximate, simplified analysis die circuit shown in Fig. 4.23 can be used for both JFET and MOSFET devices.

Figure 4.23 Small-signal high-frequency JFET equivalent circuit

The small-signal JFET equivalent circuits shown in Fig. 4.20 and 4.23 will be used in die next section to analyze properties of basic types of FET amplifiers at low and high frequencies.

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4.7 Basic Small-Signal FET Amplifier Circuits

The circuit diagram of a common-source amplifier is shown in Fig. 4.24. The ac signal to be amplified is supplied by %(/). The coupling capacitors C1 and C2 as well as the bypass capacitor Cs

axe. intended to have very small impedance for the ac signal. In this section we then carry out a midband analysis of the amplifier, in which we assume that these capacitors are short circuits for the signal. Later when we consider the frequency response of amplifiers, we include the capacitors. The resistors R^, Rs, and RD form a self-bias network, and their values are selected to obtain a suitable j2-point. The amplified output signal appears as the voltage drop across the load resistor RL.

The small-signal equivalent circuit for the amplifier is shown in Fig. 4.25. The input coupling capacitor has been replaced by a short circuit. The FET has been replaced by its small-signal equivalent, which is shown in Fig. 4.20. Because the bypass capacitor Cs is assumed to be a short circuit, the source terminal of the FET is connected direcdy to ground - which is why the circuit is called the common-source amplifier (the source is common to die input and the output). The dc supply voltage source is considered to be a short circuit for the ac signal. Consequendy, the resistor RD appears connected from drain to ground.

Figure 4.24 Common-source amplifier

Next we consider the voltage gain of the amplifier. Refer to the small-signal equivalent circuit

and notice that the resistances rd, RD, and RL are in parallel. We denote the equivalent resistance

by

R = - (4.36)

Figure 4.25 Small signal equivalent circuit for the common-source amplifier

The output voltage is the product of the current from the controlled source and the equivalent

resistance.

v0 = -ig.vJR'L (4'3?)

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Analog Electronics /FET Circuits

The minus sign is necessary because of the reference directions selected (i.e. the current g[avs

flows out of the positive end of the positive end of the voltage reference for p j .

The input voltage and the gate-to-source voltage are equal to each other

Now if we divide Equation (4.37) by (4.38), we find the voltage gain, which is given by

Av=^ = -gmR1 (4.39)

The minus sign in the expression for the voltage gain shows that the common-source amplifier is inverting.

The input resistance of the common-source amplifier is given by

R, = — = Rr h

(4.40)

This impedance forms part of the bias network, but its value is not critical. Practical values change from 0 to perhaps 10 MQ in discrete component circuits. Thus we have a great deal of freedom in design of the input resistance of a common-source amplifier. This is not true for BJT amplifier circuits. One should note, however, that the effective voltage gain

defined as the ratio of the output voltage to the signal source voltage depends on the resistance jR . Namely, one can easily demonstrate that

K = -g« Rr.

R + R, RL=AV

Rr

R + Rr (4.42)

It follows from Equation (4.42) that with the decreasing gate resistance, the effective voltage gain decreases, approaching zero when r^—>0. Therefore, high-intemal-resistance sources require larger values of RQ to maintain large values of the effective voltage gain.

Figure 4.26 Circuit used to find output resistance Ro

To find the output resistance of an amplifier, we disconnect the load, replace the signal source by its internal resistance, and then find the resistance looking into the output terminals. The equivalent circuit with these changes is shown in Fig. 4.26.

Because there is no source connected to the input side of the circuit, we conclude that fgs=0. Therefore, the controlled current source produces 2ero current and appears as an open circuit. Consequendy, the output resistance is the parallel combination of RD and ra.

R° = VRD + l/rd (4-43)

Exercise 4.8 Find the voltage gain, input resistance and output resistance for the circuit of Fig. 4.24. Also find «(/) and vQ(t). Assume %(/) = 0.1sin(20007t/) V, R = 100 kQ, J ^ = 1 MQ, RD = 2.7

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kQ, R L = 10 \sQ, rd = oo, IDSS= 8 mA, VP= -2 V and ID= 2 mA. Ans. A„= -8.5, ft = 1 MQ, Ro = 2.7 kQ.

Exercise 4.9 Find the voltage gain of the amplifier of Exercise 4.8 if an open circuit replaces R^. Ans. A,,= -10.8.

Exercise 4.10 Find the value of Rs of Exercise 4.8. Ans. Rs = 500 Q.

Exercise 4.11 Consider the circuit of Fig. 4.24 with the bypass capacitor replaced by an open circuit. Draw the small-signal equivalent circuit. Then assuming that ra is an open circuit for simplicity, derive an expression for the voltage gain in terms of gm and the resistors. Ans.

Exercise 4.12 Evaluate the gain expression found in Exercise 4.11 using the values given in Exercise 4.8 and the value of Rs found in Exercise 4.10. Compare the results with the voltage gain found in Exercise 4.8. Ans. Av = -2.84.

Another amplifier circuit known as source follower is shown in Fig. 4.27. The ac signal to be amplified is supplied by the %(/) signal source and R is the internal resistance of the signal source. The coupling capacitors C1 cause the ac input to appear at the gate of the FET. The capacitor C2

connects the load to the source terminal of the FET. (In the midband analysis of the amplifier, in which we assume that the coupling capacitors behave as short circuits.) Later when we consider the frequency response of amplifiers, we include the capacitors. The resistor Rs provides a path for the dc current flowing out of the source terminal of the FET.

Figure 4.27 Source follower

The resistor R^ provides a path for the gate leakage current. One reason for using a source follower is to obtain high input impedance, and we would pick a large value for R^. The largest resistors available are on the order of 10 Mfi. Even with such large values, the dc voltage drop caused by leakage current is usually negligible, so we can consider the bias value of the gate-to-source voltage to be zero. As a result, the bias value of the drain current is ID = IDSS. Since IDSS demonstrates considerable device-to-device variation, the bias current of this circuit is not well controlled. (This situation could be corrected by returning R^ to ground, forming the self-bias circuit discussed in Section 4.4, but this causes a significant reduction of the input resistance.) Even though the circuit of Fig. 4.27 has poor bias stability, it achieves extremely high input resistance, so it is sometimes useful.

The small-signal equivalent circuit is shown in Fig. 4.28. The coupling capacitors have been replaced by short circuits, and the FET has been replaced by its small-signal equivalent. Notice

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that die drain terminal is connected to direcdy to ground because the dc supply becomes a short in the small-signal equivalent. Therefore, the source follower is also called the common-drain amplifier. The FET equivalent circuit is drawn in different configuration than shown in Fig. 4.25, but it is the same electrically.

Drawing the small-signal equivalent for an amplifier circuit is an important skill for electronics engineers. Test yourself to see if you can obtain the small-signal circuit starting from Fig. 4.27.

Figure 4.28 Small-signal equivalent for the source follower

Now we derive an expression for the voltage gain of the source follower. Notice mat rd, Rs and

RL are in parallel. We denote the parallel combination by 1

* * = • (4.44) l/rd+l/RD+URL

The input current must flow through Rg. Therefore, the current flowing through RL is

' 'y+SmV-Tkus

v„ = K{L + g^v) (4-45)

We can write the following voltage expression: V- = V + V yl vgS ' v0

Finally,» otice that the voltage across Rg is v^, so we have

v„, = RQif

(4.46)

(4.47)

Equations (4.45), (4.46) and (4.47) form the set needed to solve for the voltage gain. First we use Equation (4.47) to substitute into Equation (4.45), resulting in

Now if we substitute Equation (4.47) and (4.48) into (4.46), we obtain

vi=RGii + RL{ii+gmRGit)

Finally, if we divide Equation (4.48) by (4.49), we find the voltage gain

A =VQ- RL(l + gm*G)

(4.48)

(4.49)

(4.50)

A few simple checks can be performed on this expression. First, voltage gain is dimensionless. Checking we see that the expression given on the right-hand side is indeed dimensionless. (Recall diat the units of g^ are Siemens, i.e. mA/V.) Another simple check is to notice that if ^ = 0 , the controlled source in Fig. 4.28 becomes an open circuit. Then the equivalent circuit becomes a

- 1 0 7 -


resistive voltage divider. Substituting g^ = 0 into the voltage-gain expression results in the voltage-division ratio of the resistive circuit. Checks such as this are useful for detecting errors in writing equations or in the algebra.

Notice that the voltage gain given in Equation (4.50) is positive and is less than unity. However, in most circuits, it is only slightly less than unity. It follows then, that the output voltage follows the input voltage that justifies the name source follower for the circuit in Fig. 4.27. To summarize, the source follower is a noninverting amplifier with a voltage gain slightly lower than unity.

The input resistance can be found from Equation (4.49) by dividing both sides by r,

Ri = Vj- = RG^RL{\ + gmRG)

We see that the input resistance can be very large compared to R^.

(4.51)

To find the output resistance, we remove the load resistance, replace the signal source with its internal resistance, and look into the output terminals. It is helpful to attach a test source vx to the output terminals as shown in Fig. 4.28. Then the output resistance is found as

R - ^ R"~i (4.52)

where Ix is the current supplied by the test source as shown in the figure. It can be shown that the output resistance is given by

R„ = ; \ —ir~ (4-53) 1 . + .&A — —

Rs+rd

+ RG+R R + RG

This can be quite low, and another reason for using a source follower is to obtain low output impedance.

Figure 4.29 Equivalent circuit used to find die output resistance of the source follower.

Exercise 4.13 Find the voltage gain, input resistance, output resistance, current gain and power gain of the source follower shown in Fig. 4.27 if R = 100 kQ, B^ = 10 MQ, Rs = 1 kQ, RL = 2.2 kQ. The FET has ra = oo, IDSS = 1 6 mA, VP = -2 V; assume it operates in saturation. Ans. Av = 0.917, ft = 120 MQ, R„= 59.4 Q,A,= 5-104, G = 4.49-101

From the results of Exercise 4.13 we see that even though the voltage gain of the source follower is less than unity, the output power is much greater than the input power because of the very high input resistance.

Exercise 4.14 Derive expressions for the voltage gain, input resistance and output resistance of the source follower shown in Fig. 4.30. Calculate their respective numerical values if R = 100 kQ,

-108-


RG= 1 0 M Q , R j = 1 k Q . R ^ 2.2 kO. The FET has rd=co,IDss= 8 mA, Vp= -2 V; assume it operates in saturation.

Exetcise 4.15 Derive expressions for the voltage gain, input resistance and output resistance of the common-gate amplifier shown in Fig. 4.31. Calculate their respective numerical values if R = 100 kQ, Rc= 10 MQ, Ks= 1 kfi, Ro= 2.7 kQ, RL= 10 kO. The FET has rd = oo, IDSS= 8 mA, VP

= -2 V; assume it operates in saturation.

TABLE 4.1 PROPERTIES OF BASIC FET AMPLIFIERS

Circuit configuration

Amplifier type

Voltage gain at midband

Input resistance

Output resistance Bandwidth

Common source Inverting -x-R',. Large Medium Medium

Common drain Noninverting s i

Large/, very large Small Very wide

Common gate Noninverting A*«. Small Medium Wide

Looking at the results obtained from Exercises 4.8, 4.14 and 4.15, one can compare the properties of the basic FET amplifier configurations. They are summarized in Table 4.1. Please note that although the common-source and common-gate amplifiers have the same magnitude of voltage gain, the common-source circuit is an inverting amplifier, unlike the common-gate configuration. The common-gate one offers larger bandwidth, as will be discussed next in dais section.

Example 4.1 Find the higher cutoff frequency of the common-source amplifier of Fig. 4.24. Assume R = 1 kQ, Rc = 10 MQ, Rs= 1 kft, RD= 5.6 kfi, R^= 10 kft, rd= oo, IDSS= 16 mA, and VP = -2 V, Qs = 10 pF, Cgd = 3 pF, Gh = 2 pF. Solution. To find the circuit small-signal transconductance, one has to determine the j2-point of the FET by using the techniques of Section 4.4. In the case of the circuit shown in Fig. 4.24, the gate-to source voltage equals to HGS = -1.407 V. This corresponds to ^ = 2.372 mS. The equivalent circuit of the amplifier, valid for high frequencies is shown in Fig. 4.32. To build this

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circuit, its model of Fig. 4.23 replaced the FET in Fig. 4.24, and the coupling and bypass capacitances were replaced by respective short circuits.

Figure 4.32 Small signal high-frequency equivalent circuit for the common-source amplifier

The capacitance Cgd in Fig. 4.32 is connected between the input and the output of the amplifying device and thus makes the derivations difficult. To simplify the analysis we will use the Miller theorem of Section 2.6. First, the midband voltage gain should be evaluated between the terminals to which the feedback capacitance is connected. We will use the circuit of Fig. 4.33 to find this gain, as

V A = -?- = -gmRL

gs

Since R'L = RD\ \ RL = 3.59 kQ, we find A = -8.52. According to Miller theorem, the capacitance Cgd may be split into two parts Cm]=Cgd(\-A)= 28.55 pF,

\-A 'ml = c gd -A

= 3.35 pF.

These capacitances are connected, respectively, from the gate to source, and drain to source terminals, as shown in Fig. 4.34. The resistance RQ has been neglected as being much larger than the signal-source resistance R and the reactance of capacitances (Cgs + Cmi) at high frequencies.

Figure 4.34 Simplified equivalent circuit for die common-source amplifier

To find the higher cut-off frequency, one has to evaluate the effective gain of the amplifier

-no-


The output voltage can be described as

^o ~ Sm'gs

= ~ Sm" gs

l + 7 « * / . ( C A + C m 2 )

R'L

(4.54)

1 + JQ)/0)2

where Q)2 =1/R^C^ +Cm2) = 1/(3.59 kQ x 5.35 pF) s 1/18.94 ns = 52.8 Mrd/s. The gate-

source voltage is equal to

V =V * gs Y

=v

1

l + jcoR(Cgs+Cml)

1 (4.55)

1 + jco/coi

where <QX =1/R(C g s +Cml) = 1/(1 kfl x 38.55 pF) £ 1/38.55 ns = 25.9 Mrd/s. Using the

approximate analysis techniques of Section 2.6, knowing t h a t ^ = 0)H/(27t) one can write using Equation (2.62) 2.77 MHz <fH < 4.13 MHz (4.56) This result compares very well with the PSpice-computed value of 3.0 MHz.

Example 4.2 Use PSpice to find the higher cut-off frequency of the common-drain amplifier shown in Fig. 4.30. Assume R = 1 kQ, 1^ = 1 Mi), Ry = 1 kQ, RL = 10 kQ. The FET has rd = oo, IDSS =16 mA, Vp = -2 V, Cgs = 10 pF, Cgd = 3 pF, Cds = 2 pF; it operates in saturation. Solution. One can find that the FET transconductance in this Example is n = 2.372 mS and R'L

= 909.1 Q. The high-frequency equivalent circuit is shown in Fig. 4.35a. The corresponding PSpice code is presented in Fig. 4.35b.


The PSpice simulation run for the circuit of Fig. 4.35a produced^ 2 27.7 MHz. The higher cutoff frequency of the common-drain amplifier is then much larger than the value of 3.0 MHz obtained for the common-source amplifier. *

(a) common-gate amplifier V 1 0 ac lmV R 1 2 Ik Rs 2 0 Ik Cgs 2 0 lOpF Cds 2 3 2pF Cdg 3 0 3pF gm 3 2 0 2 2.372m Rd 3 0 5.6k RL 3 0 10k .ac dec 100 10Hz lOOMEGHz .end

Figure 4.36 Small-signal high-frequency equivalent for the common-drain amplifier

Example 4.3 Use PSpice to find the higher cut-off frequency of the common-gate amplifier shown in Fig. 4.31. Assume R = 1 kQ, Rs = 1 kQ, RD ~ 5.6 kQ, RL = 10 kQ. The FET has rd = oo, IDSS = 1 6 mA, Kp = -2 V, Cgs = 10 pF, Cgd = 3 pF, C<k - 2 pF; it operates in saturation. Solution. One can find that the FET transconductance in this Example is = 2.372 mS and R'L

= 3.59 kQ. The high-frequency equivalent circuit is shown in Fig. 4.36.

The PSpice simulation run for the circuit of Fig. 4.36a produced^ =11.2 MHz. The higher cutoff frequency of the common-drain amplifier is then larger than the value of 3.0 MHz obtained for the common-source amplifier.

*

From the three basic configurations of single-FET voltage amplifiers, the bandwidth of the common-drain circuit is the largest one. The smallest bandwidth is offered by the common-source circuit, which is explained by the pronounced Miller effect. There is a possibility of building an amplifier that has a large input impedance and gain of the common-source circuit and maintains the wide bandwidth of the common-gate amplifier. This is a cascode 2-FET amplifier shown in Fig. 4.37. In this amplifier, the input stage is a common-source circuit whose load resistance is very small being the input impedance of the output stage that is a common-gate circuit. Thus lower device has a small voltage gain, slight Miller effect and wide bandwidth. The upper device offers large bandwidth and converts the current from the lower device into large output voltage. Investigation of the properties of this amplifier is left as an exercise to the reader.

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Exercise 4.16. Consider the amplifier shown in Figure 4.37. Both FETs have V& = 3 V, K = 0.6 mA/V2, n = oo, Cgs = 10 pF, Cgd = 3 pF, Qs = 2 pF, and operate in saturation. Assume R = 1 k£2, RD= 5.6 k£2, RL= 10 kfi. Find device Q-points and transconductance. Draw the small-signal equivalent circuit valid for medium and high frequencies (replace the capacitances by short circuits). Run .ac PSpice analysis to find the amplitude characteristic of the amplifier. Determine the effective gain and bandwidth of the whole cascode as well as gain and bandwidth of its individual stages.

24V

Figure 4.37 2-MOSFET cascode amplifier

In the next few sections, we turn our attention to other applications for the FET, such as voltage-controlled resistance and CMOS logic circuits.

4.8 The FET as a Voltage-Controlled Resistance

Besides its use as an amplifier or as a switch (see Section 4.9), the F E T is useful as a voltage-controlled resistance. In this application, the bias point is chosen at the origin of the output (drain) characteristics as illustrated in Fig. 4.38.

10

VDSOO

Figure 4.38 When used as a voltage-controlled resistance, the FET is biased at the origin

If the gate-to source voltage is greater than the pinch-off voltage, the device operates in the linear (triode) region, and the drain current is given by Equation (4.5), which we repeated here for convenience

iD=K[2(vGS-VP)vDS-v2DS]

The transconductance of the device can be found by application of Equation (4.34), which is

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dir dv GS Q-pmnt

Applying this equation to (4.5) we have

° « "»\Q-poml (4.57)

But the jg-point is vDS= VDS=Q, so we have^n=0. Another way to obtain this result is to recall that gm is a measure of vertical spacing of the drain characteristics. However, as shown in Fig. 4.38, all the characteristic curves pass through the origin, and the spacing is zero for that point.

Figure 4.39 Small-signal equivalent circuit for a FET operated at VDS=0

Because gm=0, the controlled current source of the small-signal equivalent circuit for the FET biased as shown in Fig. 4.38 becomes an open circuit. Thus as shown in Fig. 4.39, die small-signal equivalent circuit simply becomes a resistor ra connected between the drain and source terminals. This resistance can be found by application of Equation (4.32), which is repeated here, for convenience

1 dir

8v DS Q—poinl

Applying this equation to (4.5), we obtain

a

Evaluating for vDS=0 and rearranging, we find that 1

(4.58)

(4.59) 2K(VGS-VP)

which is valid provided that Vcs is above pinch-off. Of co. rse, if is less than Vp, die FET is in cutoff and ra=oo.

Figure 4.40 Voltage-controlled FET attenuator

Thus we see tiiat if the FET is biased at the origin of the drain characteristics, it behaves as a resistor connected from drain to source, the value of which is controlled by the gate-to-source voltage. This conclusion can also be made by inspection of Fig. 4.38, where die curves are approximately straight lines intersecting die origin, and their slopes depend on vGS.

One application of the FET as a variable resistance is in die voltage-controlled attenuator circuit drawn in Fig. 4.40. The resistor R and die resistance r<i of the FET form a voltage divider, so die output voltage is given by

- 1 1 4 -

file:///Q-poml

Analog Electronics / FET Circuits.

vo=vs ?d

R + rd (4.60)

The control voltage is applied to the gate of the FET. If the control voltage is less than the pinch-off voltage, ra = oo and no attenuation occurs. However, as the control voltage is raised above pinch-off, rd becomes smaller and the attenuation becomes greater.

The circuit of Fig. 4.40 is an alternative solution to the semiconductor diode voltage-controlled attenuator circuit discussed in Section 3.4. The FET-based attenuator is often used to stabilize die amplitude of RC sine-wave oscillators.

Exercise 4.15 Suppose that R = 10 kQ in the voltage-controlled attenuator in Fig. 4.40 and a FET having IDSS = 16 mA, VP= -4 V is used. Compute values of ra and Av = *b/i% for a number of values of vGS= -Vc— 0, - 1 , -2, -3 and -4V. Compare the results with those obtained in Exercise 3.6. ADS. rd = 125 fi, 167 Q, 250 Q, 500 Q and oo;Av =0.0123, 0.0164, 0.0243, 0.0476 and 1.0, respectively.

4.9 The CMOS Analog Switch

The CMOS analog switch also known as a transmission gate is shown in Fig. 4.41. We will see that it acts as a switch that either connects points A and B through a low resistance or disconnects mem, depending on the digital control signal Vc.

We assume that the logic levels for Ve are +VDD (high) or -VDD (low). Note mat the control signal is connected directly to the gate of the NMOS and to the input of the logic inverter. The inverter output is connected to the gate of the PMOS. The input signal vs to be connected to the load RL can be either analog or digital and is assumed to range between -VDD and +VDD. The NMOS substrate is connected to the negative supply. We assume the FETs are identical except for polarity. The threshold voltage for the NMOS is V^ = V^ and for the PMOS is V^ = -VA. Furthermore, we assume that KA is less than VDp.

Figure 4.41 CMOS analog switch

If Vc = -VDD, both FETs are cut off (provided that vs is within -KD D and + VDIj). Thus for Vc

low, an open circuit appears between A and B.

Now consider Vc = +KD D . To start, we assume that the input voltage vs is positive, so current

flows from left to right through the FETs. With PS = 0 both the NMOS and PMOS are

conducting. Then as v% increases, current flows through the FETs, raising the output voltage.

- 1 1 5 -


Usually, the resistance of the FETs is low enough so that vQ is approximately equal to vr (The FETs operate in the triode region.) Notice that the gate-to-source voltage of the NMOS is VGSN=VC-V0 (4.61)

However, since we are assuming that Vc = VDD, we have VGSN=VDD-V0 (4.62) When the output voltage exceeds VDD-VA, the NMOS becomes cut off, but the PMOS is heavily conducting. Thus point A is connected to point B by a low-resistance path for all values of v% between zero and VjrjD.

Similar reasoning, with source and drain terminals interchanged, applies for negative values of the input voltage. Thus for Vc high, point A is connected to point B regardless of the polarity of vs. For v0 between -VDD+VA and VDD-VA, both FETs are on. Outside this range, only one of the FETs is on.

The resistance of a FET is nonlinear. However, for an analog signal, it is undesirable for die resistance between points A and B to be nonlinear because this leads to distortion of the output voltage. Fortunately, it can be shown that the nonlinearities of the PMOS and NMOS cancel in the range of voltages for which both transistors are on. This is an advantage of the CMOS switch as compared to circuits having only a single transistor. For an analog input signal taking both positive and negative values, we should choose positive and negative logic level so that both transistors are on for the range of input voltages expected.

Exercise 4.16 Suppose that the analog switch of Fig. 4.41 uses enhancement MOSFETs having \VA\ =1V and IK^lmA/V 2 . Also, VDD=SV and RL is large enough so that vQ is approximately equal to vs. The control signal is Vc = VDDt so die gate is in the on state. Find the small-signal resistance rd of the NMOS for vs=0, 1, 2, 3, 4, and 5V. Repeat for the PMOS. Find the effective incremental resistance of each device between points A and B for each input voltage. (Hint. vDS=0, so Equation (4.56) can be used with appropriate changes in notation.)

4.10 CMOS Logic Circuits

In this section we briefly discuss an important logic family that uses complementary metal-oxide-semiconductor (CMOS) FETs. The term complementary implies that both /(-channel and p-channel devices are employed.

NMOS inverter with resistive pull-up. Before considering CMOS circuits, we discuss die simpler inverter circuit shown in Fig. 4.42. The transistor is an »-channel enhancement device (NMOS) having a threshold voltage V^. The load capacitance represents the input capacitance of driven circuits (such as gates, inverters).

- 1 1 6 -


The drain characteristics of the NMOS transistor are shown in Fig. 4.43. The input voltage Vm is applied to the gate, so we have vGS= V^. For the moment, we assume that the load capacitance is an open circuit. Using the values RD=10kQ and VDD=10V we construct the load line shown in Fig. 4.43.

Notice that if the input voltage is less than the threshold voltage of the transistor (assumed to be

Kth=3V in this example), the transistor is cut off. Then the circuit operates at point A, and the

output voltage is K0= VDD.

As the input voltage is raised above threshold, the point of operation moves up the load line. When f^n= VDD, the circuit operates at point B, and the output voltage is low. Thus the circuit operates as a logic inverter (low input corresponds to high output and vice vend).

Fig. 4.44a shows the transfer characteristic of the MOS inverter with resistive load. Points A and B are marked, as discussed above. With logic one at the input (vGS = 10 V), the output voltage is equal to 0.61 V and is considered output logic zero for this inverter circuit At the same time, the drain current is equal to 0.94 mA. Thus the inverter circuit considered draws a power from a power supply when its input is logic one. Part of this power is dissipated in die drain resistor [PR

= (10V-0.61V)x0.94mA = 8.8mW] and the rest is dissipated inside the MOS transistor structure (PT = 0.61Vx0.94mA = 0.6mW). This causes the power loss that shortens the battery life in portable equipment and leads to heating of the circuit.

- 1 1 7 -


In selecting the value of the pull-up resistor Rp, we encounter conflicting objectives. On die one hand, we want to make die resistor large because this leads to a small current the transistor is on. This, in turn, means a smaller demand on the power supply and less heating of die circuit On die other hand, we want to make RD small, so that when the FET switches off, the load capacitance is quickly charged. (Usually it is important for logic transitions to take place quickly.)

The CMOS inverter. A solution to diis conflict is to use an enhancement ^-channel MOS (PMOS) transistor in place of die pull-up resistor as shown in Fig. 4.45. (An additional benefit is diat die PMOS takes much less chip area dian a resistor and dierefore is advantageous for IC implementation.)

vDD=\0\ 1 1

In the following discussion we assume diat except for the differences in voltage polarity and current direction, die NMOS and PMOS have identical characteristics. The direshold of die NMOS is Vfan = Vfa which is a positive value, and the threshold voltage for the PMOS is V^ = -Vfa. Also we assume, as is often the case, that the supply voltage VDD is greater that twice die direshold voltage magnitude. (In the illustrations, we assume that Kth=2V and VDD=\OV.)

Notice in Fig. 4.45 that the source terminal of the PMOS is connected to VDD and that the drain is connected to the inverter output The gate-to-source voltage of the PMOS is given by v G S P = ^ - r D D (4-63) When Vm = VDLh die gate-to-source voltage of the PMOS is zero, so it is cut off. Then it acts as a very high value of R , and virtually no current flows from the supply. On the other hand, when Vm = 0, we have PGSP = -VDD, and the PMOS can deliver a large drain current to charge the load capacitance. Since the NMOS is cut off for UQ^ = V^ = 0, no current flows after die capacitance is charged.

An important advantage of CMOS logic is that, except during logic transitions, either the NMOS or the PMOS is cut off, and no current flows. Thus the static power consumption (i.e. the power consumption of a logic circuit when the logic states are not changing) is virtually zero. For this reason, CMOS is an attractive choice for battery-operated circuits such as portable computers.

Now we consider load-line constructions for the CMOS inverter. Recall that in the case of a resistive load, the load line is straight - the volt-ampere characteristic of a resistor. However, for a PMOS pull-up transistor, the load line is not straight; instead, it is a characteristic curve of the PMOS. Furthermore, the resistor results in a fixed load line, but the line (actually, it is a curve) for the PMOS pull-up changes as Vm changes. The load lines are shown for several values of Vin

on the characteristics of the NMOS in Fig. 4.46.

- 1 1 8 -


Figure 4.46 Load-line analysis of CMOS inverter. For the NMOS V^ - 2V and for the PMOS K,hp=-2V.

For Vm - 0, die PMOS is highly conductive, but the NMOS if cut off, and the point of operation is at A. Point B illustrates the operating point for a value of Vm greater than the threshold voltage of the NMOS but less than VDD/2. At point B the NMOS is in saturation and the PMOS in the triode region.

When Vm = VDD/2 = 5V, the load line and the NMOS characteristic intersect not at a single point but along a line from C to D in Fig. 4.46. Thus as Vm increases through VDD/2, the operating point switches abrupdy from C to D.

Point E illustrates an operating point for a value of Vm between VDD/2 and VDD-VA. At point E die PMOS is in saturation, whereas the NMOS is in the linear region. For Vm = KOD, the PMOS is cut off, and operating point is F.

- 1 1 9 -


KA. The transfer characteristic falls abruptly for Vm = VDD/2. The CMOS inverter closely approximates the ideal transfer characteristic for a logic inverter.

The current flowing from the supply through the transistors of the CMOS inverter, assuming an ideal open-circuit load is shown in Fig. 4.47b. Notice that if Vm = 0 or Vm = VDD> then the current is zero. Maximum current flow occurs for Vm = VDD/2. The maximum current value depends on the supply voltage and on the value of transistors' K.

The CMOS N O R and N A N D gates. The circuit diagram of a two-input CMOS NOR gate is shown in Fig. 4.48a. The source and drain terminals of the FETs are not labeled in the figure. The devices are physically symmetrical, so either end can be considered to be the source, with the other becoming the drain. Usually, we consider the source of the PMOS devices to be the terminal that current enters (i.e., the top en of this circuit). Similarly, we consider the sovirces of the NMOS devices to be the end that current leaves (Le., the bottom terminals of this circuit). Designation of source and drain is convenient in analysis of the circuit; however, the physical construction of a device is the same regardless of which end is the source or drain.

Now we consider the operation of the circuit shown in Fig. 4.48a. If both inputs A and B are low, the PMOS transistors' M1 and M2 are conductive, and both the NMOS transistors M3 and M4 are off. Consequently, the output is high. If either A or B or both are high, one or both of the PMOS devices are cut off. Furthermore, at least one of the NMOS devices is conductive. Consequendy, the output is low. Consequendy, this circuit performs the NOR logic function. A two-input CMOS NAND gate is shown in Fig. 4.48b.

A/? "H MM Mj

(») (b) Figure 4.48 CMOS two-input logic gates: (a) NOR gate, (b) NAND gate

Exercise 4.16 For the circuit of 4.48b, prepare a table showing all possible combinations of inputs (each input can be" high or low), the corresponding state of each transistor, and the corresponding output. Indicate the state of each transistor either as on for operation in the triode or saturation region or as o^for operation in cutoff.

Exercise 4.17 Draw the circuit diagram of a three-input CMOS NOR gate.

Exercise 4.18 Prepare a table showing the regions of operation (saturation, triode or cutoff) of the PMOS and the NMOS for each labeled point on the inverter transfer characteristic shown in Fig. 4.47.

Exercise 4.19 A CMOS inverter is constructed with symmetrical devices having V^ = 3V and

Vfo. = -3V. Sketch the transfer characteristic to scale if VDD = 15V.

- 1 2 0 -


Exercise 4.20 If the devices have \K\ =lmA/V2 , find the supply current through the inverter of Exercise 4.20 if Vm = VDD/2. Assume an open-circuit load. Ans. 20.25mA.

4.11 FET Dynamic Circuit Models

Figure 4.49 shows a circuit model for an ^-channel JFET and the corresponding SPICE parameters. Current source iD describes the static characteristic of the device. In pinch-off, the drain current of an ^-channel JFET is given by

iD = K(vGS - Vpfil + Xvos) (4.64) in which K is a proportionality factor that depends on a particular device, Vp is the pinch-off voltage, and the parameter X accounts for the slope of the output characteristic curves in saturation. In die preceding sections of this chapter we have assumed X = 0 to simplify discussion. The nonzero value of X leads to a nonzero value of the small-signal output conductance r<i (see Fig. 4.21). It can be shown that the output conductance can be calculated as

where ID is the dc value of the drain current For the transconductance of a JFET with nonzero X, Equation (4.29) should be modified as follows

gm=2^KID(l + XVDS) (4.66)

where VDS is the dc drain-source voltage.

Figure 4.49 Dynamic model of a discrete »-channel JFET

The diodes add to the model the reverse saturation current Js that flows through the input circuit of the physical device. If the gate is not reverse biased in simulation, these diodes conduct that is not the expected operation mode of a JFET. Since the gate is usually reverse biased relative to the channel, die diodes have nonlinear depletion capacitances Ca and CGD. The depletion capacitance of the diode is given by Equation (3.40). Making appropriate changes in notation, we have

1 - 'GS

CDS =•

^0 . CDS0

m

m (4.68)

1 - DS

- 1 2 1 -


(Additional depletion capacitances C„ and CBD connect source and drain to the substrate in IC structures.) Ohmic resistances RQ and Ry complete the model. Below there are two examples of PSpice device statement for JFETs:

Jl Dnode Gnoda Snoda JModName .MODEL JModNana NJF(VTO>-4 BETA=lE-3)

Jl Dnode Gnoda Snode J2N3819 .LIB EVAL.LIB

TABLE 4.2 SPICE PARAMETERS FOR N-CHANNEL JFKD

Text notation

SPICE notation

Parameter name Typical value

Default value

vP VTO Pinch-off voltage -3V -2V K BETA Transconductance

coefficient 600E-6A/V2 100E-6 A/V2

X LAMBDA Channel-length modulation coefficient

2E-3 V 1 0

I IS Saturation current 2E-12 A 1.0E-14A n N Emission coefficient 1 1

RD RD Ohmic drain resistance \Cl 0

Rs RS Ohmic source resistance 0.1 Q 0

^GDO CGD Gate-drain depletion capacitance (zero bias)

3pF 0

^GSO CGS Gate-source depletion capacitance (zero bias)

3.3 pF 0

m M Junction grading factor 0.333 0.5

fo PB Built-in barrier potential I V 0.5 V

"Typical values of the parameters are shown for a discrete general-purpose device

An enhancement MOSFET structure is presented in Fig. 4.50. Notice that the length JL and width W of the channel are labeled on die figure. In the saturation region, the drain current is given by

iD = j K(vGS - Vth)2{\ + XvDS) (4.69)

(Previously, we assumed for simplicity that W/L. = 1 and X = 0.) Notice that the current depends on the width-to-length ratio of the channel. The device designer can vary this ratio to obtain devices best suited for various functions in a circuit It turns out that the small-signal transconductance depends on the W/L, ratio as follows

8m = 2^KID^(\ + XVDS) (4.70)

whereas the formula (4.65) is valid for MOS as weU. Keep in mind that the equation for n and gd are valid only for operation in the saturation region.

Of course, it is desirable to construct devices with small dimensions so that a large number of mem fit in a .given chip area. Another advantage of smaller devices is that the device capacitances are smaller. Provided that the width-to-length ratio is maintained, the current available to charge and discharge these capacitances is independent of device size. Thus digital circuits constructed

-122-


with smaller MOS transistors can switch faster. Both the speed and complexity of digital MOS circuits can increase as the device dimensions become smaller.

Figure 4.50 ^-Channel enhancement MOSFET structure with channel length L and channel width W

SPICE uses Equation (4.69) to relate the current to the voltages, except that ohmic resistances are added in series with the source and the drain. This is shown in Fig. 4. In the MOSFET of Fig. 4.51 there are depletion capacitances CBS and CBD between the substrate and reverse-biased n-type wells. To describe these capacitances, SPICE uses zero bias capacitances CBS and CBD, grading coefficient MJ and bulk junction potential PB. The SPICE model also includes the exponential volt-ampere behavior of the body-drain and body-source junctions. These junctions, characterized by the reverse saturation current IS, must be kept reverse biased in the simulation (as in the physical device) by connecting the substrate to the most negative point in the circuit.

Figure 4.51 »-channel MOSFET dynamic circuit model

Fig. 4.51 also suggests capacitance, CGB, between gate and substrate, with the oxide for its dielectric. It turns out that in places where the gate slighdy overlaps the drain and source materials there are additional capacitances CG5and CGD. SPICE computes values for CGS, CGD, and CGB when we specify the value of oxide thickness, TOX, on the .MODEL line and when W and L are specified on the element lines of the transistors. TOX = 0.1U, W = 1U, and L = 1U suffice as rough estimates when actual values are unknown. Resistors Rs and RD represent the voltage drops by current flowing to the external contacts D' and S'. SPICE includes temperature variation in threshold voltage and pn junction parameters; however, variations in mobility with temperature are absent in basic versions of SPICE.

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TABLE 4.3 SPICE PARAMETERS FOR MOSFETs*)

Text notation

SPICE notation

Parameter name Typical Value, NMOS

Typical Value, PMOS

Kh VTO Threshold voltage I V - I V 2|K| KP Transconductance

coefficient 30E-6 A /V 2 12E-6 A/V2

X LAMBDA Channel-length modulation coefficient

1E-2 V-1 1E-2 V 1

Ro RD Ohmic drain resistance 10 Q ion Rs

RS Ohmic source resistance 10 Q ion "Typical values are given for devices having W/L, = 1.

Table 4.3 lists SPICE model parameters for static operation. The capacitances Ccs, CCD, and CCB

have been described in the text above. Relationships of the type (4.67) and (4.68) describe the capacitances CfBand CDB. Notice that the SPICE transconductance coefficient is KP = 2|K| Much work has been expended to obtain SPICE models based on device dimensions and process parameters. Three of the resulting models are incorporated into PSpice. A particular model can be selected in the .MODEL statement by the LEVEL=1, 2, or 3 parameter. The default is LEVEL =1. Detailed discussion of these models is beyond the scope of these lecture notes. The device statement for MOSFETs takes the form

Mdevice Dnode Gnode Snoda Bnoda MNama L»VALUE W-VALUE .MODEL MNama NMOS(VTO=l KP=30U LAMBDft-0.01 RD=10 RS-10)

Notice that the first character of a MOS device must be M.

Example 4.4 Write a PSpice code to plot the output characteristics for an NMOS having the model parameters given in Table 4.3. The device dimensions are JL = 20 um and W — 50 urn. Assume that the substrate is connected to the source. Allow the drain-to-source voltage to range from 0 to 20 V in 0.1-V steps and gate-to-source voltage to range from 0 to 10 V in 1-V steps. Solution. The program listing is

NMOS characteristics example Ml 2 1 0 0 NAME L=20u W*50u .MODEL NAME NMOS (VTO=l KP=30u LAMBDA»0.01 RD=10 RS=10) VGS 1 0 dc 5V ' VDS 2 0 dc 10V .DC VDS 0 20 0.1 VGS 0 10 1 .END

The reader is suggested to reconstruct the schematic diagram of the simulated circuit from the code.

After running the program and starting PROBE, we request a plot of ID(M1). The resulting plot of the output characteristics is shown in Fig. 4.52.

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n IBtmi

Figure 4.52 Output characteristics for Example 4.4

4.12 Summary

Field-effect transistors are 3-state devices that serve as dependent sources in analog applications and as controlled switches in digital circuits. In one kind of FET, the control gate is insulated from the conducting channel; another FET class has a gate that is in physical contact with the channel by electrically separated by a reverse biased or Schottky junction. All ^-channel FETs share the same state definitions, equations, and circuit models, except for minor notational differences. Mathematically, the transfer characteristics of all «-channel FETs are the right-hand branches of parabolas; they differ only in the algebraic sign of the threshold or pinch-off voltage. Equations for /(-channel FETs are identical to those of //-channel devices; however, output characteristics plot in the second quadrant instead of the first. The circuit models differ only in the reference directions of the drain currents. The transfer characteristics are of all />-channel devices are left branches of parabolas; individual differences are only in the algebraic sign of the threshold or pinch-off voltage. In analysis of FET circuits we encounter two general classes of problems: finding ^-points when transistor states are known and finding j2-points when the states are unknown. The tools and procedures for solving these problems are load lines, equivalent circuits and guessing and verifying states. The infinite input resistance of the FET tends to simplify circuit analysis; however, FET circuits usually require us to solve a quadratic equation and select the solution that has physical meaning. The FET can operate as a voltage-controlled linear resistor. The most significant second-order effects in FET are breakdown associated with reverse-biased junction that places an upper limit on the useful active region, channel length modulation that causes a nonzero positive slope of output characteristics in the saturation state, and the decrease of the threshold voltage and channel resistance with temperature. Internal parasitic capacitances limit the FETs ability to operate at high frequencies. Some are depletion capacitances associated with reverse-biased junctions; others are linear capacitances associated with insulated gates. Because the minority charge carriers do not take significant part in the current conduction in FETs, these devices lack large diffusion capacitances associated with stored minority charge carriers. SPICE models can simulate the nonlinearities of the static transistor models, and also include most second-order effects of FETs. Because of high input impedance and output characteristic that resemble resistor volt-ampere curves in both first and second quadrants, FETs make excellent switches. Bidirectional transmission gates constructed from FETs are widely used in both digital and linear applications. For small signals, a

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FET biased in die saturation region functions as a voltage-controlled current source with a transconductance ^n = 2K(KcrVth) and the output resistance r0 = 1/(AJD). The common-source configuration provides a high voltage gain and a very high input impedance, but a limited high-frequency response. A much wider bandwidth is achieved in the common-gate configuration but its input impedance is low. The source follower (common-drain amplifier) provides a voltage gain less than unity but features a low output resistance. Integrated-circuit MOS amplifiers utilize MOS transistors as amplifying and as load devices. In CMOS technology, both n- and/(-channel enhancement MOSFETs are used, thus providing the circuit designer with considerable flexibility. The most important things to remember about FETs are their output and transfer characteristics, the state definitions, the procedure to find their jg-point given bias circuit, and the load line concepts, including load lines for CMOS inverter sketched in Fig. 4.46.

Notes:

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Analog Electronics/BJT Circuits

5 Bipolar Transistor Circuits

Bipolar junction transistors (BJTs) are constructed as layers of semiconductor materials (most often silicon) doped with suitable impurities, producing either »-type or/Mype layer. A simplified physical structure of an integrated circuit npn transistor is shown in Fig; 5.1a. The actual transistor action takes place along die A-A' line shown in Fig. 5a. The idealized structure of the bipolar transistor, corresponding to its cross-section along the A-A1 line is presented in Fig. 5b, where a layer of p-type material is placed between two layers of the »-type material. This structure can be seen as two pn junctions made close together in a single crystal of semiconductor. The current in one junction affects the current in the other junction.

The layers of the bipolar transistor are called the emitter, the base, and the collector, as shown in Fig. 5.1b. The circuit symbol of an npn transistor is shown in Fig.5c, including reference directions for the terminal currents and voltages.

Recall that a pn junction is forward biased with applying positive polarity to the p-side. On the other hand, reverse bias occurs if the positive polarity is applied to the /|-side.

In normal operation of a BJT as an amplifier, the base-collector junction is reverse-biased and the base-emitter junction is forward biased. In the following discussion we assume that the junctions are biased in this fashion unless stated otherwise.

The Shockley equation gives die emitter current iE in terms of the base-to-emitter voltage vBE:

'£ = JES e x p ^ - l (5.1)

This is exacdy the same equation as for the current in a junction diode given in Equation (3.1), except for changes in notation. The emission coefficient n is made equal to unity since this is the appropriate value for most junction transistors. Typical values for the saturation current 1^ range from 1012A to 10"16A, depending on the size of the device. Recall that at a temperature of 300K, the thermal voltage VT is approximately 26mV.

Of course, Kirchhoff s current law requires that the current flowing out of die BJT is equal to the sum of the currents flowing into it. Thus, referring to Fig. 5.1c, we have i£=iC+iB (5.2)

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Analog Electronics /BJT Circuits

This equation is true regardless of the bias conditions of the transistor junctions.

We define the parameter a for the transistor as the ratio of the collector current to the emitter current.

'C a = lE

(5.3)

Values of a range from 0.9 to 0.999, with 0.99 being very typical. Equation (5.3) indicates that the emitter current is partly supplied through the base terminal and partly through the collector terminal. However, since a is nearly unity, the collector supplies most of the emitter current.

Substituting Equation (5.1) into (5.3) and rearranging, we have

rVBE ic = cdgs exp(——)- l (5.4)

For vBE greater than a few tens of a volt, the exponential term in the bracket is much larger than unity. Then the 1 inside the bracket can be dropped. Also, we define the scale current as

Is=a*ES " (5-5) and Equation (5.4) becornes (for the normal bias conditions)

VT (5.6)

Solving Equation (5.3) for i0 substituting into Equation (5.2), and solving for the base current, we obtain iB=(\-a)iE (5.7)

Since a is slighdy less than unity, then only a very small fraction of the emitter current is supplied by the base. Using Equation (5.1) to substitute for iE, we obtain

i B = ( l - a ) / £ S e x p ( ^ ) - l (5.8)

We define the parameter fi as the ratio of the collector current to the base current. Taking the ratio of Equations (5.4) and (5.8) results in

o 'C a

P iB l - « (5.9)

Values for/? range from about 10 to 1000, and a very common value is /£=100. We can write

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ic=PiB (5.10)

Note that since /? is usually large compared to unity, the collector current is an amplified version of the base current. Current flow in an npn BJT is illustrated in Fig. 5.2.

As in the case of the FET, the bipolar transistor is a three-terminal device. There are then three basic circuit configurations that employ the BJT as an amplifier, i.e. a circuit that has one input and one output. In each of these configurations, one of the transistor terminals is common to the input and to the output. The common-emitter configuration for an npn BJT is shown in Fig. 5.3. The battery connected between the base and the emitter supplies a positive voltage vBE that forward biases the base-emitter junction. The V& battery produces a positive voltage at the collector with respect to the emitter. Notice that the voltage across the base-collector junction is given by

VBC=VBE~VCE ( 5 1 1 ) Thus if VCE is greater than vBE, the base-collector voltage vBC is negative, which is reverse bias.

< *'c

Figure 5.3 Common-emitter circuit configuration for the npn BJT

The common-emitter characteristics of the transistor are plots of the currents iB and ic versus the voltage vBE and v^. Representative characteristics for a low-power silicon device are shown in Fig. 5.4.

The common-emitter input characteristic shown in Fig. 5.4a is a plot of iB versus vBE, which are related by Equation (5.8). Notice that the input characteristic takes the same form as the forward characteristic of a junction diode. Thus, for appreciable current to flow, the base-to-emitter voltage must be approximately 0.6V. Just as for a junction diode, the base-to-emitter voltage, for a given current, decreases with temperature by about 2mV/K.

The common-emitter output characteristic shown in Fig. 5.4b is a plot of ic versus v^ for constant values of iB. The transistor illustrated has /£=100. As long as the collector-base junction is reverse-biased (ffc^O, or equivalently vCE>t,BE)>we have ;C=/BB=IOOZB

As VCE becomes less than vBE, the base-collector junction becomes forward-biased, and eventually the collector current falls as shown at the left-hand edge of the output characteristics.

Refer to Fig. 5.4a and notice that a very small change in the base-to-emitter voltage vBE can result in an appreciable change in the base current iB, partially if the base-emitter junction is forward biased, so some current (say, 40|iA) is flowing before the change in vBE is made. Provided that v^ is more than a few tens of a volt, this change in base current causes a much larger change in the collector current i0 because i^fii^ In suitable circuits, the change in collector current is converted into a much larger voltage change than the initial change in vBE. Thus the BJT can amplify a signal applied to the base-emitter junction.

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5.1 Load-Line Analysis of a Common-Emitter Amplifier

A simple amplifier circuit is shown in Fig. 5.5. The power-supply voltages VBB and Vcc bias the device at an operating point for which amplification of die input signal ik(t) is possible. We will show that the amplified version of the input signal appears between the collector and die ground.

~ Figure 5.5 Common-emitter amplifier

The load-line technique will be used to analyze die circuit Applying the Kirchhoff s voltage law to die base loop, we obtain

VBB + V , ( / ) = RbhiO + VBEiO (5-12)

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Figure 5.6 Load-line analysis of the amplifier of Fig. 5.5: (a) input (load line shifts downwards for a smaller value of«%), (b) output.

A plot of Equation (5.12) is shown in Fig. 5.6a as the load line on the input characteristic of the transistr -. To establish the load line, we must locate two points. If we assume that iB=0, then Equatio (5.12) yields vBE=VBB+t>s- This establishes the point where trie load line intersects the voltage axis. Similarly, assuming that vBE=Q results in iB = (fflB+«fc)/.Rb, which establishes the load-line intercept on the current axis. The load line is shown in Fig. 5.6a.

Equation (5.12) represents the constraints placed on the values of iB and vBE by the external circuit. In addition, iB and vBE must fall on the device characteristic. The values that satisfy both constraints are the values at the intersection of the load line and the device characteristic.

The slope of the load line is -1/Kb. Thus the load line shifts position but maintains a constant direction as t% changes in value. For example, the lower load line in Fig. 5.6a is for a smaller value of t>s than that for the upper load line.

The quiescent operating point or Q-point corresponds to %(/)=0. Thus as the ac input signal t%(/) changes in value with time, the instantaneous operating point swings above and below the Q-point value. Values of iB can be found from the intersection of the load line with the input characteristic for each value of t%.

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After the input circuit has been analyzed to find values of iB, a load-line analysis of the output circuit is possible. Referring to Fig. 5.5, we can write a voltage equation for the collector loop, through Vcc, R& and the transistor from collector to emitter. Thus we have

YcC = Rcic+vCE (513) This is plotted on the output characteristic of the transistor in Fig. 5.6b.

Now, with the values of iB that we have already found by analysis of the input circuit, we can locate the intersection of the corresponding output curve with the load line to find values of ic

and «>££. Thus as t% swings through a range of values, iB changes, and the instantaneous operating point swings up and down the load line on the output characteristic. Usually, the ac component of V& is much larger than the input voltage; hence the amplification takes place.

Examination of Fig. 5.6a shows that as v&{t) swings positive, the value of iB increases (i.e. the intersection of the load line with the input characteristic moves upward). This in turn causes the instantaneous operating point to move upward on the output load line, and v^ decreases in value. Thus a swing in the positive direction for ik results in a (much larger) swing in the negative direction for v^. Therefore, as well as being amplified, the signal is inverted. In other words, the common-emitter amplifier is an inverting amplifier.

>«T : r :.—.,—-^

Figure 5.7 Output of the amplifier of Exercise 5.1 for ?s(/)=1.2sin(2000iu) demonstrating gross distortion

Exercise 5.1 Assume that the circuit of Fig. 5.5 has Vcc = 10 V, VBB = 1.6 V, Rb= 40l£i and

R,. = 2 ls£l. The input signal is a 0.4-V peak 1-kHz sinusoid given by t>s(f) = 0.4sin(200(br/). Use

PSpice to plot the device-characteristics assuming fip= 100 and Js = le-14 A. Using the load-line

technique find the maximum, minimum and Q-point values for vCE. Use PSpice to plot the

waveforms of vjt) and v^t). Ans. pCanki s 3 V, V^ = 5 V, VCmaai s 7 V.

It is not apparent in the waveforms that you have plotted in Exercise 5.1, but the output signal is not a precise sine wave like the input The amplifier is slightly nonlinear because of the curvature of the characteristics of the transistor. Therefore, as well as being amplified and inverted, the signal is distorted. Of course, distortion is not usually desirable. Fig. 5.7 shows the output of the amplifier of Fig. 5.5 and Exercise 5.1 if the input signal is increased in amplitude to 1.2 V peak. The distortion is obvious.

Notice that the positive peak of v^ has been clipped at KCC=10V. This occurs when iB and ic

have been reduced to zero by the negative peaks of the input signal, and the instantaneous

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operating point moves down to the voltage-axis intercept of the output load line. When this happens, we say that the transistor has been driven into cut-off.

The negative-going peak of the output waveform in Fig. 5.7 is dipped at v^ = 0.2 V. This occurs because iB becomes large enough so that operation is driven into the region at the upper end of the output load line, where the characteristic curves are crowded-together. We call this the saturation region.

Reasonably linear (undistorted) amplification occurs only if the signal swing remains in the active region between saturation and cutoff on the load line. An output load line is shown in Fig. 5.8, including labels for the cutoff, saturation and active regions.

J IC(Q1) W2

Figure 5.8 Amplification occurs in the active region. Clipping occurs when the instantaneous operating point enters saturation or cutoff. In saturation, VCE = 0.2V.

Exercise 5.2 Repeat Exercise 5.1 if Vs{t) = 0.8sin(2(XXbt^. Ans. Pamm = 1 V, V^ = 5 V, Vcsrv^S.SV.

Exercise 5.3 Repeat Exercise 5.1 if tk(t) = 0.8sin(2000it/) and VBB = 1.2 V. Ans. c un S 3 V , V^ s 7 V, Pep* s 9.8 V.

5.2 The pnp Bipolar Junction Transistor

So far we have considered the npn BJT, but an equally useful device is the pnp bipolar junction transistor, in which the base is a layer of »-type material between />-type emitter and collector layers. For proper operation of an amplifier, the polarities of the dc voltages applied to the pnp device must be opposite to those of the npn device. Furthermore, current flows in the opposite direction. Aside from the differences in voltage polarity and current direction, the two types of devices are nearly identical

A diagram of the structure of zpnp BJT and its circuit symbol are shown in Fig. 5.9. Notice that the arrow on the emitter of the pnp transistor points into the device, which is the normal direction of the emitter current For the pnp transistor we can write the following equations, which are exactly the same as for the npn transistor.

'C = ctiE (5.14) iB=(\-a)iE (5.15)

ic=fiB (5.16)

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and

i£=iC+iB ( 5 1 7 ) Equations (5.14) through (5.16) are valid only if the base-emitter junction is forward biased (vBE

negative for i-pnp) and the base-collector junction is reverse biased (y^ positive for a. pup). As for the npn transistor, typical values are a £ 0.99 and fi= 100.

and

These equations are identical to Equations (5.1) and (5.8) for the npn transistor except that - v#£ has been substituted for vBE (because vBE takes negative values for ihepnp device). As for the npn device, typical values for 1^ range from 10"12 to 10",6A, and at 300K we have V-f226tiN.

The common-emitter characteristics ofapnp transistor are exacuy the same as for the npn except that the values on the voltage axes are negative. A typical set of characteristics is shown in Fig. 5.10.

134


z.« i

1 -12M

! ItVB) (b)

Figure 5.10 Common-emitter characteristics for zpttp BJT: (a) input, (b) output

Exercise 5.4 Find the values of alpha and beta for the transistor having the characteristics shown in Fig. 5.10. Ans. a = 0.98, fi - 50.

Exercise 5.5 Use load-line analysis to find the minimum, maximum and Q-point values of iB and VCE for the amplifier circuit shown in Fig. 5.11. Use the characteristics shown in Fig. 5.10. Does this pnp BJT common-emitter amplifier invert the signal? Ans. igg^ = 5 |xA, IB = 25 |iA, tg^x = 48 uA, VOa^ £ -8.3 V, K C E S -5.3 V, Pcimax s -1.8 V.

ic Rc=3kCl

5.3 Secondary Effects

Collector breakdown. The description we have given so far is only a first-order model of the BJT. Real transistors exhibit many secondary effects that can be important in circuit design. For example, the common-emitter output characteristics of a real transistor are shown in Fig. 5.12. Notice that the collector current increases very rapidly as the collector-emitter voltage v^ approaches 30V in this case. This is due to the reverse-bias breakdown of the collector-base junction. Usually, we try to avoid having BJTs enter the collector-breakdown region because high currents and voltages can result in high power dissipation that leads to overheating and destruction of the device. Collector breakdown voltages range up to several hundred volts, depending on the device type.

Base width modulation. Another difference between the first-order BJT model and real transistors is that even before collector breakdown is reached, the collector current increases with collector-to-emitter voltage. For example, notice the positive slope of the curves in the active region of Fig. 5.12a. The slope is more pronounced at higher currents. This effect is attributed to die base width modulation effect known from the physics of the BJT operation.

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The shading of Fig. 5.12c and 5.12d suggests how the two depletion regions extend into the/>-type base region during forward active operation. The base-emitter depletion region is narrow, the reverse-biased base-collector junction has a wider depletion region. For increased v^, the depletion region of the base-collector junction extends still further into the base, which reduces the width of the base region. Thus carriers injected from the emitter spend shorter time for die transit through the base and therefore a lower number of them recombine in the base region. This brings a closer to one. Since /? is a sensitive function of a, the separation of the common-emitter output characteristics increases noticeably with f , as illustrated in Fig. 5.12a and 5.12b. For a constant base current, the collector current increases with v^. This is known as the Early effect. (The change in common-base output characteristics whose spacing is determined by a, is hardly noticeable because the percent change in a is small.)

If straight lines extend the collector characteristics in the active region, they (approximately) meet at a point on the negative v^ axis as shown in Fig. 5.12b. The magnitude of the voltage at the intersection is called the Early voltage, denoted by VA.

4 «+— ' c mm

si> m

(c) (d) Figure 5.12 Common-emitter output characteristic that shows collector breakdown (a);

extensions of die active-region collector characteristics intersect at -VA (b), base width modulation (c) and (d)

Variation of fi with Q-point. In the first order model of the BJT, the collector characteristic curves are uniformly distributed in the active region. Real transistors tend to have characteristics that are crowded closer together at very low and very high currents.

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At low values of Ic, recombination of charge carriers within the depletion region of base-emitter junction becomes significant. These phenomena manifest themselves by the emission coefficient n in the Shockley equation for base current having a value close to n = 2 which decreases to n = 1 for medium collector currents (e.g. for / ^ l m A in Fig.5.13a) whereas the emission coefficient for the collector current stays constant, n — 1. Thus for low currents, the ratio of base current to collector current is lower than for medium currents.

At high values of 7C, the unspoken assumption that the carriers injected into the base and emitter are not disturbing the original concentration of carriers is no longer valid. These high-injection-density effects, sometimes referred to as "current crowding", cause reduction of p. For large collector currents, e.g. /^lOmA in Fig. 5.13b, high current density in the base region causes a significant increase of the minority carrier concentration in the base which, in turn, produces a masking effect to the built-in nonuniform impurity concentration in -the base. In particular, the built-in electric field in the base is reduced by the injected charge and carrier transport efficiency is reduced. This reduces the value of the current gain.

Earlier we defined fi = IC/IB, but since the curves are not uniformly spaced, the value of f) is not constant for all points in the active region of real transistors. The variation of fi with collector current is illustrated in Fig. 5.13a for a typical BJT, showing the current gain decrease both at low and high currents. However, since the curves are generally broad and flat at moderate values of Ia we usually assume that ft is independent of operating point as a first approximation.

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(c) (d) Figure 5.13 Typical variation of ^with collector current (a),

input characteristics of a real transistor (b); output characteristic at temperature Tt (c), T? > T/ (d)

Parameter variation with temperature. Input and output characteristics of the BJT change with temperature, as do the BJT parameters. The common-emitter input characteristic translates to the left with increased temperature, in a similar way to the diode forward characteristic shown in Fig. 3.10. The base current is described by Equation (5.8). As in the diode, Vr = kT/q in the exponent dominates the temperature dependence and causes the voltage VBE to decrease by 2 mV for every degree Kelvin increase in temperature (at constant base current).

The output characteristics increase in separation and translate upward with increasing temperature as shown in Fig. 5.13c and 5.13d. This reflects the increase of j3 with temperature. Minority carrier lifetime increases with temperature, increasing the carrier transport efficiency through the base region and bringing a closer to one. According to Equation (5.9), /? is a sensitive function of a, the result is a large increase in /?, as temperature increases. An empirical relationship that predicts variations in /?is

flCn = fiCrJ^\ (5.20)

where T and TR are temperatures in degrees Kelvin and B is a constant called the temperature exponent. For a class of silicon bipolar transistors one may select B - 1.7, which makes (5.20) predict that J3 approximately doubles from 27°C to 175°C.

To explain the upward translation, we need to notice that equation (5.10) is an approximation. Namely, for higher accuracy it should have two terms as follows

where I^g is a small dc saturation current that doubles for every 5K increase in temperature.

From the three temperature-sensitive parameters, VBE actually proves to be the most troublesome in practical circuits. Even at elevated temperatures, J ^ is usually too small to play a major role in silicon transistors. Also, it is relatively easy to design circuits that work well for any high value of fi. Many IC designs use the VBE drops of matched transistors to cancel each other over wide temperature ranges.

Variation of/? from unit to unit. If we test many units of a transistor of a given manufacturer's type number, we generally "find that J3 displays considerable variation in the value from unit to unit. Typically, the ratio of the highest and lowest values of beta is 3:1. Furthermore, the value of beta-varies significantly with temperature for a given transistor. Therefore, m must design cinuits that junction properly for transistors having a wide range of beta values.

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Dependence of input characteristics on VCE. The input characteristics of a real transistor are shown in Fig. 5.13b. Notice that the input charactetistics ate not a single curve, as in the first-order model, but instead consist of a family of curves. The effect of base-width modulation with the varying vK voltage is mainly responsible for this property. However, assuming that v^ is larger than a few tenths of a volt (i.e. the BJT is biased in the active region), the input characteristic curves are very close together.

Charge storage effects. The characteristic curves show only die static operation of the device. For rapidly changing signals, charge storage effects occur, and the instantaneous operation of the BJT is not adequately described by the characteristic curves. These effects are important in the design of high-frequency amplifiers and high-speed logic circuits. We consider these aspects later in this chapter.

Even though real BJTs display many secondary effects that can be important in the design of critical circuits, the first-order model is sufficient for many designs. Even in critical circuits, designs often begins with die simple model. In die next few sections, we show some useful circuits man be analyzed and designed by use of first-order models.

5.4 Large-Signal dc BJT Models

In the analysis or design of BJT amplifier circuits, we often consider the dc operating point separately from the analysis of the (small) signals. This was illustrated for diode circuits and FET circuits in previous sections. Usually, we consider the dc operating point first. Then we turn our attention to the signal to be amplified. In this section, we present models for large-signal dc analysis of BJT circuits. Then, in die next section, we show how to use these models to design and analyze bias circuits for BJT amplifiers. Later we consider small-signal models used to analyze the circuit for the signal being amplified.

It is customary to use uppercase symbols with uppercase subscripts to represent large-signal dc currents and voltages in transistor circuits. Thus Ic and V^ represent the dc collector current and collector-to-emitter voltage, respectively. Similar notation is used for the other currents and voltage.

As we have seen, BJTs can operate in the active region, in saturation, or in cutoff. In the active region, the base-emitter junction is forward-biased and the base-collector junction is reverse-biased. (Actually, the active region includes the forward bias of the collector junction by a few tenths of a volt.)

C C n _ Q

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Figure 5.14 BJT large-signal models (Note: Values shown are appropriate for typical small-signal silicon devices at a temperature of 300K.)

Active-region model. Circuit models for BJTs in the active region are shown in Fig. 5.14a. A current-controlled current source models the dependence of the collector current on the base current. The constraints given in the figure for IB and K ^ must be satisfied to ensure validity of the active-region model.

0.2V VC£(V) 0.5V vae(V) (*) (b)

Figure 5.15 Regions of operation on the characteristics of an npn BJT: (a) output, (b) input characteristic.

Let us relate the active-region model to the device characteristics. Fig. 5.15 shows the characteristic curves of an npn transistor. The base current IB is positive and pBH=0.7V for forward bias of the base-to-emitter junction as shown in Fig. 5.15b. Also notice in Fig. 5.15a that VCE must be greater than about 0.2V to ensure that operation is in the active region (i.e. above the knees of the characteristic curves).

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Similarly, for the pnp BJT we must have JB>0 and VCE<-0.2V for validity of the active region model. (We have assumed that IB is referenced positive out of the base for the pnp BJT.)

Saturation-region model. The BJT models for the saturation region are shown in Fig. 5.14b. In this region, both junctions are forward biased. Examination of die collector characteristics in Fig. 5.15a shows that VQ^Q.ZV for an npn transistor in saturation. Thus the model for the saturation region includes a 0.2-V source between collector and emitter. As in die active region, IB is positive. Also, we see in Fig. 5.15a that for operation below the knee of the collector characteristic, the constraint is pHB>I(>0.

Cut-off region. In cutoff, both regions are reverse biased, and no current flows in the device. Thus the model consists of open circuits among all three terminals as shown in Fig. 5.14c. (Actually, if small forward-bias voltages up to 0.5V are applied, the .currents are non-zero but often negligible, and we still use the cutoff model.) The constraints on the voltages for the BJT to be in the cutoff region are shown in the figure.

Inverted mode. When the collector-base junction is reverse-biased and the base-emitter junction is forward biased, we say that the transistor is operating in the forward or normal mode. Sometimes, we encounter situations for which the base-collector junction is forward biased and the base-emitter junction is reverse-biased. This is the opposite of the normal situation, and we say that the transistor is operating in the inverted mode. Operation in the inverted mode is the same as in the normal mode, but with the collector and emitter interchanged. Most devices are not symmetrical, so alpha and beta take different, much lower, values for the inverted mode that for the normal mode. For now, we concentrate our attention on operation in saturation, cutoff or the normal active mode regions.

Exercise 5.6 A given npn transistor has /£=100. Determine the region of operation if (a) 7B=50uA and J ^ m A , (b) IB=50uA and VCE=5Vi (c) VBE=-2V and VCE=-1 V.

Exercise 5.7 A certain/>/#> transistor has /?=100. Determine the region of operation if (a) VBE—-0.2V and KCT=5V, (b) 7B=50uA and Ic=2mA, (c) FCE=5V and 7B=50uA.

5.5 Large-Signal dc Analysis of BJT Circuits

In this section, we will use the large-signal BJT models presented in Section 5.4 to analyze circuits.

(a) (b) (c) (d) Figure 5.16 Bias circuits for Examples 5.1 and 5.2: actual circuit (a),

equivalent circuits assuming operation in cutoff (b), in saturation (c), in the active region (d)

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In the dc analysis of BJT circuits, we first assume that the operation of the transistor is in a particular region (i.e. active, cutoff, or saturation). Then we use the appropriate model for the device and solve the circuit Next, we check to see if the solution satisfies the constraints for the region assumed. If so, the analysis is complete. If not, we assume operation in a different region and repeat until a valid solution is found. (This is very similar to the analysis of diode circuits using ideal-diode model or a piecewise-linear model.)

This approach is particularly useful in the analysis and design of bias circuits for BJT amplifiers. The objective of the bias circuit is to place the operating point in the active region so that signal can be amplified. Because transistors show considerable variation of parameters, such as (3, from unit to unit and with temperature, it is important for the bias point to be independent of these variations.

The next several examples illustrate the technique and provide some observations that are useful in bias-circuit design.

Example 5.1 The dc bias circuit shown in Fig. 5.16a has RB=200kQ, Rc=lkQ, and KCC=15V.

The transistor has /£=100. Solve for I c and VCE-Solution We will eventually see that the transistor is in the active region, but we start by assuming that the transistor is cut off (to illustrate how to test the initial guess of operating region). Since we assume operation in cutoff, the model for the transistor is shown in Fig. 5.14c, and the equivalent circuit is shown in Fig. 5.16b. We reason that 7fl=0 and there is no voltage drop across RB. Hence we conclude that VB£=15V. However, in cutoff, we must have Kfl£<0.5V for an npn transistor. Therefore, we conclude that the cutoff assumption is invalid. Next, let us assume that the transistor is in saturation. The transistor model is shown in Fig. 5.14b. Then the equivalent circuit is shown in Fig. 5.16c. Solving, we find that / c =(^ c r0 .2 ) /R c =H.8mA and /B=(^ar0.7)/R, = 71.5uA Checking the conditions for saturation, we find that /B>0 is met, but /3IB>IC is not met. Therefore, we conclude that the transistor is not in saturation. Finally, if we assume that the transistor operates in the active region, we use the BJT model of Fig. 5.14a, and the equivalent circuit is shown in Fig. 5.16d. Solving, we find that 4=(* /ar0.7)/RB=71.5uA where we have assumed a forward bias of 0.7V for the base-emitter junction. (Some authors assume 0.6V for low-power silicon devices. Others assume 0.7V.) In reality, the value depends on the particular transistor and the current level. Usually, the difference is not significant.) Now we have

lc=Ph = 7.15nA Finally, VCE=VCC-R<IC = 7.85V The requirements for the active region are KCE>0.2V and 7B>0, which are met. Thus the transistor operates in the active region.

Exercise 5.8 Repeat Example 5.1 with /£=300. Ans. 7c=14.8mA, KCE=0.2V (saturation).

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^ 1 5 V vCT(V)

(b) P = 300 Figure 5.17 Load lines for Example 5.1 and Exercise 5.8

It is instructive to consider the load-line constructions shown in Fig. 5.17 for the last two examples. For /£=100, the operating point is approximately in the center of the load line. On the other hand, for /?=300, the operating point has moved up into saturation.

To use this circuit as an amplifier, we would want a Q-point in the active region where changes <-i the base current cause the instantaneous operating point to move up and down the load line. In saturation, the operating point does not move significantly for small changes in the base current, and amplification is not achieved. Thus a suitable Q-point is obtained for /?=100 but not for /?=300. Since we often find unit-to-unit variations in fi of this magnitude, this circuit is not suitable as an amplifier bias circuit for mass production. (We could consider adjusting RB to compensate for unit-to-unit variations in /?, but tibis is usually not economical.)

Sometimes the discussed circuit of Fig. 5.16a is called a fixed-base bias circuit because the base current is fixed by Vcc and RB and does not adjust for changes in p. (Notice that if we want a circuit that achieves a particular operating point on the collector load line, the base current must change when /3 changes.)

Exercise 5.9 Repeat Exercise 5.8 for (a) ,£=50, (b) ,0=250. Ans. (a) 7c=3.575mA, V^-X 1.43V,

(b) I(f=U.ZiaA, Va,=0.2V

Exercise 5.10 Assume that R ^ k O , FBE=0.7V and VCC=20V in the circuit of Fig. 5.16a. Solve

for the value of RB needed to place the operating point exacdy in the middle of the output load

line-for (a) P=100, (b) P=300. Ans. (a) RB=965kQ, (b) RB=2.9MQ.

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Exercise 5.11 Solve the circuit shown in Fig. 5.18 to find Ic and V^ if (a) >0^5O, (b) /£=150. Ans. (a) 7c=:0.965mA, ^ = - 1 0 . 3 5 ^ (b) 7c=1.98mA, Va=-0JZV (transistor in saturation).

lOkfl

Figure 5.18 Circuit for Exercise 5.11

In the next example we consider a circuit that achieves an emitter current that is relatively independent of /3.

W (b) Figure 5.19 Circuit of Example 5.2 (a) and its equivalent circuit (b) assuming

operation in the active region.

Example 5.2 Solve for 7C and V^ in the circuit of Fig. 5.19a if VC(~=\5V, VBB=5V, Rc=2kQ,

and yS lOO. Repeat for ^=300. Solution We assume that the transistor is in the active region and use the equivalent circuit shown in Fig. 5.19b. Wr»«ing a voltage equation through VBB, the base-emitter junction and RH)

we have F f lB=0.7 + 7ERH

This can be solved for the emitter current h= {VBB-0.1)/RE= 2.15mA Notice that the emitter current does not depend on the value of fi. Next we can compute the base and collector current using Equations (5.10) and (5.2)

IE = IB+/3IB = (JS+1)IB

Solving for the base current, we obtain

7B=/E/09+l) Substituting values, we obtain the results given in Table 5.1. Notice that 7B is lower for the higher

P transistor, and Ic is nearly constant.

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TABLE 5.1 RESULTS FOR EXAMPLE 5.2

1 p JJO^A) J^mA) ^CE(V)

I 100 21.3 2.13 6.44 1 300 7.14 2.14 6.42

Now we can write a voltage equation around the collector loop to find *VCE

Vc^RcIc+Vcz+RzIz Substituting values found previously, we find that 1^=6.44V for /?=100 and KCE=6.42Vfor^=300.

The Q-point for the circuit of Fig. 5.19a is almost independent of p. However, die circuit is not usually practical for use in amplifier circuits. First, it requires two voltage sources, VBB and Vco

but often one source is readily available. Second, we may want to inject the signal into the base (through a coupling capacitor), but the base voltage is fixed with respect to ground by the VBB

source. Because the VBB source is constant, it acts as a short-circuit to ground for ac signal currents (i.e. the VBB source does not allow an ac voltage to appear at the base.)

5.6 Four-Resistor Bias Circuit

A circuit that avoids the objections discussed at the end of the previous section is shown in Fig. 5.20a. We call this the four-resistor BJT bias circuit. The resistors R, and R2 for a voltage divider that is intended to provide a nearly constant voltage at the base of the transistor (independent of transistor p). As we saw in Example 5.2, constant base voltage results in nearly constant values of Ic and K^. Because the base is not directly connected to the supply or ground in the four-resistor bias circuit, it is possible to couple an ac signal to the base through a coupling capacitor.

The circuit can be analyzed as follows. First, the circuit is redrawn as shown in Fig. 5.20b. Two separate voltage supplies are shown as an aid in the analysis to follow, but otherwise the circuits in part (a) and (b) of the figure are identical Next, we find the Thevenin equivalent for the circuit to die le t of the dashed line in Fig. 5.20b. The Thevenin resistance Rfl is the parallel combination of R, and R2 given by

RIM R^1^T2 <5-2 , )

The Thevenin voltage is R2 Vn = V, 'B CC (5.22)

The circuit with the Thevenin replacement is shown in Fig. 5.20c. Finally, its active-region large-signal model as shown in Fig. 5.20d replaces die transistor.

Now we can write a voltage equation around the base loop of Fig. 5.20d, resulting in VB = RBIB + VBE + REIE (5.23) Of course, for low-power silicon transistors at room temperature, we have KB£s0.7V. Now we can substitute /£«=(l+0)/a and solve to find that

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VB-VBE

''-Ri+Q+fiR, ( 5 2 4 )

Once IB is known, IE and Ic can be easily found. Then we can write a voltage equation around the collector loop of Fig. 5.20d and solve for V^. This yields VCE = VCC ~ Wc ~ &Eh (5-25)

« (b)

0 7 V '|/£=(P+i)4

rcc

(c) (d) Figure 5.20 Four-resistor bias circuit (a), equivalent circuit show lg separate voltage sources for base and

collector circuits (b), circuit using Thevenin's equivalent for Vcc, R/ and R2 (c), equivalent to part (c) with active-region transistor model (d).

Exercise 5.12 Find the values of Ic and V^ in the circuit of Fig. 5.20a for (a) /fc=100 and (b) y9=300. Assume that Vg^O.TV and that the circuit elements take on the following values of R,=10kQ, R,=5kQ, R ^ l k Q , RE=lkfi, FCC=15V. Ans. (a) Jc=4.12mA, VCE=6.12V, (b) 7c=4.24mA, VCE=6.5\V.

Exercise 5.13 Repeat Exercise 5.12 for R,=100kQ and R2=50kQ. Compute the ratio of Ic for

/?=300 to Ic for /fc=100 and compare to the ratio of the currents found in Exercise 5.12. Ans. The ratio of the collector currents is 1.21. On the other hand, in the previous exercise, the ratio of the collector currents is only 1.029. Larger values of Rl and R2 lead to larger changes in Ic

with changes in f3.

We "often use the four-resistor circuit of Fig. 5.20a for biasing BJTs in discrete-component amplifiers. Now we consider the design of this type of bias circuit The principal problem of bias circuit design is to achieve nearly identical operating points for the BJTs even though P may vary by a factor of 3 or

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Analog Electronics / BJT Circuits

more units. Furthermore, some circuits are required to function over a wide range of temperature, which can cause significant variations in fi and VBE.

Notice that Ic and V^ are nearly independent of fi in the circuit of Fig. 5.20a and Exercise 5.12. This is achieved by selecting values for R, and R2 that provide a nearly constant voltage to the base. As the values of R, and R2 become larger, the Q-point exhibits larger changes with /?. Comparing the results of Exercise 5.13 with those of Exercise 5.12 can see .this.

For the voltage divider to provide a nearly constant base voltage for different values of base current, the resistors R, and R2 should be small in value. However, this leads to large currents, possible overheating, and the need for a larger, more expensive power supply. Moreover, the ac impedance seen at the base decreases with the decrease of the values of the resistors R, and R2, which is undesirable in some applications. Thus we also wish to make R, and R2 as large in value as possible. As a general rule, a good compromise is to choose R2 so that the current through it is 10 to 20 times the largest base current expected.

Equation (5.24) shows that the base current is proportional to the difference between VB and VBE. Recall that VBE decreases in value by about 2mV/K as temperature increases. Furthermore, resistor tolerances cause VB to vary. If we design so that the difference between KB and VBE is very small, these variations could result in troublesome changes in the jg-point. Therefore, we should design so that VB is much larger than the changes expected in VBE due to temperature variation and the changes in VB due to resistor tolerances.

Often, we choose VB to be one-third of the supply voltage, which is usually large enough to ensure a sufficiently stable jg-point. Usually, VB is much larger than VBE, so that the drop across RE is approximately equal to VB. A rule in common use is to design so that one-third of the supply voltage is dropped across R^ one-third across the transistor (P^g) and one-third across RE.

Consideration of the frequency response, peak signal swing, available component values and various other matters place constraints on the j2-point and the selection of resistor values to be used in the bias circxiit. Thus the design of the bias circuit is intertwined with the ac performance of an i iplifier. We consider more aspects of bias design later in conjunction with amplifier performance.

Figure 5.21 Circuit for Example 5.3

Example 5.3 Suppose that considerations of the frequency response of an amplifier have dictated that the j2-point of the transistor should be at Ic = 2mA and that R^ = 4.7kQ. The supply voltage is Vcc = 25V. The transistor to be used has /? ranging from 100 to 300. Design a four-resistor bias circuit for this amplifier. Use standard 5%-tolerance resistor values.

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Solution The diagram of the circuit to be designed is shown in Fig. 5.21. The drop across R^ is Vc- IcRc= 9.4V. This leaves 25 - 9.4 = 15.6V to be allocated between V^ and the drop across

RE-

Suppose that we choose V^ = 10V leaving 5.6V across Rg. Then, since IE = Ia we have RE = VE/IB = 2.8kQ. However, the closest nominal value is RE = 2.7kQ, so that is our choice. (See Appendix A for nominal 5%-tolerance resistor values.) Next, we compute the base voltage VB = VBE + VE = 0.7 + 5.6 = 6.3V. The base current is IB = Zc/p. Since we want the maximum base current to be much less than I2 (so that VB does not change excessively when IB changes due to variations in j$), we use the minimum p. Thus IBmax. — Jc/P = 20|oA. Then using the rule of thumb that I2 should be 10 times the maximum base current, we have I2 = 0.2mA. Now, R2 = VB/I2 = (6.3V)/(0.2mA) = 31.5kQ, so we choose R2 = 33kQ, which is a standard value. Next, we see that I, = IB + I2 = 0.22mA and V, = Vcc - VB = 18.7V. Finally, R, = V,/I, = 85kQ, so we choose a close nominal value of R, = 91kQ. (We could just as well have chosen R, = 82k£l) Thus our design calls for R^ = 2.7kn, R, = 91kfi, R2 = 33kQ and R^ = 4.7kQ. Of course, many other choices could have been made in the design, resulting in different but equally useful values. Usually, there are many rijjfrt answers to the design problems.

Exercise 5.14 Analyze the circuit designed in Example 5.3 to find the jg-point values of Ic and Vcg that actually result with the nominal resistor values for (a) p=100; (b) P=300. Ans. (a) Ic = 2.00mA, VCE = 10.1V; (b) Ic = 2.13mA, V^ = 9.22V.

Exercise 5.15 In the four-resistor bias network, does Ic decrease, increase or stay the same for a (small) increase in the value of (a) R , (bJRg, (c) R„ (d) R , (e) P?

Exercise 5.16 In the four-resistor bias network, does K^ decrease, increase or stay the same for a (small) increase in the value of (a) R& (tyRg, (c) R„ (d) R , (e) P?

Exercise 5.17 Find the maximum and minimum values of Ic and V^ for the circuit designed in Example 5.3. {Hint: Consider the combination of P and values of resistors within ±5% of the nominal values.) Ans. Icmn. = 2.43mA, i ^ , = 1.77mA, VcEmax ~

1 2 . 1 ^ 1 ^ , = 6.76V. Exercise 5.18 Suppose that Vcc = 20V, R^ = lkQ and a j2-point of Ic = 5mA is desired. The transistor has P ranging from 50 to 150. Design a suitable bias circuit. Use standard 5%-tolerance resistor values.

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5.7 Small-Signal Equivalent Circuits

Now we turn our attention to small-signal currents and voltages in circuits containing BJTs. First we establish the notation used in amplifier circuits. We denote total currents and voltages by lowercase symbols with uppercase subscripts. Thus iB(t) is the total base current as a function of time.

The Q-point currents and voltages are denoted by uppercase symbols with uppercase subscripts. Thus IB is the dc base current if the input signal is set to zero.

Finally we denote the' changes in currents and voltages from the Q-point (due to the input signal being amplified) by lowercase symbols with lowercase subscripts. Thus it(/) denotes the signal component of the base current. Since the total base current is the sum of the Q-point value and die signal component we can write

iB® = h + M (5-26) Similarly

• t a W ^ r e + ^O) , ( 5 - 2 7 ) The Q-point is established by the bias circuit as discussed in the previous section. Now we consider how the small signal components are related to each other in the BJT. The total base current is given in terms of the total base-to-emitter voltage by (5.8), repeated here for convenience

iB = (1 - ayigs e x p ( ^ ) - l (5.28)

We are concerned with operation in the active region for which the 1 inside the bracket is negligible and can be dropped. Substituting (5.26) and (5.27) into the modified (5.28) one obtains

h + O = ( 1 " "VES e*P[VBE tVbeit)) (5-29) VT

This can be written as

IB + ib(l) = (1 - aVus e x t f ^ e x p O ^ )

, ^ < \ T T ( 5 - M )

= h e x p ( - r — )

We are interested in small signals for which PBE is much smaller than VT at all times, | pfc | « VT. On the other hand, for small x, exp(xr) = 1 + x. Thus (5.30) can be written as

/ . + 4 » - / . + ^ f f l (5.31)

If we cancel IB from both sides and define rx — Vr / IB, we have

W O - ^ (5-32)

Thus for small-signal variation around the Q-point, the base-emitter junction of the bipolar

transistor appears to be a resistance r* Using the relationship IB = Ic/($, we have an alternative

formula for rn

pvT r7c=-r- (5-33)

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At room temperature, K^=26mV. A typical value of f$ is 100 and a typical bias current for a small-signal amplifier is lc - 1mA. These values yield rn - 2600Q.

It is easy to show that the signal component of the collector current is given as »C(0 = A,(0 ' (5.34) Equations (5.32) and (5.34) relate the small-signal currents and voltages in a BJT. They lead to a small-signal equivalent circuit of the BJT shown in Fig. 5.22a. This circuit is very useful in the analysis of the BJT amplifier circuits. It turns out that the pnp transistor has exactly the same equivalent circuit as the npn - even the reference directions for the signal currents and voltages are the same. The resistance r„ is given by (5.33) for both transistor types.

An alternative small-signal equivalent circuit is shown in Fig. 5.22b. Instead of the current-controlled current source it uses a voltage-controlled current source to describe the signal component of the collector current »c(0 = ft»vte(0 (5.35) The coefficient g, is called the transconductance of the BJT, defined as

d( 8m

&>BE VT (5.36)

Q- point Which one of the circuits shown in Fig. 5.22 is used for circuit analysis is the matter of convenience.

Figure 5.22 Small-signal equivalent circuit for the BJT

5.8 The Common-Emitter Amplifier

In a BJT amplifier circuit, the power supply biases the transistor at an operating point in the active region for which amplification can take place. For example, we can use the four-resistor bias circuit discussed in Section 5.6. Coupling capacitors are used to connect the load and the signal source without affecting the bias point.

We can analyze amplifier circuits to find gain, input resistance and output resistance by use of the small-signal equivalent circuit. In this section, and the next we illustrate this procedure for two important amplifier circuits.

Fig. 5.23a shows the circuit diagram of a common-emitter amplifier. The resistors R,, R2, RE

and R^ form the four-resistor biasing network. The capacitor C, couples the signal source to the base of the transistor, and JC2 couples the amplified signal at the collector to the load RL. The capacitor CE is called the bypass capacitor. It provides a low-impedance connection between the emitter and ground, for ac.

The coupling and bypass capacitors are chosen large enough so that they have very low ac impedance at the signal frequencies. For simplicity, in our initial small-signal ac analysis, we treat

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the capacitors as short circuits. However, at sufficiendy low frequencies, the capacitors reduce the gain of the amplifier, because their impedance increases in magnitude with decreasing signal frequency.

Vc VC

(a) Actual circuit

'*> B

(b) Small-signal ac equivalent circuit

'b=0 B

Source "turned off ^ M J

(c) Equivalent circuit to find Z0

Figure 5.23 Common-emitter amplifier

Because the bypass capacitor grounds the emitter for ac signals, the emitter terminal is common to the input source and to the load. This is the origin of the name common-emitter-amplifier.

The analysis we give here is valid for the midband region of frequency. In the low-frequency region, the effects of the coupling and bypass capacitors must be considered. In the high-frequency region, a more complex transistor model must be used that includes the frequene limitations of the transistor. We treat this high-frequency response later in this chapter.

Before we analyze the amplifier, it is very helpful to draw its small-signal equivalent circuit. This is shown in Fig. 5.23b. The coupling capacitors have been replaced by short circuits and the transistor has been replaced by its small-signal equivalent.

The dc power supply is replaced by a short circuit. This is appropriate because it has zero internal resistance, so no ac voltage can appear on it.

Carefully compare the actual circuit of Fig. 5.23a with the small-signal ac equivalent shown in Fig. 5.23b. Notice that the signal source is connected directly to the base terminal because C, has been treated as a short circuit. Similarly, the emitter is connected direcdy to the ground and the load is connected to the collector.

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Notice that the top terminal of R, connects to the supply in the original circuit, but R, is connected from base to ground in the equivalent circuit, because the power-supply voltage source is treated as a short circuit to ground for ac signals. Notice also that R, ends up in parallel with R . Similarly, R^ and RL are in parallel. We find it convenient to define RB as the parallel combination of R, and R2

Similarly, R^' is a parallel combination of B^ and RL

R'L = - ^ \ - (5-38)

To find the voltage gain v0/v/ of the amplifier, first we note that the input voltage is equal to the

voltage across r„, given by v, = v ^ = rKib (5.39) The output voltage is produced by the collector current flowing through Rj /

vo=-RL0ib (5.40) The minus sign is necessary because of the reference directions for the current and voltage - the current flows out the positive voltage reference. Dividing (5.40) by (5.39) gives the voltage gain

V Rr A = - ^ = - / * — (5-41)

V- r vi 'it

Notice that the gain is negative showing that the common-emitter amplifier is inverting. The gain magnitude can be quite large - several hundred is not unusual. The expression for gain given in (5.41) is the gain with the load connected. We found the open-circuit voltage gain useful to characterize amplifiers in Chapter 2. With RL replaced by an open circuit, the voltage gain becomes

Avo=-/3^ (5.42)

Another important amplifier specification is the input impedance, which in this case can be obtained by inspection of the equivalent circuit. The input impedance is the impedance seen looking into the amplifier-input terminals. For the equivalent circuit of Fig. 5.23b, it is a parallel combination of RB and rn.

Z , = ^ = - ^ - (5.43) ', Rli+rx

In this case the input impedance is a pure resistance. Therefore we can find the impedance by dividing the instantaneous voltage f, by the instantaneous current if Of course, if there were capacitances or inductances in the equivalent circuit, it would be necessary to obtain the impedance as the ratio of the phasor voltage and the phasor current.

The current gain Aj can be found by use of Equation (2.3). With some changes in notation, the equation is

4-'-?- = 4%- (5.44) • li RL

The power gain G of the amplifier is the product of the current gain and the voltage gain (assuming that the input and load impedance are pure resistive).

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G = AjAv (5.45)

The output impedance is the impedance seen looking back from the load terminals with the source voltage vs set to zero. This situation is shown in Fig. 5.23c. With vs set to zero, there is no driving source for the base circuit, so ib is zero. Therefore, the controlled source P/4 produces zero current and appears as an open circuit. Thus the impedance seen from the output terminals is simply Rc. Z0 = Rc (5.46)

Exercise 5.19 Find Av, Avo, Zn, A\, G, and Z0 for the amplifier shown in Fig. 5.23a with Rs = 500Q, Ri=10kQ, R2=5kQ, RE=lkO, Rc=lkQ, RL=2kft, (3=100, VBE=0.TV, VCC = 15V. If f,(/)=0.001sin(<at), find and sketch p,(t) versus time. Ans. Av=-106, ^4vo=-158, Zm=53lQ, A>=-28.1, G=2980, Z0=lkQ, fo=-54.6sin((0t) mV.

Exercise 5.20 Repeat Exercise 5.19 if P = 300. (Hint: do not forget that the Q-point changes slighdy when beta changes.) Ans. Av=-\09, v4vo=-164, Z,= 1185Q, Ai=-64.5, G=7030, Z c=lkQ, vo=-16Jsin((0t) mV.

5.9 The Emitter Follower

The circuit diagram of another type of BJT amplifier called an emitter follower is shown in Fig. 5.24a. The resistors Rf, R2 and RE form the biasing circuit. The collector resistance is not present in diis circuit. Thus we have a four-resistor biasing circuit with R(- = 0. The input signal is applied to this circuit through the coupling capacitor C,. The output signal is coupled from the emitter to the load by the coupling capacitor C2.

Vc VC

(b) Small-signal equivalent circuit

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(c) Equivalent circuit used to find output impedance Z„. Figure 5.24 Emitter follower

The ac equivalent circuit is shown in Fig. 5.24b. As before, we replace the capacitors and power supply with short circuits. The transistor is replaced by its small-signal equivalent.

Notice that as a result, the collector terminal is connected directly to ground in the equivalent circuit. The transistor equivalent circuit is oriented with the collector at the bottom in Fig. 5.24b, but it is electrically the same as the transistor equivalent circuit we have used before. Because the collector is connected direcdy to ground, this circuit is sometimes called a common-collector amplifier.

The ability to-draw the small-signal equivalents for BJT circuits is an important skill for the electronic-circuit designer. Carefully compare the small-signal equivalent in Fig. 5.24b to the original circuit. Better still; try to draw the small-signal equivalent circuit on your own starting from the original circuit.

Notice that R, and R2 are in parallel in the equivalent circuit. We denote the combination by RB. Also, RE and RL are in parallel and we denote the combination by RL'. In equation form we have

A 1 A ?

(5.47) RB~RI+R,

and

Rr = RrR ERL

RE+RL (5.48)

Next we find the voltage gain of the emitter follower. The current flowing through RL' is 4+Pv Thus the output voltage is given by

v0=RL(\ + {3)ib (5.49)

Writing the voltage equation from the input terminals through r„ and then through the load to ground, we have

Vi=Vb+RL(l + /B)tb (5.50)

Division of (5.49) by (5.50) results in

A- = (5.51) rK + RL{\ + P)

The voltage gain of the emitter follower is less than unity because the denominator of the expression is larger than the numerator. However, the voltage gain is usually only slighdy less dian unity. An amplifier widi voltage gain less than unity can sometimes be useful because it can have a large current gain.

Also, notice that the voltage gain is positive. In odier words, the emitter follower is noninverting. Thus if the input voltage changes, the output at the emitter changes by almost the same amount

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and in the same direction as the input The output voltage follows the input voltage. This is the reason for the name emitter follower.

The input impedance Zi can be found as the parallel combination of Rg and the input impedance seen looking into the base of the transistor, which is indicated as Z« in Fig. 5.24b. Thus we can write _ RaZu

The input impedance looking into the base can be found by dividing both sides of (5.50) by ib.

Zit=T- = rx+BLL(\ + P) (5.53) lb

The input impedance of the emitter follower is relatively high compared to other BJT amplifier configurations. However, if very high input impedance is needed, we often have to resort to more complex amplifiers using feedback. We consider this approach later. We have already seen that field-effect transistors are capable of providing much higher input impedance than BJTs.

Once we have found the voltage gain and input impedance of the emitter follower, the current gain and power gain can be determined by use of (2.3) and (2.5).

The output impedance of an amplifier is the Thevenin impedance seen from the output terminals. To find the output impedance of the emitter follower, we remove the load resistance, put the signal source to zero, and look back into the output terminals of the equivalent circuit. This is shown in Fig. 5.24c. We have attached a test source vx that delivers a current ix to the impedance we want to find. The output impedance is given by

Zo=T (5-54) lx

(here again, the impedance can be expressed as the ratio of instantaneous time-varying quantities because the circuit is purely resistive. Otherwise, we should use phasors.)

To find this ratio, we write equations involving vx and ix. For example, summing current at the top of J? cr, we have

ib+flb+ix-jfe (5-55) We must eliminate ib from this equation before we can find the desired expression for the output impedance. We do not want any circuit variables such as ih in the result - only transistor parameters and resistor values. Thus we need to write another circuit equation.

First, we denote the parallel combination of R„ R, and R2 as i R*RR

Rs = „ ' „ (5.56)

The additional equation needed can now be obtained by applying Kirchhoff s voltage law to the

loop consisting of v^ rx and R/.

vx+r„ib+Rsib=0 (5.57)

If we solve Equation (5.57) for th substitute into (5.55) and rearrange the result, we obtain the output impedance.

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vx 1 Zo~ f ~ \+p 1 (5-58)

*s+*K RE This can be recognized as the parallel combination of R^ and the impedance

vx Rs+ r-z«=tr^t (559> It can be shown that Zot is the impedance seen looking into the emitter of the transistor, as indicated in Fig. 5.24c. The output impedance of the emitter follower tends to be smaller than that of other BJT amplifier configurations.

Exercise 5.21 Compute the voltage gain, input impedance, current gain, power gain and output impedance of the emitter-follower amplifier shown in Fig. 5.24a. Assume R, = lOkft, R, = lOOkO, R2=100kQ, RE=2kQ, Ri=lkQ, B=200, KBE=0.7V, VCc=20V. Verify the results using PSpice. Ans. ^4V=0.991, Zj=36.5kn, Z0=46.6Q, 4=36.2, G=35.8

In general, the output impedance of the emitter follower is much lower and the input impedance is much higher than those, of other single-stage BJT amplifiers. Thus we can use an emitter follower if high input impedance and low output impedance is needed.

Notice that even though the emitter follower gain is less than unity, the current gain is large. Thus die output power is larger than the input power and the circuit is effective as an amplifier.

If the emitter follower is cascaded with common-emitter stages, amplifiers with many useful combinations of parameters are possible. Furthermore, there are several other useful amplifier configurations using the BJT. Later we study additional circuit configurations and consider the design of multistage amplifiers.

Exercise 5.22. Repeat Exercise 5.21 widi P=300. Compare the results. Verify the results using PSpice. Ans.y4v=0.991, Zi=40.1kQ, Zo=33.2Q, 4=39.7, G=39.4.

5.10 Review of Small-Signal Equivalent-Circuit Analysis

Before we leave the important topic of small-signal equivalent-circuit analysis, we review die technique and provide a few useful observations.

The first step in analysis is to draw die small-signal equivalent circuit by making the following changes to the original circuit:

1) Replace the dc power-supply voltage sources by short circuits. 2) Sometimes we may encounter dc current sources. Replace these by open circuits. This is

appropriate because dc current sources force a constant current with no ac component to flow.

3) If a midband analysis is desired, replace the coupling and bypass capacitors with short circuits. However, if we want to find expressions for gain or impedance as a function of frequency or perform a transient analysis, the capacitors should be included in the equivalent circuit (and we should use phasors to represent currents and voltages in the ac analysis).

4) Sometimes we use inductors to provide a dc connection, but the inductance is picked large enough so that it has very high impedance for the ac signal. (Usually, this technique is practical

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only in circuits intended to operate at high frequencies.) Replace such inductors by open circuits in the small-signal equivalent

5) Replace the transistor with its equivalent circuit If the circuit has several transistors, use subscripts to distinguish the currents and parameters of different transistors.

It pays to be careful in drawing the equivalent circuit; analysis of an incorrect circuit is time and effort wasted. Double-check your circuit before writing equations.

Once the small-signal equivalent circuit is finished, we turn our attention to finding expressions for the gains and impedance of interest First, identify the pertinent currents and voltages and label them on the equivalent circuit For example, in finding the voltage gain, the pertinent variables are the input voltage vt and the output voltage tt>. On the other hand, for the input impedance, we are concerned with vt and the current if

The output resistance is the Thevenin resistance of the amplifier. To find the output resistance, we remove the load, turn off independent signal sources and look back into the output terminals to find the resistance. Turning off the independent signal sources means replacing voltage sources with short circuits and current sources with open circuits. Dependent sources, such as me controlled current source of the transistor equivalent, are not turned off - the controlled source models the effect of the transistor.

Often, it is convenient to attach a test voltage vx to the output terminals as we did in Fig. 5.24c to find the output resistance of the emitter follower. Then the output resistance is the ratio of vx and

After drawing the small-signal equivalent circuit and identifying the pertinent current and voltage variables, we use circuit analysis to write equations. Then we use substitutions to eliminate the unwanted currents and voltages until we have an equation relating the two variables of interest Make sure that the equations are not dependent. Otherwise, substitution results in cancellation of all terms, so that you have 0=0 that indicates you must return to writing additional circuit equations.

After we have found expressions for the gain or impedance, it is a good_idea to check to see that me units of the expression are correct Voltage or current gain should be. unitless. Input or output impedance should have units of ohm. In case the units do not check as expected, we should look for errors in writing the original equations or for algebraic errors.

Small-signal equivalent circuit analysis is not as troublesome as it might seem from this discussion. We have tried to mention all of the common problems encountered with this technique so that you will not waste too much time if they come up. Many useful results can be obtained with ease by the use of small-signal equivalent circuit analysis.

Possibly the thought process and viewpoints gained from the small-signal analysis technique are just as important as the expressions that we derive using them. After all, if we only wanted the formulas, we could resort to using a handbook. It is the understanding of the circuits obtained that makes the technique so important

Example 5.4 A variation of the common-emitter amplifier is shown in Fig. 5.25a. Draw die small-signal equivalent circuit and derive an expression for the voltage gain.

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Figure J3.25 Variation of the common-emitter amplifier (a), and its small-signal equivalent circuit (b)

Solution The small-signal equivalent circuit is shown in Fig. 5.25b. For convenience, we denote the parallel combination of R^ and RL by RL'. To find voltage gain, we must write equations involving t>, and v0. However, we find it necessary to involve 4, iy and L in the equations. We can write

v , = W (5-60)

because t>; is the voltage across rn. Summing currents at the collector node we have

if=j3ib+iy (5.61)

The output voltage is

v0 = RLiy (5.62)

Summing voltages around the outside of the circuit yields the fourth equation

Vi = RBif+v0 (5.63)

Equations (5.60) through (5.63) are the set we use to find the voltage gain. Before doing algebra, we check to be sure that enough equations have been written. The variables ih i, and i must be eliminated. Since a final equation relating t>( to v0 must result, a total of four equations is needed, and that is exactly the number we have written. Next, we proceed to eliminate the unwanted variables. First, we can solve Equation (5.60) for ib

and substitute into the other equations to obtain the set

If = + h, ' K

V0 = Rtfy

Vi = RBif+vo The first equation in the last set can be used to substitute for ifi resulting in the equation set

v0 = RLiy

vt=Ri ^ + i 1 + v i-ly +V0 \r*

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Then we solve the first equation in this set for ip substitute into the second equation and use algebra to form the ratio of v0 and t>,

v, r„(RL+RB) Next, we check to make it sure that our expression is unitless, as it should be for the voltage gain.

The check is satisfied. (Recall that P is unidess and rK has the units of resistance.)

Exercise 5.23 Derive the expressions for the input resistance and output resistance for the circuit of Fig. 5.25a.

Ans. Ri = RB+RL ~r, RQ-

RcRpt

where Rot =

rn+*B +(l + P)RL " *c + Rot RBRS + RBrn + Rsra

(\ + P)Rs+r„

Exercise 5.24 The circuit shown in Fig. 5.26 is known as a common-base amplifier. Derive expressions for the voltage gain, input resistance and the output resistance in terms of P, rx and die resistor values.

Ans. Ay=p-}<- where RL= ^ R, = R^/(I + J3), R0=RC.

Figure 5.26 Common-base amplifier circuit

Exercise 5.25 Evaluate the expressions found in Exercise 5.24 if R»= 100ft, RE=5kft, R2=50kft, Ri=100kft, Rc=5kQ, RL=lkft, Vcc=15V, KflE=0.7V and P=100. Find the output voltage if v,=sin(fi)t)mV. Also evaluate the current and power gain. Ans. Jc=0.799mA, r,r= 3254ft, A =25.6, R,=32ft, Ro=5kQ, %(/)=6.21sin(a>t)mV,yl^0.819, G=21.

Exercise 5.26. Draw the small-signal equivalent circuits for the circuits shown in Fig. 5.27.

vc vc

(a) Common-emitter amplifier widi unbypassed emitter resistor

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5.11 The Common-Emitter Hybrid-Parameter Small-Signal Model

Another small-signal model for the BJT is shown in Figure 5.28. It is based on a set of two-port circuit parameters, known as hybrid parameters.

Figure 5.28 Common-emitter A-parameter small-signal equivalent circuit

This equivalent circuit is completely general for small-signal conditions. Given the proper values of the four parameters, the ^-parameter model accounts for all the second-order effects in the device. (This is, however, a linear model that does not account for nonlinear effects.) If the parameters are allowed to be complex-valued functions of frequency, the model is valid for all frequencies! However, the model parameters are related to the internal device physics in complex ways, so their variation with frequency is not easy to understand. Consequendy, other models that are more easily related to the device physics are usually used for high-frequency analysis as will be seen in the following section.

In tdrms of die ^-parameters, the small-signal currents and voltages are related by

ne=hieib+Kevce (5-64)

ic=hfeib+hoevce (5-65)

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Notice that hk has the units of resistance, bn and b^ are unitless, and h„ is a conductance.

Starting from Equations (5.64) and (5.65), we can express each parameter as a partial derivative, evaluated at the operating point. For example, if we set ik — 0 in Equation (5.64) and solve for h^ we have

hro = vbe vce

Avj £

ib=0 AVCE (5.66)

Thus we can find the value of h„ by making a small change in v with /fl held constant, and taking die ratio of the resulting change in PBE and p^. In other words, h„ is the partial derivative of vBE

vidi respect to v^.

Expressions for the other three ^-parameters similar to Equation (5.66) can be found. These expressions can be used to determine low-frequency values for the A-parameters for the static characteristics. (This is similar to the procedure we used to determine low-frequency values for the FET in the previous chapter.) It is important to understand that parameter values found from the static characteristics of a device are valid only for low-frequency operation. The characteristics do not account for capacitances.

-OE Figure 5.29 The A-parameter equivalent circuit with h„ =0 and hK = 0.

The parameter hn accounts for the effect of base-width modulation on the input characteristic of die device. Typically, its value is very small. Similarly, hx is a small conductance that accounts for die upward slope of the output characteristics, which is also caused by base-width modulation. As an approximation, we can set bn and hK to zero. (Since hK is a conductance, setting it to zero causes it to become an open circuit.) With these changes, the ^-parameter equivalent circuit reduces to the circuit shown in Figure 5.29. Except for different labeling of the parameters this is the same as the equivalent circuit of Figure 5.22. Thus we have K=*K (5-67) and hfoSfi (5.68)

We do not intend to make much use of the complete A-parameter circuit in the design or analysis. However, data sheets sometimes contain information about the ^-parameters. We have included this discussion primarily so that you will be familiar with thes> parameters when you encounter them in the literature or on data sheets.

5.12 The Hybrid-* Model

A small-signal equivalent circuit for the BJT known as the hybrid-Tt is shown in Figure 5.30. This model is motivated by the internal physics of the device. It includes charge storage effects and is useful over a wide range of frequencies. The resistance rh called die base-spreading resistance, accounts for the ohmic resistance of the base region. Typically, it is small compared to rx, ranging from 10 to 100 Q for small-signal devices. Its vale is nearly independent of the operating point.

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digit

Tekst maszynowy


The resistance rK represents the dynamic resistance of the base-emitter junction as seen from the "internal" base terminal. It is the same as the rK shown in Figure 5.22 and its value is given by Equation (5.33). The resistance rM accounts for the effects of base-width modulation on the input characteristic. In other words, rM represents feedback from the collector to the base. In this sense, it plays virtually the same role that b„ plays in the / -parameter equivalent circuit The following approximate formula relates these parameters:

Ke=—— = — (5-69)

The value of rM is very large - several megaohms is typical. For simplicity, we often replace it by an open circuit At high frequencies, this is justified even further because rM is shunted by the much lower impedance of Cf,.

OE Figure 5.30 Hybrid-7i equivalent circuit

The resistance r, accounts approximately for the upward slope of the output characteristics of die transistor. Thus it plays approximately the same role as hm of the ^parameter equivalent circuit. We can write

r0=T- (5.70) "oe

Sometimes, to simplify analysis, we replace ra by an open circuit

The capacitance CM is the depletion capacitance of the base-collector junction. Its value depends on the dc base-collector voltage V^ and the device type. Values are often given on data sheets as Cobo or CVt. For example, the data sheet for the 2N2222A device lists Cbo value of 8 pF for V^ = -10V.

Sometimes the time constant of the RC circuit between the collector and base terminals is given on the data sheet For example, the data sheet for the 2N2222A gives the value labeled as rbCf

This time constant is approximately equal to r/7 . Assuming that CM is known, we can use the value given for the time constant to find rk.

The capacitance C„ accounts for the diffusion base capacitance and junction capacitance of the base-emitter junction. The value of CK depends on the jg-point and the transistor type. Values typically range from 10 to 1000 pF for small-signal devices.

Usually, data sheets do:not give values for CK directly. However, the transition frequency^ is often given. The transition frequency is related to hybrid-7t parameters by the approximate formula

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The controlled source gj>x shown in Figure 5.30 accounts for the amplification properties of the transistor. Using Equation (5.36) we can compute £, from knowledge of the j2-point (and temperature). It is easy to demonstrate diat for low frequencies and rk = 0, rM = oo and r0 = <», the hybrid-it small signal model reduces to the equivalent circuit of Figure 5.22, where

gnPn=&b (5-72) Solving for taking account of the fact that rK = »K/ih we have

8m = J- (5-73)

Example 5.5 Knowing from the data sheets for a typical 2N2222A transistor that bj, - P = 200, b„ = 4X10"4, bj, = 200, and bK= 15 - 200 yS, determine values for the hybrid-Tt equivalent circuit for a typical 2N2222A transistor at appoint of Ic = 10 mA and V^ = 10 V. Solution First, we use Equation (5.36) to compute the transconductance

Ir 10mA A „ , , „ g„ = — = = 0385S Sm VT 26mV We know mat bfi = p. Using Equation (5.32), we have

PVT 200x0.026 , r, = —~ = = 520fi * Ic 0.01

Equation (5.69) yields

M Ke 4 x l 0 ~ 4

The typical 2N2222A has rM somewhat higher than this. In any case, the value is so high that it has litde effect on the performance of most circuits. Almost certainly, the unit-to-unit variation in P will have a much larger effect. This is why we drop rM from the equivalent circuit to simplify analysis.

We can use Equation (5.70) to find a value for r0. The data sheets give a range from 15 to 200 mS. Thus, r0 ranges from 5 to 66.7 kQ. We take ro=20*O as a typical value.

For Va - 10 V and IE = 0, the data sheet gives a matimum value of Cobo= CM of 8 pF. This is the depletion capacitance of the collector junction and is nearly independent of emitter current The capacitance does depend on Va, but the j2-point given in the problem statement yields VCB =VCE -VBE =10K-0.6F = 9.4K which is very close to the data-sheet specification. As is often the case, no information is given concerning typical values of C+,. Thus we take the maximum value for use in the equivalent circuit CM=SpF

Next, we use the specification for the transition frequency fT to determine a value for C* According to the data sheet, the minimum value of fT is 300 MHz for V^ = 20 V and Ic = 20 mA. The transition frequency is a function of both V^ and Ia and the data sheet does not give data for the bias point given in the problem statement However, examination of the data published for other similar transistors indicate that^ should not vary by more than about 20%

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due to the difference inj2-points. Therefore, we u s e ^ = 300 MHz in computing a value for C^. Solving Equation (5.71) for CK and substituting values we find that

P 200 C* ~ 2»Sr/r

-C„=- %pF = \96pF 2 ^ x 5 2 0 x 3 0 0 x 1 0 '

Finally, the data sheet gives a maximum value for the collector-base time constant of 150 pF. Thus we have

/fcCy = 150xlO"1 2

Solving for rb and substituting the value found for CM, we have / i = 1 9 0 Thus we have used the value published in the data sheet to find values for the parameters of the hybrid-7t equivalent circuit The circuit and values are shown in Figure 5.31.

As you can see, determination of parameter values for a BJT model from the data sheet is not an exact science. Many parameter, such as E5, show large unit-to-unit variation. Since we must design circuits that work with all the devices of a given type, an exact model for a particular unit is not important. Often, we use the worst-case device specification in finding a device model. If our circuit design meets its goals with a range of device model parameters, including the worst case, we can be reasonably sure that it can be mass-produced with an acceptable rejection rate.

The hybrid-7i model is useful for die analysis of single- and multistage amplifiers in a wide frequency range. Slighdy modified, it is incorporated into the PSpice program to represent the BJT properties for ac analysis.

5.13 Bipolar Transistor Behavior at High Frequencies

The hybrid-7l model can be used to determine the transistor behavior at high frequencies. To derive the current gain p as a function of complex frequency s, a current source Ih(s) is connected between the base and emitter, and a short circuit is placed between the collector and emitter terminals, as shown in Figure 5.32. To simplify the analysis, the resistances ru and r, have been replaced by open circuits.

B rb B' „cu C

Figure 5 32 7 quivalent circuit used to derive die short-circuit current gain of die bipolar transistor as a function of frequency

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From the K.CL applied to the collector node, we have lc(s) = gmVA')-sCMV„{s)

i \ (5.74)

For sufficiently low frequencies (still being in the high frequency range) the following inequality can be fulfilled: &n»sCu, and accordingly Equation (5.74) can be simplified as follows Ic(s) = gmVx(s) (5.75) On die other hand, from the KVL applied to the input loop one can obtain the relationship between the base voltage and base current

Vx(s) = *„ „ s (5.76)

where &t=1/r& Substituting Equation (5.76) into (5.75) we obtain

ic(s)=—gm!i{s) „ x (5-77)

which allows us to derive expression for die short-circuit current gain

Multiplying numerator and denominator of Equation (5.78) by rK and making use of Equation (5.73) we have

" W - 1 W C . + C , ) «"*> where symbol /?, is used to denote low-frequency value of p. Putting s = j<D = j2rt/ and introducing the definition of the beta cutoff frequency

1

we obtain a single-pole approximation to P as a function of frequency

A /?(/)=

H The magnitude of P is equal to

Po Wi i+ V

2

fpj

(5.80)

(5.81)

(5.82)

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It follows from Equation (5.82) that the magnitude of the short-circuit common-emitter current gain P decreases with frequency. This is illustrated by Figure 5.33. At f—fp the gain magnitude is

lower by v 2 (or 3 dB) compared to its low-frequency value po. This gives an interpretation to the beta cutoff frequency defined by Equation (5.80).

The parameter^ as described by Equation (5.71) is the common-emitter transition frequency or unity-gain crossover frequency. In other words, fT is the frequency at which the magnitude of P is equal to unity. Putting

A |A/TO| =

1+ v2

\fpj

= 1 (5.83)

we obtain

# = i+ V 2 V 2

fp) \fp \jpj

where the value oifi was assume much bigger than^g. Finally, we have

(5.84)

(5.85)

The value oifT can be found in transistor data sheets. For example, minimum value oifT for the 2N2222A transistor is specified as being equal to 300 MHz. One has to remember that in fact for a real transistor | P(/^) | is usually larger than unity, due to the current flowing from the base to

collector terminals through capacitance CM, that was neglected under the assumption gm»sCfl. The parameter^- is thus used to describe the P frequency dependence for frequencies lower than fT, say foif<fT/\0. At larger frequencies, the single-pole approximation (5.79) is no longer valid. In these cases, another characteristic frequency^ is specified in transistor data books as the unity current gain frequency. This is shown in Figure 5.33. However, we will not take it into consideration when analyzing transistor amplifiers.

Example 5.5 Suppose the common-emitter amplifier in Fig. 5.23 employs a BC548C bipolar transistor. Compute the effective voltage gain and input impedance of the amplifier at high frequencies. Assume R, = 100 Q, R, = 68 kQ, R2 = 12 kQ, RE = 1.1 kQ, Re = 5.6 kft, RL = oo, Vcc = 12 V. Verify the results using PSpice. Solution. At high frequencies all the capacitances C„ Q , and CE may be replaced by respective short circuits. To simplify the matter further we substitute

Rl=Rs\\Rl\\R2=Rs (5-86)

RL = Rc || RL || r0 (5.87)

and draw the high-frequency equivalent circuit of the amplifier, as shown in Fig. 5.34.

Figure 5.34 Small-signal equivalent circuit of the common-emitter amplifier at medium and high frequencies

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It is easy to find in Fig. 5.23 that the dc base voltage is approximately equal to 1.8 V. Assuming I/B£=0.7 V, we calculate the dc emitter voltage VE - 1 V and the emitter current IE £ 1mA. For a typical, which is reasonably high, current gain f30 we may write

and VCE=VCC-RCIC-REIE=5AV

From the transistor data book one can find at Ic= 1 mA and V^ = 5 V:

fT = 130 MHz, p0 = b(e = 600, rQ = 1/A* = 25 kQ. Similarly,

vCB=Vcc-Rck-Vcc-^nr=4-6W-A] +K2

For this value of V^ one can find from the transistor data book:

CM=CC= 2.6 pF.

The transconductance can be calculated from Equation (5.36) to obtain gn = 38.5 mS. This can

be substituted to Equation (5.85) that can be solved for C„:

8m Q = 2nfT

•CM s44 .5pF .

Also from Equation (533) we have r„ S 15.6 kQ. The parameter rh is estimated from the collector-base time constant as rb= 25 £2.

To simplify the analysis, it is reasonable to apply the Miller theorem to the circuit of Fig. 5.34. For this purpose we note that A - Vol V„ S -#nR'L- From Equation (5.87), R'L = 4.6 kfi, then A s -177. Consequendy, Cm\ = 2.6x(l+177) s 462.8 pF and Cm2 = 2.6x178/177 = 2.6 pF. Now we can draw the simplified equivalent circuit for the common-emitter amplifier, where Ci = C^ + Cm] = 507.3 pF, C 2 = Cm2 = 2.6 pF. This circuit is shown in Fig. 5.35.

Figure 5.35 Simplified equivalent circuit of the common-emitter amplifier

The schematic diagram of Fig. 5.35 can be further simplified by using Thevenin's theorem to modify the input circuit, where

r„ + Rs+rb

and is equal to 124 Q in the present example, and

v's=vs

rn

Rs+rb+r* The resulting final equivalent circuit is shown in Fig. 5.36.

(5.88)

(5.89)

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For the circuit of Fig. 5.36 we have

V1

V - s

1 + JaX'sCi ( 5 9 0 )

-y rn * **j+'&+'* 1 + 7'®/®!

where ©j = l /(^Cj) s 15.9 Mrd/s, and

yo=-gmV^L7-^~r- (5.91)

where fi>2 = 1/(^1^2) = 83.6 Mrd/s. Combining Equations (5.90) and (5.91) we may write down the effective voltage gain of the common-emitter amplifier as:

A =YjL= -Po*l> 1 ! _ _ (5.92) ^s Vs Rs +1% + rx 1 + joaltox l + ja)/a>2 This is a transfer function of the type discussed in Section 2.6. Using Equation (2.60) and (2.61) we have 2.12 MHz <fH < 2.53 MHz (5.93)

Since a>,« Q)^ one can write an approximate expression

/ / / = ® 1 / ( 2 ^ ) = 1 / ( ^ C 1 ) (5.94) Since the gain A in the Miller equations is proportional to the load resistance, the capacitance C,

< •

increases with R^ . Then the upper cut-off frequency increases with the Ri decrease. The largest (

bandwidth is for Ri tending to zero:

On the other hand, it follows from Equation (5.88) that resistance Rs depends on the input

signal source resistance. It decreases with R, - • 0. Finally we note that the resistance rK = Ic/gn is t

typically much larger than the base resistance r¥ We conclude that in the limit of Ri -» 0 and Rs -> 0, the upper 3-dB frequency of the common-emitter amplifier is equal to the so-called transverse cutoff frequency

fb = (5.96) Jb 2nrb(C„+CM) This frequency determines the largest bandwiddi of a common-emitter amplifier without feedback. In the present example,_/J =135 MHz.

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Figure 5.37 Amplitude characteristics of the common-emitter amplifier for different load resistances

With the load resistance decreasing, as the bandwidth increases, the midband gain decreases. This follows from Equation (5.92) and is illustrated by Fig. 5.37, which is a result of PSpice simulation performed for the circuit of Fig. 5.35. A summary of PSpice results is presented in Table 5.1.

TABLE 5.1 MIDBAND GAIN AND UPPER 3-DB FREQUENCY

OF THE COMMON-EMITTER AMPLIFIER

Re kQ 5.6 1 0.1

Avso v/v 175 36.7 3.8 fH MHz 2.16 8.14 22.4

teak -. i.e» . i«» iee» ' "v- jJ*f o ttCttVlCg*)! » wtZZJ/MHiZ) a M « 2 V M B S 3 }

.:* frequency

i«o> - iee»i

Figure 5.38 Magnitude of common-emitter amplifier input impedance as a function of frequency

To find the input impedance dependence on frequency one can use the equivalent circuit in Fig. 5.35, namely

Zie=rb+: 'x (5.97) \ + j6)/a)j

where 0)j =\/(r7rC\). For low frequencies, the input impedance of the common-emitter

amplifier is equal to (r^ +rn) that is 15.7 kQ in our example. Zie decreases with frequency, and

-169


since the break frequency depends on the Miller capacitance Cu it depends also on amplifier load resistance. For high frequencies, the input impedance goes to rb. This property is sometimes used to measure the base resistance of bipolar transistors. The PSpice-simulated dependence of the magnitude of input impedance on frequency, for different load resistances is shown in Fig. 5.38.

Example 5.6 The common-base amplifier of Fig. 5.26 employs a BC548C bipolar transistor. Use PSpice to compute the effective voltage gain of the amplifier at high frequencies. Assume R, = 100 Q, R, = 68 kQ, R2 = 12 kQ, RE = 1.1 kQ, Re = 5.6 kQ, RL = oo, Vcc = 12 V. Solution. Since the^-point of the transistor is the same as calculated in Example 5.5, we can use the above-obtained values of equivalent circuit elements: rn = 15.6 kQ, ^ = 38.5 mS, CK — 44.5 pF, CM - 2.6 pF, rQ = 25 kQ, rh = 25 Q. The equivalent circuit of this amplifier is shown in Fig. 5.39.

Figure 5.39 Small-signal equivalent circuit of the common-base amplifier at medium and high frequencies

A PSpice simulation was performed for the circuit of Fig. 5.39. A summary of the simulation results is presented in Table 5.2.

TABLE 5.2 MIDBAND GAIN AND UPPER 3-DB FREQUENCY

OF THE COMMON-BASE AMPLIFIER

Re kQ 5.6 1 0.1 Avso v/v 41.5 7.7 0.78 fH MHz 9.13 42.4 113.4

Comparing the contents of Table 5.1 and 5.2, one can notice that the midband gain of the common-base amplifier is (for the same load resistance) lower than the gain of the common-emitter circuit. This is due to the fact that we compare the values of the effective voltage gain Avs =V0IVS that takes into account the input signal attenuation in the circuit made of Rs and R,,

The input resistance R, for the common-base circuit is much smaller than that of the common-emitter circuit. Indeed, in the discussed example R, = 31 Q and thus only V* of the signal

amplitude excites the amplifier. On the other hand, the gain Av = V0 I Vi is the same for both

amplifiers. For R^ = 5.6 kQ it is equal to 176 in Examples 5.5 and 5.6. Notice that the common-

base is a noninverting amplifier, unlike the common-emitter circuit.

The bandwidth of the common-base amplifier is much larger than the bandwidth of the common-emitter amplifier. This is also seen in' Tables 5.1 and 5.2. The properties of the

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common-emitter and common-base circuit resemble those of the common-source and common-gate amplifiers, respectively, discussed in Chapter 4. Main differences between them come from the generally lower transconductance in FETs.

Example 5.7 The common-collector amplifier of Fig. 5.24 employs a BC548C bipolar transistor. Use PSpice to compute the effective voltage gain and input impedance of the amplifier at high frequencies. Assume R, = 100 Q, R, = 68 kO, R2 = 12 kQ, RE = 1.1 kfi, RL = oo, Vcc = 12 V. Solution. The base-collector voltage VBC is larger in magnitude in this example as compared to Examples 5.5 and 5.6. To account for this difference, we have CM = 2.1 pF. The other elements take the previously determined values: r„ = 15.6 kQ, = 38.5 mS, Cn — 44.5 pF, r0 = 25 kQ, rb = 25 Q. The equivalent circuit of this amplifier is shown in Fig. 5.40, where it was assumed that Rs<<R, | | R2, for simplicity.

Figure 5.40 Small-signal equivalent circuit of the common-collector amplifier at medium and high frequencies

The PSpice ac simulation was performed for the circuit of Fig. 5.40. The midband gain of this amplifier is equal to 0.977. It is much closer to one than the gain of the common-drain amplifier considered in Exercise 4.13 (0.917), because of the much larger transconductance of the bipolar device (38.5 mS against 2.4 mS in the two examples discussed). The upper 3-dB frequency of the common-drain amplifier is fH = 548 MHz. This is a very large value; however, it should be mentioned that this value extends beyond the validity of the BJT hybrid-7C model. This model is valid approximately to / - /10 that is about 13 MHz in the present example. To investigate the high-frequency behavior of the common-drain amplifier, it is more appropriate to study the frequency dependence of the input and output impedances.

The input impedance of the common-collector amplifier is capacirive, mainly due to the capacitance CM present at the input (see Fig. 5.40). Then the magnitude \Zic\ decreases with frequency. This is shown in Fig. 5.41. Very high at low frequencies, this impedance is reduced twice in magnitude at 100 kHz in this example. (Larger values of the impedance break frequency, in order of several MHz, can be obtained by operating the BJT for larger transconductance.) One can conclude that the input impedance deteriorates much faster with increasing frequency than the voltage gain does for this amplifier. In the limit, for /-•oo, the input impedance goes to approximately rb, which is merely 25 Q in the discussed case.

- 1 7 1 -


Figure 5.41 Magnitude of the input impedance of the common-collector amplifier as a function of frequency

One can demonstrate by using analytical derivations applied to the circuit of Fig. 5.40 that its output impedance is inductive. Then, being very small at low frequencies, it increases in magnitude with the frequency increases. This behavior is illustrated by Fig. 5.41. Th output impedance has a small value of about 26 Q at low frequencies; however, its magnitude doubles at about 50 MHz.

Exercise 5.27. Consider the amplifier shown in Figure 5.43. Both transistors are of the same, 2N2222A, type. Assume Rs = 1 k«, J^ = 1.2 kQ, Re = 1.2 kQ, ^ = 10 kQ. Find device Q-points and transconductance. Draw the small-signal equivalent circuit valid for medium and high frequencies. Derive formula for the midband effective gain of this amplifier. Run .ac PSpice analysis to find the amplitude characteristic of the amplifier using the device model from EVAL.LIB library. Determine me effective gain and bandwidth of the whole cascode as well as gain and bandwidth of its Individual stages.

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5.14 Large-Signal Dynamic Model for the Bipolar Transistor

In Section 5.4 we presented simple large-signal dc models for the BJT in the various operating regions. These models are shown in Figure 5.14 and are appropriate for analysis of dc circuits. A nonlinear large-signal model for the BJT, known as the Ebera-Moll model is shown in Figure 5.44. This model is suitable for computer simulation of the transistor static behavior in all the regions of operation. The diodes DE and Dc model the base-emitter and base-collector junction, respectively. In parallel with each diode is a current-controlled current source, and the controlling current is the current in the other diode. This model is valid for low-frequency signals in all four operating regions.

B O

apiDE

ORiDC

Figure 5.44 Ebers-Moll static model

We have used subscripts to distinguish aF and aR. Previously, we have been concerned mainly

with the forward active region, and we used the symbol a instead of a P In equation form

c forward active region In a similar fashion, we have

lE

'C

(5.98)

(5.99) reverse active region

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We have used the = sign in Equations (5.98) and (5.99) because these expressions neglect the reverse leakage currents of DB and D0

Equation (5.9) gives (3 in terms of a. We can write similar equations for fip in terms of aFand for /?R in terms of aR. Thus we have

PF=-^— (5.100) \-aF

and

A-r£" (5 1 0 1) \-aR

Typical values for this parameters are a = aF = 0.99, 0 = fip - 100, aR = 0.5, fiR = 1. Let us consider die physical basis for dieses parameter values, assuming an npn device. Transistors are usually designed to be operated in die forward active region. Thus the doping of die emitter is much heavier dian that of die base. Furthermore, the collector junction has a relatively large area to collect the minority carriers (electrons) diffusing dirough die base. Moreover, due to nonuniform base doping^ there is an electric field "built-in" in die base which accelerates electrons toward die collector, reduces their transit time dirough me base and dius decreases die electron loss due recombination. These features ensure that almost all of the carriers crossing die emitter-base junction are swept into the collector. Thus in the forward active region, ic = iE, and aF is close to unity.

In die reverse active region, die base-collector junction is forward biased and die base-emitter junction is reverse-biased. The collector is not as heavily doped as die emitter is. Thus a significant fraction of the current crossing die collector-base junction is due to holes crossing from me base into die collector. Furthermore, the electrons mat are injected into die base region take longer to diffuse to die emitter junction. The emitter junction is smaller and it takes longer for die electrons to "find" the junction and be swept into the emitter. Consequently, more of die electrons recombine in die base. This is why iE is typically only half of ic in die reverse active region.

The currents in diodes Dc and DE of die Ebers-Moll model are given by the Schockley equation. Thus we have

4tY » D £ = / £ S e x p | ^ - ) - l (5.102)

and

'DC = / c s e x p ^ ^ | - l (5.103)

The collector current and emitter current are given by ic = aFiDE -ipc (5.104) and '£ = -<*RiDC + *DE (51°5) Of course, the base current is given by iB=iE-ic (5.106)

It can be shown diat die following relation holds ctflEs = aRIcs = / , (5.107)

-174-


where 7, is known as the device scale current, first introduced in Equation (5.5). Since aF = 1, we can write Is = IES (5-108) Therefore, these symbols are sometimes used interchangeably.

Figure 5.45 Dynamic BJT model

Base and Collector Resistance. All components in an integrated circuit are fabricated on a single piece of semiconductor material called the substrate. A consequence is that external connections to the base, emitter and collector are located at the top of the IC as shown in Fig. 5.1a. The transistor in this figure is a vertical transistor because current flows vertically through the active region beneath the emitter material. Three parasitic resistances are thus important in the planar bipolar transistor. The first, the base spreading resistance rh is the ohmic resistance of the base current path from the junction to the base contact at the surface. This parameter has been accounted for in the hybrid-n model of the transistor. It is important in high-current transistors and significantly influences amplifier frequency response. Next in importance is the ohmic resistance of the collector, rc. Because ND in the collector is relatively low to reduce base width modulation, the collector region has rather high resistivity. The result is a collector resistance of the order 10 - 100 Q that may cause internal transistor saturation due to the ic rc voltage drop on it A special highly conduction buried layer helps reduce rc. Of lesser importance than the other two is re, the ohmic resistance in the highly doped emitter material. A typical value is 1 CI. Figure 5.45 shows a large-signal transistor model, which comprises the Ebers-Moll model with parasitic resistances added.

Parasitic Capacitances. We know that diodes possess parasitic internal capacitances, nonlinear Q versus V relationships that are transparent to slow signals but important when rapid changes in voltage or current are imposed upon the device. Since the BJT contains two pn junctions, we expect it to have similar dynamic limitations. Associated with each junction are depletion and diffusion capacitances, which limit high frequency performance. In forward active region, depletion capacitance is dominant at the reverse-bias collector-base junction. At the forward-biased base-emitter junction, diffusion capacitance and depletion capacitances are both important

-175-


The transistor depletion capacitances are exactly those we described in diode theory. Thus the parameter values in Equation (3.40) and the capacitance characteristic within the transistor depend upon the individual junction grading and geometry.

The diffusion capacitance for a transistor differs slightly from that of an isolated diode because of the narrow base. For the forward active transistor, the minority charge concentration profile in the base is triangular as in Figure 5.46. This is because base width W is much smaller than the electron diffusion length, and because the electric field at the collector junction sweeps away electrons as fast as they arrive, pinning down the concentration at the collector end of the base to zero.

Emitter 0 Base W Collector

Figure 5.46 Excess minority charge stored in the base of a forward active npn transistor

For a base-emitter junction of cross-sectional area A, we use Figure 5.46 to calculate that the quantity of minority charge stored in the base is

QFA=qA~n[Q)W (5.109)

Diode theory tells us that the electron concentration at the emitter end of the base is controlled by the base-emitter junction voltage vBE

where Ncb is the concentrations of acceptor ions in the base material. Substituting Equation (5.110) into (5.109) gives the charge-voltage relationship that characterizes the diffusion capacitance of the forward-active transistor

QFA = qAW nf -fe) (5.111)

2 Nab yrT

This particular collection of stored charge represents electrons in transit from emitter to collector. On the average, these injected electrons take TF seconds to traverse the base, where TF

is called the forward transit time. For integrated npn transistors, the transit time is of the order of 1 ns, for integrated/>»p transistors TF = 30 ns. It can be shown that the forward transit time is related to the transition-frequency by

*'-WT ( 5- 1 , 2>

Similarly to the forward transit time, rR is the average time that a minority carrier spends in the base region for operation in the reverse active region. It can be shown that PFrF=PRrR (5.113)

Figure 5.45 introduces a dynamic BJT model. We recognize it as the Ebers-Moll model of Fig. 5.44 augmented by nonlinear diffusion (subscript d) and depletion (subscript J) capacitances. Each diffusion capacitance is a nonlinear Q versus V relation, which for the base-emitter diffusion capacitance takes the form of Equation (5.111). In amplifiers, these internal capacitances reduce

- 1 7 6 -


the high-frequency gain. In digital circuits, the capacitances introduce switching delays that will be considered in the following section.

SPICE Parameters for the BJT. Table 5.3 lists basic parameters required to model the static and dynamic behavior of the transistor using PSpice. It includes second-order effects, such as the Early effect and ohmic resistances. As shown in the table, the parameters fall into three groups. First are the parameters that model the static characteristics of the device (IS, BF, BR, RB, RC, RE, VAF). The second group of parameters models the depletion capacitances of the two junctions (CJC, MJC, VJC, CJE, MJE, VJE). These parameters are similar to those discussed in Section 3 for/w-junction diodes. The third group of parameters (TF, TR) models charge storage in the base region.

Tal Die 5.3 SPICE Model Parameters for the BJT*) Text

notation SPICE

notation Parameter name Typical

value Default value

I, IS Scale current 1E-14A 1.0E-16A

A BF Forward beta 100 100

A BR Reverse beta 1 1

h RB Ohmic base resistance 10 Q 0 rc RC Ohmic collector resistance \Cl 0

r, RE Ohmic emitter resistance 0.1 Q. 0

vA VAF Forward Early voltage 100 V QO

<=jc CJC B-C depletion capacitance

(zero bias) 10 pF 0

Mr MJC B-C junction grading factor 0.333 0.333

v.. VJC B-C built-in barrier potential 0.75 V 0.75 V

^ CJE B-E depletion capacitance (zero bias)

25 pF 0

Mm MJE B-E junction grading factor 0.333 0.333

v*. VJE B-E built-in barrier potential 0.75 V 0.75 V

*> TF Forward transit time 500 ps _ 0

„. \ - ,._ TR Reverse transit time 50 ns J 0

*Typical values of the parameters are shown for a discrete general-purpose device

5.15 Switching Behavior of the Bipolar Junction Transistor

Many transistor applications such as digital logic gates, interfacing circuits, power supplies and communication circuits use the BJT as a switch operated by a control signal. In such applications the transistor operates as a two-state device, with saturation corresponding to a closed switch.

In this section we discuss briefly the switching behavior of the BJT. The primary objective of this section is to relate switching behavior to the internal device physics. Consider the simple RTL inverter shown in Figure 5.47. We use the PSpice code as listed in the Figure to analyze the circuit and generate the waveforms shown in Figure 5.48.

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^cc=+3V

BJT switching bahaviour

Vin 1 0 PWL(0 0 O.lu O O.llu 3 0.3u 3 0.31u O)

KB 1 2 5K

Ql 3 2 0 Q2N2222A

.LIB EVAL.LIB

RC 4 3 2k

Vec 4 03V

.TBAN lOOn lu 0 In

.and

Figure 5.47 RTL inverter

The input voltage viH is the 3-V pulse shown in Figure 5.48a. Initially, the input voltage is zero, and the transistor is in thecutoff region. Therefore, the base current is 2ero, the collector current is zero and the output voltage vt is 3 V.

During the time interval from / = 0.10 )j.s to / = 0.11 |4.s, v-m rises rapidly to 3 V. The immediate effect is to cause iB to increase rapidly. This is shown in Figure 5.48b. The current that flows into

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Analog Electronics /BIT Circuits

the base charges die B-E junction depletion capacitance and dius raises the base-to-emitter voltage.

Part of the base current flows through the collector junction capadtance and out die collector lead (opposite to the usual current direction for an npn transistor in die active region, see Figure 5.38b). This current causes die output voltage to increase. Notice diat die output voltage actually goes slighdy higher dian die supply voltage (which is 3 V).

Shortly after the beginning of die input pulse, tine base voltage rises high enough to forward bias die emitter junction. Then electrons cross from the emitter into the base. These electrons diffuse into me collector junction. Thus conventional current begins to flow into the collector, and die collector voltage v, starts to drop. At about / = 0.19 ps, die transistor enters the saturation region (P's >'o cf- Figure 5.48b). Then die collector voltage becomes approximately constant at a few tendi of a volt.

The input switches back to zero during the time interval from / = 0.30 u.s to / = 0.31 us. However, die output voltage remains low until approximately / = 0.52 u.s. The reason for diat is die excess minority carriers (electrons) stored in die base region. When the transistor is driven into saturation, bodi junctions are forward biased. Thus a large concentration of electrons builds up in die base. Until diese electrons have been removed from the base, forward, current continues to flow across die junctions. Notice that the base current actually reverses directions at die end of die input pulse. This is due to stored charge flowing out of the base terminal.

At about / = 0.52 p.s, most of die excess charge in the base has been removed and die collector current begins to fall as shown in Figure 5.48b, causing die output voltage to rise (Figure 5.48a). However, die output voltage rises gradually because of die junction capacitances. The transistor returns to die cutoff state at / > lu.s.

The circuit of Figure 5.47 acts as a logic inverter. When die input is low, die output eventually becomes high. Similarly, when the input is high, the output eventually becomes low. Because of the charge storage effects, changes in the output do not occur immediately when die input changes. Of course, in most applications it is desirable for the switching delays to be as short as possible Several aspects of die device construction influence the switching speed. For example, reducing junction areas can reduce die device capadtances. Doping levels and junction grading also affect junction capadtances. A tiunner base region leads to quicker diffusion of minority charge carriers out of die base region. Selected impurities can be used to reduce die minority carrier lifetime.

Often, BJT data sheets give specifications for switching time intervals for test circuits similar to die RTL inverter. We define die start of a logic transition as die point at which 10% of die voltage change has occurred. For example, the start of die leading edge of the 3-V input pulse is die point at which die input pulse reaches 0.3 V. Similady, die start of the leading edge of die output pulse is die point at which % has fallen to 2.7 V. These start points are labeled in Fig. 5.49.

Similady, we define die end of a logic transition as die point for which 90% of the voltage (current) change has occurred.

- 1 7 9 -


4.6U-T ,

2.8U.

Start of leading edge of Vo

•ts-

End of

•»-N if A 2.7V

/ End of / trailing

/ edge of Vo

leading edge of Vo /

z=* 0.3V

h

au(l) ou(3)

r -1 " "I

660ns

[Start of leading edge of Vin — i — - -

200ns 400ns

Tine

Figure~5.49 Waveforms illustrating turn-on and turn-off rimes

Data sheets for BJTs intended for switching applications often specify the following switching intervals: • td is the delay time measured from start of the input leading edge to the start of the output

leading edge. • tr is the rise time, measured from the start point to the end point of the leading edge of the

output pulse. Notice that the rise time is defined for the leading edge of the output pulse even though this is the negative-going edge.

• /, is the storage time, measured from the start point on the trailing edge of the input pulse to the start point on the trailing edge of the output pulse.

• ^is the fall time measured between the start and end points of the trailing edge of the output pulse.

Turn-on and turn-off times, respectively ton =td+tr and t0ff = f, + / y , are given on transistors

data sheets. Typically, the switching times are much longer for power transistors than for small-signal devices. This is due to larger junction capacitances and charge stored in a larger volume of the base region.

S c h o t t k y - c l a a p a d RTL i n v a r t a r

V i n 1 0 FML(0 0 O . l u 0 O . l l u 3 0 . 3 u 3 0 . 3 1 u 0)

RB 1 2 5K

Ca 1 2 20pF

Ql 3 2 0 Q2N2222A

Dl 2 3 DSH

.MODIL DSH D ( I « - l « - 8 CJO-2pF V J - 0 . 6 M - 0 . 5 TT-0)

.LIB EVAL.LIB

Vaf*W

Cs=20pF

A (v 2N2222A RC 4 3 2k

^ L Vcc 4 0 3 V

.TRAM O . l u l u 0 I n

. « n d

Figure 5.50 RTL inverter with speed-up capacitor and Schottky clamp diode

- 1 8 0 -

Analog Electronics / BIT Circuits

Techniques for speeding-up the transitions of the RTL inverter are of much interest in many applications. Two such techniques are illustrated in Figure 5.50. First, a speed-up capacitor has been added in parallel with die base resistor Rj. Second, a Schottky clamp diode has been added between the base and the collector terminal. Figure 5.51 shows waveforms generated by the PSpice program shown in Figure 5.50.

*.4n «.tes

fine

Figure 5.51 Voltage waveforms for the Schottky-clamped RTL inverter

Notice that die switching times for diis circuit are much smaller than for the simple RTL inverter of Figure 5.37. The speed-up capacitor couples the leading edge of the input pulse to the base. The voltage across the capacitor cannot change instantaneously. Thus the rapid increase in the input pulse causes a rapid increase in vBE. Thus the transistor is forced to turn on very quickly. Moreover, without the speed-up capacitor, the junction capacitances must be charged through Rg, and vBE rises more gradually.

The Schottky diode prevents the transistor from entering the saturation region. When the collector voltage reaches approximately 0.4 V, the diode conducts and reduces the portion of the base current available to the transistor. Thus the output voltage is not allowed to fall below 0.4V and the transistor remains in the active region. This greatly reduces the concentration of electrons in the base region.

The important point for the circuit designer is that if fast switching is important, the circuit should be designed so that the transistors do not enter saturation.

5.16 Summary

The bipolar junction transistor is a solid-state device consisting of two pn junctions fabricated in close proximity on single-crystal semiconductor. A large-signal, static, nonlinear Ebers-Moll model, embodied in an equivalent circuit and a pair of corresponding simultaneous equations, help us understand the transistor in terms of the theory of pn junctions. For small-signal linear applications, we use external dc sources to bias the transistor in its forward active state. For this state, the Ebers-Moll predicts the characteristic curves and linear equations of a current-controlled current source. This leads to a simple linear equivalent circuit that we use to predict how die transistor interacts with other circuit elements. To do the ac circuit analysis we replace me transistor with its equivalent circuit. Parameters of this circuit depend on the device jg-point that results from the particular bias. The BJT has two other states of major importance: saturation, in which the transistor resembles a closed switch, and cut-off, where the transistor

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represents an open switch. The third state, inverse active, is of little practical importance. Each of die four states corresponds to operation in a particular region of the transistor output characteristics, and each has a circuit model, related in an obvious way to the characteristic curves. For amplifier applications the BJT is operated in the active state. Switching applications make use of the cut-off and saturation states. A BJT operating in the active state provides a collector current ic = isexp(J vBE\ / F T ) . The base current is iB = ; c / p , and the emitter current iE = ic + iB. Also, ic = aiE and thus P = a / ( l - a ) and <X=P/(1+P). To ensure operation the active state, the collector voltage of an npn transistor must be kept greater than the base voltage. For a pnp transistor, the collector voltage must be lower than the base voltage. In some important problems the state of the transistor is unknown. In these cases we must first assume a state for each transistor, and dien use its equivalent circuit to check our assumptions. An important aid in developing understanding and intuition about transistor circuits is a graphical tool, the load line. A number of static second-order effects describe differences between real transistors and idealized devices. These include temperature variations of parameters, nonzero output resistance, junction breakdown, internal feedback, and parasitic resistances. At a constant collector current, die magnitude of the base-emitter voltage decreases by about 2 mV for every °C rise in temperature. With the emitter open-circuited (iE — 0), the Base-collector junction breaks at a reverse voltage BV^Q that is typically > 50 V. For iE = 0, the breakdown voltage is less than BVCM- In the common-emitter configuration the breakdown voltage specified is BV^g, which is about half BVCBO. The emitter-base junction breaks down at the reverse bias of 6-8 V. There are also dynamic transistor limitations embodied in the depletion and diffusion capacitances of the junctions and between the collector and the substrate. Except for minor differences they are the same nonlinear capacitances we encounter in diodes. SPICE transistor models enable us to simulate both static and dynamic behavior of transistors, including all of the major nonlinearities. We generally use our simplified and more intuitive transistor concept to design, and then follow up with accurate computer simulations that include the second-order effects we consciously ignored to make our initial design work tractable. We examine and evaluate the simulation results in terms of our simple conceptual ideas and then redesign, if necessary. The dc analysis of transistor amplifiers is gready simplified by assuming diat | VBE \ = 0.7 V. To operate as a linear amplifier, the BJT is biased in the active region and the signal vh is kept small (vk « KT). Bias design seeks to establish a dc collector current that is as independent of the value of p as possible. For small signals, the BJT functions as a linear voltage-controlled current source with a transconductance &n - IJ Vv Th e inp u t resistance between base and emitter, looking into the base is r„ = P/#n. For a common-emitter configuration, a high voltage gain and reasonable input impedance are obtained, but the high-frequency response is limited. Including an unbypassed resistance in the emitter lead can increase the input resistance of a common-emitter amplifier. In the common-base configuration, a high voltage gain (from emitter to collector) and an excellent high-frequency response can be obtained, but the input resistance is low. The CB amplifier is useful as a current buffer. In the emitter follower (common-collector amplifier) the voltage gain is less than unity, the input resistance is very high, and the output resistance is very low. The circuit is useful as a voltage buffer.

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Analog Electronics / Feedback Circuits

6 Feedback Circuits

Feedback consists of returning part of the output of a circuit or system to its input In an amplifier with negative feedback, a portion of the output signal is returned in opposition to the original input signal. In positive feedback, the feedback signal aids the original input Usually, in amplifiers, negative feedback is more useful than the positive feedback. However, the positive feedback is useful in the design of oscillators, which are considered later. The advantages of adding a negative feedback to an amplifier are

• reduced sensitivity to parameter variations • increased bandwidth • reduced nonlinear distortion • improved input and output resistances

One disadvantage is the reduction of gain; however, gain is easy to obtain with modern circuits, so this is a small price to pay. The other disadvantage, a possibility of unwanted oscillations or instability, is more serious, for oscillations make the circuit worthless as an amplifier.

Fig. 6.1 shows the general structure of & feedback amplifier. A nonfeedback amplifier with gain A (the A circuit) delivers an output signal x, = Ax, to an external load. Instead of using signal x, as the amplifier input, a feedback circuit (p circuit) produces a feedback signal xf = fix, to form the actual input x> The feedback factor, P, used extensively in this chapter is unrelated to the bipolar transistor beta.

Figure 6.1 Feedback amplifier structure

Feedback theory applies to all four amplifier types named in Chapter 2.1,-but each type implies a different interpretation of Fig. 6.1. For a voltage amplifier, A denotes voltage gain and xe and x, are voltages. The external source must be a voltage source xs (ideally having zero internal resistance) and there is a voltage subtraction at the input. The feedback factor P = x/x. is a voltage gain (or attenuation) in this case.

For a current amplifier, A denotes current gain. The input comes from a source of current xs

(ideally having infinite internal resistance) and the current subtraction is required at the input. The p denotes the current gain of the feedback circuits.

In a transconductance amplifier, A is transconductance gain with dimensions of amperes/volt. Thus output x, is a current and the source xt is the voltage source; the subtraction at the input is the voltage subtraction. For this case, P has a dimension of volts/ampere, or transresistance.

Finally, the transresistance amplifier has transresistance gain with dimensions of volts/ampere. Thus output xc is a voltage and the external input source is the current source. The subtraction is a current subtraction. For this case, p has a dimension of transconductance.

From Fig. 6.1 one can write

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Af=- (6-2)

x0 = Axi = A(xs -x/) = A(xs - p* 0 )

Solving for the gain of the feedback amplifier, Aj- = x0 I xs, gives

which applies to all four amplifier classes.

Reduction of Gain. For midrange frequencies, both A and p are real quantities having the same algebraic sign. Equation (6.1) shows one of the prices we pay for negative feedback, a gain reduction. For example, suppose A~\W and the fraction of x, that is fed back to the input is P=0.01. Then the resulting feedback amplifier has gain of only

10000 nn

Usually, as in this illustration, ^ 4 P » 1 , and (6.1) gives an important approximation

P For a voltage amplifier, common practice is to obtain P from a resistor network of low-temperature coefficient, such as from a voltage divider, giving

_ 1 Rx+R2 . %

In an IC realization, such a P is easily controlled to within 1% or so by masking tolerances, and the temperature variations cancel over a wide temperature range. Thus Afis quite constant, even though A might vary greatly with temperature or other factors.

Improvement Factor. The denominator of (6.1), 1+^P, is of considerable importance in feedback theory. This factor by which the gain is reduced also turns out to be the degree of improvement effected by introducing feedback. Ideally, parameter sensitivity, distortion, bandwidth, input resistance and output resistance all improve by \+A$ when one adds feedback. Thus the quantity is referred to as the improvement factor.

6.1 Effects on Sensitivity, Bandwidth and Distortion

We will first develop an intuitive notion of how the feedback works. Suppose in Fig. 6.1, while the input xt is held constant, output x, decreases in amplitude for any reason. Being proportional to *•„ feedback signal xyalso decreases, thereby increasing x ; to compensate, at least partially, for the original change. A complementary scenario opposes increases in x,. Thus negative feedback opposes any change in x, caused by an event unrelated to x> If the cause is variation in an internal parameter/), we say that feedback has reduced the sensitivity. If it is loss of gain at either low or high frequencies because of amplifier capacitances, we say feedback has improved the frequency response. If x, changes in a manner not proportional to xs because of nonlinearities within the amplifier, we say feedback has reduced distortion. We now examine the details to obtain a more quantitative understanding to use in analysis and design.

6.1.1 Effect of Feedback on Sensitivity

If the sensitivity of gain A to parameter/) is Sff, adding negative feedback results in an amplifier

of gain Aj with lower sensitivity; specifically,

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Analog Electronics /Feedback Circuits

To prove this, we need only use the definition

s*f _ P Mf _ P d[AI{\ + AP)} p Af dp Af dp

Since the circuits we design employ feedback p that is independent of p, the derivative gives

Af

(1 + AP){dA I dp) - AfiidA I dp)

(1 + A0)2

P Af

A/3 dA

(1 + AP) (i + AJJ)2 J dp

Substituting for A, from (6.1) gives an equation that is equivalent to (6.3).

Exercise 6.1 A nonfeedback amplifier with A = 347 contains a critical resistor R. By laboratory

measurements we determine that SR =1.12. After adding negative feedback to reduce the sensitivity, we find the amplifier gain is 24. Find the gain sensitivity of the feedback amplifier to changes in K Ans. 0.077.

Example 6.1 We have an amplifier with a gain of 800. Sensitivity of gain to temperature change is 0.1; however, our specification requires temperature sensitivity to be no more than 0.001. Investigate the possibility of using negative feedback to bring the temperature sensitivity within specification. Solution. From (6.3), we need an improvement factor of

Since A = 800, P must satisfy 1 + 800^=100 or P = 0.124. The resulting feedback amplifier meets the temperature-sensitivity specification;

however, its gain is only 800/100 = 8. +

Sensitivity of Cascaded Feedback Amplifiers. Example 6.1 shows that we can improve sensitivity by sacrificing gain. Because specifications often involve both gain and sensitivity, it is interestirg to see if we can come out ahead by using a cascade'of low-gain, low-sensitivity feedback amplifiers.

Consider a cascade of n feedback amplifiers, each of gain Af. We denote the overall gain by G = (A)", and now need to find the sensitivity of G to parameter/). By definition,

SG EdG p ,dAf_ p G dp G v J' dp

Substituting G = (A)* gives

cG P „,, sn-ldA* m P dAf

Sp^niA/) -d7=n^Hp-We conclude that

Sf=nSp which shows that sensitivity increases only in proportion to n as we cascade stages, whereas G varies as die »-th power of gain. This suggests that we should be able to be better off using feedback. Table 6.1 illustrates the point using numbers from Example 6.1. Cascading feedback amplifiers is obviously an effective strategy.

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TABLE 6.1 G A I N AND SENSITIVITY O F CASCADED FEEDBACK AMPLIFIERS

n G ^P

1 ' 8 0.001 2 64 0.002 3 512 0.003

4 4096 0.004

6.1.2 Effect of Feedback on Bandwidth

Upper Half-Power Frequency. Consider using feedback to increase the bandwidth of an amplifier described by

A = A(co) = A0 , *" (6.4)

where Ae is the midband gain. Substituting this expression into (6.1) gives a>H/(ja) + a>H)

Af — At

= 4

= A

or

f °l + A0[a>H/(j6> + o>H)y3

° ja> + <0H + Aoa>Hp

<oH \+AQP

°ja> + a,H(\ + AoP)\ + Ao0

a>Hf Af = Aof

where

Ant =

J6) + a>Hf (6.5)

of = l + A B and aW = aH® + A°®'

Comparing (6.5) and (6.4) one can see that the feedback amplifier's gain function has the same general form as the original; however, its upper half-power frequency is higher by (l+A$) and its midrange gain is lower by the same factor. Figure 6.2a compares the two frequency response curves. Notice the original and final gain-bandwidth products, Afi)H and A^Q)Hj. We see that the gain-bandwidth product is preserved when one adds feedback. We conclude that for a one-pole amplifier described by (6.4), negative feedback facilitates a direct trade-off of gain for bandwidth as in Fig. 6.2a. Amplifiers with more complex gain functions do not give an exact trade-off; however one can expect a dominant high-frequency pole to approximate such a trade-off.

Gain (dB) Gain (dB)

<BH (Off (O (OLf

(a) (b) Figure 6.2 Using negative feedback to improve bandwidth:

(a) high-frequency (b) low-frequency responses

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Lower Half-Power Frequency. Consider a nonfeedback amplifier described by id)

A = A(a>) = A0 / (6.6)

Substituting into (6.1) gives

A =A ja>l(J(Q + a>L) f °\ + Ao[ja>/U<0 + Q>L)]fi

Algebraic manipulations similar to those for the high frequency case lead to id)

Af = Aof - H (6.7) J °J ja) + <aLf

where

From Eqs. (6.6) and (6.7) we conclude that negative feedback lowers the lower half-power frequency and midrange gain by (1+A$). Fig. 6.2b shows the Bode plot changes. A practical consequence can be that coupling or bypass capacitors can be smaller for the same lower -3dB frequency in a feedback amplifier. More complicated low-frequency gain functions than (6.6) are not changed in exactly this fashion; however, if there is a dominant low-frequency pole, reduction in Ct)L by (l+Afi) is usually a reasonable estimate. Wideband amplifiers approximated by Eq. (6.6) at low frequencies and Eq. (6.4) at high frequencies have their passband extended at each side by (Hv4„P).

Exercise 6.2 We need an amplifier with a rise time of 300 ns. The amplifier we have has rise time of 3 us and gain of 40. Find the resulting gain and P, if we correct the rise time problem with a negative feedback. Ans. 4, 0.225.

Example 6.2 We need an amplifier that meets the following specifications: gain > 80, fL < 50 Hz, fH > 15 kHz, and sensitivity to power supply changes < 0.2. We have an amplifier with gain = 1000,^ = 400 Hz,fH — 9 kHz and its sensitivity to changes in supply voltage is 1.5. Determine whether we can meet the specifications by adding feedback to the existing amplifier. If so, find an acceptal e value of P and give final specifications for the feedback amplifier. Solution. Assume that a pair of dominant poles characterizes the frequency response. Considering each specification individually gives the following requirements:

1000 gain: - — , ^ , , ^ 8 0 6 1 +1000^

400 lower -3 dB frequency: -—, nnn •- < 50/fe M } 1 + 1000/? upper -3 dB frequency: 9000(1 + 1000/ff) £ 15000/fe

sensitivity: - — . „ „ „ „ ^ 0.2 y 1 + 1000^

These lead, respectively, to the requirements l+103p < 12.5, 1+HPP > 8, l+103p > 1.67, and 1+103P > 7.5. Sorting out these inequalities shows that any P that satisfies 8 < 1 + 1 0 ^ < 12.5 is acceptable. To leave room for error, choose 1+103P = 10, which requires P = 0.009. Then the final amplifier will have gain = 100 ,^ = 40 H z , ^ = 90 kHz and supply sensitivity of 0.15, all within specifications.

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6.1.3 Effect of Feedback on Nonlinear Distortion

Nonlinear distortion is normally not a problem in the small-signal amplifiers. However, in power amplifiers, output signal must be large enough to develop a specified amount of power in the load. This often requires signal swings large enough to traverse a significant portion of the amplifier's nonlinear transfer characteristic. When this occurs, the output signal is the amplified input signal, plus additive harmonic distortion components that arise within the amplifier itself. Amazingly, negative feedback can be used to feed these distortion components back into the input in such a way that they subtract from themselves. The feedback also causes some signal to subtract from itself; however, this is the gain reduction we expect with negative feedback, and we can compensate for it by adding a preamplifier. The bottom line is that negative feedback reduces internally generated distortions by (\+A$). The following quasi-numerical development shows how it works.

XJ(0=0.001COS(<IDO

(a)

jco(0=10cos(a)0+d(/)

XoC/HOcosCoO+O-OOWdW

Consider a linear model of a nonlinear amplifier shown in Fig. 6.3a. To be specific, suppose that when the available input signal xt= 0.001cos(a)/) is applied, the output is the Fourier series xo(t) = \0cos(ojt) + d(t)t

where distortion d(t) consists of Fourier harmonic terms and accounts for the distorted appearance of the output. (The distortion term depends on the amplitude of the amplifier's output signal.) Suppose design specifications require an output signal of 10cos(©/) for the given x/t), but also require that the distortion be much less than d(i). In this type of problem we can add negative feedback as in Fig. 6.3b to cancel the distortion. For Fig. 6.3b

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xo(t) = d(t) + A[xs(t)-0Xo(t)] or

d(t) MO \ + A0 \ + A0 sy

Using P = 0.01, as an example, gives x0 ( 0 = 0.0099 COS(GJT) + 99xs (r) (6.8)

showing that distortion is reduced to 1 % of its former value. Notice, however, that the new input xj(t} is multiplied by only 99 in (6.8) instead of the original 104. Because specifications require 10cos(©i) at the output, from Eq. (6.8) the input to the feedback amplifier must satisfy 99x s (0 = 10cos(fi#) or x,= 0.101cos(©/), showing that the feedback amplifier requires a larger input voltage that the nonfeedback amplifier for the same output (The corresponding transfer characteristic of the feedback amplifier, x, versus x„ is much more linear than the original curve, but has lower slope.) Since only 0.001cos(©/) is available for us for our io^ut signal, we must add a preamplifier of gain Ap at the input that satisfies 0 . 0 0 1 ^ = 0 . 1 0 1

or 4 , = 101.

Figure 6.3c summarizes the design, both in general notation and in the numerical values used as examples. For this strategy to succeed, we must construct a preamplifier that does not produce distortion. The key observation is that the signal amplitude required at the preamplifier output is much smaller than the specified amplifier output voltage. That is, it is much easier to produce a distortion-free output voltage of 0.101 V than 10 V.

Vcc = +15V

V K££ = -15V

Figure 6.4 Nonlinear class-B power amplifier

Example 6.3: Crossover distortion. Distortion is mainly a problem in power amplifiers. A simplified example of an audio-amplifier output stage is shown in Fig. 6.4. Notice that if vs = 0, both transistors are in cutoff since there is no forward bias of the base-emitter junctions. In fact, neither transistor conducts until v, swings outside the range from -0.6 V to 0.6 V (for typical silicon power transistors). With both transistors cut off, the output voltage is zero. As v, swings higher than 0.6 V, the npn transistor J2 , turns on and supplies current to the load. In this case the output voltage is given by, approximately,

v0 = v5 - 0.6 for vs > 0.6

If vs is less than -0.6 V, the npn is off and the pnp transistor Q^ is in the active region. Then we have

for v0=vs+ 0.6 v , < - 0 . 6

-189 -


The transfer characteristic for the amplifier is shown in Fig. 6.5. Notice the nonlinearity in the region around vt = 0. This nonlinearity causes ctossover distortion when conduction is changing from one transistor to the other. Also, notice that the voltage gain, which is the slope of the transfer characteristic, is approximately unity (except in the region around zero input).

5.W

-S.W + -6.W -4.MI

Figure 6.5 Transfer characteristic for the amplifier of Fig. 6.4

This circuit is an example of a class B amplifier, in which each device conducts for approximately half of the signal cycle. Figure 6.6 shows the class B output stage driven by a differential amplifier that has a differential gain of 1000. The feedback network consisting of R, and R2 returns part of the output voltage to the inverting input of the differential amplifier. Normally the switch would be in position JB, so the output voltage across the load is fed back. However, we will also analyze the circuit with the switch in position A to illustrate the crossover distortion of the output stage.

The feedback ratio P is given by

V *2 P = Ri +R-,

= 0.1 "o - 4 ••• A 2

Since the gain of the differential amplifier is 1000 and the gain of the class B stage is approximately unity, the overall open-loop gain isA= 1000. Thus we have A$ = 100, which is much larger than unity. Consequendy, we expect to 6ndA/= 1/P = 10.

00 F££=-15V

RL=&n

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Figure 6.6 Class B power amplifier with feedback: (a) circuit diagram, (b) model for die differential amplifier

The differential amplifier provides the means for subtracting the feedback signal v} from the source voltage. We use the circuit model for the differential amplifier shown in Fig. 6.6b. The SPICE program to analyze the circuit is listed below.

Class B Feedback Example Vs 1 0 sin(0 0.2 1000) 82 4 0 Ik Rl 2 4 9k; change first node to 3 for switch at B EA 2 0 1 4 1000; voltage-controlled voltage source Rin 1 4 1MEG Ql 5 2 3 npnpower Q2 6 2 3 pnppower RL 3 0 8.0 Vcc 5 0 15V Vee 6 0 -15V .model npnpower npn(bf=150 Is=le-12) .model pnppower pnp(bf=150 Is=le-12) .tran lOOus 2ms 0 5us .end

After executing this program, we request plots of the drive voltage V(2) at the bases of J2, and Q2

as well as the output voltage vt — V(3). The result is shown in Fig. 6.7a. In this case, the switch is in position A, so the nonlinearity of the output stage is not included in the feedback loop. The output signal waveform thus deviates from an ideal, distortion-free shape and, consequendy, a significant distortion signal d(t) is a part of the output, as is also shown in Fig. 6.7a. The base drive is sinusoidal, but the output demonstrates considerable crossover distortion.

- 1 9 1 -


Tlaa

(b) Waveforms for the switch in position B Figure 6.7 Waveforms for the circuit of Fig. 6.6

Then we change the program to place the switch in position B, obtaining the results shown in Fig. 6.7b. In this case the output voltage is almost free of distortion, d{t) = 0. Notice that the base drive voltage V(2) has been predistorted to compensate for the nonlinearity of the output stage. Also notice that, as expected, the output voltage is Aj = 10 times larger that the source voltage signal.

Exercise 6.3 Suppose that we need to change the amplifier of Fig. 6.6, so that the gain Aj is approximately 20. What changes do you suggest? Include component values.

Exercise 6.4 Change the resistor values in Fig. 6.6 to R2= lOfi and R, = 9990Q. What is the approximate value of A$? Use a Spice program to find the output waveform for the switch in position B and vs — 0.004sin(2000rc/). Is the feedback effective in reducing distortion in this case? Explain.

6.1.4 Effect of Feedback on Noise

An undesirable aspect of amplifiers is that they add unwanted noise to the desired signal. Sources of this noise include power-supply hum, coupling of signals from other circuits, and thermally generated noise in resistors. Another noise is shot noise caused because current flow is not continuous; instead, charge is carried in discrete quantities by individual electrons. Still another source is microphone noise, which is an electrical signal arising from vibration of circuit mechanical components.

Some source of noise can, in principle, be eliminated. For example, power-supply hum can be reduced by additional filter circuitry in the power supply. However, some of the noise sources, such as thermal and shot noise, stem from the basic natural processes and cannot be totally eliminated. Thus all amplifiers add noise, but some amplifiers are much worse than others are. In this section we wish to show that feedback can, under certain circumstances, reduce noise.

If d(t) introduced in Section 6.2.3 represents noise arising within the nonfeedback amplifier, negative feedback reduces output noise just as it reduces distortion; however, it can be shown that adding negative feedback results in no improvement in the input signal-to-noise-ratio of an amplifier. Since this ratio is usually the critical factor, adding negative feedback is not a generally effective noise reduction strategy.

- 1 9 2 -


Figure 6.8 Model that accounts for the addition of noise in amplifiers

The additive noise can be modeled as shown in Fig. 6.8. The amplifier gain is denoted as A,. To quantify noise performance, engineers use the signal-to-noise tatio, which is the desired signal power delivered to the load divided by the noise power. We denote the rms values of the signal and noise by X, and X,. The rms signal delivered to the load in Fig. 6.8 is A,XS and the rms noise is A,XM. If the signals are voltages, the powers delivered to the load are

( ^ (6.9) Ps = R,

and

Ps = (Axny

The signal-to-noise ratio is given by

(6.10)

(6.11)

Equation (6.11) also applies if Xs and X, are currents.]

Figure 6.8 Model that accounts for the addition of noise-in amplifiers

Now consider the feedback amplifier shown in Figure 6.9. X, is the rms noise of amplifier A,. Amplifier A2 has been added to increase the open-loop gain of the amplifier. Amplifier A2 is assumed to be noise-free. This is a reasonable assumption if we have a situation in which amplifier A, is very noisy and amplifier A2 is well designed, so its noise is very small. For example, A, can be a very high power amplifier with a great deal of power-supply hum, but A2 is supplied with a well-filtered power. (Perhaps the designer is trying to be economical by using less filtering for the power to amplifier^!,.)

We analyze the system shown in Figure 6.9 to find an expression for the signal-to-noise ratio. We can write x2{t) = xs{t)-px0{t) (6.12)

xl(t) = A2x2(t) + xn(t) (6.13) x0(t) = AlXl(t) (6.14) Substitution of Equation (6.12) into (6.13) and the result into (6.14) results in x0{t) = Ax {A2[xs(t) - Px0{t)\ + xn{t)} (6.15) Solving for x,[t), we find that

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*»<' ) =** ( ' ) !7^ + X » ( ' ) !7M^ (616>

The first term on the right-hand side of (6.16) is the desired signal, and the second term is the noise. As in Equation (6.11), the signal-to-noise ration is given by the ratio of the rms signal squared divided by the rms noise squared, which can be shown to be equal to

SNR = [j£j (A2f (6.17)

Comparing this with the results given in Equation (6.11) for amplifier^, without feedback shows

the SNR has been increased by a factor of A\ •

Thus feedback is a powerful technique for reducing noise in some circumstances. Keep in mind, however, that the result we have derived applies only if the preamplifier A2 can be assumed noise-free. No improvement in SNR value is obtained when A2 = 1 in (6.17). In conclusion, adding negative feedback is not a generally effective noise reduction strategy.

6.2 Feedback Types

If the feedback network samples the output voltage, we say the amplifier has voltage feedback. On the other hand, if the feedback network samples the output current, the amplifier is said to have current feedback.

The feedback signal can be connected either in series or in parallel with the signal source and amplifier input terminals. Thus we have series feedback or parallel feedback, respectively. Series feedback can be combined either with voltage sampling or current sampling. Similarly, parallel feedback can be used either with current sampling or with voltage sampling. Thus we have four types of feedback: series voltage, series current, parallel voltage, parallel current.

Keep in mind that the terms series and parallel refer to the input connections, whereas die terms voltage and current refer to the output signal that is sampled. (Other books on the subject use the terms differendy. Unfortunately, a uniform usage does not exist.) Figure 6.9 illustrates the four types of feedback.

In complex circuit configurations, sometimes it is not clear whether we deal with current or voltage feedback. A simple test is to open-circuit or short-circuit the load. If the feedback signal vanishes for an open-circuit load, we have current feedback. Similarly, if the feedback signal vanishes for a short-circuited load, we have voltage feedback.

In series voltage feedback, it is natural to consider the input signal to be vt and the output signal to be vt. Thus it is appropriate to model the amplifier as a voltage amplifier for which die gain parameter is A,~vjvf This is indicated in Figure 6.9a.

In series current feedback, it is natural to consider the input signal to be vt and the output signal to be if Thus we model the amplifier as a transconductance amplifier for which the gain parameter is the transconductance gain Gm=ijvj. This is indicated in Figure 6.9b.

Similarly, for parallel voltage feedback, we model the amplifier as a transresistance amplifier with gain E ,. Finally, for parallel current feedback, we model the amplifier as a current amplifier with g a i n ^ .

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The units of p are the inverse of the units of the gain for each type of feedback. Refer to Figure 6.9b, as an example. Notice that the units of the transconductance gain Gm are Siemens. Also, we see that Vf=$ic. Therefore, p is a transresistance parameter with units of ohms.

Similarly, for parallel voltage feedback, the gain parameter is a transresistance, and the feedback ratio p is a transconductance. For series voltage feedback A = Ar which is unidess, and P is also unidess. Finally, for parallel current feedback, A = At and P are both unitless.

The effect of each type of feedback on input and output impedance of an amplifier is different. In design, we select the type of feedback in accordance with the design objectives.

(b) Series current feedback

(c) Parallel voltage feedback

(d) Parallel current feedback Figure 6.9 Types of feedback

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6.3 Effect of Feedback Types on Input and Output Impedance

Now we examine the effect of series feedback on input impedance. The model for our discussion is shown in Figure 6.10. The output signal x, is sampled by the feedback network, which produces a feedback voltage signal vf = fix, connected in series with the source and the input terminals of the amplifier. The original (before the feedback is added) input impedance of the amplifier is R,. The input impedance of the amplifier with feedback is

% = 7 " (6-18)

Writing a voltage equation around the loop in Figure 6.10, we obtain v, = *,-/, + vf (6.19)

But «y=P^ so we have vs = R,is+0Ko (6.20) Also, the input voltage is given by Vi = Riis (6.21) and the output is given by x0 = Avt (6.22) where A=Ar is a voltage gain if x,=v„ or A—Gm is a transconductance gain if die output is a current x=i,. Substituting Equation (6.21) into (6.22) and the result into (6.20), we obtain v^Riis + A/SR^ (6.23) which can be solved for the input impedance with feedback

Rif=f = Ri(l + Afi) (6.24)

Recall that for negative feedback the factor (\+A$) is larger than unity. Thus negative series feedback increases input impedance.

-O-

Load

Figure 6.10 Model for analysis of the effect of series feedback on input impedance

Load

Figure 6.11 Model for analysis of the effect of parallel feedback on input impedance

Next, we consider the effect of parallel feedback on the input impedance. The model is shown in Figure 6.11. It can be shown that the input impedance in this case is

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Ri

Thus negative parallel feedback reduces input impedance.

Exercise 6.5 Derive Equation (6.25).

To find the output impedance of an amplifier, we turn off die input source, remove the load, and look back into the output terminals. A model for the voltage feedback amplifier with these changes is shown in Figure 6.12. A test voltage source vM has replaced the load at the output terminals of the feedback amplifier. The output impedance with feedback is

Rof = vtest

hest (6.26)

To simplify our analysis, we assume that the input impedance of the feedback network is infinite. Thus the feedback network does not load the amplifier output.

'Jest

Xs=0 + vtest

Figure 6.12 Model for the analysis of output impedance widi voltage feedback

The output circuit of the amplifier is modeled by a controlled voltage source with gain parameter A^ The subscripts of the gain parameter indicate that it is the open-circuit amplifier gain. If x,=f, we have series voltage feedback and AK = A.,^. On the other hand, if x~ij, we have parallel voltage feedback and AK = R ^ In any case, the resistance R, shown in Figure 6.12 is the output resistance of the amplifier before feedback.

For die output loop of Figure 6.12 we can write vtest ~ ^ohest + ^ocxi (6.27) However, we have

*/ = -Potest (6-28) Substituting Equation (6.28) into (6.27) and solving for the output resistance with feedback, we have

Rof = vtest

hest

R„

1 + fiA, (6.29)

oc Thus negative voltage feedback reduces the output impedance of an amplifier.

Next, we consider the effect of current feedback on output resistance. The model for this analysis is shown in Figure 6.13. As before, the source signal x/is set to 2ero, the load is removed, and a test source is connected to the output terminals. The feedback network is assumed to have zero input impedance, so it produces no loading effects at the amplifier output.

197


x=0 + ^-40-^

&==&, a ^"Irjf

Figure 6.13 Model for the analysis of output impedance with current feedback

The output of the amplifier is modeled by a controlled current source in parallel with the output resistance. The gain parameter Ax has subscripts indicating that it is the gain of the amplifier with a short-circuited load. For parallel current feedback, the gain is the short-circuit current gain Ax

= Aisf For series current feedback, the gain is the short-circuit transconductance gain Ax = Gau, For the system of Figure 6.13 we can show that

Rof = vtest

hest = R0(1 + J3ASC) (6.30)

Thus negative current feedback increases the output impedance of an amplifier.

Exercise 6.6 Derive Equation (6.30).

6.4 Summary of the Effects of Various Feedback Types

We have seen that four types of feedback are possible. One effect of feedback is to stabilize and linearize gain. (i.e. Aj tends to be independent of A). However, the particular type of gain stabilized depends on the type of feedback. Table 6.1 shows the type of gain stabilized and linearized for each type of feedback.

We have seen that (negative) series feedback increases input impedance, whereas parallel feedback reduces input impedance. If yip is very large, the input impedance tends toward either an open circuit or a short circuit. The formulas for input impedance are shown in Table 6.1.

TABLE 6.1 EFFECTS O F FEEDBACK

FEEDBACK

TYPE xt xf

GAIN

STABILIZED

INPUT IMPEDANCE

OUTPUT

IMPEDANCE

IDEAL

AMPLIFIER

Series voltage t>, *>. ' A

RiQ + Av/?> Ro

Voltage Series voltage t>, *>. AV-\ + Av0 RiQ + Av/?> 1 + AvocP

Voltage

Series current », i.

Gm mf~\ + Gmp Ri(l + Gm)T> R0Q + GmscP)

Trans-conductance

Parallel voltage ', ».

j? Rm Ri Ro Trans-resistance

Parallel voltage ', ».

j? Rm

i + RmP 1 + RmocP

Trans-resistance

Parallel current *, '.

A Ai Ri Ro(\ + Aisc0) Current

Parallel current *, '. » - l + AiP 1 + 4/? Ro(\ + Aisc0) Current

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To reduce output impedance we could employ voltage feedback. On the other hand, to increase output impedance, we could choose current feedback. Of course, in making these statements, we assume negative feedback - the effect of positive feedback is the opposite. Table 6.1 also contains formulas for the output impedance for each of the four feedback types.

We can summarize the effect of each type of feedback by stating that it tends to produce an ideal amplifier of a certain type. For example, series voltage feedback increases input impedance, reduces output impedance and stabilizes voltage gain. Thus series voltage feedback tends to produce an ideal voltage amplifier. As summarized in Table 6.1, similar statements can be made for the other feedback types.

6.5 Practical Feedback Networks

So far, we have modeled feedback networks as controlled sources. This approach simplified the analysis and allowed us to focus on the main effects of the various types of feedback. However, in practice we use simple networks of resistors (or in some cases resistors and capacitors). This components are available with precise and stable values (over time and with temperature changes) compared to the parameter values of active components (transistors). We employ negative feedback, so the amplifier characteristics depend mainly on the feedback network, thereby achieving amplifiers having precision and stability. Figure 6.14 shows examples of feedback amplifiers using practical resistive feedback networks.

n Vf R2 (a) Series voltage, p = = — — (assuming U £ 0)

v0 R\ + R2

f (b) Series voltage, /? = -;— = Rf (assuming U = 0)

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n lf l

(c) Parallel voltage, p = — = — —— (assuming v,- 2 0) vo Rf

>L _

n if R\ (d) Parallel current, p = T~ = ~ T 7T (assuming p,- = 0)

l0 R\ + K2

Figure 6.14 Examples of resistive feedback networks

Notice that we have modeled the source as a voltage source for series feedback and as a current source for parallel feedback. This is consistent with Figure 6.9. The Thevenin model for the source is more natural for series feedback because the feedback voltage j^is subtracted from the source voltage v, in a series connection. The Norton model is more natural for parallel feedback because the feedback current ij\& subtracted from the source current is in a parallel connection.

Each of the feedback amplifiers shown in Figure 6.14 has negative feedback. For example, in the series voltage case shown in part (a) of the Figure, suppose that vs has a positive value. This results in a positive voltage at the noninverting input. The amplifier, in turn, produces a positive output voltage. The feedback network, composed of R, and R*, returns a fraction of the output voltage to the inverting input. This reduces the input voltage vf Thus the feedback signal acts in opposition to the original source signal, and we have negative feedback. If the inverting and noninverting input terminals were interchanged, positive feedback would result. A similar discussion applies to the remaining feedback amplifiers shown in Figure 6.14 b, c, and d.

We can identify series feedback and parallel feedback by examination of the circuit configuration at the amplifier input. Study Figure 6.14a and b to verify that the signal source, the amplifier-input terminals and the output of the feedback network are in series. Also, verify the parallel connection for Figure 6.14c and d.

To test for cutrent feedback, open-circuit the load so that the output current becomes zero. If the signal returned to the amplifier input by the feedback network becomes zero, the amplifier has current feedback.

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To test for voltage feedback, short-circuit the load so that the output voltage becomes zero. If the signal returned to the amplifier input by the feedback network becomes zero, the amplifier has voltage feedback. Verify that the types of feedback are correcdy labeled in Figure 6.14 by use of these tests.

Exercise 6.7 For each of the circuits shown in Figure 6.15, identify the type of feedback present (negative-positive, series-parallel, and voltage-current?). Determine the value of the feedback ratio, assuming zero input current and zero input voltage of the non-feedback amplifier, where appropriate. What type of ideal amplifier results if A$ is very large? What is the gain of this ideal amplifier? What value (0 or oo) do the input and output resistances approach? Ans. (a) Negative series voltage, 3 = 1, ideal voltage amplifier, A4 = l , K , - = ° o , R , = 0 (b) negative parallel current, P = 1, ideal current amplifier, A^= 1, R, = 0, R, = oo, (c) negative parallel voltage, P=-1/(3R), ideal transresistance amplifier, R^=-3R, R,=0, R„=0, (d) negative series current, P=R/2, ideal transconductance amplifier, G^ = 2/R, R,= oo, R = oo, (e) negative series voltage, p=l /12 , ideal voltage amplifier, >4^= 12, R, = oo, R, - 0.

- 2 0 1 -


6.6 Stability of Feedback Amplifiers

In the above discussion, the nonfeedback amplifier (A circuit) was considered memoryless, for simplicity. Therefore, a zero phase shift between its output and input was assumed. Because of nonzero phase shift within any real amplifier, it is possible that a component of the feedback signal at some particular frequency/ is actually added rather than subtracted from die signal source. If this component is sufficiently large, the result is sustained oscillation at frequency/ -the circuit has become an oscillator or signal generator instead of an amplifier, and we say the circuit is unstable.

AiS)

Figure 6.16 Loop gain in a feedback amplifier

For concrete illustration of how oscillations can occur, consider a series voltage circuit of Figure 6.16, where sinusoidal voltages are indicated as phasors. With the switch in position 1, we have the feedback amplifier; position 2 gives the nonfeedback amplifier. Usually, P is a constant and does not contribute to the phase shift At midband frequencies, A((0) is real. Therefore, with die switch in position 1, the feedback phasor, Vf=\SA(<Q)Vi, has the same angle as Vf For sinusoidal excitation, this means that all voltages in die KVL equation, vs(t) = v,-(f) + Vy ( /) , have identical

phase angles; hence the subtraction v , (0 = v 5 ( 0 - v / ( 0 (6.31)

required for negative feedback.

Now, with the switch in position 2, suppose signal v,(/) = Vsin(2rf0t) = v,-(0 (6.32) is applied to the nonfeedback amplifier. Further, suppose that/ is such that A(fy is complex, that is

A(f0) = \A(f0)\zMf0) (6.33)

The output of the dependent source is then

vf ( 0 = $A(f0)\v sin[2nf0t + ftf0)] (6.34)

If die condition

*K/O) = 180° (6.35) happens to be satisfied at the excitation frequency/, men according to Equation (6.34), vit) is inverted relative to ?,(/), giving

V / ( 0 = -/3[A(f0)\Vsm[2nf0t} = -j^A(f0)\vs(t) (6.36)

Under these conditions, if the switch suddenly goes to position 1, the feedback signal reinforces, or adds to vs(t). The KVL "subtraction" at the input now gives

v , (0 = v,( / ) - vf{t) = v,(/) + ^ ( / o ) K ( 0 (6.37)

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When this occurs, we say we have positive feedback at frequency/. It is possible for feedback to be negative for midrange components and positive for frequencies outside the -3dB passband of A(f) where additional phase shift occurs.

With the switch in position 2 and sinusoidal excitation at frequency/, suppose in Equation (6.36)

that in addition to ^ ( / 0 ) = 180°, we also have

Mfoi * i (6-38> This amplitude condition leads to two interesting possibilities. Equality in Equation (6.38) implies vf (/) = V sm{l7rf0t +180°) = -V sm{2nf0t +180°) (6.39)

When this condition is satisfied, we can use Vj to replace Vf That is, once the circuit is running, we can flip the switch to position 1, turn off the external signal and use V{ as the input signal. Thereafter, there would be a sustained sinusoidal output at frequency/. Circuits that operate like this are called non-self-starting oscillators.

When the inequality occurs in Equation (6.38), Vf is identical in frequency and phase to Vs but greater in amplitude. In this case, the sinusoid of frequency/ increases in strength until circuit nonlinearities limit its amplitude. The result is a sustained oscillation with a periodic output waveform of fundamental frequency/. A circuit deliberately designed to operate in this way is called a self-starting oscillator. If such oscillations occur in an amplifier, we say the amplifier is unstable.

Taking into account the complex-valued gain of the nonfeedback amplifier, the closed-loop gain of a feedback amplifier, as given by Equation (6.1), can be described by

A{f)

Mf) For a given frequency/, if pVl(/5 = -1> the closed-loop gain becomes infinite. This means that even a very small input signal may cause an infinite amplifier response. Such an amplifier is unstable and may produce oscillations with no input signal. The amplitude and phase conditions associated with oscillations both are related to the complex product L(f)=6A(f) (6.41) called the loop gain. The loop gain L 0 is the total gain of the feedback loop from the amplifier input back to the point of signal subtraction, including all loading effects at input and output. Figure 6.16 shows that JL0 is the gain VJ Vs when the switch is in position 2, that is with the feedback loop open.

We now state the Nyquist stability criterion, a necessary and sufficient condition for feedback amplifiers to be unstable. If there exists any frequency/ such that the loop gain

L(f0) = jfl4(/0) = MZl80°, and M > 1 (6.42) then the amplifier is unstable, and there will be oscillations a t / . Otherwise, the amplifier is stable.

The justification for such a simple stability criterion is that random noise is present in every circuit with its power distributed over all frequencies - an infinity of tiny signal sources. For this reason, if there is any frequency whatsoever at which Equation (6.42) is satisfied, oscillations are inevitable even with no external signal applied to the circuit With an external signal applied, the oscillations simply superimpose upon i t

Af(f) = —^±L-!— (6.40) f U J l + QA(f) K }

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Gain Margin and Phase Margin. In design of feedback amplifiers, it is often helpful to consider Bode plots of me magnitude and phase of the loop gain $A(fi. For real and positive (3, its effect on the magnitude plot is simply to shift it vertically by 201og(P) and there is no effect on the phase plot. Thus the Bode plots of the loop gain $A(fi are the same as the Bode plots of the amplifier open-loop gain A(J) except for the vertical shift in the magnitude plot

An example of the Bode plots for a BJT amplifier is shown in Figure 6.17. In considering the stability of an amplifier, we examine the Bode plot for the loop gain $A(fi to find the frequency fGM fot which the phase shift is 180°. If the magnitude of the loop gain is less than unity at this frequency, die amplifier is stable. On die other hand, if the loop gain magnitude is greater than unity, the amplifier is unstable.

For a stable amplifier, the gain a t / ^ is less than unity in magnitude (it is negative when expressed in decibels). The amount mat the gain magnitude is below 0 dB is called die gain margin. The gain margin is illustrated in Figure 6.17. It can be shown that a gain margin of zero implies a pole lies on they'll) axis on the .r-plane. As gain margin becomes larger, the pole moves back into die left half of the .r-plane. In general, larger gain margin results in less ringing and faster decay of the transient response.

Another measure of stability that can be obtained from the Bode plots is the phase margin. Phase margin is determined at the frequency fm for which the loop gain $A(fPAj) is unity in magnitude (i.e., 201og | fyAffpy) \ — 0 dB). The phase margin is the difference between me actual phase and 180°. This is also illustrated in Figure 6.17.

As we noted earlier, we usually want to design feedback amplifiers to avoid ringing transient response and gain peaks in the frequency response. A. generally accepted rule of thumb is to design for a minimum gain margin qflOdB and a minimum phase margin of 45 °

For the amplifier illustrated by Figure 6.17, the frequency fGM is approximately equal to 30.1 MHz, and the gain margin equals to 21.7 dB. The phase margin can be determined at frequency fPM £ 3.1 MHz as being equal to 79°. Thus the example amplifier is stable and shows reasonable gain and phase margins.

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Often an amplifier is unstable for a given gain l /p \ which is especially true for multistage nonfeedback amplifiers that have complicated frequency response. We can make such amplifier stable by altering its open-loop gain curve A(J). Deliberately changing the frequency response of the nonfeedback amplifier to make a feedback amplifier stable is called frequency compensation. Some techniques have been developed for frequency compensation, such as pole addition used for operational amplifier design. However, the topic of frequency compensation is outside the scope of this textbook. The modern operational amplifiers, which are most often used as nonfeedback amplifiers, are internally compensated by adding an on-chip capacitor to introduce the dominant pole for compensation.

Exercise 6.8 Use PSpice to find gain margin and phase margin for the uA741 operational amplifier. Hint Run the .ac analysis and use evailib library.

6.7 Sinusoidal Oscillators

Oscillators are intentionally unstable circuits that serve as sources of electrical waveforms. There are two broad classes of oscillators: sinusoidal oscillators, which produce sinusoidal waveforms, and relaxation oscillators, which produce triangular, or rectangular, waveforms. Both classes of oscillators are widely used for time bases in test and measurement equipment, and for signal processing in analogue and digital communication systems. Here we concentrate on sinusoidal oscillators.

6.7.1 General Theory of Sinusoidal Oscillators

A sinusoidal oscillator has three functional parts, a phase shifter to establish the frequency of oscillation, a gain circuit to compensate for energy losses in the phase shifter, and a limiter to control the amplitude of the oscillations. The gain circuit might be an operational amplifier or a transistor amplifier. The phase shifter is typically an RC or JJC circuit. The limiter might be a diode, a thermistor, or a variable-gain amplifier. In some oscillators the basic functions are combined rather than relegated to individual subcircuits. For example, the internal capacitances of the transistor that provides gain might contribute to the phase shifter, and inherent transistor nonlinearities often provide the limiting. Common to all oscillator circuits is instability, which is best understood in terms of positive feedback theory.

Figure 6.18 General structure of a sinusoidal oscillator

The voltage-shunt feedback structure of Fig. 6.18 describes many sinusoidal oscillators. A voltage amplifier with gain A((o) = VJV-, provides the gain, and a feedback network described by P(co) = VjfV, is the phase shifter. An oscillator representation, such as Fig. 6.18, differs in several ways from a feedback amplifier diagram: (3 ((D) is defined without the notion of an input subtraction; the feedback network includes reactive elements to provide the phase shift required

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for positive feedback; and, of course, there is no external signal source. Nonlinearities that limit the signal amplitude invariably arise but do not appear in this linear model. The switch helps us examine the loop gain of the circuit.

Barkhausen Criterion. Assume that A((&) and (3(co) are defined in such a way that no loading occurs when the switch is closed. The Barkhausen criterion states that there will be sinusoidal oscillations at frequency C0o when the switch is closed, provided that with the switch open, the loop gain is Vf I Vt = A{o)0)P{co0) = M{co0)Z<f>{co0) = 1 (6.43)

When this condition is satisfied, a hypothetical sinusoidal signal generator V; attached to the input can be removed when the switch is closed, because the amplitude and phase of the signal fed back to the input are exactly those needed to replace this source. Since the Barkhausen criterion involves a complex-valued function, it implies two conditions for oscillations, a magnitude condition and a phase condition. We use the magnitude condition. M(C0o) — 1, as a test to determine whether oscillations can exist in a given circuit. This condition arises from the physical requirement that the amplifier provide sufficient gain to make up exacdy for energy losses in the circuit. If Af(C0o) exceeds one, the oscillator is self-starting, with the oscillation arising spontaneously and increasing in amplitude until nonlinearities cause a reduction in M((00)- Some oscillator circuits require- a signal generator for start-up; however, self-starting circuits are die norm. Provided that oscillations can occur, the phase condition <j)(co0)

= 0 determines die frequency of oscillation co0 of the circuit. This condition physically means the signal arrives back at the input exacdy in phase with itself.

6.7.2 RC Oscillators

Two important oscillators use RC phase-shifting circuits. Both are suitable for generating oscillations at frequencies from a few hertz to hundreds of kilohertz.

Wien Bridge Oscillator. Figure 6.19a shows the Wien bridge oscillator with a noninverting op amp circuit for its gain element. It is also called a bridge oscillator because the active element is imbedded in the RC bridge circuit, as we see by redrawing the circuit as Fig. 6.19b.

- 2 0 6 -


1/coC

co„+Aco

(c) Figure 6.19 Wien bridge oscillator: (a) schematic; (b) redrawn to sliow the bridge;

(c) illustration of frequency stability.

To find design equations for this or any oscillator, we apply the Barkhausen criterion. From Fig. 6.19a, P(ffl) is the transfer function

where Z, and Z2 are the impedances of the parallel RC and series RC circuits, respectively. Since A(a>) is the gain of the noninverting amplifier, Eq. (6.43) requires

1 + *2

A{G>0)P{a>0) = R \J 1 + j<»0CR

R + R +

1 = 1

1 + jo)0CR " jo)0C

where 00o is the frequency of oscillation. Simplifying leads to the expression

1 + Ri

A(a>0)/3(a>0) = *V j(o0RC

l + 3j0)oRC-a>lR2C2 = 1 (6.44)

For the expression to be real, the real part of the denominator must be zero. This gives the phase condition

o 1 fflo=-^2

Solving for frequency gives 1

(6.45)

(6.46)

Substituting this into Eq. (6.44) gives the amplitude condition

* I Thus if R2 > 2R, the circuit will oscillate; the inequality implies oscillations of increasing amplitude.

An important attribute of an oscillator is its frequency stability, its ability to maintain a frequency close to the design value. From Eq. (6.46) it is easy to show that

,a>, con SC°=SR°=-\

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not particularly low values. To give an intuitive idea of what is involved, Fig. 6.19c shows Eq. (6.46) as the graphical solution of the equation 1/toC = R. The dashed lines show how C0o

changes with variations in C. (Like the sensitivity expression, this diagram assumes that the resistor and capacitor pairs in die P circuit are matched.)

The next example demonstrates another useful way to investigate frequency stability of an oscillator - using SPICE to plot the phase of A(a>)p((o).

Example 6.4 Plot the phase shift of the loop gain for a Wien bridge oscillator with R = 1591.5 Q and C = 1000 pF. Find the change in frequency if the value of the shunt capacitor increases by 10%. Solution. Figure 6.20a shows the phase-shifting network - Fig. 6.20b the SPICE code. An asterisk marks the statement that describes C2 for the second run. Since Eq. (6.46) indicates an oscillation frequency of 100 kHz, the phase of P(<»), which is the phase of V(l), is plotted from 80 to 120 kHz.

The upper curve of Fig. 6.20c shows that the phase curve of the original oscillator is roughly linear over the range of the plot and crosses zero at 100 kHz. Increasing C2 by 10% gives die lower curve, showing that the frequency drops to about 95 kHz, a change of 5%. Thus

Sr° s -0.5 c 2

From the discussion of frequency stability and the example we conclude that die components diat contribute to the phase-shifting circuit should be of high quality and relatively insensitive to temperature and other environmental factors.

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Phase-Shift Oscillator. Figure 6.21a shows the phase-shift oscillator, The phase shifter consists of three RC sections, The gain element is represented as an ideal inverting amplifier with voltage gain -K.

To find amplitude and phase conditions from the Barkhausen criterion, we analyze the phase-shifting circuit of Fig. 6.21b. The transfer characteristic' of such a ladder circuit is most easily found by systematic analysis from output to input as suggested by the following equations.

' - * •

V: +

1

= 1+ ,V-jcoRC) '

2 R l K jaRC) R R 2 +

jcoRC) R

Continuing in this fashion finally gives vi 1

1 + jcoRC

Thus our design must satisfy

A{O)0){3{CD0) = ^ - =

5 1

o2R2C2+Jco3R3C3

-K 6 5 1

jco0RC~ CO2

OR2C2+J o)30R

3C3

= 1

1 +

To find the phase condition, we set the imaginary part of the denominator to zero. This gives an oscillation frequency of

^-7SE (6'47)

It is easy to show that the sensitivity to changes in R and C is the same as for the Wien bridge circuit. Substituting co0 from Eq. (9,39) into the preceding equation gives the gain condition

-K

TTir1

Thus the circuit oscillates for any K > 29.

A(<o)

Vi

Figure 6.21 Phase-shift oscillator: (a) circuit; (b) notation for computing p(co) for the oscillator

Exercise 6.9 Work out the first missing step in the preceding derivation of P(co); that is, find the expression for V2 in terms of Ve

- 2 0 9 -


Ans. Vj = jaRC (wRC)2 Vt

Amplitude Limitets. To make an oscillator self-starting and to allow for uncertainties in parameter values, we usually design the circuit so that the gain condition is exceeded. The amplitude of the oscillation then increases until some nonlinearity reduces the effective loop gain. If the signal amplitude becomes too large, the signal traverses a large segment of the nonlinear transfer characteristic of the active device causing the sinusoidal output waveform to be highly distorted. There are three basic approaches to controlling the signal amplitude while keeping the waveform reasonably sinusoidal.

When the gain condition is not gready exceeded, a design can rely on inherent transistor nonlinearities to limit the signal amplitude to a value corresponding to a reasonably undistorted sine wave. This does not produce very robust designs, however, because component values are rather critically related to waveform purity.

The second approach is to insert a special nonlinear component into the loop so that loop gain begins to diminish with signal amplitude while signal amplitude is still small. A thermistor with resistance that decreases- by self-heating, or a strategically placed diode are examples of components used for this purpose. An example is Fig. 6.22a, which shows the phase-shift oscillator of Fig. 6.21a with two diodes added for limiting. As long as the voltage across resistor Rj has peak amplitude less than 0.5 V the circuit is approximately the same as Fig. 6.22a; however, when output amplitude exceeds the forward-biased diode voltage, the diodes introduce a low resistance in parallel with ly This nonlinear resistance decreases with increasing amplitude, lowering the gain of the inverting amplifier and thereby limiting the oscillation amplitude. The following example investigates this limiter in some detail.

Example 6.5 Use PSpice to examine the output waveform of the phase-shift oscillator of Fig. 6.22a without and with the diode limiter. Values are R = 10 kQ, K = 50, and C = 3000 pF. Use a dependent source with gain 105 and input impedance of 1 MQ for the op amp.

Solution. Figure 6.22b is the PSpice code with diodes omitted. The initial condition statement, ".IC V(3) = 0.1," changes the initial voltage at node 3 to a nonequilibrium value to help start oscillations. Figure 6.22c shows the output without the diode statements. Since the linear circuit model has no limiting whatsoever, the oscillation amplitude quickly increases to tens of volts in the simulation. The output of a real opamp would be driven to its saturation limits, giving a highly distorted output voltage, a statement readily verified using the more realistic operational amplifier model, e.g. from the EVAL.LIB library.

Figure 6.22d shows the output with the diode statements present in the input code. The waveform quickly converges to a sinusoidal waveshape, with amplitude limited by the diodes and virtual ground to the ±0.5 V range.

+ Exercise 6.10 Calculate the expected oscillation frequency in Example 6.5. Ans. About 1.7kHz with limiting diodes omitted; 2.17 kHz with limiting diodes present.

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(c) (d) Figure 6.22 Phase-shift oscillator with diode limiter (a) schematicj-(b) PSpice code;

(c) output with limiting diodes omitted; (d) output with limiting diodes included.

For sinusoids of very high quality, a „linear amplifier" can provide limiting with gain that decreases as amplitude increases. In Fig. 6.23, the voltage-controlled amplifier is the gain element in a Wien bridge oscillator. A half-wave rectifier with a capacitive load (envelope detector) produces a dc control signal, Vc, proportional to signal amplitude. The follower isolates the control circuit from the RC bridge so amplitude and phase conditions are unchanged. As oscillation amplitude increases, Vc becomes more negative, and gain automatically decreases. The detector time constant RDCD should be several periods of the oscillator waveform.

Because it involves nonlinear operation, limiting always introduces "impurity" into the oscillator output waveform, causing the output to differ from the desired single-frequency sinusoid. One can describe any periodic waveform as a Fourier series

00

v ( 0 = T,A„cos(na)0t+ </>„) n=0

For an oscillator, the ideal output is the n = 1 term alone; terms for which n>2 are undesired impurity terms introduced by the limiter. The smaller these harmonic terms, the greater the

- 2 1 1 -


waveform purity. A useful measure of waveform impurity is the percent total harmonic distortion, THD, where

rms value of harmonic components THD = xl00%

rms value of fundamental frequency terms If we know the fundamental frequency^. = C0o/27t of the oscillator output, we can use PSpice to compute THD by adding a SPICE statement ".FOUR". This asks SPICE to compute amplitudes of the first nine Fourier series components and to use them to estimate THD. Adding the statement

.FOUR2.0E3V(1)

reveals that the output voltage waveform contains 6.22% distortion (look into the PSpice output file). The advantage of more sophisticated limiters like Fig. 6.23 is improved waveform purity. The oscillator designer is often required to meet a THD specification along with specifications of frequency and amplitude.

Figure 6.23 A limiter that uses sip~-' amplitude to control loop gain

6.7.3 LC Oscillators

Two important oscillators use the thtee-element n structure of Fig. 6.24a for the phase shifter. In Fig. 6.24b, a transistor biased for small-signal active operation provides the gain. From Fig. 6.24b,

00 (b) Figure 6.24 Oscillator configuration with three-element ladder phase shifter:

(a) general structure; (b) oscillator with transistor active element

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A(a>) =Vf = -gm[R0\\Zl\\{Z2 + Z3)]

and

z3

This gives the loop gain

i 4 (« ) f l » ) = ~ l s ^ Z? + Zi ZJ + Z? „ J + * A +1 *o Zl

The Barkhausen criterion requires

r Z 1 Z 2 + Z 1 Z 3 + i ? 0 ( Z 3 + Z 2 + Z 1 ) v ' If each impedance is an LC element, then Z,- = jXj, where X, = fflJL,- for an inductor and Xs

//(oC for a capacitor. Then

MZd> = SmKZfo = l z o o ( 6 4 9 ) M ^ -(XlX2+XlX3) + jR0(Xl+X2 + X3)

K >

Because die numerator is real, the phase condition is satisfied only if Xx + X2 + X3 = 0 (6.50) When Eq. (6.50) is satisfied, the gain condition in Eq. (6.49) reduces to

- g m V ^ ^ ( 6 5 1 )

X2+X3

We next use these conditions to study two specific oscillators.

Colpitts Oscillator. In the Colpitts oscillator, Z2 is an inductor and Z, and Z, axe capacitors as in Fig. 6.25. Substituting Z2 -faL.^ Z, = 1/foCt and Z} = 1//oC} into Eq. (6.50) gives

1 , 1 n

Solving for Of) gives the phase condition

2 C l + C 3 ffl»=^A (6-52)

which establishes the frequency of osculation. A second design condition comes from Eq. (6.51),

If!^=_s^al (6.53) 0>oL3

Substituting C0o from Eq. (6.52) leads to the second design equation

- 2 1 3 -


gmRo> (6.54)

which specifies the gain required for sustained oscillations.

Exercise 6.11 Compute the sensitivity of the resonant frequency of a Colpitts oscillator to L? Use your answer to estimate the actual resonant frequency of an oscillator designed to operate at 1 MHz if L2 is 12% high. Ans. -0.5, 940 kHz.

+12V +12V

+12V +12V

Figure 6.26 Colpitts oscillator realizations: (a) circuit diagram for a BJT oscillator; (b) small-signal equivalent for BJT circuit; (c) MOSFET oscillator

Example 6.6 The Colpitts oscillator of Fig. 6.26a has a transistor biased at 0.5 mA; pV = 120; Cc

is a large coupling capacitor. Find values for L^ C, and C, so the circuit oscillates atf, = 1 MHz. Ignore transistor capacitances.

Solution. Figure 6.26b shows the high-frequency equivalent circuit. At 0.5 mA,&, = 0.02 S and rn

- 6 kQ. The small-signal equivalent circuit is Fig. 6.26b, where

5.5*0 = ^ ||159*Q||112Afi

From Eq. (6.54),

(0 .02)(6xl0 3 ) = 1 2 0 > § -c l

(6.55)

- 2 1 4 -


and from Eq. (6.52),

LoCea = 7TT = 25.3 x 10" 1 5 (6.56) 1 ** (2 / r l0 6 ) 2

where Ctq = C,C3/(Ct + Q .

We now have two equations involving Ch Cs and L.2. In a FET design we would make an arbitrary choice of one component value; however, in a BJT design we must minimize the effect of r„, since our theory does not include a resistor in this location. Therefore, we select C3 such that its reactance is much smaller than rx = 5.5 kQ. This gives the third design equation. Using two orders of magnitude to assure rn has negligible effect gives

1 1

2*10 6C 3 " 100

orCjS2894pF.

5.5 xlO3

Since our design depends upon approximation, and since actual component values may not have exacdy the values we expect, we satisfy Eq. (6.55) by using C,/Cf = 75 instead of the limiting value of 120 to ensure self-starting oscillations. With C} previously selected, this gives

2894 Q = — = 38.6pF

and C,q = 38.1 pF. From Eq. (6.56)

25.3 x l O - 1 5 n,tre TT

L) = 7T = 0.65 5mH 38.6 x 10"1 2

The coupling capacitor Cc must have reactance << (£>oL2 at 1 MHz. Since the latter is 4.11 kfi, Cc

- 10 nF will do.

In Colpitts oscillators, an inductor called an RF choke usually replaces the collector or drain resistor. The choke coil is a short circuit for biasing purposes but presents an open circuit at RF (radio frequency) oscillator frequencies. When a choke is used, R, in Fig. 6.25 becomes the output resistance r„ of the transistor. The RF choke reduces power dissipation of the circuit and improves the purity of the output waveform.

Exercise 6.12 Figure 6.26c shows a MOSFET oscillator with drain biased at 1 mA through an RF choke. If transistor parameters are K = 4 mA/V2 , V, = 1.2 V, and VA = 70 V, find the condition for oscillation. Ans. 197 > C3/Ct.

We have seen that SPICE simulations are useful in verifying oscillator designs, examining distortion, and exploring sensitivity limitations. There are some practical simulation difficulties when large bypass and coupling capacitors are included in simulations along with components having short time constants. Sometimes there are convergence problems in the numerical algoriuims. Sometimes a very large number of oscillator cycles are required before the circuit settles into steady-state operation. The following example shows a way to avoid time constant problems in oscillator simulations. An initial dc analysis determines the voltages across the large capacitors, which we then replace by dc voltage sources of appropriate polarity.

- 2 1 5 -


Example 6.7 Use PSpice to show how the oscillations arise in die circuit designed in Example 6.6. Solution. The SPICE code of Fig. 6.27a uses values determined in die design of Fig. 6.26a. Following initial dc analysis, capacitors CE and Cc were replaced, respectively, by sources VEE and VCC. Because the oscillation period is expected to be approximately 1 Lis, the initial .TRAN statement runs the simulation for 30 periods to show die build-up of oscillations.

Figure 6.27b shows that die oscillation is superimposed upon a 9.2 V dc collector voltage. By measuring die average period of the last nine cycles from the output data, we find that^ = 0.9414 MHz. The oscillations reach steady-state conditions after about 15 Lis; however, longer times should be expected if die capacitors CE and Cc are not replaced by voltage sources.

This simulation demonstrates limiting performed by inherent transistor nonlinearities rather man by a special limiter circuit Because we used C3/C, = 75 in our design, the loop gain is rather high and die resulting oscillation has peak amplitude of about 3.5 V. Harmonic distortion is about 13%.

Hartley Oscillator. The Hartley oscillator, Fig. 6.28, is Fig. 6.24b with inductors for Z, and Z, and a capacitor for Z? For diis circuit, Eq. (6.50) gives

(00L\~—— + G)oL3=0 tf>oc2

which establishes the oscillator frequency 1

<°o = C2(Ll + L3)

Substituting reactances into Eq. (6.51) gives

(6.57)

216-


-ZmKOok ZmRo<°oL7>C2

<0OL3-1

0>„C \-<oz

0I^C2

> 1

o«-2

or (gmR0 + l)^L3C2 > 1

Substituting Eq. (6.57) into this expression and simplifying gives the gain condition

(6.58)

Figure 6.28 Hartley oscillator small-signal circuit

6.7.4 Quartz Crystal Oscillators

Frequency Stability. We know that frequency stability is an important consideration in an oscillator. The Colpitts and Hartley design equations show that in these circuits the frequency depends entirely upon the reactive components in the resonators. We are therefore concerned with variations in these components due to aging, temperature, and tolerances, especially since transistor capacitances are sometimes part of the phase shifter.

Reactance 1/(0 C.

Figure 6.29 Frequency stability of Colpitts oscillator

By defining Ctq = C,C}/(C, + C,) for the Colpitts oscillator, we can view <a0 in Eq. (6.52) as that frequency where reactances (aL2 and / /©C^ are equal, as illustrated by the bold curves in Fig. 6.29. The light curves show how variations in Cf1 and L2 affect the frequency of oscillation. Many applications, such as radio transmitters or electronic watches, call for oscillators having long-term frequency variations of the order of 1 part per million (1 ppm) or less. Even well designed RC or LC oscillators typically have long-term variations of 100 to 1000 ppm. When greater frequency stability is required than discrete capacitance and inductance can realize, quartz crystals are used in the phase shifting circuit

Crystal Resonator. Certain materials, such as quartz, display the piezoelectric effect. If we apply an electric field to these materials, forces on the ions in the crystal lattice deform the material. For

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example, consider a bar of quartz firmly held at the left-hand end but free to flex up and down at the right-hand end as illustrated in Fig. 6.30. Conducting, e.g. silver, electrodes are plated to the upper and lower faces of the bar. Under suitable conditions, voltage applied to the electrodes forces the right-hand end of the bar to move upward. On the other hand, voltage of the opposite polarity flexes the bar downward. The piezoelectric effect is reciprocal. In other words, if the terminals are open circuited and a force is applied to flex the bar, a voltage appears across the electrodes.

\

4 Figure 6.30 Simplified physical structure of piezoelectric crystal

In quartz crystals, slight; reversible, physical deformations result in an electrical voltage, and, conversely, applied voltage produces physical deformations. The crystal is thus an electromechanical device in which electrical excitation and mechanical deformation are tightly coupled, a feature that makes the crystal highly useful as a transducer. Another unusual property of a quartz crystal is that, once set in motion, its energy losses per cycle are very slight. Its electrical equivalent circuit is an LC resonant circuit like Fig. 6.31a, in which the energy losses of the crystal are embodied in the crystal parameter r, and C is associated with the external holder that makes electrical contacts to the quartz. Representative component values for a 90 kHz crystal are L = 137 H, C = 0.0235 pF, r- 15 kQ and C - 3.5 pF.

When used as a frequency-determining element, the crystal is mounted so that it can vibrate freely at die desired frequency. The mechanical vibrations result in an ac current in the external circuit. In an oscillator circuit, an amplifier maintains the vibrations. Because quartz is an extremely stable material, frequency variations due to changes in power-supply voltage or temperature are very small compared to those of UZ or RC oscillators.

C

(a) (b) Figure 6.31 Crystal resonator: (a) schematic symbol and electrical equivalent circuit;

(b) approximate reactance curve

We now derive an expression for the reactance of the quartz crystal that allows us to compare the crystal resonator characteristics with the JJC reactance curves of Fig 6.29. Near resonance where

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me crystal is used, r « ©L. With resistance omitted to simplify die development, the impedance of the crystal in Fig. 6.31a is

jd)L + 1 1

Z = j<uC) joaC -o)2LC + l

jcoL + 1 1 - ja>5LCC+ja>(C + C )

jooC jaC where the second expression follows from multiplying numerator and denominator by {/<aQ{/0)C'). We next factor LC from the numerator and -jCoLCC from the denominator. This gives

Z = jX(a>) =

where

-LC a>2-LC -J <Q* 0)r

-jcoLCC 2_C + C aCCa2 -ml (6.59)

LCC

a''7m and (Op = I LCC

\c+c define die series and parallel resonant frequencies of the crystal, respectively. Figure 6.31b is a sketch of Eq. (6.59). Intuitively, as oo approaches G>s, JL and C go into series resonance, producing zero reactance. Above this frequency, the inductive reactance dominates the L/C branch, and this reactance then goes into parallel resonance with C at G)p. The series and parallel resonant frequencies are very close together in a quartz crystal, 88700 and 88998 Hz, respectively, for the nominal 90 kHz crystal described earlier. Thus the curve segment between series and parallel resonance is nearly a vertical line. Furthermore, in a properly cut quartz crystal, Op varies by only a few hundred ppm over a wide range of temperature. As we see next, this leads to a very stable oscillator frequency of frequency C0o = (Dp.

X(<o) Inductive

Capacitive

(b) Figure 6.32 Pierce oscillator (a) equivalent circuit;

(b) sensitivity of oscillator frequency to capacitor variation

Pierce Oscillator. The crystal-controlled Pierce oscillator is a Colpitts oscillator with inductor replaced by a crystal as in Fig. 6.32a. Substituting the reactance of the crystal X(©) for the reactance of I^in Eq. (6.50) gives

The frequency of oscillation is thus the frequency (Do that satisfies

UJar^eq

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The graphical construction of Fig. 6.32b shows why the oscillation frequency of the Pierce oscillator is virtually independent of variations in resonator capacitance. Another popular crystal oscillator circuit is obtained by replacing one of the inductors in a Hartley oscillator with a crystal.

Usually, a quartz crystal can vibrate in many different ways called modes. For example, returning to die bar of quartz fixed at one end, the bar could flex up and down. On the other hand, it could flex sideways. If the widdi and height of the bar are different, the frequency for the sideways motion is different from that of vertical flexure. Another possibility is for the bar to twist around its axis.

End stationary

Stationary A point

(c) Third overtone Figure 6.33 Overtone vibrations

Commonly, there are overtone vibrations for each mode. For example, several overtone vibrations are shown for vertical flexure of a bar in Fig. 6.33. The lowest frequency is called fundamental. The «th overtone frequency is nearly — but not exactly — n times the frequency of the fundamental vibration. {The amplitudes of vibrations in Fig. 6.33 are exaggerated for clarity. Actual amplitudes of vibration in quartz crystal are much smaller.)

The flexure modes that are illustrated in Fig. 6.33 are not often used for crystals. (An exception is 32,768-Hz crystal used in electronic watches.) We have discussed this mode mainly because it is easy to illustrate. Typical high-frequency crystals use shear modes. Crystals are practical as

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frequency determining elements for frequencies in die approximate range from 10 kHz to 200 MHz. Below about 30 MHz, the fundamental mode is used. At higher frequencies, overtones are used.

6.8 Summary

Adding negative feedback to an amplifier reduces sensitivity to parameter variations, increases bandwidth, and reduces nonlinear distortion. We can also use feedback to increase or decrease midrange input resistance and (independendy) increase or decrease output resistance. All improvements involve multiplication or division by the improvement factor 1 +Ap. The closed-loop gain is simultaneously reduced by diis factor; however, diis counts as an improvement once we realize that die new, lower, gain usually approximates 1/p. By using resistor ratios for P we can control this closed-loop gain to ±1%.

With four classes of feedback, we can make our nonfeedback amplifier more closely resemble an ideal voltage, current, transresistance, or transconductance amplifier at midrange frequencies. For each class of feedback, the definition of gain, A, corresponds to that of the ideal amplifier. The origin of the feedback signal defines the output circuit of the feedback amplifier-voltage (current) feedback lowers (raises) output resistance, making the original amplifier more closely resemble a dependent voltage (current) source. The way the feedback signal subtracts from die input signal determines die nature of die input circuit. Series (shunt) feedback involves a voltage (current) subtraction that increases (decreases) input resistance. This makes die amplifier better represent a voltage- (current-) controlled dependent source.

The resistive P circuits we use in practical feedback amplifiers introduce loading at input and output. To apply ideal feedback equations to this case, we represent die p circuit by a two-port equivalent - the one that corresponds to the particular kind of feedback we employ.

To successfully implement feedback or evaluate die designs of others, we must be able to recognize some standard practical feedback topologies. The difference amplifier structure is a voltage-series feedback arrangement that bases the input subtraction on an amplifier's differential input. In classical voltage-feedback circuits, as in the difference amplifier topology, the output node of die nonfeedback amplifier connects direcdy to the P circuit. Current feedback features indirect sensing of output current using an unbypassed emitter or source resistor. Classical series feedback involves a connection from die P circuit to an unbypassed emitter or source resistor in the input circuit of the nonfeedback amplifier; shunt feedback uses a direct connection from die P circuit to an input node of the nonfeedback amplifier. The A circuit must provide a 180° phase shift to facilitate the current subtraction needed for shunt feedback; zero phase shift is required for series feedback.

To ensure that our feedback amplifier does not oscillate, we examine die magnitude and phase of its loop-gain function, the product of the A circuit and P circuit gains. If diere exists no frequency where the loop gain is negative and also greater than one in magnitude, the feedback amplifier will be stable. Gain and phase margins are two measures of the degree of stability that might be included in design specifications. If die feedback amplifier is destined to be unstable, we must compensate it by modifying die open-loop gain curve to produce appropriate gain and phase margins. This process, called frequency compensation, usually involves adding capacitance to reduce die bandwiddi of die A circuit.

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Oscillators are circuits intentionally made unstable by positive feedback. Common to all oscillators are phase shifters, which determine the frequency of oscillation, gain circuits to make up for energy losses in the phase shifters, and limiters to control oscillation amplitude. The Barkhausen stability criterion, based upon conditions for positive feedback, gives a complex valued equation for any oscillator. The Barkhausen conditions give an equation for the frequency of oscillation and an amplitude condition that must be satisfied for oscillations to occur. In this chapter only oscillators with sinusoidal output waveforms were considered. Phase-shift and Wien bridge oscillators use RC circuits for phase shifters; Colpitis and Hartley oscillators employ tuned circuits.

Important considerations in sinusoidal oscillator design are the harmonic purity of the waveform and frequency stability, the relative insensitivity of the oscillation frequency to variations in circuit parameters, and environmental factors. Total harmonic distortion measures the impurity of the output waveform in terms of the amplitudes of undesired harmonics present. The sensitivity definitions are useful aids in oscillator analysis and design. SPICE simulations help us address both distortion and sensitivity issues in a practical fashion. Quartz crystals introduced into oscillator phase shifters result in great improvements in frequency stability.

Notes

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References

1. D. Christiansen (Ed.), Electronics Engineers'Handbook, McGraw-Hill, 1996. 2. A. R. Hambley, Electronics, Macmillan, 1994. 3. J. Keown, PSpice and Circuit Analysis, Maxwell Macmillan, 1991. 4. N. R. Malik, Electronic Circuits, Prentice Hall, 1995. 5. R Mauro, Engineering Electronics, Prentice Hall, 1989. 6. J. Millman and A. Grabel, Microelectronics, 2nd edition, McGraw-Hill, 1987. 7. J. F. Morris, Introduction to PSpice, Houghton Mifflin, 1991. 8. C. J. Savant, M. £J. Roden and G. L. Carpenter, Electronic Design, The Benjamin/Cummings,

1991. 9. J. Scott, Analog Electronic Design, Prentice Hall, 1991. 10. A. S. Sedra and K. C. Smith, Microelectronic Circuits, Saunders College, 1992. 11. W.J. Tompkins (Ed), Biomedical Digital Signal Processing, Prentice-Hall, 1993. 12. P. W. Tuinenga, SPICE: A Guide to Circuit Simulation and Analysis Using PSpice, Prentice Hall,

1992.

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Analog Electronics /Review Questions

Review Questions

Chapter 1: introduction

1.1 List five examples of electronic systems. Try to think of new examples that have not been mentioned in this chapter.

1.2 Discuss briefly what the spectrum of a signal is and why it is important. 1.3 Give five examples of useful signals and their spectra. 1.4 List five types of functional blocks found in electronic systems. 1.5 Discuss how analog signals can be converted to digital form. 1.6 List the relative advantages of digital systems compared to analog systems and vice versa. 1.7 Explain why at certain frequencies a physical resistor can be perceived as a capacitor or

inductor.

Chapter 2: Amplifiers

2.1 How does an inverting amplifier differ from a noninverting one? 2.2 Draw the voltage amplifier model. Is the gain parameter measured under open-circuit or

short-circuit conditions? Repeat for current, transconductance and transresistance models. 2.3 What are "loading effects" in an amplifier circuit? 2.4 Draw the cascade connection of two amplifiers. What is the voltage gain of the cascade

connection in terms of the voltage gains of the individual stages? 2.5 Define the efficiency of a power amplifier. What form does the dissipated power take? 2.6 How is power gain converted to decibels? Voltage gain? 2.7 Give the input and output resistances of an ideal voltage amplifier. Repeat for other ideal

amplifier types. 2.8 Sketch the gain magnitude of a typical dc-coupled amplifier versus frequency. Repeat for an

ac-coupled amplifier. 2.9 How is a narrowband amplifier different from a wideband one? 2.10 Discuss the Miller theorem. Explain its significance to circuit analysis. 2.11 What are the requirements for the gain magnitude and phase of an amplifier so that linear

distortion does not occur? 2.12 Sketch the pulse response of an amplifier, showing the rise time, overshoot, ringing and tilt.

Give an approximate relationship between rise time and the upper half-power frequency of a broadband amplifier. Give an approximate relationship between percentage tilt and the lower half-power frequency.

2.13 What is the compensated oscilloscope probe? What for is it used in electronics? 2.14 What is harmonic distortion? What causes it? Is it a problem for narrowband amplifiers?

Explain. 2.15 Discuss briefly intermodulation and crossmodulation.

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Chapter 3: Diode Circuits

3.1 Draw the circuit symbol for a diode. Label the anode and the cathode. Make a reference to die p-type and »-type regions of a corresponding/^ junction.

3.2 Draw the volt-ampere characteristic of a typical diode and label the various regions of operation.

3.3 What is a Zener diode? For what is it typically used? What are two other names for it? 3.4 Draw a circuit diagram of a simple voltage regulator. 3.5 Draw the volt-ampere characteristic of an ideal 5.8-V Zener diode. 3.6 Write the Schockley equation and define all the terms. 3.7 How does the forward voltage of a silicon diode change with temperature for a fixed value of

current? Explain. 3.8 What is an ideal diode? Draw its characteristic. 3.9 After solving a circuit with ideal diodes, what check is necessary for diodes initially assumed

to be on? Off? 3.10 If a nonlinear two-terminal device is modeled by die piecewise-linear approach, what is die

equivalent circuit of die device for each linear segment? 3.11 A resistor Ra is in series with a voltage source Va. Draw the circuit. Label die voltage across

die combination as v and the current as /. Draw and label the volt-ampere characteristic (I versus v).

3.12 Draw the circuit diagram of a half-wave rectifier for producing a nearly steady dc voltage from an ac source. Include a transformer to adjust the voltage level. Draw two different full-wave circuits.

3.13 What is a clipper circuit? Draw an example circuit diagram including component values, an input waveform, and the corresponding output waveform.

3.14 Repeat Question 3.13 for a clamp circuit. 3.15 Draw die circuit diagram of a two-input diode OR gate. Repeat for an AND gate. 3.16 Logic 1 voltages for a digital system are defined as being larger than 3V. Consider a number

k of two-input OR gates employing silicon diodes. Connect one input of each gate to the ground (logic 0). Cascade the gates such diat the output of a gate is connected to the remaining input of another gate that follows in the cascade. Apply the 5-V voltage to die input and measure die output of the cascade. At what value of k die output voltage can not be recopiized as logic 1?

3.17 Try to construct a logic inverter using diodes. Can you succeed? Based on results you obtained answering Questions 3.16 and 3.17, describe two serious drawbacks of diode logic circuits.

3.18 Of what does die small-signal equivalent circuit of a diode consist? 3.19 How is the dynamic resistance of a nonlinear circuit element determined at a given

operating point? 3.20 Sketch die voltage and current waveforms corresponding to large-signal diode switching.

Define and explain the delay times in die diode response. 3.21 What is die Schottky diode? What are its properties and applications? 3.22 Explain die difference between the photodiode and solar cell. 3.23 What is die construction of an optical isolator? List applications of diis device diat are

known to you.

Chapter 4: FET Circuits

4.1 Sketch the simplified physical structure of an »-channel JFET. Label the terminals and die channel region. Draw the corresponding circuit symbol.

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4.2 In normal operation, what bias condition exists between gate and channel of JFET? 4.3 Define the pinch-off voltage and IDSS of a JFET. 4.4 Write an equation for the drain current of a JFET in the saturation (pinch-off) in terms of

device voltages. 4.5 Sketch the characteristics of an «-channel JFET. Label the saturation, linear and cutoff

regions. Repeat for the/>-channel device. 4.6 Give the ranges of vGS and vGD in terms of the pinch-off voltage Vp for each region (cutoff,

saturation and linear) of an »-channel JFET and depletion MOSFET. 4.7 Sketch the physical structure of an ^-channel depletion MOSFET. Label the terminals and

the channel region. Draw the corresponding circuit symbol. Repeat for a ^-channel enhancement MOSFET.

4.8 Explain the physical origin of the variations in FET parameters with temperature. 4.9 What is "gate protection" for a MOSFET? Why is it necessary? 4.10 Draw the load line for a simple FET amplifier. 4.11 Why does nonlinear distortion occur in FET amplifiers? 4.12 Draw the diagram of the fixed-bias circuit, the self-bias circuit and the fixed- plus self-bias

circuit for a FET. In general, which circuit maintains the most constant drain current from device to device? Which shows the greatest variation? Which is used for enhancement devices? Why?

4.13 Draw the small-signal equivalent circuit for the FET including r^ 4.14 Give definitions of^n and rrf as partial derivatives. 4.15 Draw the circuit diagram of a resistance-capacitance coupled common-source amplifier.

Repeat for the source follower. Which amplifier would be used if a voltage gain magnitude larger than unity is needed? Which would be used to obtain low output resistance?

4.16 Draw the circuit diagram of the FET amplifier most useful if extremely high input resistance is required.

4.17 What is the function of coupling capacitors? With what are they replaced in a midband small-signal equivalent circuit? In general, what effect do the coupling capacitors have on the gain of the amplifier as a function of frequency?

4.18 Compare gain, bandwidth, input and output impedance values of basic FET amplifier configurations.

4.19 What is the value of ^n for VDS=0? Draw the small-signal equivalent circuit at this bias point. For what applications is the FET used at this bias point?

4.20 Draw the circuit diagram of a CMOS inverter. Repeat for a two-input NOR gate. 4.21 Of what does the input impedance of a CMOS inverter consist? 4.22 What is the static power consumption of CMOS gates? 4.23 Draw the circuit diagram of the CMOS transmission gate. 4.24 Draw the dynamic circuit model of the »-channel JFET. Repeat for/(-channel device and all

kinds of MOSFET transistors. 4.25 Explain how the channel-length modulation effect is incorporated into the SPICE model of

the FET.

Chapter 5: BJT Circuits

5.1 Draw the circuit symbol for an npn BJT. Label the terminals and the currents. Choose reference directions that agree with the true current direction for operation in the active region.

5.2 Repeat Question 5.1 for zpnp transistor. 5.3 In normal operation, which type of bias (forward or reverse) is applied to the emitter-base

junction? The collector-base junction?

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5.4 To forward-bias apn junction, which side of the junction should be connected to the positive voltage?

5.5 Write the Shockley equation for the emitter current of an npn transistor. 5.6 Give the definition of a and p for a BJT. What bias conditions for each junction are assumed

in diese definitions? 5.7 Sketch the input characteristic curve for a typical small-signal silicon npn BJT at room

temperature. Sketch the output characteristic curves if P = 100. Isabel the cutoff, active and saturation regions.

5.8 Draw the load lines on the input and output characteristic planes of the npn BJTfor a simple amplifier. Repeat for thepnp device.

5.9 Why does distortion occur in BJT amplifiers? 5.10 Sketch the output characteristics of a BJT, illustrating the Early voltage and collector

breakdown. 5.11 Explain the base-width modulation effect. 5.12 Discuss the BJT parameter variation with temperature. 5.13 What is the typical extreme variation of P from unit to unit for a given type of BJT? 5.14 How does vBh vary with temperature for a fixed emitter current? Assume a small-signal

silicon transistor. 5.15 Draw the large-signal dc circuit model for a silicon npn transistor in the active region at

room temperature. Include the constraints of currents and/or voltages that guarantee operation in the active region. Repeat for the saturation region. Repeat for the cutoff region.

5.16 Repeat Question 5.12 for &pnp transistor. 5.17 In the active region, how is the base-collector junction biased (forward or reverse)? How is

the base-emitter junction biased? 5.18 Repeat Question 5.14 for the saturation region. 5.19 Repeat Question 5.14 for the cutoff region. 5.20 Briefly discuss the procedure for dc analysis of a BJT circuit using the large-signal circuit

models. 5.21 Draw the fixed base bias circuit. What is the principal reason that this circuit is unsuitable

for mass production of amplifier circuit? 5.22 Draw the four-resistor bias circuit for the BJT. Give the rule-of-thumb design guidelines for

this circuit. 5.23 Whv are coupling capacitors often used to connect the signal source and the load to

amplifier circuits? Should coupling capacitors be used if it is necessary to amplify dc signals? Explain.

5.24 Draw the small-signal equivalent circuit for the BJT. 5.25 Give the formula for determination of rx, assuming that P and the Q-point are known. 5.26 Draw the circuit diagram of a common-emitter amplifier circuit that uses the four-resistor

biasing network. Include a signal source and a load resistance. 5.27 Repeat Question 5.23 for an emitter follower. What resistance did you omit from the bias?

Why? 5.28 For a small-signal midband analysis of an amplifier, with what do we replace the coupling

capacitors? Dc voltage sources? Dc current sources? Very large inductors? 5.29 Outline the small-signal analysis procedure to find the output resistance of an amplifier. 5.30 What are three important features in the structure of a BJT for high P (i.e., for the base

current to be small compared to the collector current in the active region of operation)? , 5.31 Sketch the common-emittet input characteristics of an npn transistor. Indicate the effect of

base width modulation. 5.32 Prepare a table showing the bias conditions (forward or reverse) for the collector junction in

each of the four regions of operation of a BJT.

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5.33 Draw the common-emitter h-parameter equivalent circuit for the BJT, labeling each parameter.

5.34 Draw the hybrid-7l model for the BJT. Characterize each element of the circuit. 5.35 Discuss the P dependence of frequency. 4.26 Compare gain, bandwidth, input and output impedance values of basic BJT amplifier

configurations. 5.36 What is the cascode amplifier? What are its properties? 5.37 Draw the Ebers Moll dynamic model for the BJT. Characterize each element of the model. 5.38 Draw the circuit diagram of an RTL inverter. Sketch a positive input pulse and the

corresponding output voltage. Label the delay time, the rise time, the storage time, and the fall time.

5.39 For fast switching, do we want a BJT with a thin base region or a thick base region? Explain.

5.40 Draw the circuit diagram of an RTL inverter including a speed up capacitor and a Schottky clamp diode. Discuss how the Schottky clamp diode improves switching time.

5.41 What is the function of the rt buried layer under the collector region of an npn BJT on an IC?

Chapter 6: Feedback Circuits

6.1 List four benefits that potentially result from the use of negative feedback. 6.2 What problems are associated with positive feedback in amplifiers? 6.3 Under what condition is feedback able to reduce nonlinear distortion? Draw the feedback

amplifier circuit and derive appropriate expression. 6.4 Define signal-to-noise ratio. Under what condition is feedback able to improve signal-to-

noise ratio? Draw the feedback amplifier circuit and derive appropriate expression. 6.5 Define the following terms: voltage feedback, current feedback, series feedback and parallel

feedback. 6.6 Describe a way to test a circuit for the presence of voltage feedback. Draw a schematic

diagram of such a feedback circuit. Repeat for current feedback. 6.7 In a series feedback, we usually consider the input signal to be a voltage. Explain why. In a

parallel feedback we usually consider the input signal to be a current. Explain why. 6.8 Sketch the circuit diagram of the simple class B amplifier that was discussed in this chapter.

What causes crossover distortion in this circuit? 6.9 List four types of feedback and give the appropriate amplifier gain parameter for each type.

Also give the units of P for each type. 6.10 What type of negative feedback should be employed to increase input impedance? To

reduce input impedance? 6.11 What type of negative feedback should be employed to make the amplifier output behave

as a nearly ideal voltage source? As a nearly ideal current source? 6.12 What type of (negative) feedback should be used to obtain a nearly ideal current amplifier?

Transconductance amplifier? Voltage amplifier? Transresistance amplifier? 6.13 Draw the circuit diagram of a negative feedback amplifier, including a resistive feedback

network for series current feedback; for parallel current feedback; for series voltage feedback; for parallel voltage feedback. In each case give the value of the feedback ratio in terms of the resistor values. Assume an amplifier having a differential input.

6.14 In series feedback we usually try to select small values for the resistors in the feedback network. Explain why.

6.15 In parallel feedback we usually try to select large values for the resistors in the feedback network. Explain why.

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6.16 In voltage feedback we usually try to select large values for the feedback resistors. Explain why.

6.17 In current feedback we usually try to select small values for the feedback resistors. Explain why.

6.18 Define gain margin and phase margin for a feedback amplifier. 6.19 What are the rule-of-thumb minimum values of gain margin and phase margin used in

design of feedback amplifiers? 6.20 Can a single-pole amplifier become unstable if negative feedback having constant feedback

ratio P is employed? 6.21 Explain the Barkhausen criterion of oscillations in a feedback circuit. 6.22 Draw the circuit diagram of a Wien-bridge oscillator. Explain its operation. 6.23 Draw the circuit diagram of a Wien-bridge oscillator. Explain its operation. 6.24 Explain the role of amplitude limiters in oscillator circuits. Draw schematic diagrams of

diode and FET limiters circuits used to stabilize the output waveform generated by a Wien-bridge oscillator.

6.25 Draw a block diagram of LC oscillators. Modify it to obtain (a) Collpits, and (b) Hartley oscillator.

6.26 Briefly describe the piezoelectric effect. 6.27 What is a crystal as the term used in relation to oscillator circuits? 6.28 Draw the equivalent circuit of a crystal and sketch its reactance versus frequency. Label the

series resonant frequency and the parallel resonant frequency. 6.29 A crystal has a fundamental mode at 10 MHz. What is the approximate frequency of the

second overtone? Third overtone? 6.30 Briefly discuss the way to use quartz crystal to stabilize the frequency of a conventional LC

oscillator.

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Analog Electronics /Problems

Problems

Chapter 1: Introduction

1.1 A sinusoidal signal source has an open-circuit voltage of 10 mV and a short-circuit current of 10 u A. What is the source resistance?

1.2 Give expressions for the sine-wave voltage signals having: (a) 10-V peak amplitude and 10-kHz frequency, (b) 120-V rms and 60-Hz frequency, (c) 0.2-V peak-to-peak and 1000-rd/s frequency, (d) 100-mV peak and 1-ms period.

1.3 Illustrate the composition of a square-wave signal by sketching the first four terms of its Fourier series and then by performing graphical summations.

1.4 For a square-wave audio signal, what fraction of the available signal energy is perceived by an average adult listener of age 40 whose hearing extends only to 16 kHz?

1.5 What fraction of the energy contained in a square wave of frequency / and peak-to-peak amplitude U is contained in the harmonic at frequency 9ft

Chapter 2: Amplifiers

2.1 A signal source with an open-circuit voltage of Vs = 2mV rms and an internal resistance of 50kA is connected to the input terminals of an amplifier having an open-circuit voltage gain of 100, an input resistance of lOOkQ and an output resistance of 4Q. A 4-fi load is connected to the output terminals. Find the voltage gains A„ = vjvt and Ar - vjvt Also find the current gain and the power gain.

2.2. A certain amplifier has an open-circuit voltage gain of unity, an input resistance of 1MQ, and an output resistance of 100Q. The signal source has an internal voltage of 5mV rms and an internal resistance of lOOkfl. The load resistance is 50£X If the signal source is connected to the amplifier-input terminals and the load is connected to the output terminals, find the voltage across the load and the power delivered to the load. Next consider connecting the load direcdy across the signal source without the amplifier and again find the voltage and power. Compare the results. What do you conclude about the usefulness of a unity-gain amplifier in delivering power to the load?

2.3. An amplifier has an open-circuit voltage gain of 100. With a 10-kQ load connected, die voltage gain is found to be only 90. Find the output resistance of the amplifier.

2.4. The output voltage v, of the circuit of Fig. P2.4 is lOOmV with the switch closed. With the switch open, the output voltage is 50mV. Find the input resistance of the amplifier.

4 - r " T - 4 - ( >

v,(0

— c

Figure P2.4

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2.5. Two amplifiers have the characteristics shown in Table P2.5. If the amplifiers are cascaded in order A-B, find the input impedance, output impedance and an open-circuit voltage gain of the cascade. Repeat if die order is B-A.

2.6 A certain amplifier has an input voltage of lOOmV rms, an input resistance of lOOkfl, and produces an output of lOVrms across an 8-Q resistance. The power supply has a voltage of 15V and delivers an average current of 2A. Find the power dissipated in die amplifier and the efficiency of the amplifier.

2.7. An amplifier has an input voltage of lOmV rms and an output voltage of 5V rms across a 10-Q load. The input current is l^iA rms. Find the input resistance. Find the voltage gain, current gain and power gain as ratios and in decibels.

2.8. An amplifier has a voltage gain of 30dB and a current gain of 70dB. What is the power gain in decibels? If the input resistance is 100k£2, what is the load resistance?

2.9. Find the voltage across a 50-fi resistance corresponding to (a) lOdBV, (b) -30dBV, (c) 10 dBmV, (d) 20dBW.

2.10. Find the power levels in watts corresponding to (a) 20dBm, (b) -60dBW, and (c) lOdBW.

2.11. An amplifier has an input resistance of lOOCt, an output resistance of 10Q, and a short-circuit current gain of 500. Draw the current and voltage amplifier models for the amplifier, including numerical values of all parameters. Repeat for transconductance and transtesistance models.

2.12. Amplifier A has an input resistance of 1MQ, an output resistance of 200Q and an open-circuit transresistance gain of 100MQ. Amplifier B has an input resistance of 50fi, an output resistance of 500k£2 and a short-circuit current gain of 100. Find the voltage amplifier model for the cascade of A followed by B. Find the corresponding transconductance amplifier model.

2.13 Repeat Problem 2.12 if the order of the cascade is changed to B-A.

2.14. An ideal transconductance amplifier having a short-circuit transconductance gain of 0.1 S is connected as shown in Fig. P2.14. Find the resistance JR,,= vjix seen at the input terminals.

Figure P2.14

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2.15. Repeat Problem 2.14 if the amplifier has an input resistance of lkft, an output resistance of 20Q and an open-circuit transresistance gain of 1 Okfi.

2.16. An amplifier has an input resistance of 1Q, an output resistance of 1Q, and an open-circuit voltage gain of 10. Classify this amplifier as an approximate ideal type and find the corresponding gain parameter. In deciding of an amplifier classification, assume that the source and load resistances are on the order of lkQ.

2.17. Repeat Problem 2.16 if the input resistance is 1MQ, the output resistance is lMft, and the open-circuit voltage gain is 100.

2.18. In a certain application, an amplifier is needed to sense an open-circuit voltage of a source and force current to flow through a load. The source and load resistances are variable. The current delivered to the load is to be nearly independent of both the source resistance and load resistance. What type of amplifier is needed? If the source resistance varies from 1 to 2kQ and this causes a 1-% decrease in load current, what is the value of the input resistance? If the load resistance varies from 100 to 300Q and this causes a 1-% decrease in load current, what is the value of the output resistance?

2.19. The input signal to an amplifier is v,(t) = 0.01COS(2000TI/) + 0.02cos(40007t/). The gain of the amplifier as a function of frequency is given by

100 A~ \ + j(f/1000) Find an expression for the output signal of the amplifier as a function of time.

2.20. The input signal to an amplifier is the same as in Problem 2.19. The complex gain of the amplifier at lOOOHz is 100Z-450. What complex value must the gain have at 2000Hz for distortionless amplification?

2.21. Consider the simple low-pass filter shown in Fig. P.21. (a) Find the complex gain A = V2I Fir as a function of frequency. What are the magnitudes of A at dc and at very high frequencies? Find the half-power bandwidth B of the circuit in terms of R and C. (b) Consider the case for which the capacitor is initially uncharged and v,{l) is a unit step function. Find v2(t) and an expression for its rise time tr in terms of R and C. (c) Combine the results found in parts (a) and (b) to obtain a relationship between bandwidth and rise time for the circuit. Compare the results to Equation (2.22).

R

— O

Figure P.21 Low-pass filter

2.22. Consider the simple high-pass filter shown in Fig. P.22a. (a) Find the complex gain A = V2I Vt as a function of frequency. (b) What is the magnitude of the gain at dc? At very high frequencies? Find the half-power frequency in terms of R and C.

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(c) Consider the input signal shown in Fig. P.22b. Assuming that the capacitor is initially uncharged, find an expression for the output voltage v^t) for / between 0 and T. Assuming diat RC is much greater than T, find an approximate expression for percentage tilt (d) Combine the results of parts (b) and (c) to find relationship between percentage tilt and half-power frequency.

v;(0

0 T t (a) (b)

Figure P22 High-pass filter (a), its input signal (b)

2.23. An audio amplifier is specified to have half-power frequencies of 15Hz and 15kHz. The amplifier is to be used to amplify the pulse shown in Fig. P.22b. Estimate the rise time and percentage tilt of the amplifier output The pulse width T is 2ms.

2.24. The gain magnitudes of several amplifiers are shown versus frequency in Fig. P.24. If the input to the amplifiers is the pulse shown in the figure, sketch the output of each amplifier versus time. Give quantitative estimates of as many features of each waveform as you can.

A(/)

(a) 100kHz

Figure P24

2.25. The input signal and the corresponding output are shown for several amplifiers in Fig. P.25. Sketch the gain magnitude of each amplifier versus frequency. Give quantitative estimates of as many features on die gain sketches as you can.

2.26. (a) A 1-kHz sinusoid is applied to the input of a nonlinear amplifier. l ist the frequencies of at least six frequency components that might be present at the amplifier output.

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(b) Repeat if the input is the sum of a 1-kHz sinusoid and a 1.1-kHz sinusoid.

2.27. List the frequencies of all the components of [cos(27l£j)+cos(27l/J/)]2. Repeat for the cube and fourth power. (Hint: Make use of trigonometric identities).

Chapter 3: Diode Circuits

Solve the following problems. Verify your results with SPICE where possible.

3.1. Recall that the forward voltages of low-current silicon diodes decrease about 2mV/K. Such a diode has a voltage of 0.6 V with a current of 1 mA at a temperature of 25°C. Find the diode voltage at 1 mA at a temperature of 175°C.

3.2. Sketch J versus v fot the circuits shown in Fig. P3.2. The diodes are typical low-current silicon devices at 300 K. The reverse-breakdown voltages of the Zener diodes are shown. Assume 0.6 V for all diodes in the forward-bias region.

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Analog Electronics/Problems

3.3. Use graphical load-line analysis to find the currents and voltages labeled in die circuits shown in Fig. P3.3. The following relation describes the I-V characteristic of the nonlinear element X1

\ 0, V<0.5

where voltage is in volts and current is in milliamperes. The chai j-T*^istic of element X2 is given as

I = -

1 - 0 . 5 1 = 4 -

[l + cxp(-3V) where voltage is in volts and current is in milliamperes.

/N2kO

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3.6. Design a voltage regulator circuit to provide a constant voltage of 10 V to a load from a variable supply voltage. The load current varies from 0.1 A to 0.5A and the source voltage varies from 12 to 15 V. You may assume that ideal Zener diodes are available. Resistors should be standard 5% values. Draw the circuit diagram of your regulator and specify the value of each component. Also find the worst-case (maximum) power dissipated in each component in your regulator.

3.7. Consider the circuit shown in Fig. P3.7. The diodes are identical and have »=1. The temperature of each diode is 300 K. Before the switch is closed, the voltage v is 600mV. Find v after the switch is closed. Repeat for »=2. Neglect the effect of device self-heating.

1mA

Figure P3.7

3.8. A junction diode has »=1 at 300K with a current of 1 mA and a voltage of 600 mV. By how much must the voltage be increased to (a) double the current? (b) increase the current by one order of magnitude? Repeat parts (a) and (b) if «=2.

3.9. Consider the diodes shown in Fig. P3.9. The diodes are identical and have »=1. For each diode a forward current of 100 mA results in a voltage of 700 mV at a temperature of 300K. (a) if both diodes are at 300K, what are the values of IA and 7B? (b) If diode A is at 300 K and diode B is at 305 K, again find IA and JB. Assume that I, doubles in value for a 5-K increase in temperature. (Hint: For part (b), a transcendental equation for the voltage across the diodes can be found. Solve, it by trial and error. An important observation to be made from this problem is that, starting at the same temperature, the diodes should theoretically each conduct half of the total current. However, if one diode conducts slightly more, it becomes warmer, resulting in even more current Eventually, one of die diodes "steals" most of the current. This is particularly noticeable with large currents for which significant heating occurs. One cannot straight connect diodes in parallel to increase maximum available current.)

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3.10 A certain diode has n - 1 and Rt= 0. At 300 K, vD - 650 mV when iD = 1 mA. Plot iD versus % for this diode at 300 K using linear axis for the voltage and logarithmic axis for the current Allow the current to range from 0.1 to 100 mA. Repeat if the diode has a series resistance of R, =

ion.

3.11. Find the values of I and V for the circuits of Fig. P3.11 assuming the diodes are ideal.

Figure P3.ll

3.12. Power is available from a 220-V 50-Hz ac source. Design a half-wave rectifier power supply to deliver an average voltage of 9 V with a peak-to-peak ripple of 2 V to a load. The average load current is 100 mA. Assume that ideal diodes are and transformers are available. Draw the circuit diagram for your design. Specify the values of all components used. Be sure to give the turns ratio for the transformer.

3.13. Repeat the Problem 3.12 using a mil-wave bridge rectifier.

3.14. Repeat Problem 3.12 using two diodes and a center-tapped secondary winding to form a full-wave rectifier.

3.15, Repeat Problem 3.12 assuming diodes having forward drops of 0.8 V.

3.16. Consider the circuit of Fig. P3.16 that contains ideal diodes. The capacitors are very large, so they discharge only a very small amount per cycle. (Thus no ac voltage appears across the capacitors and the ac input plus the dc voltage of C, must appear at point A) Sketch the voltage at point A versus time. Find the voltage across the load. Why this is called a voltage doubler? What is the peak inverse voltage across each diode?

Figure P3.16

3.17. Design a clipper circuit to clip off the portions of an input voltage that fall above 3 V or below -5 V. The input voltage ranges from -10 V to 10 V. Assume that diodes having a constant voltage drop of 0.7 V are available. Ideal Zener diodes of any breakdown voltage required are available. Use standard 5% resistor values and design for a peak current of about 1 mA in the diodes. The only supply voltages available are ±15 V, if needed

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http://P3.ll


3.18. Repeat Problem 3.17 if the clipping levels are +2 V and +5 V (Le. every part of the input waveform below 2 V and above 5 V is clipped off).

3.19. Design circuits that have the transfer characteristics shown in Fig. P3.22. Assume that v-m

ranges from -10 to +10 V. Use diodes, Zener diodes and standard 5% resistor values. Assume a 0.6-V forward drop for all diodes and that the Zener diodes have ideal characteristics in the breakdown region. Power supply voltages of ±15 V are available.

v0(V)

v,(V)

(b) Figure P3.22

3.20. Design a clamp circuit to clamp the negative extreme of a periodic input waveform to - 5 V. Use diodes, Zener diodes and standard 5% resistor values. Assume a 0.6-V forward drop for all diodes and that the Zener diodes have ideal characteristics in the breakdown region. Power supply voltages of ±15 V are available.

3.21. Repeat Problem 3.22 for a clamp voltage of +5 V.

3.22. Current-voltage relationship for a certain breakdown diode is described as follows:

iD = -10"

(••#

[mA], for - 5 V < vD < 0

Plot iD versus vD in the reverse-bias region. Find the dynamic resistance of this diode at ID = 1 mA and at ID = -10 mA.

3.22. Consider the voltage regulator circuit shown in Fig. P3.26. The ac ripple voltage is 1 V peak-to-peak. The dc load voltage is 8 V. What is the jg-point current in the Zener diode? What is the maximum dynamic resistance allowed for the Zener diode if the output ripple is to be less than 10 mV peak-to-peak?

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Analog Electronics / Problems

25fi

Figure P3.22

rt^ioon

Chapter 4: Field-Effect Transistor Circuits

4.1. An //-channel JFET has Vf = -3 V and IDSS = 9 mA. Assuming operation in the saturation region, what value of vcs is required for iD — 4 mA?

4.2. The FET of Problem 4.1 has y G f = - l V . For what range of vDS is the device in die saturation region? Repeat for vcs = - 2 V.

4.3. The FET of Problem 4.1 has vGS = -1 V and vDS = 1 V. Find the drain current. Repeat for v^ = -1 V and vDS = 5 V.

4.4. For what range of vGS is the FET of Problem 4.1 in cutoff? Assume that vDS > 0.

4.5. Consider the circuit shown in Figure P4.5. It is found that as VDD is increased, the voltmeter reading increases until VDD reaches 16 V, after which the reading is constant at 13 V. What are die values of IDSS and Vp for the FET?

Voltmeter

Figure P4.5

4.6. An n-channel enhancement MOSFET has Vlt = 3 V and K = 0.5 mA/V2. If vGS = 5 V, for what range of vDS is the device in die saturation region? In the triode region? Plot iD versus va in die saturation region.

4.7. An //-channel depletion MOSFET has VP = -4 V and K = 0.25 mA/V2. Find the value of IDSS. Plot die boundary between the triode region and die saturation region on die iD-vm plane.

4.8. A p-channel JFET has Vp = 4 V and 1DSS = -16 mA. Sketch die drain characteristics to scale for vDS ranging from 0 to - 10 V. Show the curves for vGS = 0,1, 2, 3, and 4 V.

4.9. The voltmeter shown in Figure P4.9 has very high impedance. Approximately what value does die*meter read?

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15V

+ 1 Voltmeter

Figure P4.9

4.10. A />-channel enhancement MOSFET has Vth - -6 V and K = -2 mA/V2 . Assuming operation in the saturation region, what value of vGS is requited for iD — 8 mA?

4.11. For the circuits shown in Figure P4. l l , find the currents and voltages labeled. For each FET, | Vp\ - 2 V and \IDSS\ = 8 mA.

15V i 15V

R

R

(b) Figure P4.11

30V

4.12. Consider the amplifier shown in Figure P4.12. (a) Find vcs(i) assuming that the coupling capacitor is a short circuit for the ac signal, (b) If the FET has Vth = 5 V and K = 0.5 mA/V2, sketch its drain characteristics to scale for %y = 5,6, 7, and 8 V. (c) Draw the load line for the amplifier on the characteristics, (d) Find the values oi.VDS, vDSmill, and vDSmM.

Figure P4.12

4.13. What is the largest value of RD allowed in the circuit of Problem 4.12 if the instantaneous operating point is required to remain in the saturation region at all times?

4.14. Find the values of ID and VDS for each of the circuits shown in Figure P4.14. Assume that Vp= .4 V and IDSS = 8 mA for all FETs.

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http://P4.ll


15V

Figure P4.14

4.15. (a) Find the value of ID for the circuit shown in Figure P4.15. Assume that Vlh = 4 V and K = ImA/V2. (b) Repeat for Vlh - 2 V and K = 2 mA/V2.

1MQ

IM«

lkQ

lkfl

20V

Figure P4.15

4.16. Find the value of Rs if ID = 4 mA in the circuit of Figure P4.16. Assume that Vp = -3 V, IDSS

= 18 mA, and operation is in saturation. What is the largest value of Rp allowed if the operating point must remain in the saturation region?

lOOkQ

20V

Figure P4.16

4.17. The FET of Figure P4.17 has Vp = -2V and IDSS = 4 mA. If ID = 9 mA, find the value of R2, assuming operation in the saturation region. What is the largest value of R 0 allowed if the operating point must remain in the saturation region?

- 2 4 1 -


Figure P4.17

4.18. Repeat Problem 4.17 if the depletion MOSFET is replaced with an «-channel enhancement MOSFET having Vlh = 4V and K = 1 mA/V2.

4.19. Two identical JFETs are connected in parallel: gate-to-gate, source-to-source, and drain-to-drain. Each FET has the parameters g*, IDSS, and Vp. Find the parameters g'^ I'DSS, and V'p of a single JFET that is equivalent to the parallel combination.

4.20. Find the value of the input resistance of the amplifier shown in Figure P4.12. Assume that the coupling capacitor is a short circuit for the frequencies of interest

4.21. Find midband values of the voltage gain, input resistance, and output resistance for the common-source amplifier shown in Fig. P4.21. The transistor has Vp = -3 V and IDSS = 9 mA. Assume that rd - «>.

h 1.2kO

4 v -20V

Figure P4.21

4.22. Repeat Problem 4.21 if VP = -1 V and IDSS = 1 2 mA. Compare the results.

RD fi 2.2kO

20V

Figure P4.23

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4.23. Find VDS and ID for the FET shown in Figure P4.23 given Krt '= 3 V and K = 0.5 mA/V2. Find the value of £, at the operating point. Draw the small-signal equivalent circuit assuming that rd = oo. Derive an expression for the resistance R„ in terms of Rp and &,. Evaluate the expression for the values given.

4.24. Consider the amplifier shown in Figure P4.24. (a) Draw the small-signal midband equivalent circuit. (b) Assume that 0 = 0 0 and derive expressions for the voltage gain, input resistance, and output resistance. (c) Find ID if R = 100 kQ, Rf = 100 kQ, Rp = 3 kQ, RL = 10 kQ, VDD = 20 V, Vlb = 5 V, and K - 1 mA/V2. Determine the value of g, at the j2-point. (d) Evaluate the expressions found in part (b). (e) Find v.(t) & VW = 0.2 sin(2000n/). (f) Is this amplifier inverting or noninverting? Would you classify-the input resistance as high, moderate, or low compared to other FET amplifier types?

20V

Figure P4.24

4.25. Consider the common-gate amplifier shown in Figure P4.25. (a) Draw die small-signal midband equivalent circuit. (b) Assume that rd = 00 and derive expressions for the voltage gain, input resistance, and output resistance. (c) Fin* ID if R = 100 Q, Rs - 1 kQ, RD = 6,8 kQ, RL = 10 kfl, VD£ = 20 V, VP = -2 V, and IDSS

= 8 mA. Determine the value of g, at the Q-point. (d) Evaluate the expressions found in part (b). (e) Find »,(/) if v(/) = 0.1 sin(20007i/). (f) Is this amplifier inverting or noninverting? Would you classify the input resistance as high, moderate, or low compared to the common source amplifier?

R Cl C2 to

I VD O——'

Figure P4.25

4.26. A depletion MOSFET is to be used as a voltage-controlled resistor with VDS = 0. The device has Vp = -2 V and IDSS - 8 mA. Find rd for VGS = -3, 2, -1 , 0, and +0.5 V.

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4.27. Consider the circuit shown in Figure P4.27. The FET has K P = - 3 V and IDSS = 9 mA. (a) Draw die small-signal equivalent circuit. Do not assume tiiat the capacitor is a short circuit (b) Derive an expression for die voltage gain as a function of frequency, r^ and C. (c) Find the values of rd for v^ = -3, - 1 , and + 1 V (d) If C - 0,01 J4.F, sketch die magnitude of die voltage gain versus frequency for each of the values found in part (c).

C

Figure P4.27

4.28. Consider the CMOS inverter of Figure 4.36. Assume diat the FETs have \Vlb\ — 3 V and | K\ - 0.1 mA/V2. Find die current drawn from die source if Vin = VDD/2 for VDD = 5,10, and 15 V. Repeat for Vfc = 0.

4.29. Consider die CMOS inverter shown in Figure 4.36. The transistors have \Vlb\ = 2 V and \K\ =0.1 mA/V2. The load capacitance is 100 pF. Prior to t = 0 the input voltage is zero. (a) Assuming that steady-state conditions have been reached, what is die output voltage prior to t = 0? (b) If die input voltage switches to VDD at / = 0, what is die output voltage waveform? (c) How much current is flowing out of die capacitor immediately after / = 0? At what time does die output voltage reach 8 V?

Chapter 5: Bipolar Transistor Circuits

5.1. An npn transistor is operating widi die base-emitter junction forward-biased and die base-collector junction reverse-biased. If ic= 9mA for iB = 300|iA, find iE, a and p.

5.2. A transistor has P = 50. What is the value of a?

5.3. Consider an npn transistor at room temperature mat has 1^= 10"13A, P = 100, v^ ~ 10V and iE = 10mA. Find vBE, iB, ic and a. (Assume VT = 26mV at room temperature.)

Figure P5.4

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5.4. Consider the circuit shown in Fig. P5.4 The transistors Qt and Q^ are identical, both having IES = lOfA and P = 100. Find VBE and ZQ. Assume a temperature of 300K for both transistors.

5.5. Repeat Problem 5.4 i fQ, has Imi = lOfA and P = 100, whereas Q has 7 ^ = lOOfA and P = 100.

5.6. Two transistors J2, and Qj, connected in parallel are equivalent to a single transistor as indicated in Fig. 5.6. If the individual transistors have I&, = IBS2 = 10"13A and Pi = P2 = 100, find igj and P for the equivalent transistor. Assume the same temperature for both transistors. {Comment: Sometimes we may be tempted to parallel transistors to obtain an equivalent transistor with higher current ratings. However, unless the transistors are mounted on the same heat sink to maintain nearly equal temperature, one of the transistors "steals" most of the current Sometimes we add resistors in series with the emitters to ensure more nearly -equal current division. See Problem 3.9.)

Figure P5.6

5.7. Find the value of |3 fot the transistors of Fig. P5.7.

10kO

rC£=7V V=5V

(b) Figure P5.7

5.8. An npn transistor has VBE = 0.7V and IE — 10mA. Find VBB if IE = 1mA. Repeat for IE = lpA. Assume a temperature of 300K. 5.9. Design a "P-meter" for the measurement of P of small-signal npn silicon transistors at room temperature. Assume that vBE = 0.7V for the transistors to be measured. The following parts are available:

• A 1-mA-full-scale meter having a resistance of 150 Q. • Standard 5%-tolerance resistors. • Potentiometers of 100ft, lkQ, lOkQ, lOOkQ and 1MQ. • A 4.7-V Zener diode. • Switches and mechanical components as required. • A 9-V battery.

The meter is to have switch-selectable full-scale values of PFS^IO, 100 and 1000. Adjustments are to be provided which allow calibration of the meter. The meter is to provide accurate readings

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for battery voltages ranging from 7 to 9V. Under reasonable battery conditions (including short-circuited test terminals), the battery current should not exceed 5mA.

5.10. A certain npn transistor has vBE = 0.7V for iB = 0.1mA at a temperature of 30°C. Sketch the input characteristic to scale at 30°C. What is the approximate value of vBB for iB = 0.1mA at 180°C? (Use the rule of thumbs that vBE is reduced in magnitude by 2mV per IK increase in temperature.) Sketch the input characteristic to scale at 180°C.

5.11. A certain npn silicon transistor has |5 = 100 and iB — 0.1mA. Sketch ic versus v^ for J^E ranging from 0 to 5V. Repeat for P = 300. Ignore second-order effects.

5.12. Repeat Problem 5.11 for znpnp transistor if v^ ranges from 0 to -5V.

5.13. At a temperature of 30°C, a particular/>«p transistor has vBE = -0.7V for % = 2mA. Estimate vBE for iE — 0.1mA at a temperature of 180°C.

5.14. An npn transistor has P = 100 and iB = 0.1mA. The collector-to-emitter breakdown voltage is 20V and the Early voltage is VA = 100V. Sketch ic versus v^ for the voltage range from 0 to 25 V.

5.15. Determine the region of operation for a room-temperature silicon npn transistor that has p = 100 if (a) V^ =10V and IB = 20\iA; (b) Ic = IB = 0; (c) Va = 3V and VBE = 0.4V; Ic - 1mA and IB = 50uA.

5.16 Determine the region of operation for a room-temperature siliconpnp transistor that has P = 100 if (a) V^ =-5V and VBE = -0.3V; (b) Ic = 10mA and IB = 1mA; (c) IB = 0.05mA and V^ --5V.

5.17. Use the large-signal models for the transistors to find Ic and V^ for the circuits of Fig. P5.17. Assume that P = 100. Repeat for p = 300 and compare the results for both values.

+15V +15V

6.8kO

(b)

+15V +15V

a iMn |6.8kn

-15V -15V

Figure P5.17

H (c)

\kCl

5.18. Find J and Kin the circuits shown in Fig. P5.18. For all transistors assume that P = 100 and I VBE I = 0.7V in both the active and the saturation regions. Repeat for P = 300.

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+ 10V

+ 10V

-•5V.

Figure P5.18

5.19. Consider the circuit shown in Fig. P5.19. A jg-point value for Ic between a minimum < •£ 4mA and a maximum of 5mA is required. Assume constant resistor values and that p ranj from 100 to 300. It is desired for Rg to have the largest possible value while meeting the otb t constraints. Find the values of Rg and RE. The resistors in this problem are not required to be nominal values.

+15V

lkn

Figure P5.19

5.20. Consider the four-resistor bias network of Fig. 5.20a with Vcc = 15V, R, = lOOkQ, R = 47kfl, Re = 4.7kfi and RE = 4.7kQ. Suppose that P varies from 50 to 200, VBE = 0.7V and the resistors have the tolerance of ±5%. Find the maximum and minimum values of Ic

5.21. Consider the circuit shown on Fig. P5.21. Find R, and Re if a bias point V^ - 5V and Ic = 2mA is required. What are the closest 5%-tolerance nominal values for R, and R^

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+ 15V

•15V Figure P5.21

5.22. Find Ic and V^ in the circuit of Fig. P5.22. + 15V

-15V

Figure P5.22

5.23. A certain npn silicon transistor at room temperature has P = 100. Find the corresponding values of rKi£Ic= 1mA, 0.1mA and l|iA. Assume operation on the active region.

5.24. Consider the common-emitter amplifier of Fig. P5.24. Draw the dc circuit and find Ic. Find the value of r*. Then calculate the values of A„ A^ Z& Ah G and Z,. Assume operation in the midband region for which the coupling and bypass capacitors are short circuits.

lkfi

Figure P5.24

5.25. Repeat Problem 5.24 if all resistance values, including Rs and R^ are increased in value by a factor of 100. Prepare a table comparing the results for the low-impedance amplifier of Problem 5.24 with those for the high-impedance amplifier. (Comment: When we consider the high-

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frequency response of these circuits, we will find that die gain of the high-impedance circuit falls off at lower frequencies than the gain of the low-impedance circuit does. Thus if we want constant gain to extend to very high frequencies, we should use die low-impedance circuit.)

5.26. Consider the emitter-follower amplifier of Fig. P5.26. Draw the dc circuit and find Ic Find the value of r* Then calculate midband values of A„ A^ Zit> Ab G and Z,.

+15V +15V

cj h iokn

j l k Q f "

| 47kQ

Figure P5.26

5.27. Repeat Problem 5.26 if all resistance values, including Rs and R^ are increased in value by a factor of 100. Prepare a table comparing the results for the low-impedance amplifier of Problem 5.26 with those for the high-impedance amplifier.

5.28. Draw the small-signal equivalent circuit for die amplifier shown in Fig. P5.28. Derive expressions for the voltage gain and input impedance in terms of the resistor values, r„ and p\ Assume that the capacitors are short circuits for the signal.

vc vc

Figure P5.28

5.29. Find the values of Ia r„, A„ and Zu for the circuit of Problem 5.28 if Vcc = 15V, p = 100, VBE = 0.7V, RB = 270kQ, r^ = lkfl, r^ = lOOfi and R^ = lkfi. Repeat for RE = 0 and prepare a table comparing the results.

5.30. Find an expression for the output impedance of the amplifier shown in Fig. P5.28.

5.31. Draw the small-signal equivalent circuit for the amplifier shown in Fig. P5.31 and derive expressions for the input impedance and die voltage gain. Assume that die capacitors are short-circuits for the signal.

- 2 4 9 -


Figure P5. 31

5.32. Consider the circuit of Problem 5.31 with V^ = 15V, R, = lOkfl, R, = lOkQ, RB = lOOkfl, RE = lOkQ and B^ = 4.7kQ. Assume a transistor having P = 200, VBE = 0.7V. Evaluate the expressions found in Problem 5.31 for input impedance and voltage gain.

5.33. A certain npn BJT has an Early voltage of V = 100 V. Find the value of r„ - 1/hK for Ic = 1 mA. Repeat for Ic = 0.1 mAand Ic = 10 mA.

5.34. A certain transistor has hp = 200. Find the approximate value of hk for lc — 0.1 mA, 1 mA and 10 mA. Assume a temperature of 300 K.

5.35. The transistor shown in Figure P5.35 has hn = 10-4. Find the reading of the voltmeter in the ac mode. Assume that the ac base current is negligible (because of the high impedance of RB and the voltmeter).

15V Ac or dc voltmeter

J Figure P5.35

5.36. The transistor shown in Figure P5.35 has hK = 10"4 S. Find the rms value of the ac collector current. Assume that the ac base current is negligible.

5.37. Consider the circuit shown in Figure P5.35. In the dc mode, the voltmeter gives a reading of 0.65 V. In the ac mode, the voltmeter gives a reading of 1 mV rms. The dc collector current is known to be Ic = 5 mA. The ac collector current is 0.1-mA rms. Find approximate values of h„, hJa hK, and h?

5.38. Derive an exact expression for bk in terms of the parameters of the hybrid-7t model at low frequencies. Evaluate the exact expression to find hk from the 2N2222A equivalent circuit shown in Figure 5.31. What percentage error results if die approximation hk = r„is used? Is this error significant considering the unit to unit variations of these devices? Consider the hybrid-7i model for the BJT with a short connected from the collector to the emitter.

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5.39. Derive an expression for the ratio of the collector current phasor to the base current phasor as a function of frequency. To simplify the analysis, replace rM by an open circuit and use the approximation lc = g^y* (In other words, neglect the current through Cf, when computing the collector current.)

5.40. The transition frequency fT is the frequency at which the short circuit common-emitter current gain has a magnitude of unity. Use the expression found in 5.39 for the current gain to obtain an expression for fT in terms of the hybrid-7t parameters. Show that your result is equivalent to Equation (5.71).

5.41. The data sheet for a certain transistor gives the following data for a j2-point of V^ — 10 V and Ic = 1 mA:

A„ =1x10-5, fr = 400MHz, hft = 500, Q = 2pF , h„= 2x10-5 S Furthermore the collector-base time constant is 20 ps. Find values for the parameters of die hybrid-n equivalent circuit.

5.42. A certain npn transistor has 7^ = lx lO 1 3 A, PF = 200, and (3R = 0.5. Use the Ebers-Moll equations to find ic, iE, and iB. Also identify the region of operation. Assume that VT = 26 mV.

(a) vBE = 0.65 V and v^ = -10 V. (b) vBE = 0.65 V and vK - 0.6 V. (c) vBE = -1 V and v^ = -10 V. (d)rBH = - 5 V a n d ^ = 0 . 7 V .

5.43. Consider die RTL inverter of Figure 5.37. (a) The value of 13 for the 2N2222A is approximately 150. Find the maximum value of RB allowed if the transistor is to be in saturation for viH = 3 V. (b) Use a PSpice program to perform a transient analysis with a 200-ns 3-V input pulse for RB = 10 kfi and for RB = 5 kQ. Prepare a table comparing the delay, rise, storage, and fall times of the output for the two values of RB Give a brief explanation of the effect that the value of RB has on each of these time intervals.

5.44. Consider the RTL inverter of Figure 5.37. (a) Use a PSpice program to perform a transient analysis with a 200-ns 3-V input pulse. Plot the output pulse. (The result should be substantially the same as Figure 5.38a.) (b) Increase the resistor values by a factor of 10 (i.e., R$ = 50 kQ and E^ = 20 kQ) and repeat die analysis for an input pulse duration of 2 j*s. (c) Prepare a table comparing the delay, rise, storage, and fall times of the output for the two sets of resistor values.

Chapter 6: Feedback Circuits

6.1. A certain negative feedback amplifier has P = 0.1. Plot the closed-loop gain Aj versus open-loop gain A. (Assume that A is a pure real number.) Also plot ^ v e r s u s A on the same set of axes for p = 0.01.

6.2. A certain negative feedback amplifier (as shown in Figure 6.1) has xs = cos(fi«), A = 103, and P = 0.1. Find x^ x;. and xf Repeat for A - 104. What does x(- approach as A approaches infinity?

2 5 1 -


6.3. An amplifier has a nominal open-loop gain of A = 104. It is found that^4 varies by ±3% with changes in ambient temperature. Negative feedback is to be used with the amplifier. What value of P should be used so that the variations in A{ with temperature are no more than ±0.1%? What is the nominal value of Aj for this value of P? Assume that P is constant with temperature.

6.4. For the feedback amplifier configurations shown in Figure P6.4, determine the overall gain Af = xjxf

*-x.

Figure P6.4

6.5. (a) Derive an expression for the closed-loop gain Af = xjx, of the feedback amplifier shown in Figure P6.5. Under what conditions is the closed-loop gain magnitude \Aj\ less than the open loop gain magnitude \A\i In other words, under what conditions is the feedback negative? Assume that A and P are real but can assume negative values. (b) Suppose that A is negative and P is positive. To have negative feedback, should the summer add the signals as in Figure P6.5 or subtract them as in Figure 6.1? (c) Repeat part (b) if A is negative and P is negative.

>x0

Figure P6.5

6.6. Consider the transfer characteristic of a certain nonlinear amplifier as shown in Figure P6.6. i

Plot the output voltage of the amplifier assuming a sinewave x,- = sin(cot) at its input. Find the voltage gain A^xjxf of the feedback amplifier in Fig. P6.6 for the positive and negative input x> Plot the output voltage x, of the feedback amplifier for xs = sia(o)t) .

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6.7. Consider using positive feedback with the nonlinear amplifier of Figure P6.6. In other words, the feedback signal is added to the source signal as shown in Figure P6.5. Assume that P = 0.09 and xs = 0.1sin((0^. Find xc(t) and sketch it to scale versus time. Find the ratio of the positive peak to the negative peak for xt(t). Compare to the ratio for the waveform without feedback (as plotted in Problem 6.6). What effect does positive feedback have on distortion?

6.8. Consider interchanging the order of the amplifiers in Figure 6.8. This is shown in Figure P6.8. Find the signal-to-noise ratio at the load. Compare the result to that given in Equation (6.17). What do you conclude concerning the best order of cascading a noisy amplifier with a low-noise amplifier?

Figure P6.8

6.9. A certain power amplifier has a voltage gain of 100. Because of poor power-supply filtering, a "hum" of 2-V peak appears in the amplifier output It is required to reduce the output hum to 0,1 V peak. It is not practical to change the internal design of either the power supply or die power amplifier. However, it is practical to cascade an additional amplifier and employ negative feedback. Design die block diagram of a feedback system to achieve the hum reduction. Give die gain of each amplifier and the feedback ratio for the feedback block. The overall voltage gain is required to remain 100.

6.10. What is the minimum phase margin possible for a single-pole amplifier? As usual, assume that P is constant - not a function of frequency.

6.11. A ceicain amplifier has an open-loop dc gain of 5000. The open-loop poles are located at s = 2071 and s = 20071. Find the allowed range for P if a minimum phase margin of 60° is required. What is the gain margin for die maximum allowed value of P? Verify your results with Spice.

6.12. Repeat Problem 6.11 if a third open-loop pole is added at s = 400071.

6.13. For die circuit of Fig. P6.13 find the product V4(CD)P((O), die frequency of zero loop-phase and R2/R, for .oscillation.

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A(a>)

6.14. Design a Wien-bridge oscillator with frequency of 5MHz.

6.15. (a) Design a phase-shift oscillator for a frequency of 20 kHz. Use SPICE to plot the phase curve of the phase-shifting circuit. (b) Find the percent change in frequency if one of the resistors increases by 10%. (c) Repeat part (b) for a 10% decrease in one capacitor.

6.16. (a) Design a 2 MHz oscillator like Fig. 6.26c using a MOSFET with k = 4xl0"3A/V2, VT = 1.2 V and Cp — C^ = 2 pF. Begin with the high-frequency equivalent circuit, assuming that your transistor is biased at 1 mA and that the Early voltage is 70 V. Include transistor capacitances as part of your design. (b) Design a suitable biasing circuit for your oscillator transistor, including all necessary biasing and coupling capacitor values. Draw the final equivalent circuit.

6.17. A Hartley oscillator uses L,+L} = 25 ^H and C2 = 40 pF. Use SPICE to plot phase versus frequency for the phase shifting network driven by an independent ac current source, both for the original design and when C2 is 10% high. One expects the circuit to oscillate at that frequency where the phase shift is 180°. From your curves, determine the nominal design frequency and the frequency when C2 is 10% high.

6.18. Use SPICE to plot the phase versus frequency curve for the phase-shifting circuit of Fig. P6.18. The input signal should be an ac current. Use the crystal equivalent of Fig. 6.30a. Crystal parameters are L = 137 H, C = 0.0235 pF, r = 15 kQ, and C - 3.5 pF. Try to determine the percent frequency change when the 32.2 pF capacitor increases by 10%.

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6.19. Figure P6.19 shows two oscillator circuits of the Colpitts type, complete with bias details. For each circuit derive an equation governing circuit operation, and find the frequency of oscillation and the gain condition that ensures the oscillation start.

Notes

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Analog Electronics /Appendix

Appendix

A. Nominal Values and the Color Code for Resistors

Several types of resistors are available for use in electronic circuits. Carbon-film and carbon-composition resistors with tolerances of 5%, 10% or 20% are available with various power ratings (such as 0.125, 0.25 and 0.5W). These resistors are used where greater precision is required. For example, we often choose metal-film resistors in applications such as feedback resistor of an op amp or as the frequency-determining elements of an oscillator.

First digit (closest to the end)

Second digit

Optional band

Multiplier

Digit Color Tolerance Color 0 Black 2% Red 1 Brown 5% Gold 2 Red 10% Silver 3 Orange 20% No fourth band 4 Yellow 5 Green 6 Blue 7 Violet 8 Gray 9 White

Examples: Yellow Violet Black Yellow Violet Red Brown Black Yellow

47xl0°=47O 47xl0 2 «4700Q 10xl04=100kO

Figure A1

Wire-wound resistors are available with high-power dissipation ratings. Wire-wound resistors often have significant series inductance because they consist of resistance wire that is wound on a form, such as ceramic. Thus they are often not suitable for use as resistance at high frequencies.

The value and tolerance are marked on 5%-, 10%- and 20%-tolerance resistors by color bands as shown in Figure Al . The first band is closest to one end of the resistor. The first and second bands give the significant digits of the resistor value. The third band gives the exponent of the

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multiplier. The fourth band indicates the tolerance. The fifth band is optional and indicates whether the resistor meets certain military reliability specifications.

Table Al shows the combinations of significant figures available as nominal values for 5%-, 10%-and 20%-tolerance resistors. Table A2 shows the standard nominal significant digits for 1-%-tolerance resistors.

TABLE Al

STANDARD NOMINAL VALUES FOR 5%-TOLERANCE RESISTORS 10 16 27 43 68 11 18 30 47 75 12 20 33 51 82 13 22 36 56 91 15 24 39 62

TABLE A2

STANDARD VALUES FOR 1%-TOLERANCE METAL-FILM RESISTORS 100 140 196 274 383 536 750 102 143 200 280 392 549 768 105 147 205 287 402 562 787 107 150 210 294 412 576 806 110 154 215 301 422 590 825 113 158 221 309 432 604 845 115 162 226 316 442 619 866 118 165 232 324 453 634 887 121 169 237 332 464 649 909 124 174 243 340 475 665 931 127 178 249 348 487 681 953 130 182 255 357 499 698 976 133 187 261 365 511 715 137 191 267 -.. 374 523 732

257


B. Introduction to PSpice

PSpice is a computer program that helps to simulate electronic circuits' design before building them.

PSpice is a member of the Spice "family" of simulators: Simulation Program with Integrated Circuits Emphasis

developed at the University of California, Berkeley.

Prescribed textbook: P. W. Tuinenga, Spice: A guide to circuit simulation and analysis using PSpice. Second edition. Prentice-Hall, 1992.

The student version 5.0^ of PSpice is available from Prof. A. Materka, Instytut Elektroniki, Politechnika Lodzka, uL StefanowsJtiego 18/22, 80-924 Lodz, [email protected] (come with two 1.44 MB floppies). Obviously, the faster your PC machine, the shorter simulation times; however, no coprocessor is required to run PSpice on a PC.

Example 1. Use PSpice to calculate the voltage at node 2 and all the branch currents in the following dc circuit;

Figure Bl

Introduction. All the respective files of the PSpice simulator are stored in a directory ..\PSEVAL5(L Call PS program from that directory. The PSpice control shell loads in a few seconds. You can see a horizontal menu bar across the top of the screen.

In PSpice, any simulation is run accordingly to circuit description and analysis commands that are included in the input file. Then before running a simulation you have to edit the appropriate input file for your circuit Suppose your input file will be stored in the A: drive, insert a floppy disk into that drive.

You have to specify a name of the file that you ate going to create. To do this, either use the arrow keys to move the highlight to Files and press <ENTBR>, or simply press <F>. The dropdown menu appears below Files. Select the Current File option. Type in your input file name AiMYFIRST. An extension .CIR will be added automatically to the file name, by default The full file name appears at the bottom of the screen, along with the notation New. The Files dropdown menu disappears. Now you are ready to call the text editor to create your input file.

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mailto:[email protected]


Creating a circuit file: the text editor. Press F or <ENTER> to bring down the Files menu again. This time all the items are intensified, meaning that all the functions are available. Select Edit. A new window opens which is a blank text field of the input file.

The line number and column number tell you the current cursor location. The notation [Insert] indicates that die editor will insert your keyboard entry at the cursor location and move right whatever text is to the right of the cursor. If you press <INSERT> on the computer keyboard diis mode will change from Insert to Overstrike. Overstrike means that your keyboard entry will overstrike or replace whatever is at the cursor location.

When typing in the PSpice circuit file, the number of spaces between entries is not important You may use <TAB> or <SPACE BAR> to separate the data. A space is equivalent to a comma, in terms of separation of data entries.

Use <ENTER>, <PGUP>, <PGDN>, <HOME>, <END>, and the arrow keys to move around die file. The <BACKSPACE> key deletes any character to the left of the cursor location. You can delete blank lines with the <DEL> key when the cursor is at the beginning of a blank line. To see Help Screen of the editor commands, press < F / > . Press <ESC> to return to the screen you were using.

Now type in your first PSpice program. Please note mat the nodes of your circuit in Figure Bl were numbered, and the node with a number '0' is a reference node.

Direct current circuit example VI 1 0 DC 5 11 2 0 DC 3 V2 3 0 DC 10 Rl 1 2 2 R2 2 0 2 R3 2 3 4 .DC VI 5 5 1 . PRIN DC V(2) I (VI) I(V2) I(R1) I(R2) I(R"3) .END

The first line in the pro gram above is the program tide line. You must even if it is blank.

The voltage source V I has its positive terminal connected to node 1, its negative terminal at the reference node 0, and a dc voltage of 5 V.

PSpice uses a convention in which all currents are assumed to pass through the device from die first listed node to the second listed node. Following this convention, the current source I I has its reference direction passing through the source from node 2 to node 0.

The lines with the resistance names are the circuit device statement lines. (A name that starts with "R" or "r" is a name of a resistance.) Each device is described widi a name, the nodes to which it is attached in the circuit, and its value.

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The . DC statement is a command statement Begin all command statements with a dot. In this case, the . DC command calls for the source voltage VI to be calculated at a single value of 5 volts.

The . PRINT command saves the dc analysis values of the listed voltages and currents to the output file. You can view the output file on the monitor screen and/or print it out on the printer.

The . END is to terminate the PSpice file.

Now, press <ESC> to indicate that you have finished file editing. You will be asked whether or not to save your edits. Press <ENTER> to accept the default (Save).

If there are any syntax errors in your file, the Files menu displays with the Edit selection highlighted. The word Errors appears at the bottom of the screen in the Current File line. In this case, press <F6> to see a listing of the line number and a description of the error. Press <ESC> to close the error screen, and press <ENTER> to re-enter the editor and correct the error. If there are no errors in the file, the Files menu selection closes and PSpice is ready to accept your next command. The word Loaded appears in the Current File line.

Running a PSpice circuit analysis. To select Analysis, either press A or use the arrow keys to highlight Analysis and press <ENTER>. The drop-down menu appears in which the Run PSpice selection is highlighted. The » arrows to the left of DC Sweep indicate that the dc analysis has been enabled. The other entries are not yet functional with this file, because you have not use the appropriate commands. This will be explored later.

Press <ENTER> to accept Run PSpice option. The status screen displays a continuous update of the actions performed by PSpice.

When the analysis is complete you return to the Control Shell menu screen. To view the data output file you can select Files and then Browse Output function.

If you select Browse Output, the output file appears in a window similar to the text editor window. You cannot edit the output file. You can use the arrow, <PGUP>, and <PGDOWN> keys to move around the output file. For this program, the second page has the output of the dc analysis, labeled DC TRANSFER CURVES. The voltage V (2) and currents I ( V I ) , I ( R l ) , I (R2) , and I (R3) are listed across the screen.

To exit the Browser, press <ESC>. +

In addition to the printed text output, PSpice can produce graphics output. The PROBE graphics post-processor is used for this purpose. As an example, we consider an analysis of the RLC filter circuit shown in Figure B2.

Example 2. Write the appropriate PSpice code and run the transient analysis for the circuit shown in Figure B2. Then create a CRT screen graph, similar to an oscilloscope screen that will show transient time-varying voltages across each of the devices in the circuit. The input voltage to the circuit will be a step of 5 volts.

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Figure B2

To get started, select Current File under the Files menu heading. Enter the file name, e.g. RLCTRAN. Select Files again. Press E to select the editor.

Type the following file for me RLC circuit:

RLC circuit transient analysis * Analyze the RLC circuit for the transient time * varying voltage across the capacitance when * input voltags is a 5-volt pulse. VI 1 0 PULSE (0 5 0.1ms O.lus) Rl 1 2 250 LI 2 3 15.9mH CI 3 0 15.9nF ;This line relates to the capacitor .TRAN 12US 600US 0 1US .PLOT TRAN V(3) .PROBE .END

The first line in the file is the required tide line. The lines beginning with an asterisk (*) are comment lines and are ignored by PSpice. An asterisk in the first column or a semicolon (;) in any column identifies everything to the right of it as a comment also.

The source VI is described as having a 5-volt pulse waveform that is zero at t=0, jumps to 5 V at t=0.1 ms and has a time of rise equal to 0.1 fj,s.

The .TRAN command tells PSpice to perform transient analysis. The first value (12US = 12 JJ.S) is the time interval between data points on the printer-plot output called for by the . PLOT command. The second value (600US s 600 |is) specifies the time interval for the analysis.

The . PLOT command specifies that the values of the node voltage V(3) calculated in the transient analysis are to be saved in the output file.

The . PROBE command tells PSpice to create an RLCTRAN. DAT file containing all of the data points calculated in the transient analysis. Those data can be used by the PROBE graphics postprocessor to construct graphs of any voltage or current waveforms in the circuit. Various functions of voltages and currents can be plotted against the horizontal axis variable, which is time in this case.

After entering and checking your file, press <ESO to leave the editor. Select Analysis. The Transient line in the menu has an indicator showing that the transient analysis has been enabled by the .TRAN command in the file. Press <ENTER> to choose the highlighted Run PSpice selection.

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When the analysis run is complete, select Probe from the Control Shell menu bar. The drop-down menu appears with the Run Probe selection highlighted. Press <ENTER>. After a few seconds an empty graph screen appears, with the available selections listed across the bottom line. Use arrow keys to move highlight to the Add_trace selection and press <ENTER>. When asked Enter Variables or Expressions type: V ( 3 ) <ENTER>. After a brief time a graph of the capacitance voltage waveform will be displayed.

Select Add_trace and add the variable V ( 2 , 3 ) . Probe re-scales the graph (automatically) and displays both the capacitance voltage and the graph of the voltage across the inductance due to pulse source.

Select Addjtrace again and add the voltage V ( 1 , 2 ) . This is the graph of the voltage across the resistance.

16U-

-5U+-6s 166us 269us 3Wus

D o(3) o u(l,2) A 11(2,3) 11+12*13 Tine

466us 566us 6Mus

Experiment According to Kirchhoffs voltage law (KVL), the sum of the voltages across the circuit loop is equal to zero, or the sum of the voltages across the R, L, and C of this circuit is equal to the source voltage. You can add the traces together by simply adding their trace numbers.

First, select Add_trace. Then, type the expression:

# 1 + #2 + # 3 <ENTER>

A waveform equal to die sum of the three voltages appears. This is equal to the 5 V input waveform, of course.

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Quick Reference for PSpice Programmers

1. 2.

3. 4.

The circuit reference node must be numbered zero. The remaining nodes may be named with unique positive integers or alphanumeric character strings. A dc path to the reference node from each node is required. Two or more components must be connected to each node.

SUFFIXES FOR POWERS OF TEN

3t 4BltJtdfi

You can use either upper- or lower-case letters for all suffixes, statements, commands, etc. in PSpice.

Program Statements

1. The first line of the program is the tide line. It may be left blank. There may be only one tide line in the input file.

2. An asterisk (*) in the first column identifies a comment. 3. Comments may also be written to the right of a semicolon (;). 4. A plus sign (+) at the beginning of a line indicates previous line continuation.

PSpice Device Statements

1. The first character of the name identifies the element type. 2. The next two fields identify node connections: N+ and N- . It is assumed that a positive

current flows through the element from node N+ to node N- . 3. The fields after the node connections are parameter fields. 4. The circuit device names and the syntax required by PSpice are listed below. Please note that

the parameter in square brackets [ ] are optional.

Resistance: Rname N+ N - Value Capacitance: Cname N+ N - Value Inductance: Lname N+ N - V a l u e

(Where IC are initial conditions.)

[ I C = v o l t s ] [ I C = a m p s ]

Magnetic Coupling Coefficient: Kname Ll L2 Value

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Dependent Sources:

VCVS: Enamo N+ N - NC+ NC- V a l u e VCCS: Gnamo N+ N - NC+ NC- V a l u e

[Where the voltage control is V(NC+,NC-).] CCVS: Hname N+ N - VX V a l u e CCVS: Fname N+ N - VX V a l u e

(Where VX is the voltage source through which the control current flows.)

Independent sources (X=V for voltage. X=I for current sources):

DC sources: Xname N+ N - [DC] [ V a l u e ]

Piecewise linear sources: Xname N+ N - PWL(t l v l t 2 (Where ti = point in time where voltage is vi.)

v 2 .)

Pulse sources: Xname N+ N - PULSE (VS VP [TD] [TR] [TF] [PW] [PER]) Parameter Default VS Initial value None VP Pulsed value None TD TR

Delay time Rise time

0 TSTEP

TF Fall time TSTEP PW Pulse width TFINAL PER Pulse period TFINAL

Damped sinusoidal source: Xname N+ N - SIN(VO VA [FREQ] [TD] [ALPHA] [PHASE]) Parameter VO

Meaning Offset value

Default None

VA FREQ TD ALPHA PHASE

Peak amplitudeNone Frequency in Hz 1 /TFIN AL Delay time 0 Damping coefficient 0 Phase in degrees 0

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Ambt Electronics /Appendix

PSpice Command and Control Statements

Operating P ^ i f ( f t i m ) AlWlyftift .OP

1. Replaces all capacitances with open circuits and all inductances with short circuits. 2. Performs a dc analysis and prints out all node voltages. 3. Calculates currents of all independent voltage sources and the power delivered by

these sources. 4. Calculates the currents and voltages for controlled sources.

***• A^fywfft .DC [SWEEP] NVAR START STOP STEP

Parameter M^anjng Default SWEEP

NVAR START STOP STEP

LIN for linear sweep LIN OCT for log sweep by octave DEC for log sweep by decade Name of independent source to be swept Starting value for NVAR Maximum value for NVAR Increment in values of NVAR

Tirana w m Analysis .TRAN TSTEP TFINAL [TNOPRINT] Parameter Meaning

[MAXSTEP] [UIC] Default

TSTEPTime step for plots or print out None TFINAL Final time for analysis None

Output suppressed until TNOPRINT 0 Maximum time step used in analysis see textbooks Specifies use of initial conditions in capacitance and inductance statements

TNOPRINT MAXSTEP UIC

AC Analysis

.AC SWEEP NPOIMTS FSTART FSTOP Parameter M i n i n g SWEEP

NPOINTS

FSTART FSTOP

LIN for linear sweep OCT for log sweep by octave DEC for log sweep by decade Total # of points for LIN Points per decade for DEC Points for octave for OCT Starting frequency for sweep Maximum frequency for sweep

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C. English-Polish Dictionary of Saiected Terms

A abrupt junction - zla_cze skokowe ac circuit - obwod prajdu przemiennego acceptor — akceptor A / D converter (ADC) — przetwornik analogowo-cyfrowy admittance — admitancja AFC (automatic frequency control) - automatyczna regulacja czestotliwosci AGC (automatic gain control) - automatyczna regulacja wzmocnienia AM (amplitude modulation) — modulacja amplitudy ambient temperature — temperatura otoczenia amplifier — wzmacniacz analog - analogowy angular frequency — pulsacja anode — anoda approximation — przyblizenie, aproksymacja attenuator - dzielnik, tlumik avalanche breakdown - przebicie lawinowe average — sredni

B bandpass — pasmowoprzepustowy bandstop — pasmowozaporowy bandwidth — pasmo base — baza bias — polaryzacja bipolar - bipolarny block diagram — schemat blokowy breakdown - przebicie bridge - mostek buffer — bufor

c capacitance - pojemnosc capacitor — kondensator cascade connection - pola.czenie kaskadowe cathode — katoda cellular — komorkowy channel — kanal characteristic — charakterystyka, charakterystyczny charge — ladunek circuit - obwod, uklad clamp - uklad przylegania clipper - ogranicznik closed-loop — w p?tli zamkni^tej CMOS (complementary MOS) - CMOS

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coil - cewka collector - kolektor common — wspolny compensated - skompensowany complex - zespolony, zlozony, skomplikowany component - cz?sc skladowa, element concentration — koncentracja conductance — przewodnosc conduction angle — ka_t przeplywu conductivity — przewodnictwo converter — przetwomik crossmodulation - modulacja skrosna crystal - krysztal current - pra_d current gain — wspolczynnik wzmocnienia pra_dowego cutoff - odciecie

D D/A converter (DAC) - przetwomik cyfrowo-analogowy dc (direct coupled, direct current) — bezposrednio sprz^zony, stalopra^dowy decibel - decybel delay - opoznienie depletion layer — wartswa zubozona detector — detektor, demodulator differential — roznicowy diffusion - dyfuzja digital — cyfrowy diode - dioda distortion — znieksztalcenia donor — donor drain - dren drift - unoszenie dynamic - dynamiczny

E discrete - dyskretny Early effect - zjawisko Early'ego efficiency - sprawnosc emitter - emiter equivalent circuit - obwod (schemat) zastepczy

F fall time - czas opadania feedback - sprz?zenie zwrotne FET - tranzystor polowy field-effect transistor - tranzystor polowy filter - filtr first harmonic - pierwsza harmoniczna FM (frequency modulation) - modulacja cz^stotliwosci follower - wtornik

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forward bias - polaryzacja w kierunku przewodzenia frequency - czestodrwoic full-w^ve — dwupotowkowy

G gain - wspolczynnik wzmocnienia, wzmocnosc gate — bramka ground — masa, ziemia

H half-wave - jednopolowkowy harmonic - harmoniczny higher cutoff frequency - gorna cz^stotliwosc graniczna high frequency - duza czcstotliwosc highpass — gomoprzepustowy high voltage — wysokie napiecie hybrid - hybrydowy

I IC -> integrated circuit impedance - impedancja incremental - przyrostowy inductance — indukcyjnosc input - wejscie integrated circuit — uklad scalony interference — interferencja intermediate frequency - cze^totliwosc posrednia intermodulation - intermodulacja inverse - inwersyjny inverter - inwerter inverting amplifier — wzmacniacz odwracajajcy

J JFET - tranzystor polowy zlajczowy junction - zlajcze

K KCL (Kirchhoff s Current Law) - pierwsze prawo Kirchhoffa knee current, voltage - prad, napiecie "kolana" (punktu zagiccia krzywej) KVL (Kirchhoff s Voltage Law) - drugie prawo Kirchhoffa

L large-signal - wielkosygnalowy layer - warstwa lead - odprowadzenie lifetime - czas zycia (nosnikow mniejszosciowych) line regulation - wspolczynnik stabilizacji napieciowej

- 2 6 8 -


load - obciazenie load regulation — wspolczynnik stabilizacji prajdowej logic - logiczny loop - petla loudspeaker - glosnik lower cutoff frequency — dolna czestotliwosc graniczna low frequency - mala czestotliwosc low voltage - niskie napiecie lowpass - dolnoprzepustowy

M microphone - mikrofon midband range - zakres srednich czestotliwosci mixer - mieszacz MOSFET - tranzystor polowy z izolowana. bramka. multistage — wielostopniowy mutual — wzajemny

N narrowband — wa.skopasmowy noise — szum, zaklocenie szumowe noninverting amplifier - wzmacniacz nieodwracajajcy

o opamp, operational amplifier - wzmacniacz operacyjny open circuit — rozwarcie operating point — punkt pracy oscillator - generator output — wyjscie output stage - stopien wyjsciowy overshoot - maksymalna amplituda oscylacji, "przerost" odpowiedzi jednostkowej

P parasitic - pasozytniczy peak value — wartosc szczytowa peak-to-peak value — wartosc miedzyszczytowa phase angle — ka_t fazowy phase shift - przesuni cie fazowe photodiode — fotodioda piecewise linear - odcinkami liniowy pin — koncowka PM (phase modulation) - modulacja fazy pole - biegun power — moc power gain - wspolczynnik wzmocnienia mocy power electronics - energoelektronika power supply — zasilacz primary winding — uzwojenie pierwotne probe - sonda

-269-


pulse — impuls PWM (pulse width modulation) — modulacja szerokosci impulsow

Q Q-point (quiescent point) - punkt pracy (punkt spoczynkowy) quantization - kwantowanie quartz crystal — krysztal kwarcowy

R reactance — reaktancja receiver — odbiornik recording head — glowica zapisuja.ca rectifier — prostownik regulator - stabilizator reverse bias — polaryzacja zaporowa resistance — rezystancja resistor - opornik, rezystor reverse recovery time — czas wyla.czania diody ringing — oscylacje ripple - t^tnienia rise time — czas narastania rms value (root mean square value) - wartosc skuteczna

s sample — probka, (to s.) probkowac sampling — probkowanie saturation - nasycenie secondary — wtorny secondary winding — uzwojenie wtorne second harmonic — druga harmoniczna self-bias - samopokryzacja semiconductor — polprzewodnik sensitivity — wrazliwosc schematic diagram - schemat ideowy short circuit - zwarcie short circuit gain — zwarciowy wspolczynnik wzmocnienia shunt — zwierac, bocznikowac slope - nachylenie small-signal - malosygnalowy smoothing capacitor - kondensator wygladzaja.cy source — zrodlo speaker - glosnik spectrum — widmo storage interval - czas magazynowania, czas pierwszej fazy wyla_czania diody stored charge — ladunek zmagazynowany stray — rozproszony switch - przel%cznik system - system, uklad

-270-


T tangent — styczna terminal — zacisk, koncowka diermal voltage (KT) - potencjal elektrokinetyczny threshold — prog direshold voltage - napiecie progowe tilt - zwis (grzbietu impulsu) time constant - stala czasowa total harmonic distortion - wspolczynnik zawartosb harmonicznych ttansconductance — transkonduktancja, przewodnosc wzajemna transducer - przetwomik transfer function — transmitancja transit rime - czas przelotu transition time - czas drugiej fazy wyla.czania diody transresistance - transrezystancja, opornosc wzajemna transmitter — nadajnik turns ratio — przekladnia transformatora

u unilateral - unilateralny unit - jednostka

V variable-capacitance diode (varicap) - dioda pojenmosciowa voltage — napi?cie voltage-controlled — sterowany napieciem voltage gain — wspolczynnik wzmocnienia napi?ciowego

w waveform — przebieg wavelength — dlugosc fali wideband — szerokopasmowy winding — uzwojenie

z Zener diode — dioda Zenera

- 2 7 1 -

Rating Symbol M B i t 2N2222 2N2222A Unit

CoHector-Emitter Voltage VCEO 30 40 Vdc

Collector-Base Voltage VCBO 60 75 Vdc

Emtoar-Baaa Voltage VEBO &0 &0 Vdc

Coaartcr Currant—Continuous t •00 HO mAdc

2M22MA M B B >

Total Davica Wtaliiatlon # T * - 2 5 X Derate above 2S*C

*> OJ)

*5! 0L4 Z2»

Watt m W C

Total Device DMpanon 9 T C . 2 5 * C :

Darata abova 2S*C

*D 3 4 17.1

1.2 •JJS

Wans

mwrc Opafatiiiy and Ssorage Junction

Tamparatura Ranga TJ.Tstg - • 5 1 0 + 2 0 0 •c

THERMAL CHAHACItWSI ICS

C k - a ^ a r i a * Symbol 2N221SA 2N2219.A 2M222ZA Unit

Tharmal Resistance. Junction to Ambiant B«JA 219 145.8 •c/w Thannal floi'mema. Junction to Caaa «*JC 58 437.5 •ow

a£CTWCALCHAWACIH«IICS{TA-25Xunla«aothaiwi»ar>otad.>

OFF CHARM. 11MB IM. 8 CoRactor-EmJttar Breakdown V o t a g a

OC - 10 m A d c *B - 0) Non-A Suffix A-Suffix

V(BfttCEO 30 4 0

— Vdc

Coaector-Base Breakdown Vokaga 0 c - l O j i A d c l E - 0) Non-A Suffix

A-Suffix

V<BRICBO 80 75

— Vdc

EmMer-Bese Braakdown Vokaga flE - 1 0 / i A d c . l c - 0) NorvA Suffix

' A-Suffix

V(BR)EBO 5.0 6.0

— Vdc

Collector Cutoff Currant ( V C E - 6 0 V d c . V E B ( o f f ) - l O V d e ) A-Suffix

<CEX — 10 nAdc

Collactor Cutoff Currant ( V C B - S o V d c l E - 0) Non-A Suffix (VC8 - O0 Vdc. I E - 0) A-Suffix ( V C B - * 0 V d c . l E - 0 . T A - 150*C) Non-A Suffix W c B - M V d c ; » E - 0 . T A - 1 5 0 * C ) A-Suffix

•CBO 1 1 1

1

aoi 0.01 10 10

MAdc

Emitter Cutoff Currant

( V E B - 3.0 V d c <C - ° ) A-Suffix 'EBO — 10 nAdc

Base Cutoff Currant (VcE - » V d c VEB(off) - 3.0 Vdc) A-Suffix

'BL — 20 nAdc

ON CHARACTERISTICS 0C Current Gain

flC - 0.1 mAdc VCE - 10 Vdc) 2N2218A 2N2219A 2N2222.A

"FE 20 35

— "

Clc - 10 mAdc. VCE = W Vdc) 2N2218A 2N2219A. 2N2222.A

25 50

—

lie - 10 mAdc VCE " lOVdeMI) 2N2218A 2N2219.A. 2N2222.A

35 75

—

OC - 10 mAdc VCE = 10 Vdc, TA - -55*CMD

2N2218A 2N2219A 2N2222.A

15 35 —

( l c = 150 mAdc. VCE = 10 Vdc)(1) 2N2218A 2N2219.A. 2N2222.A

40 100

120 300

MOTOROLA SMALL-SIGNAL TRANSISTORS. FETs AND DIODES

2N2218A/19/19A/22/22A

MOTOROLA SMAI-l S'GNAl. TRANSISTORS, FETs AND DIODES

2N2218A/19/19A/22/22A

MOTOROLA SMALL-SIGNAL TRANSISTORS. FETs AND DIODES

2N2218A/19/19A/22/22A

SWITCHING TIME CHARACTERISTICS

MOTOROLA SMALL-SIGNAL TRANSISTORS, FETs AND DIODES

Q'TQBM- s

- .

7 ' • . ' , • ' . - '

This textbook, describes principle of operation arid properties of basic analog electronic circuits that comprise diodes, field-effect and bipolar transistors, including, negative and positive feedback circuits. It is arnply illustrated by computer sitnulationT* using PSpice program. Numerous probk exercises to be solved by the reader are ] Review questions are included to turn the r elements of the theory' and to help sorting tjwi E n g l i s h - P o l i s h d i c t i o n a r y of s e l e c T h e b o o k i s a p r e s c r i b e d , t e x t I n t e r n a t i o n a l ^ JFaculty of E n g i n e e r i n of Lodz. It is' also r e C o m m e n d p to s t u d y b a s i c e l e c t r o n i c c i r . c /u i t s t e r m i n o l o g y . A m o d e r n , appl ic^at io s t udy ing e l ec t ron i c s is refleVc^tfe^r ifi^ may be a v a l u a b l f r e f e r e n c e T f o r p

210000076947

Dlitechnikatodzka^odz-biblioteka

* * * *

•

Professor Andrzej «&fmterka (Senior Member, IEEE) was graduated in radio engineering From Warsaw University of Technology in 1972. He has authored and co-authored 3 monographs and more than 100 technical papers, most of ^them published in international journals and conference proceedings. In 1980-82 he worked on microwave MESFET oscillators in Shizuoka University, Japan. In 1991-94 he was with Monashy University, Australia lecturing analog'

of Electronics and Head of Medical Electronics Division, Technical University of Lodz. His current research interests include computer vision and applications of a r t i f i c i a l i n t e l l i g e n c e ( h t t p i Z / w w w ^ e l e t e L p J o d z ^ p l V -

El e< ZtV4 - Cybra

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