EC25 Reference Design - Aurora Evernet

EC25 Reference Design

LTE Module Series

Rev. EC25_Reference_Design_Rev.G

Date: 2018-02-09

Status: Released

www.quectel.com

http://www.quectel.com/

LTE Module Series EC25 Reference Design

EC25_Reference_Design 1 / 6

Our aim is to provide customers with timely and comprehensive service. For any

assistance, please contact our company headquarters:

Quectel Wireless Solutions Co., Ltd.

7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, China

Tel: +86 21 5108 6236

Email: [email protected]

Or our local office. For more information, please visit:

http://quectel.com/support/sales.htm

For technical support, or to report documentation errors, please visit:

http://quectel.com/support/technical.htm

Or Email to: [email protected]

GENERAL NOTES

QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION

PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT

TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT

MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT

ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR

RELIANCE UPON THE INFORMATION. ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO

CHANGE WITHOUT PRIOR NOTICE.

COPYRIGHT

THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF

QUECTEL WIRELESS SOLUTIONS CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION

AND EDITING OF THIS DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT ARE

FORBIDDEN WITHOUT PERMISSION. OFFENDERS WILL BE HELD LIABLE FOR PAYMENT OF

DAMAGES. ALL RIGHTS ARE RESERVED IN THE EVENT OF A PATENT GRANT OR

REGISTRATION OF A UTILITY MODEL OR DESIGN.

Copyright © Quectel Wireless Solutions Co., Ltd. 2018. All rights reserved.

mailto:[email protected]

mailto:[email protected]



About the Document

History

Revision Date Author Description

A 2016-04-01 Winter CHEN Initial

B 2016-08-22 Yeoman CHEN

1. Added ADC interface design in Sheet 1

2. Added power supply for codec in Sheet 3

3. Added note for UART Translator (Transistor

Solution) in Sheet 4

4. Changed some DGND to AGND in audio design in

Sheet 5

C 2016-10-14 Eden LIU Added the reference design of SGMII and FC20

module

D 2016-11-11 Power JIN

1. Modified the connection of network name

PCM_IN_BT and PCM_OUT_BT in Sheet 1

2. Added note 7 in Sheet 7

3. Added note 6 in Sheet 9

E 2017-04-06 Eden LIU

1. Newly opened pins 37~40 for BT UART, and

removed the multiplexing between Main UART

and BT UART in Sheet 1

2. Newly opened the SD card interface

3. Added the power supply control pin of SD card

interface in Sheet 2

4. Modified network name TXD_MCU as RXD,

RXD_MCU as TXD, CTS_MCU as CTS,

RTS_MCU as RTS, RI_MCU as RI, DCD_MCU as

DCD, DTR_MCU as DTR in Sheet 2 and Sheet 4

5. Modified the power supply circuit for PCM Codec

in Sheet 3

6. R0904 is not mounted because SDIO_CLK in

FC20 is pulled up internally

7. Modified network name PCM_IN_BT as



PCM_OUT_BT, PCM_OUT_BT as PCM_IN_BT in

Sheet 1 and Sheet 9

8. Modified the unidirectional off-page connectors of

SDIO_CMD, SDIO_D0, SDIO_D1, SDIO_D2 and

SDIO_D3 to bidirectional ones in Sheet 1 and

Sheet 9

9. Removed resistors R912, R913 and added

resistor R0920 in Sheet 9

10. Added the reference design for SD card interface

in Sheet 10

11. Modified the drive circuit of indicator STATUS in

Sheet 11

F 2017-06-15 Lorry XU

1. Modified the names of the pins 28~33 on U0101-A

from SD2_XXX to SDC2_XXX in Sheet 1

2. Modified the unidirectional off-page connectors

TXD and RXD that connect to U0201 in Sheet 2

3. Added resistors R0524, R0525 to pins 17, 20 on

audio codec ALC5616 respectively in Sheet 5 and

added note 2

4. Added Sheet 6 of the reference design for audio

codec TLV32AIC3104 (Optional)

5. Moved the reference design for audio interfaces

(handset and earphone applications) to Sheet 7

and added notes 3~7

6. Renamed the components in Sheets 7~13 (due to

the addition of Sheet 6)

7. Added capacitors C1202, C1204 and C1205 for

SD card interface in Sheet 12 and removed the

previous note 3

8. Added a TVS component D1304 on USB_BOOT

network in Sheet 13

G 2018-02-09 Woody WU

1. Changed R0110 and R0112 to L0101 on the USB

differential signals in Sheet 1

2. Added C0201, C0202 and C0203 capacitors on

the PWRKEY, WAKEUP_IN_EC25 and

W_DISABLE_EC25 signals in Sheet 2

3. Deleted C0201 capacitor between Q0205 source

and gate electrodes in Sheet 2

4. Changed R0407~R0409 resistors value from 22R

to 0R in Sheet 4

5. Added R0618~R0621 0R resistors on 19, 23, 29

and 30 pins of U0601 in Sheet 6

6. Added pull-down resistors R1119~R1121 on

COEX_UART_RX, COEX_UART_TX and



RTS_BT signals in Sheet 11

7. Changed STATUS reference design in Sheet 13

8. Changed R1306 resistance from 10K to 4.7K in

Sheet 13



Contents

About the Document ................................................................................................................................... 2

Contents ....................................................................................................................................................... 5

1 Reference Design ................................................................................................................................. 6

1.1. Introduction ................................................................................................................................ 6

1.2. Schematics ................................................................................................................................ 6



1 Reference Design

1.1. Introduction

This document provides the reference design for Quectel EC25 module.

1.2. Schematics

The schematics illustrated in the following pages are provided for your reference only.

TITLEPROJECT

Reference Design

A2

EC25

2018/2/9DATE

G

1 13

VERSIZE

Quectel Wireless Solutions

B

C

D

6 5 4 3 2 1

D

C

B

A

SHEET

123456

A

OF

DRAWN BY

CHECKED BY

Woody WU

Lorry XU

Module Interface

1. Keep all RESERVED and unused pins unconnected, and ensure all GND pins are connected to the ground network.Notes:

2. Pins 73～84 are unused in the design, and can be ignored in schematic and PCB decal.

3. A common mode choke L0101 is recommended to be added in series between the module and customer’s MCU in order to

Meanwhile, it is recommended to reserve the test points for upgrading the firmware over USB interface and minimize the

4. ADC pins can not be directly connected to the module's power supply and the input voltage must not exceed VABT_BB.5. C0101 and C0102 must be placed close to the SGMII interface of the module.

Note 3

Note 6

Note 6

Note 4

EC25

EC25

Note 5

extra stubs of the trace. The two resistors should be placed close to the module.

suppress EMI spurious transmission, and it should be placed close to the module.

Note 6

6. Do not pull up WAKEUP_IN, NET_MODE, BT_CTS, COEX_UART_TX, COEXT_UART_RX and WLAN_EN pins unlessthe module starts up sucessfully.

7. When the EC25 module and the FC20 module are used jointly,the BT_UART and PCM interfaces of the EC25 module areconnected to the FC20 module BT_UART and PCM interfaces

Meanwhile, these pins should be served as a keepout area.

respectively.

R0111 NM_0R

R0109 NM_0R

R0113 100K

R0114 100K

R0116100K

R0115100K

R0117 NM_0R

R0118 0R

R0119 NM_0RR0120 0R

R0121 NM_0RR0122 0R

R0123 NM_0RR0124 0R

R0108 0R

R0104 0R

R0106 0R

R0102 0R

1 WAKEUP_IN2 AP_READY3 RESERVED4 W_DISABLE#5 NET_MODE6 NET_STATUS7 VDD_EXT

8 GND9 GND

10 USIM_GND11 DBG_RXD12 DBG_TXD13 USIM_PRESENCE14 USIM_VDD15 USIM_DATA16 USIM_CLK17 USIM_RST18 RESERVED

19G

ND

20R

ES

ET

_N

21P

WR

KE

Y

22G

ND

23S

D2_

INS

_DE

T

24P

CM

_IN

25P

CM

_OU

T

26P

CM

_SY

NC

27P

CM

_CLK

28S

DC

2_D

AT

A3

29S

DC

2_D

AT

A2

30S

DC

2_D

AT

A1

31S

DC

2_D

AT

A0

32S

DC

2_C

LK

33S

DC

2_C

MD

34V

DD

_SD

IO

35A

NT

_DIV

36G

ND

37BT_RTS

38BT_TXD

39BT_RXD

40BT_CTS

41I2C_SCL

42I2C_SDA

43RESERVED

44ADC1

45ADC0

46GND

47ANT_GNSS

48GND

49ANT_MAIN

50GND

51GND

52GND

53GND

54GND

55R

ES

ER

VE

D56

GN

D57

VB

AT

_RF

58V

BA

T_R

F59

VB

AT

_BB

60V

BA

T_B

B61

ST

AT

US

62R

I63

DC

D64

CT

S65

RT

S66

DT

R67

TX

D68

RX

D69

US

B_D

P70

US

B_D

M71

US

B_V

BU

S72

GN

D11

5U

SB

_BO

OT

116

RE

SE

RV

ED

113

RE

SE

RV

ED

114

RE

SE

RV

ED

141 RESERVED142 RESERVED 143RESERVED

144RESERVED

U0101-A

85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97 GND98 GND99 GND

100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND 111GND

112GND

117RESERVED

118WLAN_SLP_CLK

119EPHY_RST_N

120EPHY_INT_N

121SGMII_MDATA

122SGMII_MCLK

123SGMII_TX_M

124SGMII_TX_P

125SGMII_RX_P

126SGMII_RX_M

127PM_ENABLE

128USIM2_VDD

129SDC1_DATA3

130SDC1_DATA2

131SDC1_DATA1

132SDC1_DATA0

133SDC1_CLK

134SDC1_CMD

135WAKE_ON_WIRELESS

136WLAN_EN

137COEX_UART_RX

138COEX_UART_TX

139BT_EN

140RESERVED

U0101-B

R01010R

R01030RR01050RR01070R

C0101 100nFC0102 100nF

1 2

34

L0101

DLM0NSN900HY2D

[4] USIM_GND[13] DBG_RXD[13] DBG_TXD

[4] USIM_VDD

[4] USIM_CLK[4] USIM_RST

[4] USIM_DATA

[2,3,4,9,11,12,13] VDD_EXT

[13] NET_STATUS

[13] NET_MODE[2] W_DISABLE_EC25

[2] AP_READY_EC25

[2] RESET_N[2,13] PWRKEY

[8]

AN

T_D

IV

[8]ANT_MAIN

[8]ANT_GNSS

[2,13] USB_VBUS

[4] RXD_EC25

[4] TXD_EC25

[4]

DT

R_E

C25

[4] RTS_EC25

[4] CTS_EC25

[4]

DC

D_E

C25

[4]

RI_

EC

25[1

3]S

TA

TU

S[1

,3,1

3]V

BA

T

[1,3

,13]

VB

AT

[4] USIM_PRESENCE

[5,6] CODEC_PCM_IN

[5,6] CODEC_PCM_OUT

[5,6] CODEC_PCM_SYNC

[5,6] CODEC_PCM_CLK

[5,6]I2C_SDA

[13] USB_DM_TEST

[13] USB_DP_TEST

ADC0_INPUTADC1_INPUT

[5,6]I2C_SCL

[11] PCM_IN_BT

[11] PCM_OUT_BT

[11] PCM_SYNC_BT

[11] PCM_CLK_BT

[13] USB_BOOT

[2] WAKEUP_IN_EC25

[11] BT_EN[11]COEX_UART_TX[11]COEX_UART_RX[11]WLAN_EN

[11]WAKE_ON_WIRELESS[11]SDIO_CMD[11]SDIO_CLK[11]SDIO_D0[11]SDIO_D1[11]SDIO_D2[11]SDIO_D3

[11]WLAN_SLP_CLK

[3]PM_ENABLE

[11]CTS_BT

[11]RTS_BT[11]TXD_BT

[11]RXD_BT

[12] SD2_INS_DET

[12]

SD2_

DAT

A3

[12]

SD2_

DAT

A2

[12]

SD2_

DAT

A1[1

2]SD

2_D

ATA0

[12]

SD2_

CLK

[12]

SD2_

CM

D

[12]

VDD

_SD

IO

[9]USIM2_VDD

[9]SGMII_RX_M[9]SGMII_RX_P

[9]SGMII_TX_P[9]SGMII_TX_M[9]SGMII_MDIO_CLK[9]SGMII_MDIO_DATA[9]EPHY_INT_N[9]EPHY_RST_N

[2] USB_DP

[2] USB_DM

TITLEPROJECTLorry XU

Woody WU

CHECKED BY

DRAWN BY

OF

A

6 5 4 3 2 1

SHEET

A

B

C

D

123456

D

C

B


SIZE VER

132

G

DATE 2018/2/9

EC25

A2

Reference Design

5V power source from main board.

It is used to reset the module.It is used to turn on or off the module.

MCU Interface

OTG function. The USB_VBUS pins of MCU and EC25 should be powered by a 5V power system for USB detection, and VBUS_CTRL is used to turn on/off2. EC25 can only work as a USB device and supports Full Speed and High Speed modes. To communicate with USB interface, MCU needs to support USB host or1. U0201 represents customer's MCU. The power domain of GPIO interfaces on EC25 modules is 1.8V, if the domain on U0201's GPIO interfaces is the same, then the level translation circuit can be omitted.Notes:

USB_VBUS power supply.3. AP_READY is used to detect the MCU's sleep state. For more details, please refer to

It is used to wake up the module. It is used to let the module enter the airplane mode.

4. WAKEUP_IN_EC25 should should be kept at low level before the module starts up successfully.Quectel_EC25_Hardware_Design.

G

S D

Q0205

SI2333CDS-T1

Q0207

DTC043ZEBTL

R0204

10K

Q0202

DTC043ZEBTLQ0201

DTC043ZEBTL

Q0206

2SC4617TLQ

R02014.7K R0202

4.7K

Q0204

DTC043ZEBTL

Q0203

DTC043ZEBTL

VDDGNDTXDRXDCTSRTS

USB_VBUSUSB_D+USB_D-

GPIO_01GPIO_02GPIO_03

USB_ID

GPIO_04GPIO_05GPIO_06GPIO_07GPIO_08GPIO_09GPIO_10GPIO_11GPIO_12GPIO_13

RIDCDDTR

U0201C0201

10nF

C0202

10nF

C0203

10nF

C0204

1nF

VDD_MCU

[4]RXD[4]TXD

[1]USB_DP[1]USB_DM

[1,2,13]USB_VBUS

[2]ON/OFF_MCU[2]RESET_MCU

[2]VBUS_CTRL

[3,13] DC_5V [1,2,13]USB_VBUS

[2] VBUS_CTRL

[2]W_DISABLE_MCU[2]SLEEP_STATUS

[1]RESET_N

[2] RESET_MCU

[1,13]PWRKEY

[2] ON/OFF_MCU

[4]CTS[4]RTS

[3]VBAT_EN

[1] AP_READY_EC25 [2]SLEEP_STATUS

VDD_EXT VDD_EXT

[1]W_DISABLE_EC25

[2] W_DISABLE_MCU

[3]CODEC_POWER_EN

[1]WAKEUP_IN_EC25

[2] WAKEUP_IN_MCU

[2]WAKEUP_IN_MCU[12]SD_PWR_EN

[4]DTR

[4]RI[4]DCD

G

EC25

PROJECT TITLELorry XU

Woody WU

CHECKED BY

DRAWN BY

OF

A

6 5 4 3 2 1

SHEET

A

B

C

D

123456

D

C

B


SIZE VER

133 DATE 2018/2/9

A2

Reference Design

DC-DC Application

Notes:

2. VBAT should be routed in star mode to VBAT_BB and VBAT_RF pins.

Power Supply Design

VBAT DesignClosed to VBAT_BB pins.

Closed to VBAT_RF pins.

1. The power supply must be able to provide sufficient current up to 2A or more.

VDD_1V8 = (R0310/R0312+1)*1.207 = 1.8V

Power Supply for PCM CodecVDD_3.3V = (R0305/R0308+1)*1.207 = 3.3V

LDO ApplicationIt is used when the input voltage is below 7V.

VBAT = (R0301/R0307+1)*1.24 = 3.88VThe recommended load current is greater than 10mA.

Power Supply for FC20, SGMII and SD Card

VBAT = (R0314/R0318+1)*1.24 = 3.3V

Notes:

DC-DC LDO

LDODC 1.8V

LDO DC 3.3V

Codec

LDO FC20DC 3.3V 3.0A

EC25

SD Card

DC 5V OUT DC 3.8V 2.0Ae.g. DC12V IN

3. The recommended operating voltage of VBAT is 3.3V～4.3V.

2. The RC circuit, which is assembled with R0317 and C0327,

Note 2

1. The recommended load current of MIC29302WU is greater than 10mA.

Notes:1. CODEC_POWER_EN must be at low level in order to ensure the normal output voltage of VDD_3.3V.

2. The following power-on/off sequences should be complied with to ensure the audio codec

Power-on Sequence: power on VDD_1V8 first, then VDD_3.3V.

Note 1

If VDD_3.3V power supply needs to be switched off, please keep CODEC_POWER_EN at high level.

SGMII

It is used when the input voltage is above 7V. Use a DC-DC converter to convert a high input voltageinto a 5V output, and then the LDOs will generate 3.8V, 3.3V and 1.8V typical voltages.

is used to delay the start-up of MOSFET switch circuit.

Power-off Sequence: power off VDD_3.3V first, then VDD_1V8.

works normally.

+

C0301

100uF

C0302

100nF

C0303

33pF

C0304

10pF

C0306

100nF

C0307

33pF

C0308

10pF

+

C0305

100uF

D0301

PZ3D4V2H

1 IN3 EN

5OUT4BP

2G

ND

U0303

SGM2019-ADJYN5G/TR

C0320

4.7uF

R0310

39K1%

R0312

75K1%

C0318

100nFC0321

100nF

C0322

33pF

C0319

1uF

C0315

4.7uF

R030573.2K1%

R030842.2K1%

C0316

100nF

C0313

1uF

C0314

100nF

1 IN3 EN

5OUT4BP

2G

ND

U0302

SGM2019-ADJYN5G/TR

C0317

33pF

R030610K

+ C0311

470uF

1E

N

2 IN

3G

ND

4OUT

5A

DJ

U0301

MIC29302WU

C0312

100nF

C0310

100nF

+ C0309

470uF

R0301100K1%

R030747K1%

R0302

51KR0303330R

Q0301DTC043ZEBTL

R0311

100K

R0309 0R

+ C0325

470uF1E

N

2 IN

3G

ND

4OUT

5A

DJ

U0304

MIC29302WU

C0326

100nF

C0324

100nF

+ C0323

470uF

R0314

75K1%

R031847K1%

R0313

51KR0315

330RR0316

10K

G

S D

Q0302

SI2333C0327

100nF

R0317

100K

Q0303

DTC043ZE

Q0304

DTC043ZE

[1,3,13]VBAT

[1,3,13]VBAT

VBAT

VDD_1V8

VDD_3.3V[2,3,13] DC_5V

[2] CODEC_POWER_EN

[2,3,13] DC_5V

VBAT

[2] VBAT_EN

[2,3,13] DC_5V

[1,2,4,9,11,12,13] VDD_EXT

[2,3,13] DC_5V

VDD3V3

[1] PM_ENABLE

[11]VDD3V3_FC20

[3,5,6] VDD_1V8


Woody WU

CHECKED BY

DRAWN BY

OF

A

6 5 4 3 2 1

SHEET

A

B

C

D

123456

D

C

B


SIZE VER

134

G

DATE 2018/2/9

EC25

A2

Reference Design

(U)SIM and UART Designs

UART Translation - Transistor Solution

UART Translation - IC Solution

Notes:

(U)SIM Interface

1. There are two translation solutions: transistor solution and IC solution,

3. The transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps.The 1nF capacitors C0402 and C0403 can improve the signal quality.

2. The power supply voltage of VCCA should not exceed that of VCCB.

Notes:1. U401 is recommended to be used to offer good ESD protection,

2. It is recommended to connect the (U)SIM card connector GND to the module USIM_GND.

3. The pull-up resistor R0401 can improve anti-jamming capability,

4. R0407～R0409 are used for debugging,

5. C0401 capacitance should be less than 1uF,4. The RTS and DTR transistor circuits are similar to that of RXD interface.

If the ground is complete on customers' PCB, USIM_GND can be connected to PCB ground directly.

Quectel_EC25_Hardware_Design.

and the parasitic capacitance should not be more than 15pF.

and should be placed close to the (U)SIM card connector.

6. For more information about the layout, please refer to

For more information about TXS0108E, please refer to the datasheet from TI.

The CTS, RI and DCD transistor circuits are similar to that of TXD interface.

C0404～C0406 are used for filtering interference of GSM900MHz.

and should be placed close to the (U)SIM card connector.

and it is recommended to select the IC solution.

Q0401

2SC4617TLQ

Q0402

2SC4617TLQ

R040610K

R0405

10K

R040310K

R040410K

C0401 100nF

1GND

2VPP

3I/O4 CLK

5 RST

6 VCC

78 PRESENCE

J0401

(U)SIM card connector

1

2

3 4 5 6

U0401 ESDA6V8AV6

R0402

51K

C0405

33pF

C0406

33pF

C0404

33pF

R0407 0R

R0408 0R

R0409 0R

R040115K

C0407100nF

R0411120K

R041010K

C0408 100nF

6 A5

7 A6

8 A7

9 A8

10 OE

5 A4

4 A3

19VCCB

20B1

18B2

14B6

13B7

12B8

11GND

3 A2

2 VCCA

1 A1

17B3

16B4

15B5

U0402

TXS0108E

C0403

1nF

C0402

1nF

[2,4] RXD [1,4]RXD_EC25

VDD_EXTVDD_EXT

[2,4] TXD [1,4]TXD_EC25

VDD_EXTVDD_MCU

[1]USIM_GND

VDD_EXTUSIM_VDD

[1] USIM_RST

[1] USIM_CLK

[1] USIM_DATA

USIM_VDD

[1] USIM_PRESENCE

VDD_EXT

VDD_EXT VDD_MCU

[1,4] TXD_EC25

[1,4] RXD_EC25

[1] RI_EC25

[1] DTR_EC25

[2,4]TXD

[2,4]RXD

[2]DTR

[2]RI

[2]CTS

[2]RTS

[1] CTS_EC25

[1] RTS_EC25

[1] DCD_EC25 [2]DCD


Woody WU

CHECKED BY

DRAWN BY

OF

A

6 5 4 3 2 1

SHEET

A

B

C

D

123456

D

C

B


SIZE VER

135

G

DATE 2018/2/9

EC25

A2

Reference Design

Audio Codec Design (ALC5616)

1. ALC5616 power-on sequence: DBVDD/I2C pull-up power/AVDD/DACREF/CPVDD -> MICVDD -> software initialization.Notes:

2. ALC5616 power-off sequence: close codec function by software-> MICVDD -> DBVDD/I2C pull-up power/AVDD/DACREF/CPVDD.3. EC25 module will automatically initialize the codec via I2C interface after it is turned on successfully, so all power supplies for the codec need to be powered on before that.

2 IN1P/DMC_DAT

3 IN2P4 IN2N/JD2

5D

AC

RE

F6

AV

DD

7A

GN

D

10LOUTR/N

11CPN2

12CPP2

13CPN1

14CPP1

15C

PV

DD

16CPVPP

18CPVREF

19CPVEE

20HPO_L

21 ADCDAT1

22 DACDAT1

23 LRCK1

26SCL

27SDA

28 GPIO1/IRQ1

29D

BV

DD

30D

CV

DD

31M

ICV

DD

32 MICBIAS1

8VREF2

24 BCLK1

1 JD1

9LOUTL/P

17HPO_R

25 MCLK

33D

GN

DU0501

ALC5616

C0504

4.7uF

C0505

4.7uF

C0506

100nF

R0503 0R

C0502

4.7uF

C0503

100nF

C05

112.

2uF

C05

1210

0nF

C05

074.

7uF

C05

0810

0nF

C05

102.

2uF

C0514 2.2uF

C0516 2.2uF

C0513 4.7uF R0507

0R

R0516 NM_10KR05174.7K

R0518

4.7K

C0528 4.7uF

C0523 2.2uFC0524 2.2uF

R0509 0R

R0511 0RR0513 0R

R0515 0R

C0526

NM

C0525

NM

C0527

NM

C0515 2.2uFC0517 2.2uF

R05141K

R05061.5K

R05051K

R05081.5K

C051910uF

R0502 0R

C0518 1uFC0520 1uF

C0521 1uFC0522 1uF

R0510 0RR0512 0R

R05010R

R05040R

C05

09N

M_3

3pF

C0501

NM_33pF

R0519 0RR0520 0R

VD

D_3

.3V

VD

D_1

V8

VDD_3.3V[1,6]I2C_SDA[1,6]I2C_SCL

VD

D_1

V8

VDD_1V8

[1,6] CODEC_PCM_OUT[1,6] CODEC_PCM_IN[1,6] CODEC_PCM_CLK[1,6] CODEC_PCM_SYNC

[5] MIC+[5] MIC-

[6,7]SPK_P[6,7]SPK_N

MICBIAS

[6,7] MIC_P[6,7] MIC_N

MICBIAS

[5]MIC+[5]MIC-

VDD_1V8

[6,7]SPK_R[6,7]SPK_L

PROJECT TITLE

A2

EC25 Reference Design

2018/2/9DATE

G

6 13

VERSIZE


B

C

D

6 5 4 3 2 1

D

C

B

A

SHEET

123456

A

OF

DRAWN BY

CHECKED BY

Woody WU

Lorry XU

Power on reset

Differential signals, connect to handset and audio power amplifier

Left and right channels, connect to headset

Delay Circuit

Audio Codec Design (TLV320AIC3104)

1. TLV320AIC3104 power-on sequence: IOVDD -> AVDD/DRVDD -> DVDD -> software initialization.Notes:

2. The RC delay circuit, which is assembled with C0621 and R0608, is used to ensure that the power-on time difference between AVDD and DVDD is within 5ms.

4. EC25 module will automatically initialize the codec via I2C interface after it is turned on successfully, so all power supplies for the codec need to be powered on before that.3. The RESET pin must be driven at low level for at least 10ns after all power supplies for TLV320AIC3104 are at their specified values.

1M

CLK

2B

CLK

3W

CLK

4D

IN

5D

OU

T

6DVSS

7IOVDD

8S

CL

9S

DA

10 MIC1LP/LINE1LP11 MIC1LM/LINE1LM

12 MIC1RP/LINE1RP13 MIC1RM/LINE1RM

14 MIC2L/LINE2L/MICDET

15 MICBIAS

16 MIC2R/LINE2R

17AVSS1

18DRVDD

19H

PLO

UT

20H

PLC

OM

21DRVSS

22H

PR

CO

M

23H

PR

OU

T

24DRVDD

25AVDD

26AVSS2

27LE

FT

_LO

P28

LEF

T_L

OM

29R

IGH

T_L

OP

30R

IGH

T_L

OM

31R

ES

ET

32DVDD

33G

ND

U0601TLV320AIC3104

C0619 100nF

C0618 100nF

R0614

1.5K

R06161.5K

C0613

2.2uF

C06

0510

0nF

C06

1110

uF

C06

061u

F

C06

0710

0nF

C06

081u

F

C06

101u

F

C06

1410

0nF

C06

151u

F

R0613 0R

C06

1610

0nF

C06

171u

F

C0622 1uFC0623 1uF

R0607 10K

R0605 0RR0604 0R

R0601 0RR0603 0R

C0612

100nF

C0603

NM

C0601

NM

C0602

NM

C06

0910

0nF

R06091K

R06121K

C0620

10uF

R06104.7K

R0611

4.7K

R061710K

G

S D

Q0601

Si2333DS-T1-E3

C0621

10nF

R0608100K

Q0602

DTC043ZEBTL

R0615 NM_0R

C0624 22uF

C0604 22uF

R0606 NM_0R

R0602 0R

R0618 0RR0619 0R

R0620 0R

R0621 0R

[5,7] MIC_P[5,7] MIC_N

MICBIAS_3104

[1,5] I2C_SCL[1,5] I2C_SDA

VDD_3.3V

VDD_1V8

[5,7]SPK_P

[5,7]SPK_N

DVDD

[1,5] CODEC_PCM_CLK[1,5] CODEC_PCM_SYNC

[5,7]SPK_R

[5,7]SPK_L

[3,5,6] VDD_1V8 [6]DVDD

[3,5,6] VDD_3.3V[6]DVDD

[3,5,6] VDD_1V8

[1,5] CODEC_PCM_OUT[1,5] CODEC_PCM_IN

PROJECT TITLELorry XU

Woody WU

CHECKED BY

DRAWN BY

OF

A

6 5 4 3 2 1

SHEET

A

B

C

D

123456

D

C

B


SIZE VER

137

G

DATE 2018/2/9

EC25

A2

Reference Design

Handset Application

Earphone Application

Close to earphone interface

Notes:

Audio Interface

CTIA OMTPR0702/R0705R0701/R0704 M

MNMNM

1. The analog output only drives earphone and headset. For larger power loads such as speakers, an audio power amplifier should be added in the design.2. In handset application, both the MIC and SPK signal traces need to be routed as differential pairs.3. In earphone application, the MIC signal traces need to be routed as differential pairs.4. All MIC and SPK signal traces should be routed with total grounding and far away from noise such as clock and DC-DC signals, etc. 5. ALC5616 and TLV320AIC3104 cannot be used simultaneously in audio codec design.

4132

J0701

D07

01

ESD9X5.0ST5G

D07

02

C07

02

33pF

C07

04

33pF

C07

05

10pF

C07

03

10pF

C07

06

33pF

C07

01

10pF

C07

09

10pF

C07

10

33pF

C07

11

10pF

C07

12

33pF

C07

08

33pF

C07

07

10pF

C0713

10pF

C0714

33pF

C0715

4.7uF

D07

03

PESD5V0S1BL

D07

04

R0703 0R

R-0805

1

2

3

45

J0702

C07

16

10pF

C07

17

33pF

D07

05E

SD

9X5.

0ST

5G

R0702 NM_0R

R0701 0R

R0704 0R

R0705 NM_0R

D07

06P

ES

D5V

0S1B

L

C07

18

10pF

C07

19

33pF

D07

07P

ES

D5V

0S1B

L

C07

20

10pF

C07

21

33pF

F0701 0R

F0702 0R

F0704 0RF0703 0R[5,6] SPK_P

[5,6,7] MIC_P[5,6,7] MIC_N

[5,6,7] MIC_N

[5,6] SPK_N

[5,6] SPK_R

[5,6] SPK_L

[5,6,7] MIC_P

[5,6,7]MIC_P


Woody WU

CHECKED BY

DRAWN BY

OF

A

6 5 4 3 2 1

SHEET

A

B

C

D

123456

D

C

B


SIZE VER

138

G

DATE 2018/2/9

EC25

A2

Reference Design

RF and GNSS Designs

Main Antenna Circuit Diversity Antenna Circuit

GNSS Antenna Circuit

Notes:1. It is recommended to use PI type main/Rx-diversity/FC20 antenna circuit, thus ensuring convenient subsequent debugging.2. The diversity reception function is ON by default. If diversity antenna is not used, there is a need to use AT command to turn off diversity reception.3. An external LDO can be selected to supply power for active antenna.4. If passive antenna is used, then R0803 and L0801 are not needed.

Active Antenna

FC20 Antenna Circuit

5. The impedance of the RF signal traces must be controlled as 50Ω when routing.

Passive Antenna

C0801NM

R0801 0R

J0801

C0802NM C0803

NM

R0802 0R

J0802

C0804

NM

L0801

47nH

C0805

0.1uF

R080310R

C0808 100pF

J0804

C0809NM

C0810NM

C0806

NM

R0804 0R

J0803

C0807

NM

[1]ANT_MAIN [1]ANT_DIV

[1]ANT_GNSS

VDD

[11]FC20_ANT


Woody WU

CHECKED BY

DRAWN BY

OF

A

6 5 4 3 2 1

SHEET

A

B

C

D

123456

D

C

B


SIZE VER

139

G

DATE 2018/2/9

EC25

A2

Reference Design

To minimize crosstalk, the reset trace must be at least 20

R916 should be placed close to AR8033.

The traces of the resistor must be away from other

and the trace width needs to be at least 25 mils.

EMI filter is reserved. If LED pins are not used, keep C0920/C0923/C0924=470pF.

SGMII_MDIO_DAT should be connected to the USIM2_VDD

MODE 2

MODE 1

MODE 0

MODE 3

Ethernet PHY Design

PHY_

AD2

PHY_AD1PHY_AD0

traces (especially the clock and MDI interface traces),

The two capacitors should be selected according to the actualload capacitance of crystal and the board-level test results.

Close to AR8033

Notes:1. In the following description, the SGMII data signal refers to the SGMII TX and RX difference pair, and the SGMII control signal refers to the SGMII_MDIO_CLK, SGMII_MDIO_DATA, EPHY_RST_N and EPHY_INT_N.

3. Keep the maximum trace length of SGMII data signal less than 10-inch and keep skew of the TX and RX signals less than 20mil.4. The differential impedance of SGMII data signal is 100Ω±10%, and the reference ground of the area should be complete.

EXT_INT_SEL

5. Make sure the trace spacing between SGMII RX and TX is at least 3 times of the trace width, and the same to the adjacent signal traces.6. The peripheral circuit layout of Ethernet PHY chip AR8033 should be designed on a four-layer PCB,

7. RJ45, network transformer, AR8033, and the SGMII interface should be placed close to each other.

beside the module with a 1.5K pull-up resistor.

mils away from other signal traces.

L0901, C0913 and C0914 need to be placed close to Pin 3.

2. SGMII data and control signals should be strictly protected with ground and kept away from RF, analog, clock and DCDC signals etc.

and the second layer should be total grounded as the AR8033 reference GND.

1 MDC2 RSTN3 LX4 VDD335 INT6 XTLO7 XTLI8 AVDDL9 RBIAS

10 VDDH_REG11 TRXP012 TRXN0

13A

VD

DL

14T

RX

P1

15T

RX

N1

16A

VD

D33

17T

RX

P2

18T

RX

N2

19A

VD

DL

20T

RX

P3

21T

RX

N3

22N

C23

LED

_AC

T24

LED

_100

0 25CLK_25M

26LED_10_100

27RXD3

28RXD2

29VDDIO_REG

30RXD1

31RXD0

32RX_DV

33RX_CLK

34TX_EN

35GTX_CLK

36TXD0

37T

XD

138

TX

D2

39T

XD

340

WO

L_IN

T41

SD

42S

ON

43S

OP

44A

VD

DL

45S

IN46

SIP

47D

VD

DL

48M

DIO

49G

ND

U901AR8033-AL1B-R

R903

NM_100K

C910 NM_1uF

R916

2.37K 1%

R908 10K

R906 NM_10K

C921

0.1uF

C9250.1uF

C92

60.

1uF

C911

10uF

C927

1uF

C928

0.1uF

FB902

BLM15AX700SN1D

C922

1uF

C916

0.1uF

C915

100pF

1XTAL

2 GND 3XTAL

4 GND

Y901

25MHz C917

10pF

C918

10pF

C924 NM/470pF

C923 NM/470pF

C919

NM

C920

NM/470pF

D901

GREEN

R915 510R

R901 0R

C908 0.1uFC909 0.1uF

R904 0R

R907 0R

+C904

100uF

C902

33pF

C901

10pF

C903

100nF

C912

0.1uF

FB901

BLM15AX700SN1D

R905 NM_10K

L901

4.7uH

C913

10uF

C914

0.1uF

C905

0.1uF

R914 10K

R909 10K

R913 10K

R910 10KR911 10KR912 10K

R917 10KR918 10K

R9021.5K

C906

2.2uF

C907

0.1uF

[1] EPHY_RST_N

[1] EPHY_INT_N

AV

DD

_1V

1

[9]VDD33_SGMII

[1]SGMII_TX_M[1]SGMII_RX_P[1]SGMII_RX_M

[1]SGMII_TX_P

[9] VDD33_SGMII

[9] VDDH_2V5[10] TRXP0[10] TRXN0

[10]TRXP1

[10]TRXN1

[10]TRXP2

[10]TRXN2

[10]TRXP3

[10]TRXN3

[10]LED_ACT[10]LED_1000

[1] SGMII_MDIO_DATA[1] SGMII_MDIO_CLK

[9] VDD33_SGMII

CLK_25M

[9] VDD33_SGMII [3,12]VDD3V3

[1,2,3,4,11,12,13] VDD_EXT

[9]

VD

DH

_2V

5

[9]AVDD_1V1

[9] DVDD_1V1

[9]DVDD_1V1

[9] AVDD_1V1

[9]VDDH_2V5

[1]

US

IM2_

VD

D

AV

DD

_1V

1

[9]AVDD_1V1

[9] AVDD_1V1

Application external

0 = Pull-down, 1 = Pull-up.

An external 10K pull-down resistor is required.

Mode select bit 0

Mode select bit 1

Mode select bit 2

Mode select bit 3

weak pull-up/down

01

1

0

0

0

0

0

0

0

0

0

0

0

0

configuration signal weak pull-up/down

EXT_INT_SEL

MODE 0

MODE 1

MODE 2

MODE 3

PHY_AD0

PHY_AD1

PHY_AD2

PHY core

1

Default internal

The upper two bits of the physical address are set to 00.PHY_AD[2:0] set the lower three bits of the physical address.

Description


Woody WU

CHECKED BY

DRAWN BY

OF

A

6 5 4 3 2 1

SHEET

A

B

C

D

123456

D

C

B


SIZE VER

1310

G

DATE 2018/2/9

EC25

A2

Reference Design

Ethernet Network Port Design

Notes:1. Route MDI differential signals with 100Ω±10%, and the reference ground of the area should be complete.2. Keep skew of the MDI differential signals less than 20mils, and the maximum trace length must be less than10 inches.3. To minimize crosstalk, the distance between separate adjacent pairs that are on the same layer must be equal to or larger than 40 mils.

1 TCT12 TD1+3 TD1-4 TCT25 TD2+6 TD2-7 TCT38 TD3+9 TD3-

10 TCT411 TD4+12 TD4- 13MX4-

14MX4+

15MCT4

16MX3-

17MX3+

18MCT3

19MX2-

20MX2+

21MCT2

22MX1-

23MX1+

24MCT1

U1001

FC3004

C10

03

0.1uF

C10

04

0.1uFC

1005

0.1uF

C10

06

0.1uF

1 TA+

14H

213

H1

3 TB+

5 TC-

7 TD+

2 TA-

4 TC+

6 TB-

8 TD-

9G-

10G+

11Y-

12Y+

J1001

FC601-56-LED

R1001 75R 1%

R1003 75R 1%

R1004 75R 1%

R1006 75R 1%

C1001 1000pF/2KV_NM

C1002

1000pF/2KV

R1002 510R

R1007 510RR1005 0R

[9]LED_ACT

[9]LED_1000

[9] TRXP0[9] TRXN0

[9] TRXP1[9] TRXN1

[9] TRXP2[9] TRXN2

[9] TRXP3[9] TRXN3


Woody WU

CHECKED BY

DRAWN BY

OF

A

6 5 4 3 2 1

SHEET

A

B

C

D

123456

D

C

B


SIZE VER

1311

G

DATE 2018/2/9

EC25

A2

Reference Design

1. Keep all RESERVED and unused pins unconnected.Notes:

Reserved for debugging

2. BT function of FC20 is under development.

FC20 Design

4. Route SDIO signals with 50Ω±10% impedance. It is important to route the SDIO signal traces with total grounding, and the total routing length should be less than 50mm.3. Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals, etc, as well as noisy signals such as clock and DC-DC signals, etc.

5. It is recommended to keep the matching length between CLK and DATA/CMD less than 1mm.6. Make sure the adjacent trace spacing is two times of the trace width and the bus capacitance is less than 15pF. 7. The pins 5～8, 10, 13～18 should be unconnected when using FC20-N.8. FC20 power-on sequence: VIO -> VDD_3V3.

R1105 must be mounted.

R11

03N

M_1

0K

C1110

100nF

C1109

33pF

C1108

10pF

+ C1111

100uF

R1102 0R

R110110K

C1102

NM_0.1uF

C1104

10uF

C1105

100nF

C1106

33pF

C1107

10pF

R1118 0R

C1112

NM

R1117 10K

C1103

NM_0.1uF

R110910K

1 GND

2 RESERVED

3 RESERVED

4 DBG_TXD

5 LTE_UART_TXD

6 LTE_UART_RXD

7 BT_UART_RTS

8 BT_UART_CTS

9 WLAN_EN

10 BT_EN

11 VIO

12 GND 20GND

21VDD_3V3

22SDIO_D3

23SDIO_D2

24SDIO_D1

25SDIO_D0

26SDIO_CLK

27SDIO_CMD

28GND

29GND

30RF_ANT

31GND

13P

CM

_IN

14P

CM

_SY

NC

15P

CM

_CLK

16P

CM

_OU

T

17B

T_U

AR

T_T

XD

18B

T_U

AR

T_R

XD

1932

KH

Z_I

N32

WA

KE

_ON

_WIR

ELE

SS

33R

ES

ER

VE

D

34R

ES

ER

VE

D

35R

ES

ER

VE

D

36G

ND

37R

ES

ER

VE

D

38G

ND

U1101-A

FC20

39 GND

40 GND

41 RESERVED

42 RESERVED

43G

ND

44G

ND

45G

ND

46RESERVED

47RESERVED

48GND

49GND

50G

ND

51G

ND

52G

ND

U1101-B

FC20

R1115 0R

R1114 0R

R1112 0R

R1111 0R

R1110 0R

R1113 0R

R11

04N

M_1

0K

R11

0510

K

R11

06N

M_1

0K

R11

07N

M_1

0K

R11

08N

M_1

0K

C11

01N

M_1

0nF

R1116

51K

R111915K

R112010K

R112110K

[8]FC20_ANT

[1]SDIO_CMD

[1]SDIO_CLK

[1]SDIO_D0

[1]SDIO_D1

[1]SDIO_D2

[1]SDIO_D3

[3]VDD3V3_FC20

[1,2

,3,4

,9,1

1,12

,13]

VD

D_E

XT

[1,2,3,4,9,11,12,13]VDD_EXT

[1]WAKE_ON_WIRELESS

[1] WLAN_EN

[1,2,3,4,9,11,12,13] VDD_EXT

[1]WLAN_SLP_CLK[1] PCM_OUT_BT

[1] PCM_SYNC_BT

[1] PCM_CLK_BT

[1] PCM_IN_BT[1]TXD_BT[1]RXD_BT

[1,2,3,4,9,11,12,13] VDD_EXT

[1] BT_EN

[1] CTS_BT

[1] RTS_BT

[1] COEX_UART_RX

[1] COEX_UART_TX

[1,2

,3,4

,9,1

1,12

,13]

VD

D_E

XT

[1,2,3,4,9,11,12,13]VDD_EXT

[13] DBG_TXD_FC20


Woody WU

CHECKED BY

DRAWN BY

OF

A

6 5 4 3 2 1

SHEET

A

B

C

D

123456

D

C

B


SIZE VER

1312

G

DATE 2018/2/9

EC25

A2

Reference Design

SD Card Interface Design

6. Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals, etc, as well as noisy signals such as clock and DC-DC signals, etc.

3. To avoid the jitter of bus, resistors R1204～R1208 are needed to pull up SDIO to VDD_SDIO.

4. In order to adjust signal quality, it is recommended to add 0Ω resistors R1209～R1214 in series between the module and the SD card connector.

9. Make sure the adjacent trace spacing is two times of the trace width and the bus capacitance is less than 15pF.

5. It is recommended to add ESD protection devices near the pins of SD card connector. The parasitic capacitance of ESD protection devices should be smaller than 15pF.

2. The supply voltage range of VDD for SD card is 2.7V～3.6V and sufficient current up to 0.8A needs to be provided.1. The pin 34 (VDD_SDIO) on the module can only be used for SDIO pull-up resistors and its maximum output current is 50mA.Notes:

The bypass capacitors C1206～C1211 are reserved and not mounted by default.

The value of these resistors is among 10KΩ～100KΩ and the recommended value is 100KΩ.

7. Route SDIO signals with 50Ω±10% impedance. It is important to route SDIO signals with total grounding, and the total trace length should be less than 23mm.8. It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm.

C1203

100nF

R1209 0R

R1210 0R

R1212 0R

R1213 0R

R1214 0R

R1215120K

D1207

ESD9X3.3ST5G

R12161K

CMD

DATA3

DATA2

DATA0

DATA1

VSS

VDD

CLK

DETECT

J1201

SD card connector

C1206

NM

C1207

NM

C1208

NM

C1209

NM

C1210

NM

C1211

NM

R1204100K

R1205100K

R1206100K

R1207100K

R1208100K

R1211 0R

D1201

ESD9L5.0ST5G

D1202 D1203 D1204 D1205 D1206

R1202

10K

G

S D

Q1201

SI2333C1201

100nF

R1203100K

Q1202

DTC043ZE

R1201 0R

C1204

33pF

C1205

10pF

+

C1202

100uF

VDD_EXT

[1]SD2_INS_DET

[2] SD_PWR_EN

[1] SD2_CLK

[1] SD2_CMD

[1] SD2_DATA3

[1] SD2_DATA2

[1] SD2_DATA1

[1] SD2_DATA0

[1] VDD_SDIO

[3,9] VDD3V3


Woody WU

CHECKED BY

DRAWN BY

OF

A

6 5 4 3 2 1

SHEET

A

B

C

D

123456

D

C

B


SIZE VER

1313

G

DATE 2018/2/9

EC25

A2

Reference Design

Reserved Test Points

1. Both USB and debug UART interfaces are reserved for software debugging.2. USB interface also can be used to upgrade firmware.

Indicators

2. For more details about NET_MODE and NET_STATUS, please refer to

Notes:1. The STATUS is an open drain output pin, and its drive current is less than 1mA.

Other Designs

3. Junction capacitance of ESD protection devices on USB data lines should be less than 1pF.

Notes:

3. If the current consumption is required as low as possible when the device is in sleep, replace the power supply of indicators with controllable one.

4. The module DBG interface supports 1.8V power domain,

Turn off the power when the module enters into sleep mode.

1. It is recommended to reserve USB_BOOT design.Notes:

2. USB_BOOT is kept open by default.

Quectel_EC25_Hardware_Design.

When it is at high level, the module will enter download mode.

A level translator should be used if the power domain of customers' application is 3.3V.

D1307

SD12

D1308

SE

SD

3Z5V

D1306

ES

D9L

5.0S

T5G

D1305

ES

D9L

5.0S

T5G

D1309

ES

D9X

3.3S

T5G

D1310

ES

D9X

3.3S

T5G

Q1303

DTC043ZEBTL

R1304

2.2K

D1302

Q1302

DTC043ZEBTL

R13032.2K

D1301

D1311

ES

D9X

3.3S

T5G

1 2

J1301

R1306 4.7K

D1304

ESD9X3.3ST5G

4

5

6

3

2

1

7

8

9

J1302

Connector

R13072.2K

D1312

[1,3,13]VBAT

[1,2]PWRKEY

[1]USB_DP_TEST

[1]USB_DM_TEST

[1,2]USB_VBUS

[1]DBG_RXD

[1]DBG_TXD

[1] NET_STATUS

DC_5V

[1] NET_MODE

DC_5V

[1,2,3,4,9,11,12] VDD_EXT [1]USB_BOOT

[11]DBG_TXD_FC20

[1] STATUS

VBAT

EC25 Reference Design - Aurora Evernet

Documents

Transcript of EC25 Reference Design - Aurora Evernet